From b7591cfd19d308091dc67ae698c112cdb52a044f Mon Sep 17 00:00:00 2001 From: Dan Halbert Date: Wed, 11 Oct 2017 18:30:01 -0400 Subject: Replace asf4 tree with submodule repo adafruit/asf4, branch circuitpython. --- .gitmodules | 4 + atmel-samd/asf4 | 1 + .../asf4/patches/samd21/assert_redefined.patch | 20 - atmel-samd/asf4/patches/samd21/cast-align.patch | 36 - atmel-samd/asf4/patches/samd21/cortex_sc.patch | 20 - atmel-samd/asf4/patches/samd21/flash-const.patch | 61 - atmel-samd/asf4/patches/samd21/gclk_defined.patch | 11 - .../patches/samd21/little_endian_redefined.patch | 22 - .../patches/samd21/make_usb_cache_accessible.patch | 11 - .../asf4/patches/samd21/mark_used_no_c.patch | 20 - atmel-samd/asf4/patches/samd21/sysctrl_fix.patch | 11 - atmel-samd/asf4/patches/samd21/usb_undefined.patch | 22 - atmel-samd/asf4/patches/samd51/array-bounds.patch | 13 - .../asf4/patches/samd51/assert_redefined.patch | 20 - atmel-samd/asf4/patches/samd51/cast-align.patch | 49 - atmel-samd/asf4/patches/samd51/flash-const.patch | 63 - .../patches/samd51/little_endian_redefined.patch | 99 - .../patches/samd51/make_usb_cache_accessible.patch | 19 - .../asf4/patches/samd51/mark_used_no_c.patch | 20 - atmel-samd/asf4/patches/samd51/usb_undefined.patch | 22 - .../CMSIS/Documentation/Core/html/index.html | 241 - .../asf4/samd21/CMSIS/Include/arm_common_tables.h | 136 - .../asf4/samd21/CMSIS/Include/arm_const_structs.h | 79 - atmel-samd/asf4/samd21/CMSIS/Include/arm_math.h | 7544 ------------ atmel-samd/asf4/samd21/CMSIS/Include/core_cm0.h | 711 -- .../asf4/samd21/CMSIS/Include/core_cm0plus.h | 822 -- atmel-samd/asf4/samd21/CMSIS/Include/core_cm3.h | 1650 --- atmel-samd/asf4/samd21/CMSIS/Include/core_cm4.h | 1802 --- atmel-samd/asf4/samd21/CMSIS/Include/core_cm7.h | 2221 ---- atmel-samd/asf4/samd21/CMSIS/Include/core_cmFunc.h | 637 - .../asf4/samd21/CMSIS/Include/core_cmInstr.h | 880 -- atmel-samd/asf4/samd21/CMSIS/Include/core_cmSimd.h | 697 -- atmel-samd/asf4/samd21/CMSIS/Include/core_sc000.h | 842 -- atmel-samd/asf4/samd21/CMSIS/Include/core_sc300.h | 1630 --- atmel-samd/asf4/samd21/armcc/Makefile | 273 - atmel-samd/asf4/samd21/atmel_start.c | 10 - atmel-samd/asf4/samd21/atmel_start.h | 19 - atmel-samd/asf4/samd21/atmel_start_config.atstart | 1114 -- atmel-samd/asf4/samd21/atmel_start_pins.h | 63 - atmel-samd/asf4/samd21/config/hpl_adc_config.h | 296 - atmel-samd/asf4/samd21/config/hpl_dac_config.h | 86 - atmel-samd/asf4/samd21/config/hpl_dmac_config.h | 3057 ----- atmel-samd/asf4/samd21/config/hpl_gclk_config.h | 618 - atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h | 38 - atmel-samd/asf4/samd21/config/hpl_pm_config.h | 134 - atmel-samd/asf4/samd21/config/hpl_rtc_config.h | 117 - atmel-samd/asf4/samd21/config/hpl_sercom_config.h | 534 - atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h | 678 - atmel-samd/asf4/samd21/config/hpl_systick_config.h | 18 - atmel-samd/asf4/samd21/config/hpl_tc_config.h | 181 - atmel-samd/asf4/samd21/config/hpl_usb_config.h | 355 - .../asf4/samd21/config/peripheral_clk_config.h | 369 - .../samd21/documentation/usb_device_composite.rst | 32 - .../asf4/samd21/documentation/usb_device_core.rst | 41 - .../asf4/samd21/documentation/usb_protocol_cdc.rst | 24 - .../samd21/documentation/usb_protocol_core.rst | 40 - .../asf4/samd21/documentation/usb_protocol_hid.rst | 24 - .../asf4/samd21/documentation/usb_protocol_hub.rst | 32 - .../asf4/samd21/documentation/usb_protocol_msc.rst | 25 - .../samd21/documentation/usb_protocol_vendor.rst | 24 - atmel-samd/asf4/samd21/driver_init.c | 788 -- atmel-samd/asf4/samd21/driver_init.h | 99 - atmel-samd/asf4/samd21/examples/driver_examples.c | 140 - atmel-samd/asf4/samd21/examples/driver_examples.h | 32 - atmel-samd/asf4/samd21/gcc/Makefile | 286 - atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_flash.ld | 142 - atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_sram.ld | 141 - atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c | 254 - atmel-samd/asf4/samd21/gcc/system_samd21.c | 63 - .../asf4/samd21/hal/documentation/adc_sync.rst | 74 - .../asf4/samd21/hal/documentation/dac_sync.rst | 41 - atmel-samd/asf4/samd21/hal/documentation/flash.rst | 52 - .../samd21/hal/documentation/i2c_master_sync.rst | 87 - atmel-samd/asf4/samd21/hal/documentation/pwm.rst | 53 - .../samd21/hal/documentation/spi_master_sync.rst | 51 - atmel-samd/asf4/samd21/hal/documentation/timer.rst | 52 - .../asf4/samd21/hal/documentation/usart_sync.rst | 58 - .../samd21/hal/documentation/usb_device_async.rst | 195 - atmel-samd/asf4/samd21/hal/include/hal_adc_sync.h | 287 - atmel-samd/asf4/samd21/hal/include/hal_atomic.h | 137 - atmel-samd/asf4/samd21/hal/include/hal_dac_sync.h | 134 - atmel-samd/asf4/samd21/hal/include/hal_delay.h | 99 - atmel-samd/asf4/samd21/hal/include/hal_flash.h | 219 - atmel-samd/asf4/samd21/hal/include/hal_gpio.h | 212 - .../asf4/samd21/hal/include/hal_i2c_m_sync.h | 254 - atmel-samd/asf4/samd21/hal/include/hal_init.h | 82 - atmel-samd/asf4/samd21/hal/include/hal_io.h | 120 - atmel-samd/asf4/samd21/hal/include/hal_pwm.h | 161 - atmel-samd/asf4/samd21/hal/include/hal_sleep.h | 84 - .../asf4/samd21/hal/include/hal_spi_m_sync.h | 220 - atmel-samd/asf4/samd21/hal/include/hal_timer.h | 216 - .../asf4/samd21/hal/include/hal_usart_sync.h | 257 - .../asf4/samd21/hal/include/hal_usb_device.h | 305 - atmel-samd/asf4/samd21/hal/include/hpl_adc_async.h | 274 - atmel-samd/asf4/samd21/hal/include/hpl_adc_dma.h | 253 - atmel-samd/asf4/samd21/hal/include/hpl_adc_sync.h | 281 - atmel-samd/asf4/samd21/hal/include/hpl_calendar.h | 252 - atmel-samd/asf4/samd21/hal/include/hpl_core.h | 66 - atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h | 182 - atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h | 148 - atmel-samd/asf4/samd21/hal/include/hpl_delay.h | 88 - atmel-samd/asf4/samd21/hal/include/hpl_dma.h | 167 - atmel-samd/asf4/samd21/hal/include/hpl_flash.h | 228 - atmel-samd/asf4/samd21/hal/include/hpl_gpio.h | 195 - .../asf4/samd21/hal/include/hpl_i2c_m_async.h | 215 - .../asf4/samd21/hal/include/hpl_i2c_m_sync.h | 195 - .../asf4/samd21/hal/include/hpl_i2c_s_async.h | 194 - .../asf4/samd21/hal/include/hpl_i2c_s_sync.h | 185 - atmel-samd/asf4/samd21/hal/include/hpl_init.h | 134 - atmel-samd/asf4/samd21/hal/include/hpl_irq.h | 126 - .../asf4/samd21/hal/include/hpl_missing_features.h | 47 - atmel-samd/asf4/samd21/hal/include/hpl_pwm.h | 203 - atmel-samd/asf4/samd21/hal/include/hpl_reset.h | 101 - atmel-samd/asf4/samd21/hal/include/hpl_sleep.h | 98 - atmel-samd/asf4/samd21/hal/include/hpl_spi.h | 173 - atmel-samd/asf4/samd21/hal/include/hpl_spi_async.h | 137 - atmel-samd/asf4/samd21/hal/include/hpl_spi_dma.h | 98 - .../asf4/samd21/hal/include/hpl_spi_m_async.h | 248 - atmel-samd/asf4/samd21/hal/include/hpl_spi_m_dma.h | 187 - .../asf4/samd21/hal/include/hpl_spi_m_sync.h | 171 - .../asf4/samd21/hal/include/hpl_spi_s_async.h | 227 - .../asf4/samd21/hal/include/hpl_spi_s_sync.h | 237 - atmel-samd/asf4/samd21/hal/include/hpl_spi_sync.h | 80 - .../asf4/samd21/hal/include/hpl_time_measure.h | 104 - atmel-samd/asf4/samd21/hal/include/hpl_timer.h | 170 - atmel-samd/asf4/samd21/hal/include/hpl_usart.h | 123 - .../asf4/samd21/hal/include/hpl_usart_async.h | 280 - .../asf4/samd21/hal/include/hpl_usart_sync.h | 253 - atmel-samd/asf4/samd21/hal/include/hpl_usb.h | 281 - .../asf4/samd21/hal/include/hpl_usb_device.h | 387 - atmel-samd/asf4/samd21/hal/include/hpl_usb_host.h | 628 - atmel-samd/asf4/samd21/hal/include/hpl_user_area.h | 133 - atmel-samd/asf4/samd21/hal/src/hal_adc_sync.c | 254 - atmel-samd/asf4/samd21/hal/src/hal_atomic.c | 76 - atmel-samd/asf4/samd21/hal/src/hal_dac_sync.c | 141 - atmel-samd/asf4/samd21/hal/src/hal_delay.c | 90 - atmel-samd/asf4/samd21/hal/src/hal_flash.c | 330 - atmel-samd/asf4/samd21/hal/src/hal_gpio.c | 54 - atmel-samd/asf4/samd21/hal/src/hal_i2c_m_sync.c | 268 - atmel-samd/asf4/samd21/hal/src/hal_init.c | 57 - atmel-samd/asf4/samd21/hal/src/hal_io.c | 73 - atmel-samd/asf4/samd21/hal/src/hal_pwm.c | 169 - atmel-samd/asf4/samd21/hal/src/hal_sleep.c | 83 - atmel-samd/asf4/samd21/hal/src/hal_spi_m_sync.c | 212 - atmel-samd/asf4/samd21/hal/src/hal_timer.c | 263 - atmel-samd/asf4/samd21/hal/src/hal_usart_sync.c | 285 - atmel-samd/asf4/samd21/hal/src/hal_usb_device.c | 602 - .../asf4/samd21/hal/utils/include/compiler.h | 28 - .../asf4/samd21/hal/utils/include/err_codes.h | 83 - atmel-samd/asf4/samd21/hal/utils/include/events.h | 64 - atmel-samd/asf4/samd21/hal/utils/include/parts.h | 51 - atmel-samd/asf4/samd21/hal/utils/include/utils.h | 364 - .../asf4/samd21/hal/utils/include/utils_assert.h | 103 - .../hal/utils/include/utils_decrement_macro.h | 319 - .../asf4/samd21/hal/utils/include/utils_event.h | 125 - .../hal/utils/include/utils_increment_macro.h | 318 - .../asf4/samd21/hal/utils/include/utils_list.h | 174 - .../hal/utils/include/utils_recursion_macro.h | 79 - .../samd21/hal/utils/include/utils_repeat_macro.h | 332 - .../asf4/samd21/hal/utils/src/utils_assert.c | 56 - atmel-samd/asf4/samd21/hal/utils/src/utils_event.c | 135 - atmel-samd/asf4/samd21/hal/utils/src/utils_list.c | 146 - .../asf4/samd21/hal/utils/src/utils_syscalls.c | 162 - atmel-samd/asf4/samd21/hpl/adc/hpl_adc.c | 761 -- atmel-samd/asf4/samd21/hpl/adc/hpl_adc_base.h | 82 - .../asf4/samd21/hpl/core/hpl_core_m0plus_base.c | 210 - atmel-samd/asf4/samd21/hpl/core/hpl_core_port.h | 71 - atmel-samd/asf4/samd21/hpl/core/hpl_init.c | 69 - atmel-samd/asf4/samd21/hpl/dac/hpl_dac.c | 248 - atmel-samd/asf4/samd21/hpl/dmac/hpl_dmac.c | 226 - atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk.c | 162 - atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk_base.h | 91 - atmel-samd/asf4/samd21/hpl/nvmctrl/hpl_nvmctrl.c | 684 -- atmel-samd/asf4/samd21/hpl/pm/hpl_pm.c | 87 - atmel-samd/asf4/samd21/hpl/pm/hpl_pm_base.h | 213 - atmel-samd/asf4/samd21/hpl/port/hpl_gpio_base.h | 172 - atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc.c | 201 - atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc_base.h | 62 - atmel-samd/asf4/samd21/hpl/sercom/hpl_sercom.c | 2897 ----- atmel-samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c | 265 - atmel-samd/asf4/samd21/hpl/systick/hpl_systick.c | 113 - atmel-samd/asf4/samd21/hpl/tc/hpl_tc.c | 369 - atmel-samd/asf4/samd21/hpl/tc/hpl_tc_base.h | 87 - atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c | 2051 --- atmel-samd/asf4/samd21/hri/hri_ac_d21.h | 1586 --- atmel-samd/asf4/samd21/hri/hri_adc_d21.h | 2513 ---- atmel-samd/asf4/samd21/hri/hri_d21.h | 73 - atmel-samd/asf4/samd21/hri/hri_dac_d21.h | 1033 -- atmel-samd/asf4/samd21/hri/hri_dmac_d21.h | 4308 ------- atmel-samd/asf4/samd21/hri/hri_dsu_d21.h | 979 -- atmel-samd/asf4/samd21/hri/hri_eic_d21.h | 3233 ----- atmel-samd/asf4/samd21/hri/hri_evsys_d21.h | 1729 --- atmel-samd/asf4/samd21/hri/hri_gclk_d21.h | 933 -- atmel-samd/asf4/samd21/hri/hri_hmatrixb_d21.h | 289 - atmel-samd/asf4/samd21/hri/hri_i2s_d21.h | 2516 ---- atmel-samd/asf4/samd21/hri/hri_mtb_d21.h | 560 - atmel-samd/asf4/samd21/hri/hri_nvic_d21.h | 2304 ---- atmel-samd/asf4/samd21/hri/hri_nvmctrl_d21.h | 1024 -- atmel-samd/asf4/samd21/hri/hri_pac_d21.h | 130 - atmel-samd/asf4/samd21/hri/hri_pm_d21.h | 2545 ---- atmel-samd/asf4/samd21/hri/hri_port_d21.h | 1324 -- atmel-samd/asf4/samd21/hri/hri_rtc_d21.h | 5921 --------- atmel-samd/asf4/samd21/hri/hri_sercom_d21.h | 7188 ----------- atmel-samd/asf4/samd21/hri/hri_sysctrl_d21.h | 4760 ------- atmel-samd/asf4/samd21/hri/hri_systemcontrol_d21.h | 1477 --- atmel-samd/asf4/samd21/hri/hri_systick_d21.h | 620 - atmel-samd/asf4/samd21/hri/hri_tc_d21.h | 2190 ---- atmel-samd/asf4/samd21/hri/hri_tcc_d21.h | 10318 ---------------- atmel-samd/asf4/samd21/hri/hri_usb_d21.h | 9811 --------------- atmel-samd/asf4/samd21/hri/hri_wdt_d21.h | 616 - atmel-samd/asf4/samd21/include/component-version.h | 65 - atmel-samd/asf4/samd21/include/component/ac.h | 544 - atmel-samd/asf4/samd21/include/component/adc.h | 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atmel-samd/asf4/samd21/include/component/tcc.h | 1802 --- atmel-samd/asf4/samd21/include/component/usb.h | 1790 --- atmel-samd/asf4/samd21/include/component/wdt.h | 288 - atmel-samd/asf4/samd21/include/instance/ac.h | 72 - atmel-samd/asf4/samd21/include/instance/adc.h | 84 - atmel-samd/asf4/samd21/include/instance/dac.h | 59 - atmel-samd/asf4/samd21/include/instance/dmac.h | 94 - atmel-samd/asf4/samd21/include/instance/dsu.h | 84 - atmel-samd/asf4/samd21/include/instance/eic.h | 63 - atmel-samd/asf4/samd21/include/instance/evsys.h | 179 - atmel-samd/asf4/samd21/include/instance/gclk.h | 64 - atmel-samd/asf4/samd21/include/instance/i2s.h | 79 - atmel-samd/asf4/samd21/include/instance/mtb.h | 88 - atmel-samd/asf4/samd21/include/instance/nvmctrl.h | 76 - atmel-samd/asf4/samd21/include/instance/pac0.h | 44 - atmel-samd/asf4/samd21/include/instance/pac1.h | 44 - atmel-samd/asf4/samd21/include/instance/pac2.h | 44 - atmel-samd/asf4/samd21/include/instance/pm.h | 72 - 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100 - atmel-samd/asf4/samd21/include/instance/usb.h | 329 - atmel-samd/asf4/samd21/include/instance/wdt.h | 56 - atmel-samd/asf4/samd21/include/pio/samd21e15a.h | 651 - atmel-samd/asf4/samd21/include/pio/samd21e16a.h | 651 - atmel-samd/asf4/samd21/include/pio/samd21e17a.h | 651 - atmel-samd/asf4/samd21/include/pio/samd21e18a.h | 651 - atmel-samd/asf4/samd21/include/pio/samd21g15a.h | 937 -- atmel-samd/asf4/samd21/include/pio/samd21g16a.h | 937 -- atmel-samd/asf4/samd21/include/pio/samd21g17a.h | 937 -- atmel-samd/asf4/samd21/include/pio/samd21g17au.h | 882 -- atmel-samd/asf4/samd21/include/pio/samd21g18a.h | 937 -- atmel-samd/asf4/samd21/include/pio/samd21g18au.h | 882 -- atmel-samd/asf4/samd21/include/pio/samd21j15a.h | 1225 -- atmel-samd/asf4/samd21/include/pio/samd21j16a.h | 1225 -- atmel-samd/asf4/samd21/include/pio/samd21j17a.h | 1225 -- atmel-samd/asf4/samd21/include/pio/samd21j18a.h | 1225 -- atmel-samd/asf4/samd21/include/sam.h | 63 - atmel-samd/asf4/samd21/include/samd21.h | 69 - atmel-samd/asf4/samd21/include/samd21e15a.h | 552 - atmel-samd/asf4/samd21/include/samd21e16a.h | 552 - atmel-samd/asf4/samd21/include/samd21e17a.h | 552 - atmel-samd/asf4/samd21/include/samd21e18a.h | 552 - atmel-samd/asf4/samd21/include/samd21g15a.h | 564 - atmel-samd/asf4/samd21/include/samd21g16a.h | 564 - atmel-samd/asf4/samd21/include/samd21g17a.h | 564 - atmel-samd/asf4/samd21/include/samd21g17au.h | 576 - atmel-samd/asf4/samd21/include/samd21g18a.h | 564 - atmel-samd/asf4/samd21/include/samd21g18au.h | 576 - atmel-samd/asf4/samd21/include/samd21j15a.h | 576 - atmel-samd/asf4/samd21/include/samd21j16a.h | 576 - atmel-samd/asf4/samd21/include/samd21j17a.h | 576 - atmel-samd/asf4/samd21/include/samd21j18a.h | 576 - atmel-samd/asf4/samd21/include/system_samd21.h | 47 - atmel-samd/asf4/samd21/main.c | 11 - .../Device/SAMD21/Source/ARM/startup_SAMD21.s | 247 - .../armcc/Device/SAMD21/Source/system_samd21.c | 78 - .../asf4/samd21/usb/class/cdc/device/cdcdf_acm.c | 389 - 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.../samd21/usb/class/vendor/usb_protocol_vendor.h | 63 - atmel-samd/asf4/samd21/usb/device/usbdc.c | 838 -- atmel-samd/asf4/samd21/usb/device/usbdc.h | 246 - atmel-samd/asf4/samd21/usb/usb_atmel.h | 189 - atmel-samd/asf4/samd21/usb/usb_debug.h | 47 - atmel-samd/asf4/samd21/usb/usb_includes.h | 137 - atmel-samd/asf4/samd21/usb/usb_protocol.c | 146 - atmel-samd/asf4/samd21/usb/usb_protocol.h | 765 -- atmel-samd/asf4/samd21/usb_start.c | 82 - atmel-samd/asf4/samd21/usb_start.h | 48 - .../CMSIS/Documentation/Core/html/index.html | 241 - .../asf4/samd51/CMSIS/Include/arm_common_tables.h | 136 - .../asf4/samd51/CMSIS/Include/arm_const_structs.h | 79 - atmel-samd/asf4/samd51/CMSIS/Include/arm_math.h | 7544 ------------ atmel-samd/asf4/samd51/CMSIS/Include/core_cm0.h | 711 -- .../asf4/samd51/CMSIS/Include/core_cm0plus.h | 822 -- atmel-samd/asf4/samd51/CMSIS/Include/core_cm3.h | 1650 --- atmel-samd/asf4/samd51/CMSIS/Include/core_cm4.h | 1806 --- atmel-samd/asf4/samd51/CMSIS/Include/core_cm7.h | 2221 ---- atmel-samd/asf4/samd51/CMSIS/Include/core_cmFunc.h | 637 - .../asf4/samd51/CMSIS/Include/core_cmInstr.h | 880 -- atmel-samd/asf4/samd51/CMSIS/Include/core_cmSimd.h | 697 -- atmel-samd/asf4/samd51/CMSIS/Include/core_sc000.h | 842 -- atmel-samd/asf4/samd51/CMSIS/Include/core_sc300.h | 1630 --- atmel-samd/asf4/samd51/armcc/Makefile | 291 - atmel-samd/asf4/samd51/atmel_start.c | 10 - atmel-samd/asf4/samd51/atmel_start.h | 19 - atmel-samd/asf4/samd51/atmel_start_config.atstart | 1716 --- atmel-samd/asf4/samd51/atmel_start_pins.h | 40 - atmel-samd/asf4/samd51/config/hpl_adc_config.h | 303 - atmel-samd/asf4/samd51/config/hpl_dac_config.h | 169 - atmel-samd/asf4/samd51/config/hpl_dmac_config.h | 7277 ----------- atmel-samd/asf4/samd51/config/hpl_evsys_config.h | 8359 ------------- atmel-samd/asf4/samd51/config/hpl_gclk_config.h | 908 -- atmel-samd/asf4/samd51/config/hpl_mclk_config.h | 104 - atmel-samd/asf4/samd51/config/hpl_nvmctrl_config.h | 36 - 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391 - atmel-samd/asf4/samd51/driver_init.h | 107 - atmel-samd/asf4/samd51/examples/driver_examples.c | 162 - atmel-samd/asf4/samd51/examples/driver_examples.h | 34 - atmel-samd/asf4/samd51/gcc/Makefile | 312 - atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_flash.ld | 163 - atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_sram.ld | 162 - atmel-samd/asf4/samd51/gcc/gcc/startup_samd51.c | 680 - atmel-samd/asf4/samd51/gcc/system_samd51.c | 64 - .../asf4/samd51/hal/documentation/adc_sync.rst | 74 - .../asf4/samd51/hal/documentation/dac_sync.rst | 41 - atmel-samd/asf4/samd51/hal/documentation/evsys.rst | 24 - atmel-samd/asf4/samd51/hal/documentation/flash.rst | 52 - .../samd51/hal/documentation/i2c_master_sync.rst | 87 - atmel-samd/asf4/samd51/hal/documentation/pwm.rst | 53 - .../asf4/samd51/hal/documentation/rand_sync.rst | 43 - .../samd51/hal/documentation/spi_master_sync.rst | 51 - atmel-samd/asf4/samd51/hal/documentation/timer.rst | 52 - .../asf4/samd51/hal/documentation/usart_sync.rst | 58 - .../samd51/hal/documentation/usb_device_async.rst | 195 - atmel-samd/asf4/samd51/hal/include/hal_adc_sync.h | 287 - atmel-samd/asf4/samd51/hal/include/hal_atomic.h | 137 - atmel-samd/asf4/samd51/hal/include/hal_dac_sync.h | 134 - atmel-samd/asf4/samd51/hal/include/hal_delay.h | 99 - atmel-samd/asf4/samd51/hal/include/hal_evsys.h | 126 - atmel-samd/asf4/samd51/hal/include/hal_flash.h | 219 - atmel-samd/asf4/samd51/hal/include/hal_gpio.h | 212 - .../asf4/samd51/hal/include/hal_i2c_m_sync.h | 254 - atmel-samd/asf4/samd51/hal/include/hal_init.h | 82 - atmel-samd/asf4/samd51/hal/include/hal_io.h | 120 - atmel-samd/asf4/samd51/hal/include/hal_pwm.h | 161 - atmel-samd/asf4/samd51/hal/include/hal_rand_sync.h | 144 - atmel-samd/asf4/samd51/hal/include/hal_sleep.h | 84 - .../asf4/samd51/hal/include/hal_spi_m_sync.h | 220 - atmel-samd/asf4/samd51/hal/include/hal_timer.h | 216 - .../asf4/samd51/hal/include/hal_usart_sync.h | 257 - .../asf4/samd51/hal/include/hal_usb_device.h | 305 - atmel-samd/asf4/samd51/hal/include/hpl_adc_async.h | 274 - atmel-samd/asf4/samd51/hal/include/hpl_adc_dma.h | 253 - atmel-samd/asf4/samd51/hal/include/hpl_adc_sync.h | 281 - atmel-samd/asf4/samd51/hal/include/hpl_calendar.h | 252 - atmel-samd/asf4/samd51/hal/include/hpl_core.h | 66 - atmel-samd/asf4/samd51/hal/include/hpl_dac_async.h | 181 - atmel-samd/asf4/samd51/hal/include/hpl_dac_sync.h | 147 - atmel-samd/asf4/samd51/hal/include/hpl_delay.h | 88 - atmel-samd/asf4/samd51/hal/include/hpl_dma.h | 167 - atmel-samd/asf4/samd51/hal/include/hpl_evsys.h | 104 - atmel-samd/asf4/samd51/hal/include/hpl_flash.h | 228 - atmel-samd/asf4/samd51/hal/include/hpl_gpio.h | 195 - .../asf4/samd51/hal/include/hpl_i2c_m_async.h | 215 - .../asf4/samd51/hal/include/hpl_i2c_m_sync.h | 195 - .../asf4/samd51/hal/include/hpl_i2c_s_async.h | 194 - .../asf4/samd51/hal/include/hpl_i2c_s_sync.h | 185 - atmel-samd/asf4/samd51/hal/include/hpl_init.h | 134 - atmel-samd/asf4/samd51/hal/include/hpl_irq.h | 126 - .../asf4/samd51/hal/include/hpl_missing_features.h | 47 - atmel-samd/asf4/samd51/hal/include/hpl_pwm.h | 203 - atmel-samd/asf4/samd51/hal/include/hpl_ramecc.h | 110 - atmel-samd/asf4/samd51/hal/include/hpl_rand_sync.h | 109 - atmel-samd/asf4/samd51/hal/include/hpl_reset.h | 103 - atmel-samd/asf4/samd51/hal/include/hpl_sleep.h | 98 - atmel-samd/asf4/samd51/hal/include/hpl_spi.h | 173 - atmel-samd/asf4/samd51/hal/include/hpl_spi_async.h | 137 - atmel-samd/asf4/samd51/hal/include/hpl_spi_dma.h | 98 - .../asf4/samd51/hal/include/hpl_spi_m_async.h | 248 - atmel-samd/asf4/samd51/hal/include/hpl_spi_m_dma.h | 187 - .../asf4/samd51/hal/include/hpl_spi_m_sync.h | 171 - .../asf4/samd51/hal/include/hpl_spi_s_async.h | 227 - .../asf4/samd51/hal/include/hpl_spi_s_sync.h | 237 - atmel-samd/asf4/samd51/hal/include/hpl_spi_sync.h | 80 - .../asf4/samd51/hal/include/hpl_time_measure.h | 104 - atmel-samd/asf4/samd51/hal/include/hpl_timer.h | 170 - atmel-samd/asf4/samd51/hal/include/hpl_usart.h | 123 - .../asf4/samd51/hal/include/hpl_usart_async.h | 280 - .../asf4/samd51/hal/include/hpl_usart_sync.h | 253 - atmel-samd/asf4/samd51/hal/include/hpl_usb.h | 281 - .../asf4/samd51/hal/include/hpl_usb_device.h | 387 - atmel-samd/asf4/samd51/hal/include/hpl_usb_host.h | 628 - atmel-samd/asf4/samd51/hal/include/hpl_user_area.h | 133 - atmel-samd/asf4/samd51/hal/src/hal_adc_sync.c | 254 - atmel-samd/asf4/samd51/hal/src/hal_atomic.c | 76 - atmel-samd/asf4/samd51/hal/src/hal_dac_sync.c | 141 - atmel-samd/asf4/samd51/hal/src/hal_delay.c | 90 - atmel-samd/asf4/samd51/hal/src/hal_evsys.c | 108 - atmel-samd/asf4/samd51/hal/src/hal_flash.c | 330 - atmel-samd/asf4/samd51/hal/src/hal_gpio.c | 54 - atmel-samd/asf4/samd51/hal/src/hal_i2c_m_sync.c | 268 - atmel-samd/asf4/samd51/hal/src/hal_init.c | 57 - atmel-samd/asf4/samd51/hal/src/hal_io.c | 73 - atmel-samd/asf4/samd51/hal/src/hal_pwm.c | 169 - atmel-samd/asf4/samd51/hal/src/hal_rand_sync.c | 132 - atmel-samd/asf4/samd51/hal/src/hal_sleep.c | 83 - atmel-samd/asf4/samd51/hal/src/hal_spi_m_sync.c | 212 - atmel-samd/asf4/samd51/hal/src/hal_timer.c | 263 - atmel-samd/asf4/samd51/hal/src/hal_usart_sync.c | 285 - atmel-samd/asf4/samd51/hal/src/hal_usb_device.c | 602 - .../asf4/samd51/hal/utils/include/compiler.h | 28 - .../asf4/samd51/hal/utils/include/err_codes.h | 83 - atmel-samd/asf4/samd51/hal/utils/include/events.h | 64 - atmel-samd/asf4/samd51/hal/utils/include/parts.h | 51 - atmel-samd/asf4/samd51/hal/utils/include/utils.h | 364 - .../asf4/samd51/hal/utils/include/utils_assert.h | 103 - .../hal/utils/include/utils_decrement_macro.h | 319 - .../asf4/samd51/hal/utils/include/utils_event.h | 125 - .../hal/utils/include/utils_increment_macro.h | 318 - .../asf4/samd51/hal/utils/include/utils_list.h | 174 - .../hal/utils/include/utils_recursion_macro.h | 79 - .../samd51/hal/utils/include/utils_repeat_macro.h | 332 - .../asf4/samd51/hal/utils/src/utils_assert.c | 56 - atmel-samd/asf4/samd51/hal/utils/src/utils_event.c | 135 - atmel-samd/asf4/samd51/hal/utils/src/utils_list.c | 146 - .../asf4/samd51/hal/utils/src/utils_syscalls.c | 162 - atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c | 786 -- atmel-samd/asf4/samd51/hpl/adc/hpl_adc_base.h | 82 - atmel-samd/asf4/samd51/hpl/core/hpl_core_m4.c | 213 - atmel-samd/asf4/samd51/hpl/core/hpl_core_port.h | 71 - atmel-samd/asf4/samd51/hpl/core/hpl_init.c | 69 - atmel-samd/asf4/samd51/hpl/dac/hpl_dac.c | 326 - atmel-samd/asf4/samd51/hpl/dmac/hpl_dmac.c | 262 - atmel-samd/asf4/samd51/hpl/evsys/hpl_evsys.c | 151 - atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk.c | 200 - atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk_base.h | 90 - atmel-samd/asf4/samd51/hpl/mclk/hpl_mclk.c | 54 - atmel-samd/asf4/samd51/hpl/nvmctrl/hpl_nvmctrl.c | 702 -- .../asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c | 94 - atmel-samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c | 244 - atmel-samd/asf4/samd51/hpl/pm/hpl_pm.c | 65 - atmel-samd/asf4/samd51/hpl/pm/hpl_pm_base.h | 55 - atmel-samd/asf4/samd51/hpl/port/hpl_gpio_base.h | 172 - atmel-samd/asf4/samd51/hpl/ramecc/hpl_ramecc.c | 93 - atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc.c | 193 - atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc_base.h | 62 - atmel-samd/asf4/samd51/hpl/sercom/hpl_sercom.c | 2922 ----- atmel-samd/asf4/samd51/hpl/systick/hpl_systick.c | 117 - atmel-samd/asf4/samd51/hpl/tc/hpl_tc.c | 377 - atmel-samd/asf4/samd51/hpl/tc/hpl_tc_base.h | 87 - atmel-samd/asf4/samd51/hpl/trng/hpl_trng.c | 120 - atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c | 2087 ---- atmel-samd/asf4/samd51/hri/hri_ac_d51.h | 1827 --- atmel-samd/asf4/samd51/hri/hri_adc_d51.h | 3736 ------ atmel-samd/asf4/samd51/hri/hri_aes_d51.h | 1296 -- atmel-samd/asf4/samd51/hri/hri_ccl_d51.h | 785 -- atmel-samd/asf4/samd51/hri/hri_cmcc_d51.h | 370 - atmel-samd/asf4/samd51/hri/hri_d51.h | 85 - atmel-samd/asf4/samd51/hri/hri_dac_d51.h | 1701 --- atmel-samd/asf4/samd51/hri/hri_dmac_d51.h | 6844 ----------- atmel-samd/asf4/samd51/hri/hri_dsu_d51.h | 3766 ------ atmel-samd/asf4/samd51/hri/hri_eic_d51.h | 1841 --- atmel-samd/asf4/samd51/hri/hri_evsys_d51.h | 1716 --- atmel-samd/asf4/samd51/hri/hri_freqm_d51.h | 467 - atmel-samd/asf4/samd51/hri/hri_gclk_d51.h | 770 -- atmel-samd/asf4/samd51/hri/hri_hmatrixb_d51.h | 246 - atmel-samd/asf4/samd51/hri/hri_i2s_d51.h | 3107 ----- atmel-samd/asf4/samd51/hri/hri_icm_d51.h | 770 -- atmel-samd/asf4/samd51/hri/hri_mclk_d51.h | 3445 ------ atmel-samd/asf4/samd51/hri/hri_nvmctrl_d51.h | 1627 --- atmel-samd/asf4/samd51/hri/hri_osc32kctrl_d51.h | 1208 -- atmel-samd/asf4/samd51/hri/hri_oscctrl_d51.h | 4360 ------- atmel-samd/asf4/samd51/hri/hri_pac_d51.h | 1493 --- atmel-samd/asf4/samd51/hri/hri_pcc_d51.h | 307 - atmel-samd/asf4/samd51/hri/hri_pdec_d51.h | 2642 ---- atmel-samd/asf4/samd51/hri/hri_pm_d51.h | 829 -- atmel-samd/asf4/samd51/hri/hri_port_d51.h | 2537 ---- atmel-samd/asf4/samd51/hri/hri_qspi_d51.h | 2067 ---- atmel-samd/asf4/samd51/hri/hri_ramecc_d51.h | 371 - atmel-samd/asf4/samd51/hri/hri_rstc_d51.h | 151 - atmel-samd/asf4/samd51/hri/hri_rtc_d51.h | 12310 ------------------- atmel-samd/asf4/samd51/hri/hri_sdhc_d51.h | 9878 --------------- atmel-samd/asf4/samd51/hri/hri_sercom_d51.h | 8591 ------------- atmel-samd/asf4/samd51/hri/hri_supc_d51.h | 2311 ---- atmel-samd/asf4/samd51/hri/hri_tal_d51.h | 10867 ---------------- atmel-samd/asf4/samd51/hri/hri_tc_d51.h | 2861 ----- atmel-samd/asf4/samd51/hri/hri_tcc_d51.h | 10329 ---------------- atmel-samd/asf4/samd51/hri/hri_trng_d51.h | 389 - atmel-samd/asf4/samd51/hri/hri_usb_d51.h | 9851 --------------- atmel-samd/asf4/samd51/hri/hri_wdt_d51.h | 619 - atmel-samd/asf4/samd51/include/component-version.h | 65 - atmel-samd/asf4/samd51/include/component/ac.h | 598 - atmel-samd/asf4/samd51/include/component/adc.h | 871 -- atmel-samd/asf4/samd51/include/component/aes.h | 375 - atmel-samd/asf4/samd51/include/component/can.h | 3207 ----- atmel-samd/asf4/samd51/include/component/ccl.h | 228 - atmel-samd/asf4/samd51/include/component/cmcc.h | 357 - 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atmel-samd/asf4/samd51/include/instance/adc1.h | 100 - atmel-samd/asf4/samd51/include/instance/aes.h | 105 - atmel-samd/asf4/samd51/include/instance/can0.h | 153 - atmel-samd/asf4/samd51/include/instance/can1.h | 151 - atmel-samd/asf4/samd51/include/instance/ccl.h | 57 - atmel-samd/asf4/samd51/include/instance/cmcc.h | 61 - atmel-samd/asf4/samd51/include/instance/dac.h | 88 - atmel-samd/asf4/samd51/include/instance/dmac.h | 596 - atmel-samd/asf4/samd51/include/instance/dsu.h | 121 - atmel-samd/asf4/samd51/include/instance/eic.h | 73 - atmel-samd/asf4/samd51/include/instance/evsys.h | 722 -- atmel-samd/asf4/samd51/include/instance/freqm.h | 59 - atmel-samd/asf4/samd51/include/instance/gclk.h | 191 - atmel-samd/asf4/samd51/include/instance/hmatrix.h | 133 - atmel-samd/asf4/samd51/include/instance/i2s.h | 81 - atmel-samd/asf4/samd51/include/instance/icm.h | 77 - atmel-samd/asf4/samd51/include/instance/mclk.h | 61 - atmel-samd/asf4/samd51/include/instance/nvmctrl.h | 75 - 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+ path = atmel-samd/asf4 + url = https://github.com/adafruit/asf4.git + branch = circuitpython diff --git a/atmel-samd/asf4 b/atmel-samd/asf4 new file mode 160000 index 000000000..8dc86ee76 --- /dev/null +++ b/atmel-samd/asf4 @@ -0,0 +1 @@ +Subproject commit 8dc86ee7657c92553e70803fdcef681a257f7e32 diff --git a/atmel-samd/asf4/patches/samd21/assert_redefined.patch b/atmel-samd/asf4/patches/samd21/assert_redefined.patch deleted file mode 100644 index 7d8c9e762..000000000 --- a/atmel-samd/asf4/patches/samd21/assert_redefined.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- samd21_vanilla/hal/utils/include/utils_assert.h 2017-09-28 12:05:22.000000000 -0700 -+++ samd21/hal/utils/include/utils_assert.h 2017-09-19 13:07:29.000000000 -0700 -@@ -72,7 +72,7 @@ - if (!(condition)) \ - __asm("BKPT #0"); - #else --#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) -+#define ASSERT_IMPL(condition, file, line) asf_assert((condition), file, line) - #endif - - #else /* DEBUG */ -@@ -95,7 +95,7 @@ - * \param[in] file File name - * \param[in] line Line number - */ --void assert(const bool condition, const char *const file, const int line); -+void asf_assert(const bool condition, const char *const file, const int line); - - #ifdef __cplusplus - } diff --git a/atmel-samd/asf4/patches/samd21/cast-align.patch b/atmel-samd/asf4/patches/samd21/cast-align.patch deleted file mode 100644 index 2059867e4..000000000 --- a/atmel-samd/asf4/patches/samd21/cast-align.patch +++ /dev/null @@ -1,36 +0,0 @@ ---- samd21_vanilla/hal/src/hal_timer.c 2017-09-28 12:05:22.000000000 -0700 -+++ samd21/hal/src/hal_timer.c 2017-09-19 13:07:29.000000000 -0700 -@@ -236,7 +236,10 @@ - */ - static void timer_process_counted(struct _timer_device *device) - { -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wcast-align" - struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); -+ #pragma GCC diagnostic pop - struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); - uint32_t time = ++timer->time; ---- a/hal/src/hal_flash.c -+++ b/hal/src/hal_flash.c -@@ -304,7 +304,10 @@ static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const ui - */ - static void flash_ready(struct _flash_device *device) - { -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wcast-align" - struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); -+ #pragma GCC diagnostic pop - if (descr->callbacks.cb_ready) { - descr->callbacks.cb_ready(descr); - } -@@ -317,7 +320,10 @@ static void flash_ready(struct _flash_device *device) - */ - static void flash_error(struct _flash_device *device) - { -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wcast-align" - struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); -+ #pragma GCC diagnostic pop - if (descr->callbacks.cb_error) { - descr->callbacks.cb_error(descr); - } diff --git a/atmel-samd/asf4/patches/samd21/cortex_sc.patch b/atmel-samd/asf4/patches/samd21/cortex_sc.patch deleted file mode 100644 index ed10e0573..000000000 --- a/atmel-samd/asf4/patches/samd21/cortex_sc.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- samd21_vanilla/CMSIS/Include/core_cmInstr.h 2017-09-28 12:05:22.000000000 -0700 -+++ samd21/CMSIS/Include/core_cmInstr.h 2017-09-19 13:07:29.000000000 -0700 -@@ -171,7 +171,7 @@ - #define __BKPT(value) __breakpoint(value) - - --#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) -+#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300) - - /** \brief Reverse bit order of value - -@@ -538,7 +538,7 @@ - #define __BKPT(value) __ASM volatile ("bkpt "#value) - - --#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) -+#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300) - - /** \brief Reverse bit order of value - diff --git a/atmel-samd/asf4/patches/samd21/flash-const.patch b/atmel-samd/asf4/patches/samd21/flash-const.patch deleted file mode 100644 index cac428ab3..000000000 --- a/atmel-samd/asf4/patches/samd21/flash-const.patch +++ /dev/null @@ -1,61 +0,0 @@ ---- a/hal/include/hal_flash.h -+++ b/hal/include/hal_flash.h -@@ -132,7 +132,7 @@ int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t * - * \param[in] length Number of bytes to append - * \return Append status. - */ --int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); -+int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - - /** \brief Reads a number of bytes to a page in the internal Flash - * ---- a/hal/include/hpl_flash.h -+++ b/hal/include/hpl_flash.h -@@ -125,7 +125,7 @@ void _flash_read(struct _flash_device *const device, const uint32_t src_addr, ui - * write is stored - * \param[in] length Number of bytes to write - */ --void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); -+void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - - /** - * \brief Appends a number of bytes in the internal Flash. -@@ -135,7 +135,7 @@ void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, u - * \param[in] buffer Pointer to buffer with data to write to flash - * \param[in] length Number of bytes to write - */ --void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); -+void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - - /** \brief Execute lock in the internal flash - * \param[in] device The pointer to FLASH device instance ---- a/hal/src/hal_flash.c -+++ b/hal/src/hal_flash.c -@@ -135,7 +135,7 @@ int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t * - /** - * \brief Appends a number of bytes to a page in the internal Flash - */ --int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) -+int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length) - { - ASSERT(flash && buffer && length); ---- a/hpl/nvmctrl/hpl_nvmctrl.c -+++ b/hpl/nvmctrl/hpl_nvmctrl.c -@@ -175,7 +175,7 @@ void _flash_read(struct _flash_device *const device, const uint32_t src_addr, ui - /** - * \brief Writes a number of bytes to a page in the internal Flash. - */ --void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) -+void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length) - { - uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE]; - uint32_t row_start_addr, row_end_addr; -@@ -219,7 +219,7 @@ void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, u - /** - * \brief Appends a number of bytes in the internal Flash. - */ --void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) -+void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length) - { - uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1); - uint32_t size; diff --git a/atmel-samd/asf4/patches/samd21/gclk_defined.patch b/atmel-samd/asf4/patches/samd21/gclk_defined.patch deleted file mode 100644 index 9a26609dd..000000000 --- a/atmel-samd/asf4/patches/samd21/gclk_defined.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- samd21_vanilla/hpl/gclk/hpl_gclk.c 2017-09-28 12:05:22.000000000 -0700 -+++ samd21/hpl/gclk/hpl_gclk.c 2017-09-19 13:07:29.000000000 -0700 -@@ -147,7 +147,7 @@ - | CONF_GCLK_GEN_7_SRC - | GCLK_GENCTRL_ID(7)); - #endif --#if CONF_GCLK_GEN_8_GENEN == 1 -+#if defined(CONF_GCLK_GEN_8_GENEN) && CONF_GCLK_GEN_8_GENEN == 1 - hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_8_DIV) | GCLK_GENDIV_ID(8)); - hri_gclk_write_GENCTRL_reg(GCLK, - (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) diff --git a/atmel-samd/asf4/patches/samd21/little_endian_redefined.patch b/atmel-samd/asf4/patches/samd21/little_endian_redefined.patch deleted file mode 100644 index 48b739350..000000000 --- a/atmel-samd/asf4/patches/samd21/little_endian_redefined.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- samd21_vanilla/include/samd21e18a.h 2017-09-28 12:05:22.000000000 -0700 -+++ samd21/include/samd21e18a.h 2017-09-19 13:07:30.000000000 -0700 -@@ -210,7 +210,7 @@ - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - --#define LITTLE_ENDIAN 1 -+// #define LITTLE_ENDIAN 1 - #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ - #define __MPU_PRESENT 0 /*!< MPU present or not */ - #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ ---- samd21_vanilla/include/samd21g18a.h 2017-09-28 12:05:22.000000000 -0700 -+++ samd21/include/samd21g18a.h 2017-09-19 13:07:30.000000000 -0700 -@@ -214,7 +214,7 @@ - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - --#define LITTLE_ENDIAN 1 -+//#define LITTLE_ENDIAN 1 - #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ - #define __MPU_PRESENT 0 /*!< MPU present or not */ - #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ diff --git a/atmel-samd/asf4/patches/samd21/make_usb_cache_accessible.patch b/atmel-samd/asf4/patches/samd21/make_usb_cache_accessible.patch deleted file mode 100644 index d80879160..000000000 --- a/atmel-samd/asf4/patches/samd21/make_usb_cache_accessible.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- samd21_vanilla/hpl/usb/hpl_usb.c 2017-09-28 12:05:22.000000000 -0700 -+++ samd21/hpl/usb/hpl_usb.c 2017-09-19 13:07:29.000000000 -0700 -@@ -300,7 +300,7 @@ - /** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ - #if CONF_USB_EP1_CACHE && CONF_USB_D_MAX_EP_N >= 1 --static uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; -+uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; - #else - #define _usb_ep1_cache NULL - #endif diff --git a/atmel-samd/asf4/patches/samd21/mark_used_no_c.patch b/atmel-samd/asf4/patches/samd21/mark_used_no_c.patch deleted file mode 100644 index 8949d6ff6..000000000 --- a/atmel-samd/asf4/patches/samd21/mark_used_no_c.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- samd21_vanilla/gcc/gcc/startup_samd21.c 2017-09-20 22:33:52.000000000 -0700 -+++ samd21/gcc/gcc/startup_samd21.c 2017-09-19 13:07:30.000000000 -0700 -@@ -104,7 +105,7 @@ - void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); - - /* Exception Table */ --__attribute__((section(".vectors"))) const DeviceVectors exception_table = { -+__attribute__((section(".vectors"), used)) const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void *)(&_estack), -@@ -234,7 +234,7 @@ - NVMCTRL->CTRLB.bit.MANW = 1; - - /* Initialize the C library */ -- __libc_init_array(); -+ //__libc_init_array(); - - /* Branch to main function */ - main(); diff --git a/atmel-samd/asf4/patches/samd21/sysctrl_fix.patch b/atmel-samd/asf4/patches/samd21/sysctrl_fix.patch deleted file mode 100644 index f271c21ad..000000000 --- a/atmel-samd/asf4/patches/samd21/sysctrl_fix.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- samd21_vanilla/hpl/sysctrl/hpl_sysctrl.c 2017-09-28 12:05:22.000000000 -0700 -+++ samd21/hpl/sysctrl/hpl_sysctrl.c 2017-09-19 13:07:29.000000000 -0700 -@@ -114,7 +114,7 @@ - - #if CONF_OSCULP32K_CONFIG == 1 - hri_sysctrl_write_OSCULP32K_reg(hw, --#if OSC32K_OVERWRITE_CALIBRATION == 1 -+#if CONF_OSC32K_OVERWRITE_CALIBRATION == 1 - SYSCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) | - #else - SYSCTRL_OSCULP32K_CALIB(calib) | diff --git a/atmel-samd/asf4/patches/samd21/usb_undefined.patch b/atmel-samd/asf4/patches/samd21/usb_undefined.patch deleted file mode 100644 index ec677cb70..000000000 --- a/atmel-samd/asf4/patches/samd21/usb_undefined.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- samd21_vanilla/usb/device/usbdc.c 2017-09-28 12:05:22.000000000 -0700 -+++ samd21/usb/device/usbdc.c 2017-09-19 13:07:30.000000000 -0700 -@@ -739,7 +737,7 @@ - */ - int32_t usbdc_check_desces(struct usbdc_descriptors *desces) - { --#if CONF_USBD_HS_SP -+#ifdef CONF_USBD_HS_SP - int32_t rc; - if (desces->hs == NULL && desces->ls_fs == NULL) { - return ERR_NOT_FOUND; ---- samd21_vanilla/usb/device/usbdc.h 2017-09-28 12:05:22.000000000 -0700 -+++ samd21/usb/device/usbdc.h 2017-09-19 13:07:30.000000000 -0700 -@@ -105,7 +105,7 @@ - /** Describes the USB device core descriptors. */ - struct usbdc_descriptors { - struct usbd_descriptors *ls_fs; --#if CONF_USBD_HS_SP -+#ifdef CONF_USBD_HS_SP - struct usbd_descriptors *hs; - #endif - }; diff --git a/atmel-samd/asf4/patches/samd51/array-bounds.patch b/atmel-samd/asf4/patches/samd51/array-bounds.patch deleted file mode 100644 index 30f40cb79..000000000 --- a/atmel-samd/asf4/patches/samd51/array-bounds.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/CMSIS/Include/core_cm4.h -+++ b/CMSIS/Include/core_cm4.h -@@ -1493,8 +1493,12 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) - */ - __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) - { -+ -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Warray-bounds" - /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -+ #pragma GCC diagnostic pop - } diff --git a/atmel-samd/asf4/patches/samd51/assert_redefined.patch b/atmel-samd/asf4/patches/samd51/assert_redefined.patch deleted file mode 100644 index 58a2e6207..000000000 --- a/atmel-samd/asf4/patches/samd51/assert_redefined.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- samd51_vanilla/hal/utils/include/utils_assert.h 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/hal/utils/include/utils_assert.h 2017-09-19 13:07:30.000000000 -0700 -@@ -72,7 +72,7 @@ - if (!(condition)) \ - __asm("BKPT #0"); - #else --#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) -+#define ASSERT_IMPL(condition, file, line) asf_assert((condition), file, line) - #endif - - #else /* DEBUG */ -@@ -95,7 +95,7 @@ - * \param[in] file File name - * \param[in] line Line number - */ --void assert(const bool condition, const char *const file, const int line); -+void asf_assert(const bool condition, const char *const file, const int line); - - #ifdef __cplusplus - } diff --git a/atmel-samd/asf4/patches/samd51/cast-align.patch b/atmel-samd/asf4/patches/samd51/cast-align.patch deleted file mode 100644 index 399c1ff80..000000000 --- a/atmel-samd/asf4/patches/samd51/cast-align.patch +++ /dev/null @@ -1,49 +0,0 @@ ---- samd51_vanilla/hal/src/hal_timer.c 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/hal/src/hal_timer.c 2017-09-19 13:07:30.000000000 -0700 -@@ -236,7 +236,10 @@ - */ - static void timer_process_counted(struct _timer_device *device) - { -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wcast-align" - struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); -+ #pragma GCC diagnostic pop - struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); - uint32_t time = ++timer->time; - ---- a/hal/src/hal_flash.c -+++ b/hal/src/hal_flash.c -@@ -304,7 +304,10 @@ static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const ui - */ - static void flash_ready(struct _flash_device *device) - { -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wcast-align" - struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); -+ #pragma GCC diagnostic pop - if (descr->callbacks.cb_ready) { - descr->callbacks.cb_ready(descr); - } -@@ -317,7 +320,10 @@ static void flash_ready(struct _flash_device *device) - */ - static void flash_error(struct _flash_device *device) - { -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wcast-align" - struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); -+ #pragma GCC diagnostic pop - if (descr->callbacks.cb_error) { - descr->callbacks.cb_error(descr); - } ---- a/hpl/nvmctrl/hpl_nvmctrl.c -+++ b/hpl/nvmctrl/hpl_nvmctrl.c -@@ -386,7 +386,10 @@ static void _flash_erase_block(void *const hw, const uint32_t dst_addr) - */ - static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size) - { -+ #pragma GCC diagnostic push -+ #pragma GCC diagnostic ignored "-Wcast-align" - uint32_t *ptr_read = (uint32_t *)buffer; -+ #pragma GCC diagnostic pop - uint32_t nvm_address = dst_addr / 4; - uint16_t i; diff --git a/atmel-samd/asf4/patches/samd51/flash-const.patch b/atmel-samd/asf4/patches/samd51/flash-const.patch deleted file mode 100644 index 087581ff0..000000000 --- a/atmel-samd/asf4/patches/samd51/flash-const.patch +++ /dev/null @@ -1,63 +0,0 @@ ---- a/hal/include/hal_flash.h -+++ b/hal/include/hal_flash.h -@@ -132,7 +132,7 @@ int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t * - * \param[in] length Number of bytes to append - * \return Append status. - */ --int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); -+int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - - /** \brief Reads a number of bytes to a page in the internal Flash - * ---- a/hal/include/hpl_flash.h -+++ b/hal/include/hpl_flash.h -@@ -125,7 +125,7 @@ void _flash_read(struct _flash_device *const device, const uint32_t src_addr, ui - * write is stored - * \param[in] length Number of bytes to write - */ --void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); -+void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - - /** - * \brief Appends a number of bytes in the internal Flash. -@@ -135,7 +135,7 @@ void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, u - * \param[in] buffer Pointer to buffer with data to write to flash - * \param[in] length Number of bytes to write - */ --void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length); -+void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - - /** \brief Execute lock in the internal flash - * \param[in] device The pointer to FLASH device instance - ---- a/hal/src/hal_flash.c -+++ b/hal/src/hal_flash.c -@@ -135,7 +135,7 @@ int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t * - /** - * \brief Appends a number of bytes to a page in the internal Flash - */ --int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) -+int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length) - { - ASSERT(flash && buffer && length); - ---- a/hpl/nvmctrl/hpl_nvmctrl.c -+++ b/hpl/nvmctrl/hpl_nvmctrl.c -@@ -167,7 +167,7 @@ void _flash_read(struct _flash_device *const device, const uint32_t src_addr, ui - /** - * \brief Writes a number of bytes to a page in the internal Flash. - */ --void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) -+void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length) - { - uint8_t tmp_buffer[NVMCTRL_BLOCK_PAGES][NVMCTRL_PAGE_SIZE]; - uint32_t block_start_addr, block_end_addr; -@@ -212,7 +212,7 @@ void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, u - /** - * \brief Appends a number of bytes in the internal Flash. - */ --void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, uint8_t *buffer, uint32_t length) -+void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length) - { - uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1); - uint32_t size; diff --git a/atmel-samd/asf4/patches/samd51/little_endian_redefined.patch b/atmel-samd/asf4/patches/samd51/little_endian_redefined.patch deleted file mode 100644 index 0fb55caea..000000000 --- a/atmel-samd/asf4/patches/samd51/little_endian_redefined.patch +++ /dev/null @@ -1,99 +0,0 @@ ---- samd51_vanilla/include/samd51g18a.h 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/include/samd51g18a.h 2017-09-19 13:07:30.000000000 -0700 -@@ -511,7 +512,7 @@ - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - --#define LITTLE_ENDIAN 1 -+//#define LITTLE_ENDIAN 1 - #define __CM4_REV 1 /*!< Core revision r0p1 */ - #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ - #define __FPU_PRESENT 1 /*!< FPU present or not */ ---- samd51_vanilla/include/samd51g19a.h 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/include/samd51g19a.h 2017-09-19 13:07:30.000000000 -0700 -@@ -511,7 +512,7 @@ - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - --#define LITTLE_ENDIAN 1 -+//#define LITTLE_ENDIAN 1 - #define __CM4_REV 1 /*!< Core revision r0p1 */ - #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ - #define __FPU_PRESENT 1 /*!< FPU present or not */ ---- samd51_vanilla/include/samd51j18a.h 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/include/samd51j18a.h 2017-09-19 13:07:30.000000000 -0700 -@@ -529,7 +530,7 @@ - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - --#define LITTLE_ENDIAN 1 -+//#define LITTLE_ENDIAN 1 - #define __CM4_REV 1 /*!< Core revision r0p1 */ - #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ - #define __FPU_PRESENT 1 /*!< FPU present or not */ ---- samd51_vanilla/include/samd51j19a.h 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/include/samd51j19a.h 2017-09-19 13:07:30.000000000 -0700 -@@ -529,7 +530,7 @@ - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - --#define LITTLE_ENDIAN 1 -+//#define LITTLE_ENDIAN 1 - #define __CM4_REV 1 /*!< Core revision r0p1 */ - #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ - #define __FPU_PRESENT 1 /*!< FPU present or not */ ---- samd51_vanilla/include/samd51j20a.h 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/include/samd51j20a.h 2017-09-19 13:07:30.000000000 -0700 -@@ -529,7 +530,7 @@ - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - --#define LITTLE_ENDIAN 1 -+//#define LITTLE_ENDIAN 1 - #define __CM4_REV 1 /*!< Core revision r0p1 */ - #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ - #define __FPU_PRESENT 1 /*!< FPU present or not */ ---- samd51_vanilla/include/samd51n19a.h 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/include/samd51n19a.h 2017-09-19 13:07:30.000000000 -0700 -@@ -551,7 +552,7 @@ - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - --#define LITTLE_ENDIAN 1 -+//#define LITTLE_ENDIAN 1 - #define __CM4_REV 1 /*!< Core revision r0p1 */ - #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ - #define __FPU_PRESENT 1 /*!< FPU present or not */ ---- samd51_vanilla/include/samd51n20a.h 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/include/samd51n20a.h 2017-09-19 13:07:30.000000000 -0700 -@@ -551,7 +552,7 @@ - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - --#define LITTLE_ENDIAN 1 -+//#define LITTLE_ENDIAN 1 - #define __CM4_REV 1 /*!< Core revision r0p1 */ - #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ - #define __FPU_PRESENT 1 /*!< FPU present or not */ ---- samd51_vanilla/include/samd51p19a.h 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/include/samd51p19a.h 2017-09-19 13:07:30.000000000 -0700 -@@ -551,7 +552,7 @@ - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - --#define LITTLE_ENDIAN 1 -+//#define LITTLE_ENDIAN 1 - #define __CM4_REV 1 /*!< Core revision r0p1 */ - #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ - #define __FPU_PRESENT 1 /*!< FPU present or not */ ---- samd51_vanilla/include/samd51p20a.h 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/include/samd51p20a.h 2017-09-19 13:07:30.000000000 -0700 -@@ -551,7 +552,7 @@ - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - --#define LITTLE_ENDIAN 1 -+//#define LITTLE_ENDIAN 1 - #define __CM4_REV 1 /*!< Core revision r0p1 */ - #define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ - #define __FPU_PRESENT 1 /*!< FPU present or not */ diff --git a/atmel-samd/asf4/patches/samd51/make_usb_cache_accessible.patch b/atmel-samd/asf4/patches/samd51/make_usb_cache_accessible.patch deleted file mode 100644 index f287c7c01..000000000 --- a/atmel-samd/asf4/patches/samd51/make_usb_cache_accessible.patch +++ /dev/null @@ -1,19 +0,0 @@ ---- samd51_vanilla/hpl/usb/hpl_usb.c 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/hpl/usb/hpl_usb.c 2017-09-19 13:07:30.000000000 -0700 -@@ -299,14 +299,14 @@ - /** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ - #if CONF_USB_EP1_CACHE && CONF_USB_D_MAX_EP_N >= 1 --static uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; -+uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; - #else - #define _usb_ep1_cache NULL - #endif - - /** Endpoint cache buffer for IN transactions (none-control). */ - #if CONF_USB_EP1_I_CACHE && CONF_USB_D_MAX_EP_N >= 1 --static uint32_t _usb_ep1_i_cache[_usb_align_up(CONF_USB_EP1_I_CACHE) / 4]; -+uint32_t _usb_ep1_i_cache[_usb_align_up(CONF_USB_EP1_I_CACHE) / 4]; - #else - #define _usb_ep1_i_cache NULL - #endif diff --git a/atmel-samd/asf4/patches/samd51/mark_used_no_c.patch b/atmel-samd/asf4/patches/samd51/mark_used_no_c.patch deleted file mode 100644 index 3380db976..000000000 --- a/atmel-samd/asf4/patches/samd51/mark_used_no_c.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- samd51_vanilla/gcc/gcc/startup_samd51.c 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/gcc/gcc/startup_samd51.c 2017-09-19 13:07:30.000000000 -0700 -@@ -314,7 +315,7 @@ - #endif - - /* Exception Table */ --__attribute__((section(".vectors"))) const DeviceVectors exception_table -+__attribute__((section(".vectors"), used)) const DeviceVectors exception_table - = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ -@@ -660,7 +661,7 @@ - #endif - - /* Initialize the C library */ -- __libc_init_array(); -+ //__libc_init_array(); - - /* Branch to main function */ - main(); diff --git a/atmel-samd/asf4/patches/samd51/usb_undefined.patch b/atmel-samd/asf4/patches/samd51/usb_undefined.patch deleted file mode 100644 index 0ca9182ca..000000000 --- a/atmel-samd/asf4/patches/samd51/usb_undefined.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- samd51_vanilla/usb/device/usbdc.c 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/usb/device/usbdc.c 2017-09-19 13:07:30.000000000 -0700 -@@ -739,7 +741,7 @@ - */ - int32_t usbdc_check_desces(struct usbdc_descriptors *desces) - { --#if CONF_USBD_HS_SP -+#ifdef CONF_USBD_HS_SP - int32_t rc; - if (desces->hs == NULL && desces->ls_fs == NULL) { - return ERR_NOT_FOUND; ---- samd51_vanilla/usb/device/usbdc.h 2017-09-20 22:33:52.000000000 -0700 -+++ samd51/usb/device/usbdc.h 2017-09-19 13:07:30.000000000 -0700 -@@ -105,7 +105,7 @@ - /** Describes the USB device core descriptors. */ - struct usbdc_descriptors { - struct usbd_descriptors *ls_fs; --#if CONF_USBD_HS_SP -+#ifdef CONF_USBD_HS_SP - struct usbd_descriptors *hs; - #endif - }; diff --git a/atmel-samd/asf4/samd21/CMSIS/Documentation/Core/html/index.html b/atmel-samd/asf4/samd21/CMSIS/Documentation/Core/html/index.html deleted file mode 100644 index 3e7503ea9..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Documentation/Core/html/index.html +++ /dev/null @@ -1,241 +0,0 @@ - - - - - -CMSIS-CORE: Overview - - - - - - - - - - - - - - -
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- - - - - - - -
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CMSIS-CORE -  Version 4.00 -
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CMSIS-CORE support for Cortex-M processor-based devices
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Overview
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CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

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  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
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  • System exception names to interface to system exceptions without having compatibility issues.
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  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
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  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
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  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
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  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • -
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This chapter provides details about the CMSIS-CORE and contains the following sections:

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CMSIS-CORE in ARM::CMSIS Pack

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Files relevant to CMSIS-CORE are present in the following ARM::CMSIS directories:

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File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Include CMSIS-CORE header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device ARM reference implementations of Cortex-M devices
Device\_Template_Vendor Template Files for extension by silicon vendors
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-Cortex-M Reference Manuals

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The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.

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Todo:
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-Tested and Verified Toolchains

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The CMSIS-CORE Template Files supplied by ARM have been tested and verified with the following toolchains:

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  • ARM: MDK-ARM Version 5.12
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  • GNU: GNU Tools ARM Embedded 4.8 2014.q3
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  • IAR: IAR Embedded Workbench Kickstart Edition V6.10
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Revision History of CMSIS-CORE

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Version Description
V4.00 Added: Cortex-M7 support.
- Added: intrinsic functions for __RRX, __LDRBT, __LDRHT, __LDRT, __STRBT, __STRHT, and __STRT
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V3.40 Corrected: C++ include guard settings.
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V3.30 Added: COSMIC tool chain support.
- Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.
- Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.
- Corrected: GCC/CLang warnings.
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V3.20 Added: __BKPT instruction intrinsic.
- Added: __SMMLA instruction intrinsic for Cortex-M4.
- Corrected: ITM_SendChar.
- Corrected: __enable_irq, __disable_irq and inline assembly for GCC Compiler.
- Corrected: NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000. Corrected: rework of in-line assembly functions to remove potential compiler warnings.
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V3.01 Added support for Cortex-M0+ processor.
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V3.00 Added support for GNU GCC ARM Embedded Compiler.
- Added function __ROR.
- Added Register Mapping for TPIU, DWT.
- Added support for SC000 and SC300 processors.
- Corrected ITM_SendChar function.
- Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section.
- Documentation restructured.
V2.10 Updated documentation.
- Updated CMSIS core include files.
- Changed CMSIS/Device folder structure.
- Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.
- Reworked CMSIS DSP library examples.
V2.00 Added support for Cortex-M4 processor.
V1.30 Reworked Startup Concept.
- Added additional Debug Functionality.
- Changed folder structure.
- Added doxygen comments.
- Added definitions for bit.
V1.01 Added support for Cortex-M0 processor.
V1.01 Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX
V1.00 Initial Release for Cortex-M3 processor.
-
-
- - - - diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/arm_common_tables.h b/atmel-samd/asf4/samd21/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 76aadca49..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 31. July 2014 -* $Revision: V1.4.4 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -//extern const q31_t realCoefAQ31[1024]; -//extern const q31_t realCoefBQ31[1024]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/arm_const_structs.h b/atmel-samd/asf4/samd21/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 217f1d50e..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 31. July 2014 -* $Revision: V1.4.4 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/arm_math.h b/atmel-samd/asf4/samd21/CMSIS/Include/arm_math.h deleted file mode 100644 index 49e23ee66..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7544 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 12. March 2014 -* $Revision: V1.4.4 -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 4.60. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvproj - * - * - * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2014 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY - #elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __ICCARM__ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t __packed -#elif defined __GNUC__ -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __CSMC__ /* Cosmic */ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t -#else -#error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) - -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) - -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ( - q31_t data); - - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + - ((q15_t) x * (q15_t) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } - - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); - -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in > 0) - { - -// #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - -//SMMLAR -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMLSR -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMULR -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -//SMMLA -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -//SMMLS -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) //Keil - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) //IAR - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - - #define LOW_OPTIMIZATION_EXIT - - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) // Cosmic - -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_cm0.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cm0.h deleted file mode 100644 index 5186cb483..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,711 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_cm0plus.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index 17e43984f..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,822 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_cm3.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cm3.h deleted file mode 100644 index e1357c673..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1650 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_cm4.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cm4.h deleted file mode 100644 index bb6be1305..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1802 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_cm7.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cm7.h deleted file mode 100644 index 242540f8b..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2221 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 01. September 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000 - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0 - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0 - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0 - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x07) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x07) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1]; - __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93]; - __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15]; - __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1]; - __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1]; - __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6]; - __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1]; - __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/* Cache Level ID register */ -#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* Cache Type register */ -#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ - -/* Cache Size ID Register */ -#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ - -/* Cache Size Selection Register */ -#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register */ -#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ - -/* Instruction Tightly-Coupled Memory Control Register*/ -#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Registers */ -#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register */ -#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register */ -#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ - -/* AHBS control register */ -#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register */ -#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## Cache functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) -#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) - - -/** \brief Enable I-Cache - - The function turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0; // invalidate I-Cache - SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache - __DSB(); - __ISB(); - #endif -} - - -/** \brief Disable I-Cache - - The function turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache - SCB->ICIALLU = 0; // invalidate I-Cache - __DSB(); - __ISB(); - #endif -} - - -/** \brief Invalidate I-Cache - - The function invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0; - __DSB(); - __ISB(); - #endif -} - - -/** \brief Enable D-Cache - - The function turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - __DSB(); - - SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Disable D-Cache - - The function turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache - - do { // clean & invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Invalidate D-Cache - - The function invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Clean D-Cache - - The function cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // clean D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCSW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Clean & Invalidate D-Cache - - The function cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // clean & invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_cmFunc.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 01089f133..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,637 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.00 - * @date 28. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_cmInstr.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index ab045fee8..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,880 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.00 - * @date 28. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) || (defined(__CORTEX_SC) && __CORTEX_SC >= 300) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_cmSimd.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_cmSimd.h deleted file mode 100644 index ee58eee56..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/core_cmSimd.h +++ /dev/null @@ -1,697 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* not yet supported */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_sc000.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_sc000.h deleted file mode 100644 index 5d0219c89..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,842 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000 - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1]; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154]; - __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/* SCB Security Features Register Definitions */ -#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ -#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ - -#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ -#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2]; - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd21/CMSIS/Include/core_sc300.h b/atmel-samd/asf4/samd21/CMSIS/Include/core_sc300.h deleted file mode 100644 index b6f6e8b5f..000000000 --- a/atmel-samd/asf4/samd21/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1630 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000 - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd21/armcc/Makefile b/atmel-samd/asf4/samd21/armcc/Makefile deleted file mode 100644 index 5c51dc09b..000000000 --- a/atmel-samd/asf4/samd21/armcc/Makefile +++ /dev/null @@ -1,273 +0,0 @@ - -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -ifdef SystemRoot - SHELL = cmd.exe - MK_DIR = mkdir -else - ifeq ($(shell uname), Linux) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW32) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW64) - MK_DIR = mkdir -p - endif -endif - -# List the subdirectories for creating object files -SUB_DIRS += \ - \ -hpl/adc \ -hal/src \ -samd21a/armcc/Device/SAMD21/Source/ARM \ -examples \ -hpl/systick \ -hpl/tc \ -usb \ -hpl/dmac \ -usb/class/cdc/device \ -hal/utils/src \ -hpl/rtc \ -usb/class/hid/device \ -hpl/usb \ -hpl/pm \ -hpl/sysctrl \ -hpl/gclk \ -usb/device \ -hpl/dac \ -samd21a/armcc/Device/SAMD21/Source \ -hpl/sercom \ -hpl/nvmctrl \ -hpl/core \ -usb/class/msc/device - -# List the object files -OBJS += \ -hal/src/hal_io.o \ -hpl/systick/hpl_systick.o \ -usb/usb_protocol.o \ -usb/class/hid/device/hiddf_generic.o \ -usb/class/cdc/device/cdcdf_acm.o \ -hpl/nvmctrl/hpl_nvmctrl.o \ -usb/class/msc/device/mscdf.o \ -hal/src/hal_spi_m_sync.o \ -hal/src/hal_timer.o \ -hal/src/hal_pwm.o \ -hpl/usb/hpl_usb.o \ -hal/src/hal_i2c_m_sync.o \ -hal/src/hal_delay.o \ -hpl/sysctrl/hpl_sysctrl.o \ -hpl/core/hpl_init.o \ -hal/utils/src/utils_list.o \ -hpl/core/hpl_core_m0plus_base.o \ -hal/utils/src/utils_assert.o \ -hpl/dmac/hpl_dmac.o \ -hpl/pm/hpl_pm.o \ -usb/class/hid/device/hiddf_keyboard.o \ -hal/src/hal_usart_sync.o \ -hpl/dac/hpl_dac.o \ -hpl/gclk/hpl_gclk.o \ -hal/src/hal_flash.o \ -hal/src/hal_init.o \ -samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.o \ -hal/src/hal_usb_device.o \ -main.o \ -hpl/rtc/hpl_rtc.o \ -examples/driver_examples.o \ -driver_init.o \ -samd21a/armcc/Device/SAMD21/Source/system_samd21.o \ -hal/src/hal_adc_sync.o \ -hal/src/hal_dac_sync.o \ -hpl/sercom/hpl_sercom.o \ -hal/src/hal_gpio.o \ -usb/class/hid/device/hiddf_mouse.o \ -hal/utils/src/utils_event.o \ -hal/src/hal_sleep.o \ -usb_start.o \ -atmel_start.o \ -usb/device/usbdc.o \ -hpl/tc/hpl_tc.o \ -hal/src/hal_atomic.o \ -hpl/adc/hpl_adc.o - -OBJS_AS_ARGS += \ -"hal/src/hal_io.o" \ -"hpl/systick/hpl_systick.o" \ -"usb/usb_protocol.o" \ -"usb/class/hid/device/hiddf_generic.o" \ -"usb/class/cdc/device/cdcdf_acm.o" \ -"hpl/nvmctrl/hpl_nvmctrl.o" \ -"usb/class/msc/device/mscdf.o" \ -"hal/src/hal_spi_m_sync.o" \ -"hal/src/hal_timer.o" \ -"hal/src/hal_pwm.o" \ -"hpl/usb/hpl_usb.o" \ -"hal/src/hal_i2c_m_sync.o" \ -"hal/src/hal_delay.o" \ -"hpl/sysctrl/hpl_sysctrl.o" \ -"hpl/core/hpl_init.o" \ -"hal/utils/src/utils_list.o" \ -"hpl/core/hpl_core_m0plus_base.o" \ -"hal/utils/src/utils_assert.o" \ -"hpl/dmac/hpl_dmac.o" \ -"hpl/pm/hpl_pm.o" \ -"usb/class/hid/device/hiddf_keyboard.o" \ -"hal/src/hal_usart_sync.o" \ -"hpl/dac/hpl_dac.o" \ -"hpl/gclk/hpl_gclk.o" \ -"hal/src/hal_flash.o" \ -"hal/src/hal_init.o" \ -"samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.o" \ -"hal/src/hal_usb_device.o" \ -"main.o" \ -"hpl/rtc/hpl_rtc.o" \ -"examples/driver_examples.o" \ -"driver_init.o" \ -"samd21a/armcc/Device/SAMD21/Source/system_samd21.o" \ -"hal/src/hal_adc_sync.o" \ -"hal/src/hal_dac_sync.o" \ -"hpl/sercom/hpl_sercom.o" \ -"hal/src/hal_gpio.o" \ -"usb/class/hid/device/hiddf_mouse.o" \ -"hal/utils/src/utils_event.o" \ -"hal/src/hal_sleep.o" \ -"usb_start.o" \ -"atmel_start.o" \ -"usb/device/usbdc.o" \ -"hpl/tc/hpl_tc.o" \ -"hal/src/hal_atomic.o" \ -"hpl/adc/hpl_adc.o" - -# List the dependency files -DEPS := $(OBJS:%.o=%.d) - -DEPS_AS_ARGS += \ -"usb/usb_protocol.d" \ -"hal/utils/src/utils_event.d" \ -"hal/src/hal_io.d" \ -"hpl/systick/hpl_systick.d" \ -"usb/class/hid/device/hiddf_generic.d" \ -"usb/class/cdc/device/cdcdf_acm.d" \ -"usb/class/hid/device/hiddf_mouse.d" \ -"samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.d" \ -"hal/src/hal_i2c_m_sync.d" \ -"hpl/usb/hpl_usb.d" \ -"samd21a/armcc/Device/SAMD21/Source/system_samd21.d" \ -"usb/class/msc/device/mscdf.d" \ -"hpl/nvmctrl/hpl_nvmctrl.d" \ -"hal/src/hal_pwm.d" \ -"hal/src/hal_timer.d" \ -"hal/src/hal_spi_m_sync.d" \ -"hpl/core/hpl_core_m0plus_base.d" \ -"hal/utils/src/utils_list.d" \ -"hpl/dmac/hpl_dmac.d" \ -"hal/utils/src/utils_assert.d" \ -"hal/src/hal_delay.d" \ -"hpl/core/hpl_init.d" \ -"hpl/sysctrl/hpl_sysctrl.d" \ -"hal/src/hal_flash.d" \ -"hpl/gclk/hpl_gclk.d" \ -"hal/src/hal_usb_device.d" \ -"usb_start.d" \ -"hal/src/hal_init.d" \ -"hal/src/hal_usart_sync.d" \ -"usb/class/hid/device/hiddf_keyboard.d" \ -"hpl/dac/hpl_dac.d" \ -"driver_init.d" \ -"hal/src/hal_adc_sync.d" \ -"main.d" \ -"examples/driver_examples.d" \ -"hpl/rtc/hpl_rtc.d" \ -"hal/src/hal_sleep.d" \ -"hpl/sercom/hpl_sercom.d" \ -"hal/src/hal_dac_sync.d" \ -"hal/src/hal_gpio.d" \ -"hal/src/hal_atomic.d" \ -"hpl/tc/hpl_tc.d" \ -"usb/device/usbdc.d" \ -"hpl/pm/hpl_pm.d" \ -"hpl/adc/hpl_adc.d" \ -"atmel_start.d" - -OUTPUT_FILE_NAME :=AtmelStart -QUOTE := " -OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf -OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf - -vpath %.c ../ -vpath %.s ../ -vpath %.S ../ - -# All Target -all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) - -# Linker target - -$(OUTPUT_FILE_PATH): $(OBJS) - @echo Building target: $@ - @echo Invoking: ARMCC Linker - $(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \ ---strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \ ---info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \ --o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M0+ \ -$(OBJS_AS_ARGS) - - @echo Finished building target: $@ - -# Compiler target(s) - - - - -%.o: %.c - @echo Building file: $< - @echo ARMCC Compiler - $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMD21G18A__ \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ ---depend "$@" -o "$@" "$<" - - @echo Finished building: $< - -%.o: %.s - @echo Building file: $< - @echo ARMCC Assembler - $(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M0+ --pd "D__SAMD21G18A__ SETA 1" \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ ---depend "$(@:%.o=%.d)" -o "$@" "$<" - - @echo Finished building: $< - -%.o: %.S - @echo Building file: $< - @echo ARMCC Preprocessing Assembler - $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMD21G18A__ \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ ---depend "$@" -o "$@" "$<" - - @echo Finished building: $< - -# Detect changes in the dependent files and recompile the respective object files. -ifneq ($(MAKECMDGOALS),clean) -ifneq ($(strip $(DEPS)),) --include $(DEPS) -endif -endif - -$(SUB_DIRS): - $(MK_DIR) "$@" - -clean: - rm -f $(OBJS_AS_ARGS) - rm -f $(OUTPUT_FILE_PATH) - rm -f $(DEPS_AS_ARGS) - rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf diff --git a/atmel-samd/asf4/samd21/atmel_start.c b/atmel-samd/asf4/samd21/atmel_start.c deleted file mode 100644 index a075fcfa6..000000000 --- a/atmel-samd/asf4/samd21/atmel_start.c +++ /dev/null @@ -1,10 +0,0 @@ -#include - -/** - * Initializes MCU, drivers and middleware in the project -**/ -void atmel_start_init(void) -{ - system_init(); - usb_init(); -} diff --git a/atmel-samd/asf4/samd21/atmel_start.h b/atmel-samd/asf4/samd21/atmel_start.h deleted file mode 100644 index 71d54c217..000000000 --- a/atmel-samd/asf4/samd21/atmel_start.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef ATMEL_START_H_INCLUDED -#define ATMEL_START_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include "driver_init.h" -#include "usb_start.h" - -/** - * Initializes MCU, drivers and middleware in the project -**/ -void atmel_start_init(void); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/atmel-samd/asf4/samd21/atmel_start_config.atstart b/atmel-samd/asf4/samd21/atmel_start_config.atstart deleted file mode 100644 index 92e741938..000000000 --- a/atmel-samd/asf4/samd21/atmel_start_config.atstart +++ /dev/null @@ -1,1114 +0,0 @@ -format_version: '2' -name: My Project -board: - identifier: CustomBoard - device: SAMD21G18A-MF -details: null -application: null -middlewares: - USB_CHAPTER_9: - user_label: USB_CHAPTER_9 - configuration: {} - definition: Atmel:USB:0.0.1::USB_Chapter_9 - functionality: USB_Chapter_9 - api: USB:Protocol:Core - dependencies: {} - USB_CLASS_HUB: - user_label: USB_CLASS_HUB - configuration: {} - definition: Atmel:USB:0.0.1::USB_Class_HUB - functionality: USB_Class_HUB - api: USB:Protocol:HUB - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB_CLASS_HID: - user_label: USB_CLASS_HID - configuration: {} - definition: Atmel:USB:0.0.1::USB_Class_HID - functionality: USB_Class_HID - api: USB:Protocol:HID - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB_CLASS_CDC: - user_label: USB_CLASS_CDC - configuration: {} - definition: Atmel:USB:0.0.1::USB_Class_CDC - functionality: USB_Class_CDC - api: USB:Protocol:CDC - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB_CLASS_MSC: - user_label: USB_CLASS_MSC - configuration: {} - definition: Atmel:USB:0.0.1::USB_Class_MSC - functionality: USB_Class_Mass_Storage_(MSC) - api: USB:Protocol:MSC - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB_CLASS_VENDOR: - user_label: USB_CLASS_VENDOR - configuration: {} - definition: Atmel:USB:0.0.1::USB_Class_VENDOR - functionality: USB_Class_VENDOR - api: USB:Protocol:VENDOR - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB_DEVICE_STACK_CORE_INSTANCE: - user_label: USB_DEVICE_STACK_CORE_INSTANCE - configuration: {} - definition: Atmel:USB:0.0.1::USB_Device_Core - functionality: USB_Device_Core - api: USB:Device:Core - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB Device instance: USB_0 - USB_DEVICE_COMPOSITE_0: - user_label: USB_DEVICE_COMPOSITE_0 - configuration: - usb_composite_bcddevice: 256 - usb_composite_bcdusb: USB 2.0 version - usb_composite_bconfigval: 1 - usb_composite_bmattri: Bus power supply, not support for remote wakeup - usb_composite_bmaxpksz0: 64 bytes - usb_composite_bmaxpower: 50 - usb_composite_bnumconfig: 1 - usb_composite_cdc_acm_comm_int_maxpksz: 64 bytes - usb_composite_cdc_acm_data_buckout_maxpksz: 64 bytes - usb_composite_cdc_acm_data_builin_maxpksz: 64 bytes - usb_composite_cdc_acm_data_bulkin_epaddr: EndpointAddress = 0x81 - usb_composite_cdc_acm_data_bulkout_epaddr: EndpointAddress = 0x01 - usb_composite_cdc_acm_epaddr: EndpointAddress = 0x82 - usb_composite_cdc_acm_support: true - usb_composite_hid_generic_intin_epaddr: EndpointAddress = 0x85 - usb_composite_hid_generic_intin_maxpksz: 64 bytes - usb_composite_hid_generic_intout_epaddr: EndpointAddress = 0x03 - usb_composite_hid_generic_intout_maxpksz: 64 bytes - usb_composite_hid_generic_support: false - usb_composite_hid_keyboard_intin_epaddr: EndpointAddress = 0x84 - usb_composite_hid_keyboard_intin_maxpksz: 8 bytes - usb_composite_hid_keyboard_intout_epaddr: EndpointAddress = 0x02 - usb_composite_hid_keyboard_intout_maxpksz: 8 bytes - usb_composite_hid_keyboard_support: false - usb_composite_hid_mouse_intin_epaddr: EndpointAddress = 0x83 - usb_composite_hid_mouse_intin_maxpksz: 8 bytes - usb_composite_hid_mouse_support: false - usb_composite_iconfig: 0 - usb_composite_idproduct: 9249 - usb_composite_idvender: 1003 - usb_composite_imanufact: 0 - usb_composite_iproduct: 0 - usb_composite_iserialnum: 0 - definition: Atmel:USB:0.0.1::USB_Device_Composite - functionality: USB_Device_COMPOSITE - api: USB:Device:COMPOSITE - dependencies: - USB Class MSC: USB_CLASS_MSC - USB Class CDC: USB_CLASS_CDC - USB Device Stack Core Instance: USB_DEVICE_STACK_CORE_INSTANCE - USB Class VENDOR: USB_CLASS_VENDOR - USB Class HID: USB_CLASS_HID - USB Class HUB: USB_CLASS_HUB -drivers: - ADC_0: - user_label: ADC_0 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::ADC::driver_config_definition::ADC::HAL:Driver:ADC.Sync - functionality: ADC - api: HAL:Driver:ADC_Sync - configuration: - adc_advanced_settings: false - adc_arch_adjres: 0 - adc_arch_corren: false - adc_arch_dbgrun: false - adc_arch_event_settings: false - adc_arch_gain: 1x - adc_arch_gaincorr: 0 - adc_arch_inputoffset: 0 - adc_arch_inputscan: 0 - adc_arch_leftadj: false - adc_arch_offsetcorr: 0 - adc_arch_refcomp: false - adc_arch_resrdyeo: false - adc_arch_runstdby: false - adc_arch_samplen: 0 - adc_arch_samplenum: 1 sample - adc_arch_startei: false - adc_arch_syncei: false - adc_arch_winlt: 0 - adc_arch_winmode: No window mode - adc_arch_winmoneo: false - adc_arch_winut: 0 - adc_differential_mode: false - adc_freerunning_mode: false - adc_pinmux_negative: ADC AIN0 pin - adc_pinmux_positive: ADC AIN0 pin - adc_prescaler: Peripheral clock divided by 4 - adc_reference: 1.0V voltage reference - adc_resolution: 12-bit - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: ADC - input: Generic clock generator 0 - configuration: - adc_gclk_selection: Generic clock generator 0 - GCLK: - user_label: GCLK - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK - functionality: System - api: HAL:HPL:GCLK - configuration: - enable_gclk_gen_0: true - enable_gclk_gen_1: false - enable_gclk_gen_2: false - enable_gclk_gen_3: false - enable_gclk_gen_4: false - enable_gclk_gen_5: false - enable_gclk_gen_6: false - enable_gclk_gen_7: false - gclk_arch_gen_0_RUNSTDBY: false - gclk_arch_gen_0_enable: true - gclk_arch_gen_0_idc: false - gclk_arch_gen_0_oe: false - gclk_arch_gen_0_oov: false - gclk_arch_gen_1_RUNSTDBY: false - gclk_arch_gen_1_enable: false - gclk_arch_gen_1_idc: false - gclk_arch_gen_1_oe: false - gclk_arch_gen_1_oov: false - gclk_arch_gen_2_RUNSTDBY: false - gclk_arch_gen_2_enable: false - gclk_arch_gen_2_idc: false - gclk_arch_gen_2_oe: false - gclk_arch_gen_2_oov: false - gclk_arch_gen_3_RUNSTDBY: false - gclk_arch_gen_3_enable: false - gclk_arch_gen_3_idc: false - gclk_arch_gen_3_oe: false - gclk_arch_gen_3_oov: false - gclk_arch_gen_4_RUNSTDBY: false - gclk_arch_gen_4_enable: false - gclk_arch_gen_4_idc: false - gclk_arch_gen_4_oe: false - gclk_arch_gen_4_oov: false - gclk_arch_gen_5_RUNSTDBY: false - gclk_arch_gen_5_enable: false - gclk_arch_gen_5_idc: false - gclk_arch_gen_5_oe: false - gclk_arch_gen_5_oov: false - gclk_arch_gen_6_RUNSTDBY: false - gclk_arch_gen_6_enable: false - gclk_arch_gen_6_idc: false - gclk_arch_gen_6_oe: false - gclk_arch_gen_6_oov: false - gclk_arch_gen_7_RUNSTDBY: false - gclk_arch_gen_7_enable: false - gclk_arch_gen_7_idc: false - gclk_arch_gen_7_oe: false - gclk_arch_gen_7_oov: false - gclk_gen_0_div: 1 - gclk_gen_0_div_sel: false - gclk_gen_0_oscillator: 8MHz Internal Oscillator (OSC8M) - gclk_gen_1_div: 1 - gclk_gen_1_div_sel: false - gclk_gen_1_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) - gclk_gen_2_div: 1 - gclk_gen_2_div_sel: false - gclk_gen_2_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) - gclk_gen_3_div: 1 - gclk_gen_3_div_sel: false - gclk_gen_3_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) - gclk_gen_4_div: 1 - gclk_gen_4_div_sel: false - gclk_gen_4_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) - gclk_gen_5_div: 1 - gclk_gen_5_div_sel: false - gclk_gen_5_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) - gclk_gen_6_div: 1 - gclk_gen_6_div_sel: false - gclk_gen_6_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) - gclk_gen_7_div: 1 - gclk_gen_7_div_sel: false - gclk_gen_7_oscillator: External Crystal Oscillator 0.4-32MHz (XOSC) - optional_signals: [] - variant: null - clocks: - domain_group: null - FLASH_0: - user_label: FLASH_0 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::NVMCTRL::driver_config_definition::Flash::HAL:Driver:FLASH - functionality: Flash - api: HAL:Driver:FLASH - configuration: - nvm_arch_cache: false - nvm_arch_read_mode: No Miss Penalty - nvm_arch_sleepprm: Wake On Access - optional_signals: [] - variant: null - clocks: - domain_group: null - PM: - user_label: PM - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::PM::driver_config_definition::PM::HAL:HPL:PM - functionality: System - api: HAL:HPL:PM - configuration: - apba_div: '1' - apbb_div: '1' - apbc_div: '1' - cpu_clock_source: Generic clock generator 0 - cpu_div: '1' - enable_cpu_clock: true - nvm_wait_states: '0' - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: CPU - input: CPU - configuration: {} - SPI_0: - user_label: SPI_0 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::SERCOM0::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync - functionality: SPI - api: HAL:Driver:SPI_Master_Sync - configuration: - spi_master_advanced: false - spi_master_arch_cpha: Sample input on leading edge - spi_master_arch_cpol: SCK is low when idle - spi_master_arch_dbgstop: Keep running - spi_master_arch_dord: MSB first - spi_master_arch_ibon: In data stream - spi_master_arch_runstdby: false - spi_master_baud_rate: 50000 - spi_master_character_size: 8 bits - spi_master_dummybyte: 511 - spi_master_rx_enable: true - optional_signals: [] - variant: - specification: TXPO=0, RXPO=2 - required_signals: - - name: SERCOM0/PAD/0 - pad: PA04 - label: MOSI - - name: SERCOM0/PAD/1 - pad: PA05 - label: SCK - - name: SERCOM0/PAD/2 - pad: PA06 - label: MISO - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - - name: Slow - input: Generic clock generator 3 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 - I2C_0: - user_label: I2C_0 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::SERCOM1::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync - functionality: I2C - api: HAL:Driver:I2C_Master_Sync - configuration: - i2c_master_advanced: false - i2c_master_arch_dbgstop: Keep running - i2c_master_arch_inactout: Disabled - i2c_master_arch_lowtout: false - i2c_master_arch_mexttoen: false - i2c_master_arch_runstdby: false - i2c_master_arch_sdahold: 300-600ns hold time - i2c_master_arch_sexttoen: false - i2c_master_arch_trise: 215 - i2c_master_baud_rate: 100000 - optional_signals: [] - variant: - specification: SDA=0, SCL=1 - required_signals: - - name: SERCOM1/PAD/0 - pad: PA16 - label: SDA - - name: SERCOM1/PAD/1 - pad: PA17 - label: SCL - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - - name: Slow - input: Generic clock generator 3 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 - USART_0: - user_label: USART_0 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Sync - functionality: USART - api: HAL:Driver:USART_Sync - configuration: - usart_advanced: false - usart_arch_clock_mode: USART with internal clock - usart_arch_cloden: false - usart_arch_dbgstop: Keep running - usart_arch_dord: LSB is transmitted first - usart_arch_enc: No encoding - usart_arch_fractional: 0 - usart_arch_ibon: false - usart_arch_runstdby: false - usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) - usart_arch_sampr: 16x arithmetic - usart_arch_sfde: false - usart_baud_rate: 9600 - usart_character_size: 8 bits - usart_parity: No parity - usart_rx_enable: true - usart_stop_bit: One stop bit - usart_tx_enable: true - optional_signals: [] - variant: - specification: TXPO=0, RXPO=1, CMODE=0 - required_signals: - - name: SERCOM2/PAD/0 - pad: PA08 - label: TX - - name: SERCOM2/PAD/1 - pad: PA09 - label: RX - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - - name: Slow - input: Generic clock generator 3 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 - DELAY_0: - user_label: DELAY_0 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::SysTick::driver_config_definition::Delay::HAL:Driver:Delay - functionality: Delay - api: HAL:Driver:Delay - configuration: - systick_arch_tickint: false - optional_signals: [] - variant: null - clocks: - domain_group: null - TIMER_0: - user_label: TIMER_0 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::RTC::driver_config_definition::Timer::HAL:Driver:Timer - functionality: Timer - api: HAL:Driver:Timer - configuration: - rtc_arch_comp_val: 1024 - rtc_arch_prescaler: Peripheral clock divided by 1 - rtc_cmpeo0: false - rtc_event_control: false - rtc_ovfeo: false - rtc_pereo0: false - rtc_pereo1: false - rtc_pereo2: false - rtc_pereo3: false - rtc_pereo4: false - rtc_pereo5: false - rtc_pereo6: false - rtc_pereo7: false - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: RTC - input: Generic clock generator 0 - configuration: - rtc_clk_selection: Generic clock generator 0 - PWM_0: - user_label: PWM_0 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::TC3::driver_config_definition::PWM::HAL:Driver:PWM - functionality: PWM - api: HAL:Driver:PWM - configuration: - tc_arch_dbgrun: false - tc_arch_evact: Event action disabled - tc_arch_mceo0: false - tc_arch_mceo1: false - tc_arch_mode: Counter in 16-bit mode - tc_arch_ovfeo: false - tc_arch_presync: Reload or reset counter on next GCLK - tc_arch_runstdby: false - tc_arch_tcei: false - tc_arch_tceinv: false - tc_arch_wave_duty_val: 500 - tc_arch_wave_per_val: 1000 - tc_per: 50 - tc_prescaler: Divide by 8 - timer_event_control: false - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: TC - input: Generic clock generator 0 - configuration: - tc_gclk_selection: Generic clock generator 0 - DAC_0: - user_label: DAC_0 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::DAC::driver_config_definition::DAC::HAL:Driver:DAC.Sync - functionality: DAC - api: HAL:Driver:DAC_Sync - configuration: - dac_advanced_settings: false - dac_arch_bdwp: false - dac_arch_emptyeo: false - dac_arch_eoen: true - dac_arch_ioen: false - dac_arch_leftadj: false - dac_arch_refsel: Internal 1.0v reference - dac_arch_runstdby: false - dac_arch_startei: false - dac_arch_vpd: false - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: DAC - input: Generic clock generator 0 - configuration: - dac_gclk_selection: Generic clock generator 0 - DMAC: - user_label: DMAC - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC - functionality: System - api: HAL:HPL:DMAC - configuration: - dmac_beatsize_0: 8-bit bus transfer - dmac_beatsize_1: 8-bit bus transfer - dmac_beatsize_10: 8-bit bus transfer - dmac_beatsize_11: 8-bit bus transfer - dmac_beatsize_12: 8-bit bus transfer - dmac_beatsize_13: 8-bit bus transfer - dmac_beatsize_14: 8-bit bus transfer - dmac_beatsize_15: 8-bit bus transfer - dmac_beatsize_2: 8-bit bus transfer - dmac_beatsize_3: 8-bit bus transfer - dmac_beatsize_4: 8-bit bus transfer - dmac_beatsize_5: 8-bit bus transfer - dmac_beatsize_6: 8-bit bus transfer - dmac_beatsize_7: 8-bit bus transfer - dmac_beatsize_8: 8-bit bus transfer - dmac_beatsize_9: 8-bit bus transfer - dmac_blockact_0: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_1: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_10: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_11: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_12: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_13: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_14: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_15: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_2: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_3: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_4: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_5: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_6: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_7: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_8: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_9: Channel will be disabled if it is the last block transfer in - the transaction - dmac_channel_0_settings: false - dmac_channel_10_settings: false - dmac_channel_11_settings: false - dmac_channel_12_settings: false - dmac_channel_13_settings: false - dmac_channel_14_settings: false - dmac_channel_15_settings: false - dmac_channel_1_settings: false - dmac_channel_2_settings: false - dmac_channel_3_settings: false - dmac_channel_4_settings: false - dmac_channel_5_settings: false - dmac_channel_6_settings: false - dmac_channel_7_settings: false - dmac_channel_8_settings: false - dmac_channel_9_settings: false - dmac_dbgrun: false - dmac_dstinc_0: false - dmac_dstinc_1: false - dmac_dstinc_10: false - dmac_dstinc_11: false - dmac_dstinc_12: false - dmac_dstinc_13: false - dmac_dstinc_14: false - dmac_dstinc_15: false - dmac_dstinc_2: false - dmac_dstinc_3: false - dmac_dstinc_4: false - dmac_dstinc_5: false - dmac_dstinc_6: false - dmac_dstinc_7: false - dmac_dstinc_8: false - dmac_dstinc_9: false - dmac_enable: false - dmac_enable_0: false - dmac_enable_1: false - dmac_enable_10: false - dmac_enable_11: false - dmac_enable_12: false - dmac_enable_13: false - dmac_enable_14: false - dmac_enable_15: false - dmac_enable_2: false - dmac_enable_3: false - dmac_enable_4: false - dmac_enable_5: false - dmac_enable_6: false - dmac_enable_7: false - dmac_enable_8: false - dmac_enable_9: false - dmac_evact_0: No action - dmac_evact_1: No action - dmac_evact_10: No action - dmac_evact_11: No action - dmac_evact_12: No action - dmac_evact_13: No action - dmac_evact_14: No action - dmac_evact_15: No action - dmac_evact_2: No action - dmac_evact_3: No action - dmac_evact_4: No action - dmac_evact_5: No action - dmac_evact_6: No action - dmac_evact_7: No action - dmac_evact_8: No action - dmac_evact_9: No action - dmac_evie_0: false - dmac_evie_1: false - dmac_evie_10: false - dmac_evie_11: false - dmac_evie_12: false - dmac_evie_13: false - dmac_evie_14: false - dmac_evie_15: false - dmac_evie_2: false - dmac_evie_3: false - dmac_evie_4: false - dmac_evie_5: false - dmac_evie_6: false - dmac_evie_7: false - dmac_evie_8: false - dmac_evie_9: false - dmac_evoe_0: false - dmac_evoe_1: false - dmac_evoe_10: false - dmac_evoe_11: false - dmac_evoe_12: false - dmac_evoe_13: false - dmac_evoe_14: false - dmac_evoe_15: false - dmac_evoe_2: false - dmac_evoe_3: false - dmac_evoe_4: false - dmac_evoe_5: false - dmac_evoe_6: false - dmac_evoe_7: false - dmac_evoe_8: false - dmac_evoe_9: false - dmac_evosel_0: Event generation disabled - dmac_evosel_1: Event generation disabled - dmac_evosel_10: Event generation disabled - dmac_evosel_11: Event generation disabled - dmac_evosel_12: Event generation disabled - dmac_evosel_13: Event generation disabled - dmac_evosel_14: Event generation disabled - dmac_evosel_15: Event generation disabled - dmac_evosel_2: Event generation disabled - dmac_evosel_3: Event generation disabled - dmac_evosel_4: Event generation disabled - dmac_evosel_5: Event generation disabled - dmac_evosel_6: Event generation disabled - dmac_evosel_7: Event generation disabled - dmac_evosel_8: Event generation disabled - dmac_evosel_9: Event generation disabled - dmac_lvl_0: Channel priority 0 - dmac_lvl_1: Channel priority 0 - dmac_lvl_10: Channel priority 0 - dmac_lvl_11: Channel priority 0 - dmac_lvl_12: Channel priority 0 - dmac_lvl_13: Channel priority 0 - dmac_lvl_14: Channel priority 0 - dmac_lvl_15: Channel priority 0 - dmac_lvl_2: Channel priority 0 - dmac_lvl_3: Channel priority 0 - dmac_lvl_4: Channel priority 0 - dmac_lvl_5: Channel priority 0 - dmac_lvl_6: Channel priority 0 - dmac_lvl_7: Channel priority 0 - dmac_lvl_8: Channel priority 0 - dmac_lvl_9: Channel priority 0 - dmac_lvlen0: false - dmac_lvlen1: false - dmac_lvlen2: false - dmac_lvlen3: false - dmac_lvlpri0: 0 - dmac_lvlpri1: 0 - dmac_lvlpri2: 0 - dmac_lvlpri3: 0 - dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 - dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 - dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 - dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 - dmac_srcinc_0: false - dmac_srcinc_1: false - dmac_srcinc_10: false - dmac_srcinc_11: false - dmac_srcinc_12: false - dmac_srcinc_13: false - dmac_srcinc_14: false - dmac_srcinc_15: false - dmac_srcinc_2: false - dmac_srcinc_3: false - dmac_srcinc_4: false - dmac_srcinc_5: false - dmac_srcinc_6: false - dmac_srcinc_7: false - dmac_srcinc_8: false - dmac_srcinc_9: false - dmac_stepsel_0: Step size settings apply to the destination address - dmac_stepsel_1: Step size settings apply to the destination address - dmac_stepsel_10: Step size settings apply to the destination address - dmac_stepsel_11: Step size settings apply to the destination address - dmac_stepsel_12: Step size settings apply to the destination address - dmac_stepsel_13: Step size settings apply to the destination address - dmac_stepsel_14: Step size settings apply to the destination address - dmac_stepsel_15: Step size settings apply to the destination address - dmac_stepsel_2: Step size settings apply to the destination address - dmac_stepsel_3: Step size settings apply to the destination address - dmac_stepsel_4: Step size settings apply to the destination address - dmac_stepsel_5: Step size settings apply to the destination address - dmac_stepsel_6: Step size settings apply to the destination address - dmac_stepsel_7: Step size settings apply to the destination address - dmac_stepsel_8: Step size settings apply to the destination address - dmac_stepsel_9: Step size settings apply to the destination address - dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_trifsrc_0: Only software/event triggers - dmac_trifsrc_1: Only software/event triggers - dmac_trifsrc_10: Only software/event triggers - dmac_trifsrc_11: Only software/event triggers - dmac_trifsrc_12: Only software/event triggers - dmac_trifsrc_13: Only software/event triggers - dmac_trifsrc_14: Only software/event triggers - dmac_trifsrc_15: Only software/event triggers - dmac_trifsrc_2: Only software/event triggers - dmac_trifsrc_3: Only software/event triggers - dmac_trifsrc_4: Only software/event triggers - dmac_trifsrc_5: Only software/event triggers - dmac_trifsrc_6: Only software/event triggers - dmac_trifsrc_7: Only software/event triggers - dmac_trifsrc_8: Only software/event triggers - dmac_trifsrc_9: Only software/event triggers - dmac_trigact_0: One trigger required for each block transfer - dmac_trigact_1: One trigger required for each block transfer - dmac_trigact_10: One trigger required for each block transfer - dmac_trigact_11: One trigger required for each block transfer - dmac_trigact_12: One trigger required for each block transfer - dmac_trigact_13: One trigger required for each block transfer - dmac_trigact_14: One trigger required for each block transfer - dmac_trigact_15: One trigger required for each block transfer - dmac_trigact_2: One trigger required for each block transfer - dmac_trigact_3: One trigger required for each block transfer - dmac_trigact_4: One trigger required for each block transfer - dmac_trigact_5: One trigger required for each block transfer - dmac_trigact_6: One trigger required for each block transfer - dmac_trigact_7: One trigger required for each block transfer - dmac_trigact_8: One trigger required for each block transfer - dmac_trigact_9: One trigger required for each block transfer - optional_signals: [] - variant: null - clocks: - domain_group: null - SYSCTRL: - user_label: SYSCTRL - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::SYSCTRL::driver_config_definition::SYSCTRL::HAL:HPL:SYSCTRL - functionality: System - api: HAL:HPL:SYSCTRL - configuration: - dfll48m_arch_bplckc: false - dfll48m_arch_calibration: true - dfll48m_arch_ccdis: false - dfll48m_arch_coarse: 10 - dfll48m_arch_enable: false - dfll48m_arch_fine: 512 - dfll48m_arch_llaw: false - dfll48m_arch_ondemand: true - dfll48m_arch_qldis: false - dfll48m_arch_runstdby: false - dfll48m_arch_stable: false - dfll48m_arch_usbcrm: true - dfll48m_arch_waitlock: false - dfll48m_mode: Closed Loop Mode - dfll48m_mul: 0 - dfll48m_ref_clock: Generic clock generator 4 - dfll_arch_cstep: 1 - dfll_arch_fstep: 1 - enable_dfll48m: false - enable_fdpll96m: false - enable_osc32k: false - enable_osc8m: true - enable_osculp32k: true - enable_xosc: false - enable_xosc32k: false - fdpll96m_arch_enable: false - fdpll96m_arch_lbypass: false - fdpll96m_arch_ondemand: true - fdpll96m_arch_runstdby: false - fdpll96m_clock_div: 0 - fdpll96m_ldr: 1463 - fdpll96m_ldrfrac: 13 - fdpll96m_ref_clock: Generic clock generator 3 - osc32k_arch_calib: 0 - osc32k_arch_en1k: false - osc32k_arch_en32k: false - osc32k_arch_enable: false - osc32k_arch_ondemand: true - osc32k_arch_overwrite_calibration: false - osc32k_arch_runstdby: false - osc32k_arch_startup: 3 Clock Cycles (92us) - osc32k_arch_wrtlock: false - osc8m_arch_calib: 0 - osc8m_arch_enable: true - osc8m_arch_ondemand: true - osc8m_arch_overwrite_calibration: false - osc8m_arch_runstdby: false - osc8m_presc: '8' - osculp32k_arch_calib: 0 - osculp32k_arch_overwrite_calibration: false - osculp32k_arch_wrtlock: false - xosc32k_arch_aampen: false - xosc32k_arch_en1k: false - xosc32k_arch_en32k: false - xosc32k_arch_enable: false - xosc32k_arch_ondemand: true - xosc32k_arch_runstdby: false - xosc32k_arch_startup: 122 us - xosc32k_arch_wrtlock: false - xosc32k_arch_xtalen: false - xosc_arch_ampgc: false - xosc_arch_enable: false - xosc_arch_gain: 2Mhz - xosc_arch_ondemand: true - xosc_arch_runstdby: false - xosc_arch_startup: 31 us - xosc_arch_xtalen: false - xosc_frequency: 400000 - optional_signals: [] - variant: null - clocks: - domain_group: null - USB_0: - user_label: USB_0 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::USB::driver_config_definition::USB.Device::HAL:Driver:USB.Device - functionality: USB - api: HAL:Driver:USB_Device - configuration: - usb_arch_ep0_cache: Cached by 64 bytes buffer - usb_arch_ep1_cache: Cached by 64 bytes buffer - usb_arch_ep2_cache: Cached by 64 bytes buffer - usb_arch_ep3_cache: Cached by 64 bytes buffer - usb_arch_ep4_cache: Cached by 64 bytes buffer - usb_arch_ep5_cache: Cached by 64 bytes buffer - usb_arch_ep6_cache: Cached by 64 bytes buffer - usb_arch_ep7_cache: Cached by 64 bytes buffer - usb_ep1_I_CACHE: No cache - usb_ep2_I_CACHE: No cache - usb_ep3_I_CACHE: No cache - usb_ep4_I_CACHE: No cache - usb_ep5_I_CACHE: No cache - usb_ep6_I_CACHE: No cache - usb_ep7_I_CACHE: No cache - usbd_arch_max_ep_n: 2 (EP 0x82 or 0x02) - usbd_arch_speed: Full speed - usbd_num_ep_sp: 4 (EP0 + 3 endpoints) - optional_signals: [] - variant: - specification: default - required_signals: - - name: USB/DM - pad: PA24 - label: Data- - - name: USB/DP - pad: PA25 - label: Data+ - clocks: - domain_group: - nodes: - - name: USB - input: Generic clock generator 0 - configuration: - usb_gclk_selection: Generic clock generator 0 -pads: - PA00: - name: PA00 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA00 - mode: Digital input - user_label: PA00 - configuration: null - PA01: - name: PA01 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA01 - mode: Digital input - user_label: PA01 - configuration: null - PA02: - name: PA02 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA02 - mode: Digital input - user_label: PA02 - configuration: null - PA03: - name: PA03 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA03 - mode: Digital input - user_label: PA03 - configuration: null - PB08: - name: PB08 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB08 - mode: Digital input - user_label: PB08 - configuration: null - PB09: - name: PB09 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB09 - mode: Digital input - user_label: PB09 - configuration: null - PA04: - name: PA04 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA04 - mode: Digital output - user_label: PA04 - configuration: null - PA05: - name: PA05 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA05 - mode: Digital output - user_label: PA05 - configuration: null - PA06: - name: PA06 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA06 - mode: Digital input - user_label: PA06 - configuration: null - PA07: - name: PA07 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA07 - mode: Digital input - user_label: PA07 - configuration: null - PA08: - name: PA08 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA08 - mode: Peripheral IO - user_label: PA08 - configuration: null - PA09: - name: PA09 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA09 - mode: Peripheral IO - user_label: PA09 - configuration: null - PA10: - name: PA10 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA10 - mode: Digital input - user_label: PA10 - configuration: null - PA11: - name: PA11 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA11 - mode: Digital input - user_label: PA11 - configuration: null - PB10: - name: PB10 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB10 - mode: Digital input - user_label: PB10 - configuration: null - PB11: - name: PB11 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB11 - mode: Digital input - user_label: PB11 - configuration: null - PA12: - name: PA12 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA12 - mode: Digital input - user_label: PA12 - configuration: null - PA13: - name: PA13 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA13 - mode: Digital input - user_label: PA13 - configuration: null - PA14: - name: PA14 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA14 - mode: Digital input - user_label: PA14 - configuration: null - PA15: - name: PA15 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA15 - mode: Digital input - user_label: PA15 - configuration: null - PA16: - name: PA16 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA16 - mode: I2C - user_label: PA16 - configuration: null - PA17: - name: PA17 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA17 - mode: I2C - user_label: PA17 - configuration: null - PA18: - name: PA18 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA18 - mode: Digital input - user_label: PA18 - configuration: null - PA19: - name: PA19 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA19 - mode: Digital input - user_label: PA19 - configuration: null - PA20: - name: PA20 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA20 - mode: Digital input - user_label: PA20 - configuration: null - PA21: - name: PA21 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA21 - mode: Digital input - user_label: PA21 - configuration: null - PA22: - name: PA22 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA22 - mode: Digital input - user_label: PA22 - configuration: null - PA23: - name: PA23 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA23 - mode: Digital input - user_label: PA23 - configuration: null - PA24: - name: PA24 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA24 - mode: Advanced - user_label: PA24 - configuration: null - PA25: - name: PA25 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA25 - mode: Advanced - user_label: PA25 - configuration: null - PB22: - name: PB22 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB22 - mode: Digital input - user_label: PB22 - configuration: null - PB23: - name: PB23 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB23 - mode: Digital input - user_label: PB23 - configuration: null - PA27: - name: PA27 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA27 - mode: Digital input - user_label: PA27 - configuration: null - PA28: - name: PA28 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA28 - mode: Digital input - user_label: PA28 - configuration: null - PA30: - name: PA30 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA30 - mode: Digital input - user_label: PA30 - configuration: null - PA31: - name: PA31 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PA31 - mode: Digital input - user_label: PA31 - configuration: null - PB02: - name: PB02 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB02 - mode: Digital input - user_label: PB02 - configuration: null - PB03: - name: PB03 - definition: Atmel:SAMD21_Drivers:0.0.1::SAMD21G18A-MF::pad::PB03 - mode: Digital input - user_label: PB03 - configuration: null -toolchain_options: [] diff --git a/atmel-samd/asf4/samd21/atmel_start_pins.h b/atmel-samd/asf4/samd21/atmel_start_pins.h deleted file mode 100644 index f8d0bd350..000000000 --- a/atmel-samd/asf4/samd21/atmel_start_pins.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef ATMEL_START_PINS_H_INCLUDED -#define ATMEL_START_PINS_H_INCLUDED - -#include - -// SAMD21 has 8 pin functions - -#define GPIO_PIN_FUNCTION_A 0 -#define GPIO_PIN_FUNCTION_B 1 -#define GPIO_PIN_FUNCTION_C 2 -#define GPIO_PIN_FUNCTION_D 3 -#define GPIO_PIN_FUNCTION_E 4 -#define GPIO_PIN_FUNCTION_F 5 -#define GPIO_PIN_FUNCTION_G 6 -#define GPIO_PIN_FUNCTION_H 7 - -#define PA00 GPIO(GPIO_PORTA, 0) -#define PA01 GPIO(GPIO_PORTA, 1) -#define PA02 GPIO(GPIO_PORTA, 2) -#define PA03 GPIO(GPIO_PORTA, 3) -#define PA04 GPIO(GPIO_PORTA, 4) -#define PA05 GPIO(GPIO_PORTA, 5) -#define PA06 GPIO(GPIO_PORTA, 6) -#define PA07 GPIO(GPIO_PORTA, 7) -#define PA08 GPIO(GPIO_PORTA, 8) -#define PA09 GPIO(GPIO_PORTA, 9) -#define PA10 GPIO(GPIO_PORTA, 10) -#define PA11 GPIO(GPIO_PORTA, 11) -#define PA12 GPIO(GPIO_PORTA, 12) -#define PA13 GPIO(GPIO_PORTA, 13) -#define PA14 GPIO(GPIO_PORTA, 14) -#define PA15 GPIO(GPIO_PORTA, 15) -#define PA16 GPIO(GPIO_PORTA, 16) -#define PA17 GPIO(GPIO_PORTA, 17) -#define PA18 GPIO(GPIO_PORTA, 18) -#define PA19 GPIO(GPIO_PORTA, 19) -#define PA20 GPIO(GPIO_PORTA, 20) -#define PA21 GPIO(GPIO_PORTA, 21) -#define PA22 GPIO(GPIO_PORTA, 22) -#define PA23 GPIO(GPIO_PORTA, 23) -#define PA24 GPIO(GPIO_PORTA, 24) -#define PA25 GPIO(GPIO_PORTA, 25) -#define PA27 GPIO(GPIO_PORTA, 27) -#define PA28 GPIO(GPIO_PORTA, 28) -#define PA30 GPIO(GPIO_PORTA, 30) -#define PA31 GPIO(GPIO_PORTA, 31) -#define PB02 GPIO(GPIO_PORTB, 2) -#define PB03 GPIO(GPIO_PORTB, 3) -#define PB08 GPIO(GPIO_PORTB, 8) -#define PB09 GPIO(GPIO_PORTB, 9) -#define PB10 GPIO(GPIO_PORTB, 10) -#define PB11 GPIO(GPIO_PORTB, 11) -#define PB22 GPIO(GPIO_PORTB, 22) -#define PB23 GPIO(GPIO_PORTB, 23) - -#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/atmel-samd/asf4/samd21/config/hpl_adc_config.h b/atmel-samd/asf4/samd21/config/hpl_adc_config.h deleted file mode 100644 index ea69d4a69..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_adc_config.h +++ /dev/null @@ -1,296 +0,0 @@ -/* Auto-generated config file hpl_adc_config.h */ -#ifndef HPL_ADC_CONFIG_H -#define HPL_ADC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef CONF_ADC_0_ENABLE -#define CONF_ADC_0_ENABLE 1 -#endif - -// Basic Configuration - -// Conversion resolution -// <0x0=>12-bit -// <0x1=>16-bit (averaging must be enabled) -// <0x2=>10-bit -// <0x3=>8-bit -// Defines the bit resolution for the ADC sample values (RESSEL) -// adc_resolution -#ifndef CONF_ADC_0_RESSEL -#define CONF_ADC_0_RESSEL 0x0 -#endif - -// Reference Selection -// <0x0=>1.0V voltage reference -// <0x1=>1/1.48 VDDANA -// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V) -// <0x3=>External reference A -// <0x4=>External reference B -// Select the reference for the ADC (REFSEL) -// adc_reference -#ifndef CONF_ADC_0_REFSEL -#define CONF_ADC_0_REFSEL 0x0 -#endif - -// Prescaler configuration -// <0x0=>Peripheral clock divided by 4 -// <0x1=>Peripheral clock divided by 8 -// <0x2=>Peripheral clock divided by 16 -// <0x3=>Peripheral clock divided by 32 -// <0x4=>Peripheral clock divided by 64 -// <0x5=>Peripheral clock divided by 128 -// <0x6=>Peripheral clock divided by 256 -// <0x7=>Peripheral clock divided by 512 -// These bits define the ADC clock relative to the peripheral clock (PRESCALER) -// adc_prescaler -#ifndef CONF_ADC_0_PRESCALER -#define CONF_ADC_0_PRESCALER 0x0 -#endif - -// Free Running Mode -// When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN) -// adc_freerunning_mode -#ifndef CONF_ADC_0_FREERUN -#define CONF_ADC_0_FREERUN 0 -#endif - -// Differential Mode -// In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE) -// adc_differential_mode -#ifndef CONF_ADC_0_DIFFMODE -#define CONF_ADC_0_DIFFMODE 0 -#endif - -// Positive Mux Input Selection -// <0x00=>ADC AIN0 pin -// <0x01=>ADC AIN1 pin -// <0x02=>ADC AIN2 pin -// <0x03=>ADC AIN3 pin -// <0x04=>ADC AIN4 pin -// <0x05=>ADC AIN5 pin -// <0x06=>ADC AIN6 pin -// <0x07=>ADC AIN7 pin -// <0x08=>ADC AIN8 pin -// <0x09=>ADC AIN9 pin -// <0x0A=>ADC AIN10 pin -// <0x0B=>ADC AIN11 pin -// <0x0C=>ADC AIN12 pin -// <0x0D=>ADC AIN13 pin -// <0x0E=>ADC AIN14 pin -// <0x0F=>ADC AIN15 pin -// <0x10=>ADC AIN16 pin -// <0x11=>ADC AIN17 pin -// <0x12=>ADC AIN18 pin -// <0x13=>ADC AIN19 pin -// <0x18=>Temperature reference -// <0x19=>Bandgap voltage -// <0x1A=>1/4 scaled core supply -// <0x1B=>1/4 scaled I/O supply -// <0x1C=>DAC output -// These bits define the Mux selection for the positive ADC input. (MUXPOS) -// adc_pinmux_positive -#ifndef CONF_ADC_0_MUXPOS -#define CONF_ADC_0_MUXPOS 0x0 -#endif - -// Negative Mux Input Selection -// <0x00=>ADC AIN0 pin -// <0x01=>ADC AIN1 pin -// <0x02=>ADC AIN2 pin -// <0x03=>ADC AIN3 pin -// <0x04=>ADC AIN4 pin -// <0x05=>ADC AIN5 pin -// <0x06=>ADC AIN6 pin -// <0x07=>ADC AIN7 pin -// <0x18=>Internal ground -// <0x19=>I/O ground -// These bits define the Mux selection for the negative ADC input. (MUXNEG) -// adc_pinmux_negative -#ifndef CONF_ADC_0_MUXNEG -#define CONF_ADC_0_MUXNEG 0x0 -#endif - -// - -// Advanced Configuration -// adc_advanced_settings -#ifndef CONF_ADC_0_ADVANCED_CONFIG -#define CONF_ADC_0_ADVANCED_CONFIG 0 -#endif - -// Run in standby -// Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY) -// adc_arch_runstdby -#ifndef CONF_ADC_0_RUNSTDBY -#define CONF_ADC_0_RUNSTDBY 0 -#endif - -// Debug Run -// If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN) -// adc_arch_dbgrun -#ifndef CONF_ADC_0_DBGRUN -#define CONF_ADC_0_DBGRUN 0 -#endif - -// Left-Adjusted Result -// When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ) -// adc_arch_leftadj -#ifndef CONF_ADC_0_LEFTADJ -#define CONF_ADC_0_LEFTADJ 0 -#endif - -// Reference Buffer Offset Compensation Enable -// The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP) -// adc_arch_refcomp -#ifndef CONF_ADC_0_REFCOMP -#define CONF_ADC_0_REFCOMP 0 -#endif - -// Digital Correction Logic Enabled -// When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN) -// adc_arch_corren -#ifndef CONF_ADC_0_CORREN -#define CONF_ADC_0_CORREN 0 -#endif - -// Offset Correction Value <0-4095> -// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR) -// adc_arch_offsetcorr -#ifndef CONF_ADC_0_OFFSETCORR -#define CONF_ADC_0_OFFSETCORR 0 -#endif - -// Gain Correction Value <0-4095> -// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR) -// adc_arch_gaincorr -#ifndef CONF_ADC_0_GAINCORR -#define CONF_ADC_0_GAINCORR 0 -#endif - -// Gain Factor Selection -// <0x0=>1x -// <0x1=>2x -// <0x2=>4x -// <0x3=>8x -// <0x4=>16x -// <0xF=>1/2x -// These bits set the gain factor of the ADC gain stage. (GAIN) -// adc_arch_gain -#ifndef CONF_ADC_0_GAIN -#define CONF_ADC_0_GAIN 0x0 -#endif - -// Adjusting Result / Division Coefficient <0-7> -// These bits define the division coefficient in 2n steps. (ADJRES) -// adc_arch_adjres -#ifndef CONF_ADC_0_ADJRES -#define CONF_ADC_0_ADJRES 0x0 -#endif - -// Number of Samples to be Collected -// <0x0=>1 sample -// <0x1=>2 samples -// <0x2=>4 samples -// <0x3=>8 samples -// <0x4=>16 samples -// <0x5=>32 samples -// <0x6=>64 samples -// <0x7=>128 samples -// <0x8=>256 samples -// <0x9=>512 samples -// <0xA=>1024 samples -// Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM) -// adc_arch_samplenum -#ifndef CONF_ADC_0_SAMPLENUM -#define CONF_ADC_0_SAMPLENUM 0x0 -#endif - -// Sampling Time Length <0-63> -// These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN) -// adc_arch_samplen -#ifndef CONF_ADC_0_SAMPLEN -#define CONF_ADC_0_SAMPLEN 0 -#endif - -// Window Monitor Mode -// <0x0=>No window mode -// <0x1=>Mode 1: RESULT above lower threshold -// <0x2=>Mode 2: RESULT beneath upper threshold -// <0x3=>Mode 3: RESULT inside lower and upper threshold -// <0x4=>Mode 4: RESULT outside lower and upper threshold -// These bits enable and define the window monitor mode. (WINMODE) -// adc_arch_winmode -#ifndef CONF_ADC_0_WINMODE -#define CONF_ADC_0_WINMODE 0x0 -#endif - -// Window Monitor Lower Threshold <0-65535> -// If the window monitor is enabled, these bits define the lower threshold value. (WINLT) -// adc_arch_winlt -#ifndef CONF_ADC_0_WINLT -#define CONF_ADC_0_WINLT 0 -#endif - -// Window Monitor Upper Threshold <0-65535> -// If the window monitor is enabled, these bits define the lower threshold value. (WINUT) -// adc_arch_winut -#ifndef CONF_ADC_0_WINUT -#define CONF_ADC_0_WINUT 0 -#endif - -// Number of Input Channels Included in Scan <0-15> -// This register gives the number of input sources included in pin scan. The number of input sources included is INPUTSCAN + 1. 0 disables the input scan feature. (INPUTSCAN) -// adc_arch_inputscan -#ifndef CONF_ADC_0_INPUTSCAN -#define CONF_ADC_0_INPUTSCAN 0 -#endif - -// Positive Mux Setting Offset <0-15> -// When inputscan is enabled this value define the pin offset, which means that the actual input pin sampled is the muxpos pin + input offset. (INPUTOFFSET) -// adc_arch_inputoffset -#ifndef CONF_ADC_0_INPUTOFFSET -#define CONF_ADC_0_INPUTOFFSET 0 -#endif - -// - -// Event Control -// adc_arch_event_settings -#ifndef CONF_ADC_0_EVENT_CONFIG -#define CONF_ADC_0_EVENT_CONFIG 0 -#endif - -// Window Monitor Event Out -// Enables event output on window event (WINMONEO) -// adc_arch_winmoneo -#ifndef CONF_ADC_0_WINMONEO -#define CONF_ADC_0_WINMONEO 0 -#endif - -// Result Ready Event Out -// Enables event output on result ready event (RESRDEO) -// adc_arch_resrdyeo -#ifndef CONF_ADC_0_RESRDYEO -#define CONF_ADC_0_RESRDYEO 0 -#endif - -// Trigger Synchronization On Event -// Trigger a flush operation and a new conversion on event in (SYNCEI) -// adc_arch_syncei -#ifndef CONF_ADC_0_SYNCEI -#define CONF_ADC_0_SYNCEI 0 -#endif - -// Trigger Conversion On Event -// Trigger a conversion on event. (STARTEI) -// adc_arch_startei -#ifndef CONF_ADC_0_STARTEI -#define CONF_ADC_0_STARTEI 0 -#endif - -// - -// <<< end of configuration section >>> - -#endif // HPL_ADC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_dac_config.h b/atmel-samd/asf4/samd21/config/hpl_dac_config.h deleted file mode 100644 index 4b1b152fb..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_dac_config.h +++ /dev/null @@ -1,86 +0,0 @@ -/* Auto-generated config file hpl_dac_config.h */ -#ifndef HPL_DAC_CONFIG_H -#define HPL_DAC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic configuration -// Reference Selection -// <0x00=> Internal 1.0v reference -// <0x01=> AVCC -// <0x02=> External reference -// dac_arch_refsel -#ifndef CONF_DAC_REFSEL -#define CONF_DAC_REFSEL 0 -#endif -// - -// Advanced Configuration -// dac_advanced_settings -#ifndef CONF_DAC_ADVANCED_CONFIG -#define CONF_DAC_ADVANCED_CONFIG 0 -#endif - -// Run in standby -// Indicates whether the DAC will continue running in standby sleep mode or not -// dac_arch_runstdby -#ifndef CONF_DAC_RUNSTDBY -#define CONF_DAC_RUNSTDBY 0 -#endif - -// Bypass DATABUF Write Protection -// Indicate whether DATABUF write protection is bypass -// dac_arch_bdwp -#ifndef CONF_DAC_BDWP -#define CONF_DAC_BDWP 0 -#endif - -// Voltage Pump Disable -// Indicate whether voltage pump is disable or not -// dac_arch_vpd -#ifndef CONF_DAC_VPD -#define CONF_DAC_VPD 0 -#endif - -// Left Adjusted Data -// Indicate how the data is adjusted in the Data and Data Buffer register -// dac_arch_leftadj -#ifndef CONF_DAC_LEFTADJ -#define CONF_DAC_LEFTADJ 0 -#endif - -// Internal Output Enable -// Indicate whether internal output is enable or not -// dac_arch_ioen -#ifndef CONF_DAC_IOEN -#define CONF_DAC_IOEN 0 -#endif - -// External Output Enable -// Indicate whether external output is enable or not -// dac_arch_eoen -#ifndef CONF_DAC_EOEN -#define CONF_DAC_EOEN 1 -#endif - -// - -// Event configuration -// Data Buffer Empty Event Output -// Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not -// dac_arch_emptyeo -#ifndef CONF_DAC_EMPTYEO -#define CONF_DAC_EMPTYEO 0 -#endif - -// Start Conversion on Event Input -// Indicate whether Start Conversion is enabled and data are loaded from the Data Buffer register to the Data register upon event reception or not -// dac_arch_startei -#ifndef CONF_DAC_STARTEI -#define CONF_DAC_STARTEI 0 -#endif -// - -// <<< end of configuration section >>> - -#endif // HPL_DAC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_dmac_config.h b/atmel-samd/asf4/samd21/config/hpl_dmac_config.h deleted file mode 100644 index 3667e873b..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_dmac_config.h +++ /dev/null @@ -1,3057 +0,0 @@ -/* Auto-generated config file hpl_dmac_config.h */ -#ifndef HPL_DMAC_CONFIG_H -#define HPL_DMAC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// DMAC enable -// Indicates whether dmac is enabled or not -// dmac_enable -#ifndef CONF_DMAC_ENABLE -#define CONF_DMAC_ENABLE 0 -#endif - -// Priority Level 0 -// Indicates whether Priority Level 0 is enabled or not -// dmac_lvlen0 -#ifndef CONF_DMAC_LVLEN0 -#define CONF_DMAC_LVLEN0 0 -#endif - -// Level 0 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 0 -// <1=> Round-robin arbitration scheme for channel with priority 0 -// Defines Level 0 Arbitration for DMA channels -// dmac_rrlvlen0 -#ifndef CONF_DMAC_RRLVLEN0 -#define CONF_DMAC_RRLVLEN0 0 -#endif - -// Level 0 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri0 -#ifndef CONF_DMAC_LVLPRI0 -#define CONF_DMAC_LVLPRI0 0 -#endif - -// Priority Level 1 -// Indicates whether Priority Level 1 is enabled or not -// dmac_lvlen1 -#ifndef CONF_DMAC_LVLEN1 -#define CONF_DMAC_LVLEN1 0 -#endif - -// Level 1 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 1 -// <1=> Round-robin arbitration scheme for channel with priority 1 -// Defines Level 1 Arbitration for DMA channels -// dmac_rrlvlen1 -#ifndef CONF_DMAC_RRLVLEN1 -#define CONF_DMAC_RRLVLEN1 0 -#endif - -// Level 1 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri1 -#ifndef CONF_DMAC_LVLPRI1 -#define CONF_DMAC_LVLPRI1 0 -#endif - -// Priority Level 2 -// Indicates whether Priority Level 2 is enabled or not -// dmac_lvlen2 -#ifndef CONF_DMAC_LVLEN2 -#define CONF_DMAC_LVLEN2 0 -#endif - -// Level 2 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 2 -// <1=> Round-robin arbitration scheme for channel with priority 2 -// Defines Level 2 Arbitration for DMA channels -// dmac_rrlvlen2 -#ifndef CONF_DMAC_RRLVLEN2 -#define CONF_DMAC_RRLVLEN2 0 -#endif - -// Level 2 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri2 -#ifndef CONF_DMAC_LVLPRI2 -#define CONF_DMAC_LVLPRI2 0 -#endif - -// Priority Level 3 -// Indicates whether Priority Level 3 is enabled or not -// dmac_lvlen3 -#ifndef CONF_DMAC_LVLEN3 -#define CONF_DMAC_LVLEN3 0 -#endif - -// Level 3 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 3 -// <1=> Round-robin arbitration scheme for channel with priority 3 -// Defines Level 3 Arbitration for DMA channels -// dmac_rrlvlen3 -#ifndef CONF_DMAC_RRLVLEN3 -#define CONF_DMAC_RRLVLEN3 0 -#endif - -// Level 3 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri3 -#ifndef CONF_DMAC_LVLPRI3 -#define CONF_DMAC_LVLPRI3 0 -#endif - -// Debug Run -// Indicates whether Debug Run is enabled or not -// dmac_dbgrun -#ifndef CONF_DMAC_DBGRUN -#define CONF_DMAC_DBGRUN 0 -#endif - -// Channel 0 settings -// dmac_channel_0_settings -#ifndef CONF_DMAC_CHANNEL_0_SETTINGS -#define CONF_DMAC_CHANNEL_0_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 0 is enabled or not -// dmac_enable_0 -#ifndef CONF_DMAC_ENABLE_0 -#define CONF_DMAC_ENABLE_0 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_0 -#ifndef CONF_DMAC_TRIGACT_0 -#define CONF_DMAC_TRIGACT_0 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_0 -#ifndef CONF_DMAC_TRIGSRC_0 -#define CONF_DMAC_TRIGSRC_0 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_0 -#ifndef CONF_DMAC_LVL_0 -#define CONF_DMAC_LVL_0 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_0 -#ifndef CONF_DMAC_EVOE_0 -#define CONF_DMAC_EVOE_0 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_0 -#ifndef CONF_DMAC_EVIE_0 -#define CONF_DMAC_EVIE_0 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_0 -#ifndef CONF_DMAC_EVACT_0 -#define CONF_DMAC_EVACT_0 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_0 -#ifndef CONF_DMAC_STEPSIZE_0 -#define CONF_DMAC_STEPSIZE_0 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_0 -#ifndef CONF_DMAC_STEPSEL_0 -#define CONF_DMAC_STEPSEL_0 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_0 -#ifndef CONF_DMAC_SRCINC_0 -#define CONF_DMAC_SRCINC_0 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_0 -#ifndef CONF_DMAC_DSTINC_0 -#define CONF_DMAC_DSTINC_0 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_0 -#ifndef CONF_DMAC_BEATSIZE_0 -#define CONF_DMAC_BEATSIZE_0 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_0 -#ifndef CONF_DMAC_BLOCKACT_0 -#define CONF_DMAC_BLOCKACT_0 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_0 -#ifndef CONF_DMAC_EVOSEL_0 -#define CONF_DMAC_EVOSEL_0 0 -#endif -// - -// Channel 1 settings -// dmac_channel_1_settings -#ifndef CONF_DMAC_CHANNEL_1_SETTINGS -#define CONF_DMAC_CHANNEL_1_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 1 is enabled or not -// dmac_enable_1 -#ifndef CONF_DMAC_ENABLE_1 -#define CONF_DMAC_ENABLE_1 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_1 -#ifndef CONF_DMAC_TRIGACT_1 -#define CONF_DMAC_TRIGACT_1 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_1 -#ifndef CONF_DMAC_TRIGSRC_1 -#define CONF_DMAC_TRIGSRC_1 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_1 -#ifndef CONF_DMAC_LVL_1 -#define CONF_DMAC_LVL_1 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_1 -#ifndef CONF_DMAC_EVOE_1 -#define CONF_DMAC_EVOE_1 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_1 -#ifndef CONF_DMAC_EVIE_1 -#define CONF_DMAC_EVIE_1 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_1 -#ifndef CONF_DMAC_EVACT_1 -#define CONF_DMAC_EVACT_1 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_1 -#ifndef CONF_DMAC_STEPSIZE_1 -#define CONF_DMAC_STEPSIZE_1 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_1 -#ifndef CONF_DMAC_STEPSEL_1 -#define CONF_DMAC_STEPSEL_1 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_1 -#ifndef CONF_DMAC_SRCINC_1 -#define CONF_DMAC_SRCINC_1 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_1 -#ifndef CONF_DMAC_DSTINC_1 -#define CONF_DMAC_DSTINC_1 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_1 -#ifndef CONF_DMAC_BEATSIZE_1 -#define CONF_DMAC_BEATSIZE_1 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_1 -#ifndef CONF_DMAC_BLOCKACT_1 -#define CONF_DMAC_BLOCKACT_1 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_1 -#ifndef CONF_DMAC_EVOSEL_1 -#define CONF_DMAC_EVOSEL_1 0 -#endif -// - -// Channel 2 settings -// dmac_channel_2_settings -#ifndef CONF_DMAC_CHANNEL_2_SETTINGS -#define CONF_DMAC_CHANNEL_2_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 2 is enabled or not -// dmac_enable_2 -#ifndef CONF_DMAC_ENABLE_2 -#define CONF_DMAC_ENABLE_2 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_2 -#ifndef CONF_DMAC_TRIGACT_2 -#define CONF_DMAC_TRIGACT_2 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_2 -#ifndef CONF_DMAC_TRIGSRC_2 -#define CONF_DMAC_TRIGSRC_2 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_2 -#ifndef CONF_DMAC_LVL_2 -#define CONF_DMAC_LVL_2 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_2 -#ifndef CONF_DMAC_EVOE_2 -#define CONF_DMAC_EVOE_2 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_2 -#ifndef CONF_DMAC_EVIE_2 -#define CONF_DMAC_EVIE_2 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_2 -#ifndef CONF_DMAC_EVACT_2 -#define CONF_DMAC_EVACT_2 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_2 -#ifndef CONF_DMAC_STEPSIZE_2 -#define CONF_DMAC_STEPSIZE_2 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_2 -#ifndef CONF_DMAC_STEPSEL_2 -#define CONF_DMAC_STEPSEL_2 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_2 -#ifndef CONF_DMAC_SRCINC_2 -#define CONF_DMAC_SRCINC_2 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_2 -#ifndef CONF_DMAC_DSTINC_2 -#define CONF_DMAC_DSTINC_2 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_2 -#ifndef CONF_DMAC_BEATSIZE_2 -#define CONF_DMAC_BEATSIZE_2 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_2 -#ifndef CONF_DMAC_BLOCKACT_2 -#define CONF_DMAC_BLOCKACT_2 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_2 -#ifndef CONF_DMAC_EVOSEL_2 -#define CONF_DMAC_EVOSEL_2 0 -#endif -// - -// Channel 3 settings -// dmac_channel_3_settings -#ifndef CONF_DMAC_CHANNEL_3_SETTINGS -#define CONF_DMAC_CHANNEL_3_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 3 is enabled or not -// dmac_enable_3 -#ifndef CONF_DMAC_ENABLE_3 -#define CONF_DMAC_ENABLE_3 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_3 -#ifndef CONF_DMAC_TRIGACT_3 -#define CONF_DMAC_TRIGACT_3 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_3 -#ifndef CONF_DMAC_TRIGSRC_3 -#define CONF_DMAC_TRIGSRC_3 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_3 -#ifndef CONF_DMAC_LVL_3 -#define CONF_DMAC_LVL_3 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_3 -#ifndef CONF_DMAC_EVOE_3 -#define CONF_DMAC_EVOE_3 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_3 -#ifndef CONF_DMAC_EVIE_3 -#define CONF_DMAC_EVIE_3 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_3 -#ifndef CONF_DMAC_EVACT_3 -#define CONF_DMAC_EVACT_3 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_3 -#ifndef CONF_DMAC_STEPSIZE_3 -#define CONF_DMAC_STEPSIZE_3 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_3 -#ifndef CONF_DMAC_STEPSEL_3 -#define CONF_DMAC_STEPSEL_3 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_3 -#ifndef CONF_DMAC_SRCINC_3 -#define CONF_DMAC_SRCINC_3 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_3 -#ifndef CONF_DMAC_DSTINC_3 -#define CONF_DMAC_DSTINC_3 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_3 -#ifndef CONF_DMAC_BEATSIZE_3 -#define CONF_DMAC_BEATSIZE_3 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_3 -#ifndef CONF_DMAC_BLOCKACT_3 -#define CONF_DMAC_BLOCKACT_3 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_3 -#ifndef CONF_DMAC_EVOSEL_3 -#define CONF_DMAC_EVOSEL_3 0 -#endif -// - -// Channel 4 settings -// dmac_channel_4_settings -#ifndef CONF_DMAC_CHANNEL_4_SETTINGS -#define CONF_DMAC_CHANNEL_4_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 4 is enabled or not -// dmac_enable_4 -#ifndef CONF_DMAC_ENABLE_4 -#define CONF_DMAC_ENABLE_4 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_4 -#ifndef CONF_DMAC_TRIGACT_4 -#define CONF_DMAC_TRIGACT_4 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_4 -#ifndef CONF_DMAC_TRIGSRC_4 -#define CONF_DMAC_TRIGSRC_4 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_4 -#ifndef CONF_DMAC_LVL_4 -#define CONF_DMAC_LVL_4 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_4 -#ifndef CONF_DMAC_EVOE_4 -#define CONF_DMAC_EVOE_4 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_4 -#ifndef CONF_DMAC_EVIE_4 -#define CONF_DMAC_EVIE_4 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_4 -#ifndef CONF_DMAC_EVACT_4 -#define CONF_DMAC_EVACT_4 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_4 -#ifndef CONF_DMAC_STEPSIZE_4 -#define CONF_DMAC_STEPSIZE_4 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_4 -#ifndef CONF_DMAC_STEPSEL_4 -#define CONF_DMAC_STEPSEL_4 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_4 -#ifndef CONF_DMAC_SRCINC_4 -#define CONF_DMAC_SRCINC_4 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_4 -#ifndef CONF_DMAC_DSTINC_4 -#define CONF_DMAC_DSTINC_4 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_4 -#ifndef CONF_DMAC_BEATSIZE_4 -#define CONF_DMAC_BEATSIZE_4 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_4 -#ifndef CONF_DMAC_BLOCKACT_4 -#define CONF_DMAC_BLOCKACT_4 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_4 -#ifndef CONF_DMAC_EVOSEL_4 -#define CONF_DMAC_EVOSEL_4 0 -#endif -// - -// Channel 5 settings -// dmac_channel_5_settings -#ifndef CONF_DMAC_CHANNEL_5_SETTINGS -#define CONF_DMAC_CHANNEL_5_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 5 is enabled or not -// dmac_enable_5 -#ifndef CONF_DMAC_ENABLE_5 -#define CONF_DMAC_ENABLE_5 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_5 -#ifndef CONF_DMAC_TRIGACT_5 -#define CONF_DMAC_TRIGACT_5 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_5 -#ifndef CONF_DMAC_TRIGSRC_5 -#define CONF_DMAC_TRIGSRC_5 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_5 -#ifndef CONF_DMAC_LVL_5 -#define CONF_DMAC_LVL_5 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_5 -#ifndef CONF_DMAC_EVOE_5 -#define CONF_DMAC_EVOE_5 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_5 -#ifndef CONF_DMAC_EVIE_5 -#define CONF_DMAC_EVIE_5 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_5 -#ifndef CONF_DMAC_EVACT_5 -#define CONF_DMAC_EVACT_5 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_5 -#ifndef CONF_DMAC_STEPSIZE_5 -#define CONF_DMAC_STEPSIZE_5 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_5 -#ifndef CONF_DMAC_STEPSEL_5 -#define CONF_DMAC_STEPSEL_5 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_5 -#ifndef CONF_DMAC_SRCINC_5 -#define CONF_DMAC_SRCINC_5 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_5 -#ifndef CONF_DMAC_DSTINC_5 -#define CONF_DMAC_DSTINC_5 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_5 -#ifndef CONF_DMAC_BEATSIZE_5 -#define CONF_DMAC_BEATSIZE_5 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_5 -#ifndef CONF_DMAC_BLOCKACT_5 -#define CONF_DMAC_BLOCKACT_5 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_5 -#ifndef CONF_DMAC_EVOSEL_5 -#define CONF_DMAC_EVOSEL_5 0 -#endif -// - -// Channel 6 settings -// dmac_channel_6_settings -#ifndef CONF_DMAC_CHANNEL_6_SETTINGS -#define CONF_DMAC_CHANNEL_6_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 6 is enabled or not -// dmac_enable_6 -#ifndef CONF_DMAC_ENABLE_6 -#define CONF_DMAC_ENABLE_6 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_6 -#ifndef CONF_DMAC_TRIGACT_6 -#define CONF_DMAC_TRIGACT_6 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_6 -#ifndef CONF_DMAC_TRIGSRC_6 -#define CONF_DMAC_TRIGSRC_6 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_6 -#ifndef CONF_DMAC_LVL_6 -#define CONF_DMAC_LVL_6 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_6 -#ifndef CONF_DMAC_EVOE_6 -#define CONF_DMAC_EVOE_6 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_6 -#ifndef CONF_DMAC_EVIE_6 -#define CONF_DMAC_EVIE_6 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_6 -#ifndef CONF_DMAC_EVACT_6 -#define CONF_DMAC_EVACT_6 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_6 -#ifndef CONF_DMAC_STEPSIZE_6 -#define CONF_DMAC_STEPSIZE_6 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_6 -#ifndef CONF_DMAC_STEPSEL_6 -#define CONF_DMAC_STEPSEL_6 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_6 -#ifndef CONF_DMAC_SRCINC_6 -#define CONF_DMAC_SRCINC_6 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_6 -#ifndef CONF_DMAC_DSTINC_6 -#define CONF_DMAC_DSTINC_6 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_6 -#ifndef CONF_DMAC_BEATSIZE_6 -#define CONF_DMAC_BEATSIZE_6 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_6 -#ifndef CONF_DMAC_BLOCKACT_6 -#define CONF_DMAC_BLOCKACT_6 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_6 -#ifndef CONF_DMAC_EVOSEL_6 -#define CONF_DMAC_EVOSEL_6 0 -#endif -// - -// Channel 7 settings -// dmac_channel_7_settings -#ifndef CONF_DMAC_CHANNEL_7_SETTINGS -#define CONF_DMAC_CHANNEL_7_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 7 is enabled or not -// dmac_enable_7 -#ifndef CONF_DMAC_ENABLE_7 -#define CONF_DMAC_ENABLE_7 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_7 -#ifndef CONF_DMAC_TRIGACT_7 -#define CONF_DMAC_TRIGACT_7 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_7 -#ifndef CONF_DMAC_TRIGSRC_7 -#define CONF_DMAC_TRIGSRC_7 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_7 -#ifndef CONF_DMAC_LVL_7 -#define CONF_DMAC_LVL_7 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_7 -#ifndef CONF_DMAC_EVOE_7 -#define CONF_DMAC_EVOE_7 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_7 -#ifndef CONF_DMAC_EVIE_7 -#define CONF_DMAC_EVIE_7 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_7 -#ifndef CONF_DMAC_EVACT_7 -#define CONF_DMAC_EVACT_7 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_7 -#ifndef CONF_DMAC_STEPSIZE_7 -#define CONF_DMAC_STEPSIZE_7 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_7 -#ifndef CONF_DMAC_STEPSEL_7 -#define CONF_DMAC_STEPSEL_7 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_7 -#ifndef CONF_DMAC_SRCINC_7 -#define CONF_DMAC_SRCINC_7 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_7 -#ifndef CONF_DMAC_DSTINC_7 -#define CONF_DMAC_DSTINC_7 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_7 -#ifndef CONF_DMAC_BEATSIZE_7 -#define CONF_DMAC_BEATSIZE_7 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_7 -#ifndef CONF_DMAC_BLOCKACT_7 -#define CONF_DMAC_BLOCKACT_7 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_7 -#ifndef CONF_DMAC_EVOSEL_7 -#define CONF_DMAC_EVOSEL_7 0 -#endif -// - -// Channel 8 settings -// dmac_channel_8_settings -#ifndef CONF_DMAC_CHANNEL_8_SETTINGS -#define CONF_DMAC_CHANNEL_8_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 8 is enabled or not -// dmac_enable_8 -#ifndef CONF_DMAC_ENABLE_8 -#define CONF_DMAC_ENABLE_8 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_8 -#ifndef CONF_DMAC_TRIGACT_8 -#define CONF_DMAC_TRIGACT_8 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_8 -#ifndef CONF_DMAC_TRIGSRC_8 -#define CONF_DMAC_TRIGSRC_8 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_8 -#ifndef CONF_DMAC_LVL_8 -#define CONF_DMAC_LVL_8 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_8 -#ifndef CONF_DMAC_EVOE_8 -#define CONF_DMAC_EVOE_8 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_8 -#ifndef CONF_DMAC_EVIE_8 -#define CONF_DMAC_EVIE_8 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_8 -#ifndef CONF_DMAC_EVACT_8 -#define CONF_DMAC_EVACT_8 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_8 -#ifndef CONF_DMAC_STEPSIZE_8 -#define CONF_DMAC_STEPSIZE_8 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_8 -#ifndef CONF_DMAC_STEPSEL_8 -#define CONF_DMAC_STEPSEL_8 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_8 -#ifndef CONF_DMAC_SRCINC_8 -#define CONF_DMAC_SRCINC_8 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_8 -#ifndef CONF_DMAC_DSTINC_8 -#define CONF_DMAC_DSTINC_8 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_8 -#ifndef CONF_DMAC_BEATSIZE_8 -#define CONF_DMAC_BEATSIZE_8 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_8 -#ifndef CONF_DMAC_BLOCKACT_8 -#define CONF_DMAC_BLOCKACT_8 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_8 -#ifndef CONF_DMAC_EVOSEL_8 -#define CONF_DMAC_EVOSEL_8 0 -#endif -// - -// Channel 9 settings -// dmac_channel_9_settings -#ifndef CONF_DMAC_CHANNEL_9_SETTINGS -#define CONF_DMAC_CHANNEL_9_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 9 is enabled or not -// dmac_enable_9 -#ifndef CONF_DMAC_ENABLE_9 -#define CONF_DMAC_ENABLE_9 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_9 -#ifndef CONF_DMAC_TRIGACT_9 -#define CONF_DMAC_TRIGACT_9 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_9 -#ifndef CONF_DMAC_TRIGSRC_9 -#define CONF_DMAC_TRIGSRC_9 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_9 -#ifndef CONF_DMAC_LVL_9 -#define CONF_DMAC_LVL_9 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_9 -#ifndef CONF_DMAC_EVOE_9 -#define CONF_DMAC_EVOE_9 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_9 -#ifndef CONF_DMAC_EVIE_9 -#define CONF_DMAC_EVIE_9 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_9 -#ifndef CONF_DMAC_EVACT_9 -#define CONF_DMAC_EVACT_9 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_9 -#ifndef CONF_DMAC_STEPSIZE_9 -#define CONF_DMAC_STEPSIZE_9 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_9 -#ifndef CONF_DMAC_STEPSEL_9 -#define CONF_DMAC_STEPSEL_9 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_9 -#ifndef CONF_DMAC_SRCINC_9 -#define CONF_DMAC_SRCINC_9 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_9 -#ifndef CONF_DMAC_DSTINC_9 -#define CONF_DMAC_DSTINC_9 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_9 -#ifndef CONF_DMAC_BEATSIZE_9 -#define CONF_DMAC_BEATSIZE_9 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_9 -#ifndef CONF_DMAC_BLOCKACT_9 -#define CONF_DMAC_BLOCKACT_9 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_9 -#ifndef CONF_DMAC_EVOSEL_9 -#define CONF_DMAC_EVOSEL_9 0 -#endif -// - -// Channel 10 settings -// dmac_channel_10_settings -#ifndef CONF_DMAC_CHANNEL_10_SETTINGS -#define CONF_DMAC_CHANNEL_10_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 10 is enabled or not -// dmac_enable_10 -#ifndef CONF_DMAC_ENABLE_10 -#define CONF_DMAC_ENABLE_10 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_10 -#ifndef CONF_DMAC_TRIGACT_10 -#define CONF_DMAC_TRIGACT_10 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_10 -#ifndef CONF_DMAC_TRIGSRC_10 -#define CONF_DMAC_TRIGSRC_10 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_10 -#ifndef CONF_DMAC_LVL_10 -#define CONF_DMAC_LVL_10 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_10 -#ifndef CONF_DMAC_EVOE_10 -#define CONF_DMAC_EVOE_10 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_10 -#ifndef CONF_DMAC_EVIE_10 -#define CONF_DMAC_EVIE_10 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_10 -#ifndef CONF_DMAC_EVACT_10 -#define CONF_DMAC_EVACT_10 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_10 -#ifndef CONF_DMAC_STEPSIZE_10 -#define CONF_DMAC_STEPSIZE_10 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_10 -#ifndef CONF_DMAC_STEPSEL_10 -#define CONF_DMAC_STEPSEL_10 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_10 -#ifndef CONF_DMAC_SRCINC_10 -#define CONF_DMAC_SRCINC_10 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_10 -#ifndef CONF_DMAC_DSTINC_10 -#define CONF_DMAC_DSTINC_10 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_10 -#ifndef CONF_DMAC_BEATSIZE_10 -#define CONF_DMAC_BEATSIZE_10 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_10 -#ifndef CONF_DMAC_BLOCKACT_10 -#define CONF_DMAC_BLOCKACT_10 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_10 -#ifndef CONF_DMAC_EVOSEL_10 -#define CONF_DMAC_EVOSEL_10 0 -#endif -// - -// Channel 11 settings -// dmac_channel_11_settings -#ifndef CONF_DMAC_CHANNEL_11_SETTINGS -#define CONF_DMAC_CHANNEL_11_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 11 is enabled or not -// dmac_enable_11 -#ifndef CONF_DMAC_ENABLE_11 -#define CONF_DMAC_ENABLE_11 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_11 -#ifndef CONF_DMAC_TRIGACT_11 -#define CONF_DMAC_TRIGACT_11 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_11 -#ifndef CONF_DMAC_TRIGSRC_11 -#define CONF_DMAC_TRIGSRC_11 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_11 -#ifndef CONF_DMAC_LVL_11 -#define CONF_DMAC_LVL_11 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_11 -#ifndef CONF_DMAC_EVOE_11 -#define CONF_DMAC_EVOE_11 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_11 -#ifndef CONF_DMAC_EVIE_11 -#define CONF_DMAC_EVIE_11 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_11 -#ifndef CONF_DMAC_EVACT_11 -#define CONF_DMAC_EVACT_11 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_11 -#ifndef CONF_DMAC_STEPSIZE_11 -#define CONF_DMAC_STEPSIZE_11 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_11 -#ifndef CONF_DMAC_STEPSEL_11 -#define CONF_DMAC_STEPSEL_11 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_11 -#ifndef CONF_DMAC_SRCINC_11 -#define CONF_DMAC_SRCINC_11 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_11 -#ifndef CONF_DMAC_DSTINC_11 -#define CONF_DMAC_DSTINC_11 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_11 -#ifndef CONF_DMAC_BEATSIZE_11 -#define CONF_DMAC_BEATSIZE_11 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_11 -#ifndef CONF_DMAC_BLOCKACT_11 -#define CONF_DMAC_BLOCKACT_11 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_11 -#ifndef CONF_DMAC_EVOSEL_11 -#define CONF_DMAC_EVOSEL_11 0 -#endif -// - -// Channel 12 settings -// dmac_channel_12_settings -#ifndef CONF_DMAC_CHANNEL_12_SETTINGS -#define CONF_DMAC_CHANNEL_12_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 12 is enabled or not -// dmac_enable_12 -#ifndef CONF_DMAC_ENABLE_12 -#define CONF_DMAC_ENABLE_12 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_12 -#ifndef CONF_DMAC_TRIGACT_12 -#define CONF_DMAC_TRIGACT_12 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_12 -#ifndef CONF_DMAC_TRIGSRC_12 -#define CONF_DMAC_TRIGSRC_12 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_12 -#ifndef CONF_DMAC_LVL_12 -#define CONF_DMAC_LVL_12 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_12 -#ifndef CONF_DMAC_EVOE_12 -#define CONF_DMAC_EVOE_12 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_12 -#ifndef CONF_DMAC_EVIE_12 -#define CONF_DMAC_EVIE_12 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_12 -#ifndef CONF_DMAC_EVACT_12 -#define CONF_DMAC_EVACT_12 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_12 -#ifndef CONF_DMAC_STEPSIZE_12 -#define CONF_DMAC_STEPSIZE_12 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_12 -#ifndef CONF_DMAC_STEPSEL_12 -#define CONF_DMAC_STEPSEL_12 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_12 -#ifndef CONF_DMAC_SRCINC_12 -#define CONF_DMAC_SRCINC_12 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_12 -#ifndef CONF_DMAC_DSTINC_12 -#define CONF_DMAC_DSTINC_12 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_12 -#ifndef CONF_DMAC_BEATSIZE_12 -#define CONF_DMAC_BEATSIZE_12 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_12 -#ifndef CONF_DMAC_BLOCKACT_12 -#define CONF_DMAC_BLOCKACT_12 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_12 -#ifndef CONF_DMAC_EVOSEL_12 -#define CONF_DMAC_EVOSEL_12 0 -#endif -// - -// Channel 13 settings -// dmac_channel_13_settings -#ifndef CONF_DMAC_CHANNEL_13_SETTINGS -#define CONF_DMAC_CHANNEL_13_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 13 is enabled or not -// dmac_enable_13 -#ifndef CONF_DMAC_ENABLE_13 -#define CONF_DMAC_ENABLE_13 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_13 -#ifndef CONF_DMAC_TRIGACT_13 -#define CONF_DMAC_TRIGACT_13 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_13 -#ifndef CONF_DMAC_TRIGSRC_13 -#define CONF_DMAC_TRIGSRC_13 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_13 -#ifndef CONF_DMAC_LVL_13 -#define CONF_DMAC_LVL_13 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_13 -#ifndef CONF_DMAC_EVOE_13 -#define CONF_DMAC_EVOE_13 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_13 -#ifndef CONF_DMAC_EVIE_13 -#define CONF_DMAC_EVIE_13 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_13 -#ifndef CONF_DMAC_EVACT_13 -#define CONF_DMAC_EVACT_13 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_13 -#ifndef CONF_DMAC_STEPSIZE_13 -#define CONF_DMAC_STEPSIZE_13 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_13 -#ifndef CONF_DMAC_STEPSEL_13 -#define CONF_DMAC_STEPSEL_13 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_13 -#ifndef CONF_DMAC_SRCINC_13 -#define CONF_DMAC_SRCINC_13 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_13 -#ifndef CONF_DMAC_DSTINC_13 -#define CONF_DMAC_DSTINC_13 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_13 -#ifndef CONF_DMAC_BEATSIZE_13 -#define CONF_DMAC_BEATSIZE_13 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_13 -#ifndef CONF_DMAC_BLOCKACT_13 -#define CONF_DMAC_BLOCKACT_13 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_13 -#ifndef CONF_DMAC_EVOSEL_13 -#define CONF_DMAC_EVOSEL_13 0 -#endif -// - -// Channel 14 settings -// dmac_channel_14_settings -#ifndef CONF_DMAC_CHANNEL_14_SETTINGS -#define CONF_DMAC_CHANNEL_14_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 14 is enabled or not -// dmac_enable_14 -#ifndef CONF_DMAC_ENABLE_14 -#define CONF_DMAC_ENABLE_14 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_14 -#ifndef CONF_DMAC_TRIGACT_14 -#define CONF_DMAC_TRIGACT_14 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_14 -#ifndef CONF_DMAC_TRIGSRC_14 -#define CONF_DMAC_TRIGSRC_14 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_14 -#ifndef CONF_DMAC_LVL_14 -#define CONF_DMAC_LVL_14 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_14 -#ifndef CONF_DMAC_EVOE_14 -#define CONF_DMAC_EVOE_14 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_14 -#ifndef CONF_DMAC_EVIE_14 -#define CONF_DMAC_EVIE_14 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_14 -#ifndef CONF_DMAC_EVACT_14 -#define CONF_DMAC_EVACT_14 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_14 -#ifndef CONF_DMAC_STEPSIZE_14 -#define CONF_DMAC_STEPSIZE_14 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_14 -#ifndef CONF_DMAC_STEPSEL_14 -#define CONF_DMAC_STEPSEL_14 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_14 -#ifndef CONF_DMAC_SRCINC_14 -#define CONF_DMAC_SRCINC_14 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_14 -#ifndef CONF_DMAC_DSTINC_14 -#define CONF_DMAC_DSTINC_14 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_14 -#ifndef CONF_DMAC_BEATSIZE_14 -#define CONF_DMAC_BEATSIZE_14 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_14 -#ifndef CONF_DMAC_BLOCKACT_14 -#define CONF_DMAC_BLOCKACT_14 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_14 -#ifndef CONF_DMAC_EVOSEL_14 -#define CONF_DMAC_EVOSEL_14 0 -#endif -// - -// Channel 15 settings -// dmac_channel_15_settings -#ifndef CONF_DMAC_CHANNEL_15_SETTINGS -#define CONF_DMAC_CHANNEL_15_SETTINGS 0 -#endif - -// Channel Enable -// Indicates whether channel 15 is enabled or not -// dmac_enable_15 -#ifndef CONF_DMAC_ENABLE_15 -#define CONF_DMAC_ENABLE_15 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_15 -#ifndef CONF_DMAC_TRIGACT_15 -#define CONF_DMAC_TRIGACT_15 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> SERCOM0 RX Trigger -// <0x02=> SERCOM0 TX Trigger -// <0x03=> SERCOM1 RX Trigger -// <0x04=> SERCOM1 TX Trigger -// <0x05=> SERCOM2 RX Trigger -// <0x06=> SERCOM2 TX Trigger -// <0x07=> SERCOM3 RX Trigger -// <0x08=> SERCOM3 TX Trigger -// <0x09=> SERCOM4 RX Trigger -// <0x0A=> SERCOM4 TX Trigger -// <0x0B=> SERCOM5 RX Trigger -// <0x0C=> SERCOM5 TX Trigger -// <0x0D=> TCC0 Overflow Trigger -// <0x0E=> TCC0 Match/Compare 0 Trigger -// <0x0F=> TCC0 Match/Compare 1 Trigger -// <0x10=> TCC0 Match/Compare 2 Trigger -// <0x11=> TCC0 Match/Compare 3 Trigger -// <0x12=> TCC1 Overflow Trigger -// <0x13=> TCC1 Match/Compare 0 Trigger -// <0x14=> TCC1 Match/Compare 1 Trigger -// <0x15=> TCC2 Overflow Trigger -// <0x16=> TCC2 Match/Compare 0 Trigger -// <0x17=> TCC2 Match/Compare 1 Trigger -// <0x18=> TC3 Overflow Trigger -// <0x19=> TC3 Match/Compare 0 Trigger -// <0x1A=> TC3 Match/Compare 1 Trigger -// <0x1B=> TC4 Overflow Trigger -// <0x1C=> TC4 Match/Compare 0 Trigger -// <0x1D=> TC4 Match/Compare 1 Trigger -// <0x1E=> TC5 Overflow Trigger -// <0x1F=> TC5 Match/Compare 0 Trigger -// <0x20=> TC5 Match/Compare 1 Trigger -// <0x21=> TC6 Overflow Trigger -// <0x22=> TC6 Match/Compare 0 Trigger -// <0x23=> TC6 Match/Compare 1 Trigger -// <0x24=> TC7 Overflow Trigger -// <0x25=> TC7 Match/Compare 0 Trigger -// <0x26=> TC7 Match/Compare 1 Trigger -// <0x27=> ADC Result Ready Trigger -// <0x28=> DAC Empty Trigger -// <0x29=> I2S Rx 0 Trigger -// <0x2A=> I2S Rx 1 Trigger -// <0x2B=> I2S Tx 0 Trigger -// <0x2C=> I2S Tx 1 Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_15 -#ifndef CONF_DMAC_TRIGSRC_15 -#define CONF_DMAC_TRIGSRC_15 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_15 -#ifndef CONF_DMAC_LVL_15 -#define CONF_DMAC_LVL_15 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_15 -#ifndef CONF_DMAC_EVOE_15 -#define CONF_DMAC_EVOE_15 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_15 -#ifndef CONF_DMAC_EVIE_15 -#define CONF_DMAC_EVIE_15 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_15 -#ifndef CONF_DMAC_EVACT_15 -#define CONF_DMAC_EVACT_15 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_15 -#ifndef CONF_DMAC_STEPSIZE_15 -#define CONF_DMAC_STEPSIZE_15 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_15 -#ifndef CONF_DMAC_STEPSEL_15 -#define CONF_DMAC_STEPSEL_15 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_15 -#ifndef CONF_DMAC_SRCINC_15 -#define CONF_DMAC_SRCINC_15 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_15 -#ifndef CONF_DMAC_DSTINC_15 -#define CONF_DMAC_DSTINC_15 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_15 -#ifndef CONF_DMAC_BEATSIZE_15 -#define CONF_DMAC_BEATSIZE_15 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_15 -#ifndef CONF_DMAC_BLOCKACT_15 -#define CONF_DMAC_BLOCKACT_15 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_15 -#ifndef CONF_DMAC_EVOSEL_15 -#define CONF_DMAC_EVOSEL_15 0 -#endif -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_DMAC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_gclk_config.h b/atmel-samd/asf4/samd21/config/hpl_gclk_config.h deleted file mode 100644 index 790aa293a..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_gclk_config.h +++ /dev/null @@ -1,618 +0,0 @@ -/* Auto-generated config file hpl_gclk_config.h */ -#ifndef HPL_GCLK_CONFIG_H -#define HPL_GCLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Generic clock generator 0 configuration -// Indicates whether generic clock 0 configuration is enabled or not -// enable_gclk_gen_0 -#ifndef CONF_GCLK_GENERATOR_0_CONFIG -#define CONF_GCLK_GENERATOR_0_CONFIG 1 -#endif - -// Generic Clock Generator Control -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_0_RUNSTDBY -#ifndef CONF_GCLK_GEN_0_RUNSTDBY -#define CONF_GCLK_GEN_0_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_0_div_sel -#ifndef CONF_GCLK_GEN_0_DIVSEL -#define CONF_GCLK_GEN_0_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_0_oe -#ifndef CONF_GCLK_GEN_0_OE -#define CONF_GCLK_GEN_0_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_0_oov -#ifndef CONF_GCLK_GEN_0_OOV -#define CONF_GCLK_GEN_0_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_0_idc -#ifndef CONF_GCLK_GEN_0_IDC -#define CONF_GCLK_GEN_0_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_0_enable -#ifndef CONF_GCLK_GEN_0_GENEN -#define CONF_GCLK_GEN_0_GENEN 1 -#endif - -// Generic clock generator 0 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 8MHz Internal Oscillator (OSC8M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 0 -// gclk_gen_0_oscillator -#ifndef CONF_GCLK_GEN_0_SRC -#define CONF_GCLK_GEN_0_SRC GCLK_GENCTRL_SRC_OSC8M -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 0 division <0x0000-0xFFFF> -// -// gclk_gen_0_div -#ifndef CONF_GCLK_GEN_0_DIV -#define CONF_GCLK_GEN_0_DIV 1 -#endif - -// -// // Generic clock generator 1 configuration -// Indicates whether generic clock 1 configuration is enabled or not -// enable_gclk_gen_1 -#ifndef CONF_GCLK_GENERATOR_1_CONFIG -#define CONF_GCLK_GENERATOR_1_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_1_RUNSTDBY -#ifndef CONF_GCLK_GEN_1_RUNSTDBY -#define CONF_GCLK_GEN_1_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_1_div_sel -#ifndef CONF_GCLK_GEN_1_DIVSEL -#define CONF_GCLK_GEN_1_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_1_oe -#ifndef CONF_GCLK_GEN_1_OE -#define CONF_GCLK_GEN_1_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_1_oov -#ifndef CONF_GCLK_GEN_1_OOV -#define CONF_GCLK_GEN_1_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_1_idc -#ifndef CONF_GCLK_GEN_1_IDC -#define CONF_GCLK_GEN_1_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_1_enable -#ifndef CONF_GCLK_GEN_1_GENEN -#define CONF_GCLK_GEN_1_GENEN 0 -#endif - -// Generic clock generator 1 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 8MHz Internal Oscillator (OSC8M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 1 -// gclk_gen_1_oscillator -#ifndef CONF_GCLK_GEN_1_SRC -#define CONF_GCLK_GEN_1_SRC GCLK_GENCTRL_SRC_XOSC -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 1 division <0x0000-0xFFFF> -// -// gclk_gen_1_div -#ifndef CONF_GCLK_GEN_1_DIV -#define CONF_GCLK_GEN_1_DIV 1 -#endif - -// -// // Generic clock generator 2 configuration -// Indicates whether generic clock 2 configuration is enabled or not -// enable_gclk_gen_2 -#ifndef CONF_GCLK_GENERATOR_2_CONFIG -#define CONF_GCLK_GENERATOR_2_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_2_RUNSTDBY -#ifndef CONF_GCLK_GEN_2_RUNSTDBY -#define CONF_GCLK_GEN_2_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_2_div_sel -#ifndef CONF_GCLK_GEN_2_DIVSEL -#define CONF_GCLK_GEN_2_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_2_oe -#ifndef CONF_GCLK_GEN_2_OE -#define CONF_GCLK_GEN_2_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_2_oov -#ifndef CONF_GCLK_GEN_2_OOV -#define CONF_GCLK_GEN_2_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_2_idc -#ifndef CONF_GCLK_GEN_2_IDC -#define CONF_GCLK_GEN_2_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_2_enable -#ifndef CONF_GCLK_GEN_2_GENEN -#define CONF_GCLK_GEN_2_GENEN 0 -#endif - -// Generic clock generator 2 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 8MHz Internal Oscillator (OSC8M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 2 -// gclk_gen_2_oscillator -#ifndef CONF_GCLK_GEN_2_SRC -#define CONF_GCLK_GEN_2_SRC GCLK_GENCTRL_SRC_XOSC -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 2 division <0x0000-0xFFFF> -// -// gclk_gen_2_div -#ifndef CONF_GCLK_GEN_2_DIV -#define CONF_GCLK_GEN_2_DIV 1 -#endif - -// -// // Generic clock generator 3 configuration -// Indicates whether generic clock 3 configuration is enabled or not -// enable_gclk_gen_3 -#ifndef CONF_GCLK_GENERATOR_3_CONFIG -#define CONF_GCLK_GENERATOR_3_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_3_RUNSTDBY -#ifndef CONF_GCLK_GEN_3_RUNSTDBY -#define CONF_GCLK_GEN_3_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_3_div_sel -#ifndef CONF_GCLK_GEN_3_DIVSEL -#define CONF_GCLK_GEN_3_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_3_oe -#ifndef CONF_GCLK_GEN_3_OE -#define CONF_GCLK_GEN_3_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_3_oov -#ifndef CONF_GCLK_GEN_3_OOV -#define CONF_GCLK_GEN_3_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_3_idc -#ifndef CONF_GCLK_GEN_3_IDC -#define CONF_GCLK_GEN_3_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_3_enable -#ifndef CONF_GCLK_GEN_3_GENEN -#define CONF_GCLK_GEN_3_GENEN 0 -#endif - -// Generic clock generator 3 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 8MHz Internal Oscillator (OSC8M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 3 -// gclk_gen_3_oscillator -#ifndef CONF_GCLK_GEN_3_SRC -#define CONF_GCLK_GEN_3_SRC GCLK_GENCTRL_SRC_XOSC -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 3 division <0x0000-0xFFFF> -// -// gclk_gen_3_div -#ifndef CONF_GCLK_GEN_3_DIV -#define CONF_GCLK_GEN_3_DIV 1 -#endif - -// -// // Generic clock generator 4 configuration -// Indicates whether generic clock 4 configuration is enabled or not -// enable_gclk_gen_4 -#ifndef CONF_GCLK_GENERATOR_4_CONFIG -#define CONF_GCLK_GENERATOR_4_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_4_RUNSTDBY -#ifndef CONF_GCLK_GEN_4_RUNSTDBY -#define CONF_GCLK_GEN_4_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_4_div_sel -#ifndef CONF_GCLK_GEN_4_DIVSEL -#define CONF_GCLK_GEN_4_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_4_oe -#ifndef CONF_GCLK_GEN_4_OE -#define CONF_GCLK_GEN_4_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_4_oov -#ifndef CONF_GCLK_GEN_4_OOV -#define CONF_GCLK_GEN_4_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_4_idc -#ifndef CONF_GCLK_GEN_4_IDC -#define CONF_GCLK_GEN_4_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_4_enable -#ifndef CONF_GCLK_GEN_4_GENEN -#define CONF_GCLK_GEN_4_GENEN 0 -#endif - -// Generic clock generator 4 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 8MHz Internal Oscillator (OSC8M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 4 -// gclk_gen_4_oscillator -#ifndef CONF_GCLK_GEN_4_SRC -#define CONF_GCLK_GEN_4_SRC GCLK_GENCTRL_SRC_XOSC -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 4 division <0x0000-0xFFFF> -// -// gclk_gen_4_div -#ifndef CONF_GCLK_GEN_4_DIV -#define CONF_GCLK_GEN_4_DIV 1 -#endif - -// -// // Generic clock generator 5 configuration -// Indicates whether generic clock 5 configuration is enabled or not -// enable_gclk_gen_5 -#ifndef CONF_GCLK_GENERATOR_5_CONFIG -#define CONF_GCLK_GENERATOR_5_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_5_RUNSTDBY -#ifndef CONF_GCLK_GEN_5_RUNSTDBY -#define CONF_GCLK_GEN_5_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_5_div_sel -#ifndef CONF_GCLK_GEN_5_DIVSEL -#define CONF_GCLK_GEN_5_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_5_oe -#ifndef CONF_GCLK_GEN_5_OE -#define CONF_GCLK_GEN_5_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_5_oov -#ifndef CONF_GCLK_GEN_5_OOV -#define CONF_GCLK_GEN_5_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_5_idc -#ifndef CONF_GCLK_GEN_5_IDC -#define CONF_GCLK_GEN_5_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_5_enable -#ifndef CONF_GCLK_GEN_5_GENEN -#define CONF_GCLK_GEN_5_GENEN 0 -#endif - -// Generic clock generator 5 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 8MHz Internal Oscillator (OSC8M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 5 -// gclk_gen_5_oscillator -#ifndef CONF_GCLK_GEN_5_SRC -#define CONF_GCLK_GEN_5_SRC GCLK_GENCTRL_SRC_XOSC -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 5 division <0x0000-0xFFFF> -// -// gclk_gen_5_div -#ifndef CONF_GCLK_GEN_5_DIV -#define CONF_GCLK_GEN_5_DIV 1 -#endif - -// -// // Generic clock generator 6 configuration -// Indicates whether generic clock 6 configuration is enabled or not -// enable_gclk_gen_6 -#ifndef CONF_GCLK_GENERATOR_6_CONFIG -#define CONF_GCLK_GENERATOR_6_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_6_RUNSTDBY -#ifndef CONF_GCLK_GEN_6_RUNSTDBY -#define CONF_GCLK_GEN_6_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_6_div_sel -#ifndef CONF_GCLK_GEN_6_DIVSEL -#define CONF_GCLK_GEN_6_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_6_oe -#ifndef CONF_GCLK_GEN_6_OE -#define CONF_GCLK_GEN_6_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_6_oov -#ifndef CONF_GCLK_GEN_6_OOV -#define CONF_GCLK_GEN_6_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_6_idc -#ifndef CONF_GCLK_GEN_6_IDC -#define CONF_GCLK_GEN_6_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_6_enable -#ifndef CONF_GCLK_GEN_6_GENEN -#define CONF_GCLK_GEN_6_GENEN 0 -#endif - -// Generic clock generator 6 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 8MHz Internal Oscillator (OSC8M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 6 -// gclk_gen_6_oscillator -#ifndef CONF_GCLK_GEN_6_SRC -#define CONF_GCLK_GEN_6_SRC GCLK_GENCTRL_SRC_XOSC -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 6 division <0x0000-0xFFFF> -// -// gclk_gen_6_div -#ifndef CONF_GCLK_GEN_6_DIV -#define CONF_GCLK_GEN_6_DIV 1 -#endif - -// -// // Generic clock generator 7 configuration -// Indicates whether generic clock 7 configuration is enabled or not -// enable_gclk_gen_7 -#ifndef CONF_GCLK_GENERATOR_7_CONFIG -#define CONF_GCLK_GENERATOR_7_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_7_RUNSTDBY -#ifndef CONF_GCLK_GEN_7_RUNSTDBY -#define CONF_GCLK_GEN_7_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_7_div_sel -#ifndef CONF_GCLK_GEN_7_DIVSEL -#define CONF_GCLK_GEN_7_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_7_oe -#ifndef CONF_GCLK_GEN_7_OE -#define CONF_GCLK_GEN_7_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_7_oov -#ifndef CONF_GCLK_GEN_7_OOV -#define CONF_GCLK_GEN_7_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_7_idc -#ifndef CONF_GCLK_GEN_7_IDC -#define CONF_GCLK_GEN_7_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_7_enable -#ifndef CONF_GCLK_GEN_7_GENEN -#define CONF_GCLK_GEN_7_GENEN 0 -#endif - -// Generic clock generator 7 source -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz High Accuracy Internal Oscillator (OSC32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// 8MHz Internal Oscillator (OSC8M) -// Digital Frequency Locked Loop (DFLL48M) -// Fractional Digital Phase Locked Loop (FDPLL96M) -// This defines the clock source for generic clock generator 7 -// gclk_gen_7_oscillator -#ifndef CONF_GCLK_GEN_7_SRC -#define CONF_GCLK_GEN_7_SRC GCLK_GENCTRL_SRC_XOSC -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 7 division <0x0000-0xFFFF> -// -// gclk_gen_7_div -#ifndef CONF_GCLK_GEN_7_DIV -#define CONF_GCLK_GEN_7_DIV 1 -#endif - -// -// - -// <<< end of configuration section >>> - -#endif // HPL_GCLK_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h b/atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h deleted file mode 100644 index 88d6bb93f..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_nvmctrl_config.h +++ /dev/null @@ -1,38 +0,0 @@ -/* Auto-generated config file hpl_nvmctrl_config.h */ -#ifndef HPL_NVMCTRL_CONFIG_H -#define HPL_NVMCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic Settings - -// Read Mode Selection -// <0x00=> No Miss Penalty -// <0x01=> Low Power -// <0x02=> Deterministic -// nvm_arch_read_mode -#ifndef CONF_NVM_READ_MODE -#define CONF_NVM_READ_MODE 0 -#endif - -// Power Reduction Mode During Sleep -// <0x00=> Wake On Access -// <0x01=> Wake Up Instant -// <0x03=> Disabled -// nvm_arch_sleepprm -#ifndef CONF_NVM_SLEEPPRM -#define CONF_NVM_SLEEPPRM 0 -#endif - -// Cache Disable -// Indicate whether cache is disable or not -// nvm_arch_cache -#ifndef CONF_NVM_CACHE -#define CONF_NVM_CACHE 0 -#endif - -// - -// <<< end of configuration section >>> - -#endif // HPL_NVMCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_pm_config.h b/atmel-samd/asf4/samd21/config/hpl_pm_config.h deleted file mode 100644 index b4c704d12..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_pm_config.h +++ /dev/null @@ -1,134 +0,0 @@ -/* Auto-generated config file hpl_pm_config.h */ -#ifndef HPL_PM_CONFIG_H -#define HPL_PM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -// System Configuration -// Indicates whether configuration for system is enabled or not -// enable_cpu_clock -#ifndef CONF_SYSTEM_CONFIG -#define CONF_SYSTEM_CONFIG 1 -#endif - -// CPU Clock Settings -// CPU Clock source -// Generic clock generator 0 -// This defines the clock source for the CPU -// cpu_clock_source -#ifndef CONF_CPU_SRC -#define CONF_CPU_SRC GCLK_CLKCTRL_GEN_GCLK0_Val -#endif - -// CPU clock Prescalar -// 1 -// 2 -// 4 -// 8 -// 16 -// 32 -// 64 -// 128 -// Prescalar for Main CPU clock -// cpu_div -#ifndef CONF_CPU_DIV -#define CONF_CPU_DIV PM_CPUSEL_CPUDIV_DIV1_Val -#endif -// - -// NVM Settings -// NVM Wait States -// These bits select the number of wait states for a read operation. -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 -// <8=> 8 -// <9=> 9 -// <10=> 10 -// <11=> 11 -// <12=> 12 -// <13=> 13 -// <14=> 14 -// <15=> 15 -// nvm_wait_states -#ifndef CONF_NVM_WAIT_STATE -#define CONF_NVM_WAIT_STATE 0 -#endif - -// - -// APBA Clock Select -// APBA clock prescalar -// 1 -// 2 -// 4 -// 8 -// 16 -// 32 -// 64 -// 128 -// APBA clock prescalar -// apba_div -#ifndef CONF_APBA_DIV -#define CONF_APBA_DIV PM_APBASEL_APBADIV_DIV1 -#endif -// - -#if CONF_APBA_DIV < CONF_CPU_DIV -#warning APBA DIV cannot less than CPU DIV -#endif - -// APBB Clock Select -// APBB clock prescalar -// 1 -// 2 -// 4 -// 8 -// 16 -// 32 -// 64 -// 128 -// APBB clock prescalar -// apbb_div -#ifndef CONF_APBB_DIV -#define CONF_APBB_DIV PM_APBBSEL_APBBDIV_DIV1 -#endif -// - -#if CONF_APBB_DIV < CONF_CPU_DIV -#warning APBB DIV cannot less than CPU DIV -#endif - -// APBC Clock Select -// APBC clock prescalar -// 1 -// 2 -// 4 -// 8 -// 16 -// 32 -// 64 -// 128 -// APBC clock prescalar -// apbc_div -#ifndef CONF_APBC_DIV -#define CONF_APBC_DIV PM_APBCSEL_APBCDIV_DIV1 -#endif -// - -#if CONF_APBC_DIV < CONF_CPU_DIV -#warning APBC DIV cannot less than CPU DIV -#endif - -// - -// <<< end of configuration section >>> - -#endif // HPL_PM_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_rtc_config.h b/atmel-samd/asf4/samd21/config/hpl_rtc_config.h deleted file mode 100644 index 929c70c8c..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_rtc_config.h +++ /dev/null @@ -1,117 +0,0 @@ -/* Auto-generated config file hpl_rtc_config.h */ -#ifndef HPL_RTC_CONFIG_H -#define HPL_RTC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic settings - -#ifndef CONF_RTC_ENABLE -#define CONF_RTC_ENABLE 1 -#endif - -// Prescaler configuration -// <0x0=>Peripheral clock divided by 1 -// <0x1=>Peripheral clock divided by 2 -// <0x2=>Peripheral clock divided by 4 -// <0x3=>Peripheral clock divided by 8 -// <0x4=>Peripheral clock divided by 16 -// <0x5=>Peripheral clock divided by 32 -// <0x6=>Peripheral clock divided by 64 -// <0x7=>Peripheral clock divided by 128 -// <0x8=>Peripheral clock divided by 256 -// <0x9=>Peripheral clock divided by 512 -// <0xA=>Peripheral clock divided by 1024 -// These bits define the RTC clock relative to the peripheral clock -// rtc_arch_prescaler -#ifndef CONF_RTC_PRESCALER -#define CONF_RTC_PRESCALER 0x0 - -#endif - -// Compare Value <1-4294967295> -// These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), -// by default 1M clock input, 1 prescaler, 1024 compare value, the ticks period equals to 1ms. -// rtc_arch_comp_val - -#ifndef CONF_RTC_COMP_VAL -#define CONF_RTC_COMP_VAL 1024 - -#endif - -// Event control -// rtc_event_control -#ifndef CONF_RTC_EVENT_CONTROL_ENABLE -#define CONF_RTC_EVENT_CONTROL_ENABLE 0 -#endif - -// Periodic Interval 0 Event Output -// This bit indicates whether Periodic interval 0 event is enabled and will be generated -// rtc_pereo0 -#ifndef CONF_RTC_PEREO0 -#define CONF_RTC_PEREO0 0 -#endif -// Periodic Interval 1 Event Output -// This bit indicates whether Periodic interval 1 event is enabled and will be generated -// rtc_pereo1 -#ifndef CONF_RTC_PEREO1 -#define CONF_RTC_PEREO1 0 -#endif -// Periodic Interval 2 Event Output -// This bit indicates whether Periodic interval 2 event is enabled and will be generated -// rtc_pereo2 -#ifndef CONF_RTC_PEREO2 -#define CONF_RTC_PEREO2 0 -#endif -// Periodic Interval 3 Event Output -// This bit indicates whether Periodic interval 3 event is enabled and will be generated -// rtc_pereo3 -#ifndef CONF_RTC_PEREO3 -#define CONF_RTC_PEREO3 0 -#endif -// Periodic Interval 4 Event Output -// This bit indicates whether Periodic interval 4 event is enabled and will be generated -// rtc_pereo4 -#ifndef CONF_RTC_PEREO4 -#define CONF_RTC_PEREO4 0 -#endif -// Periodic Interval 5 Event Output -// This bit indicates whether Periodic interval 5 event is enabled and will be generated -// rtc_pereo5 -#ifndef CONF_RTC_PEREO5 -#define CONF_RTC_PEREO5 0 -#endif -// Periodic Interval 6 Event Output -// This bit indicates whether Periodic interval 6 event is enabled and will be generated -// rtc_pereo6 -#ifndef CONF_RTC_PEREO6 -#define CONF_RTC_PEREO6 0 -#endif -// Periodic Interval 7 Event Output -// This bit indicates whether Periodic interval 7 event is enabled and will be generated -// rtc_pereo7 -#ifndef CONF_RTC_PEREO7 -#define CONF_RTC_PEREO7 0 -#endif - -// Compare 0 Event Output -// This bit indicates whether Compare O event is enabled and will be generated -// rtc_cmpeo0 -#ifndef CONF_RTC_COMPE0 -#define CONF_RTC_COMPE0 0 -#endif - -// Overflow Event Output -// This bit indicates whether Overflow event is enabled and will be generated -// rtc_ovfeo -#ifndef CONF_RTC_OVFEO -#define CONF_RTC_OVFEO 0 -#endif - -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_RTC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_sercom_config.h b/atmel-samd/asf4/samd21/config/hpl_sercom_config.h deleted file mode 100644 index 50515745d..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_sercom_config.h +++ /dev/null @@ -1,534 +0,0 @@ -/* Auto-generated config file hpl_sercom_config.h */ -#ifndef HPL_SERCOM_CONFIG_H -#define HPL_SERCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -// Enable configuration of module -#ifndef CONF_SERCOM_0_SPI_ENABLE -#define CONF_SERCOM_0_SPI_ENABLE 1 -#endif - -// Set module in SPI Master mode -#ifndef CONF_SERCOM_0_SPI_MODE -#define CONF_SERCOM_0_SPI_MODE 0x03 -#endif - -// Basic Configuration - -// Receive buffer enable -// Enable receive buffer to receive data from slave (RXEN) -// spi_master_rx_enable -#ifndef CONF_SERCOM_0_SPI_RXEN -#define CONF_SERCOM_0_SPI_RXEN 0x1 -#endif - -// Character Size -// Bit size for all characters sent over the SPI bus (CHSIZE) -// <0x0=>8 bits -// <0x1=>9 bits -// spi_master_character_size -#ifndef CONF_SERCOM_0_SPI_CHSIZE -#define CONF_SERCOM_0_SPI_CHSIZE 0x0 -#endif - -// Baud rate <1-12000000> -// The SPI data transfer rate -// spi_master_baud_rate -#ifndef CONF_SERCOM_0_SPI_BAUD -#define CONF_SERCOM_0_SPI_BAUD 50000 -#endif - -// - -// Advanced Configuration -// spi_master_advanced -#ifndef CONF_SERCOM_0_SPI_ADVANCED -#define CONF_SERCOM_0_SPI_ADVANCED 0 -#endif - -// Dummy byte <0x00-0x1ff> -// spi_master_dummybyte -// Dummy byte used when reading data from the slave without sending any data -#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE -#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff -#endif - -// Data Order -// <0=>MSB first -// <1=>LSB first -// I least significant or most significant bit is shifted out first (DORD) -// spi_master_arch_dord -#ifndef CONF_SERCOM_0_SPI_DORD -#define CONF_SERCOM_0_SPI_DORD 0x0 -#endif - -// Clock Polarity -// <0=>SCK is low when idle -// <1=>SCK is high when idle -// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) -// spi_master_arch_cpol -#ifndef CONF_SERCOM_0_SPI_CPOL -#define CONF_SERCOM_0_SPI_CPOL 0x0 -#endif - -// Clock Phase -// <0x0=>Sample input on leading edge -// <0x1=>Sample input on trailing edge -// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) -// spi_master_arch_cpha -#ifndef CONF_SERCOM_0_SPI_CPHA -#define CONF_SERCOM_0_SPI_CPHA 0x0 -#endif - -// Immediate Buffer Overflow Notification -// Controls when OVF is asserted (IBON) -// <0x0=>In data stream -// <0x1=>On buffer overflow -// spi_master_arch_ibon -#ifndef CONF_SERCOM_0_SPI_IBON -#define CONF_SERCOM_0_SPI_IBON 0x0 -#endif - -// Run in stand-by -// Module stays active in stand-by sleep mode. (RUNSTDBY) -// spi_master_arch_runstdby -#ifndef CONF_SERCOM_0_SPI_RUNSTDBY -#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) -// <0=>Keep running -// <1=>Halt -// spi_master_arch_dbgstop -#ifndef CONF_SERCOM_0_SPI_DBGSTOP -#define CONF_SERCOM_0_SPI_DBGSTOP 0 -#endif - -// - -// Address mode disabled in master mode -#ifndef CONF_SERCOM_0_SPI_AMODE_EN -#define CONF_SERCOM_0_SPI_AMODE_EN 0 -#endif - -#ifndef CONF_SERCOM_0_SPI_AMODE -#define CONF_SERCOM_0_SPI_AMODE 0 -#endif - -#ifndef CONF_SERCOM_0_SPI_ADDR -#define CONF_SERCOM_0_SPI_ADDR 0 -#endif - -#ifndef CONF_SERCOM_0_SPI_ADDRMASK -#define CONF_SERCOM_0_SPI_ADDRMASK 0 -#endif - -#ifndef CONF_SERCOM_0_SPI_SSDE -#define CONF_SERCOM_0_SPI_SSDE 0 -#endif - -#ifndef CONF_SERCOM_0_SPI_MSSEN -#define CONF_SERCOM_0_SPI_MSSEN 0x0 -#endif - -#ifndef CONF_SERCOM_0_SPI_PLOADEN -#define CONF_SERCOM_0_SPI_PLOADEN 0 -#endif - -// Receive Data Pinout -// <0x0=>PAD[0] -// <0x1=>PAD[1] -// <0x2=>PAD[2] -// <0x3=>PAD[3] -// spi_master_rxpo -#ifndef CONF_SERCOM_0_SPI_RXPO -#define CONF_SERCOM_0_SPI_RXPO 2 -#endif - -// Transmit Data Pinout -// <0x0=>PAD[0,1]_DO_SCK -// <0x1=>PAD[2,3]_DO_SCK -// <0x2=>PAD[3,1]_DO_SCK -// <0x3=>PAD[0,3]_DO_SCK -// spi_master_txpo -#ifndef CONF_SERCOM_0_SPI_TXPO -#define CONF_SERCOM_0_SPI_TXPO 0 -#endif - -// Calculate baud register value from requested baudrate value -#ifndef CONF_SERCOM_0_SPI_BAUD_RATE -#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1 -#endif - -#include - -#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER -#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) -#endif - -#ifndef CONF_SERCOM_1_I2CM_ENABLE -#define CONF_SERCOM_1_I2CM_ENABLE 1 -#endif - -// Basic - -// I2C Bus clock speed (Hz) <1-400000> -// I2C Bus clock (SCL) speed measured in Hz -// i2c_master_baud_rate -#ifndef CONF_SERCOM_1_I2CM_BAUD -#define CONF_SERCOM_1_I2CM_BAUD 100000 -#endif - -// - -// Advanced -// i2c_master_advanced -#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG -#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0 -#endif - -// TRise (ns) <0-300> -// Determined by the bus impedance, check electric characteristics in the datasheet -// Standard Fast Mode: typical 215ns, max 300ns -// Fast Mode +: typical 60ns, max 100ns -// High Speed Mode: typical 20ns, max 40ns -// i2c_master_arch_trise - -#ifndef CONF_SERCOM_1_I2CM_TRISE -#define CONF_SERCOM_1_I2CM_TRISE 215 -#endif - -// Master SCL Low Extended Time-Out (MEXTTOEN) -// This enables the master SCL low extend time-out -// i2c_master_arch_mexttoen -#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN -#define CONF_SERCOM_1_I2CM_MEXTTOEN 0 -#endif - -// Slave SCL Low Extend Time-Out (SEXTTOEN) -// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine -// i2c_master_arch_sexttoen -#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN -#define CONF_SERCOM_1_I2CM_SEXTTOEN 0 -#endif - -// SCL Low Time-Out (LOWTOUT) -// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold -// i2c_master_arch_lowtout -#ifndef CONF_SERCOM_1_I2CM_LOWTOUT -#define CONF_SERCOM_1_I2CM_LOWTOUT 0 -#endif - -// Inactive Time-Out (INACTOUT) -// <0x0=>Disabled -// <0x1=>5-6 SCL cycle time-out(50-60us) -// <0x2=>10-11 SCL cycle time-out(100-110us) -// <0x3=>20-21 SCL cycle time-out(200-210us) -// Defines if inactivity time-out should be enabled, and how long the time-out should be -// i2c_master_arch_inactout -#ifndef CONF_SERCOM_1_I2CM_INACTOUT -#define CONF_SERCOM_1_I2CM_INACTOUT 0x0 -#endif - -// SDA Hold Time (SDAHOLD) -// <0=>Disabled -// <1=>50-100ns hold time -// <2=>300-600ns hold time -// <3=>400-800ns hold time -// Defines the SDA hold time with respect to the negative edge of SCL -// i2c_master_arch_sdahold -#ifndef CONF_SERCOM_1_I2CM_SDAHOLD -#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2 -#endif - -// Run in stand-by -// Determine if the module shall run in standby sleep mode -// i2c_master_arch_runstdby -#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY -#define CONF_SERCOM_1_I2CM_RUNSTDBY 0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. -// <0=>Keep running -// <1=>Halt -// i2c_master_arch_dbgstop -#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE -#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0 -#endif - -// - -#ifndef CONF_SERCOM_1_I2CM_SPEED -#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode -#endif -#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300 -#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns -#undef CONF_SERCOM_1_I2CM_TRISE -#define CONF_SERCOM_1_I2CM_TRISE 215 -#endif - -// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) -// BAUD + BAUDLOW = -------------------------------------------------------------------- -// i2c_scl_freq -// BAUD: register value low [7:0] -// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW -#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10) \ - - (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000) \ - / 1000)) \ - * 10 \ - + 5) \ - / (CONF_SERCOM_1_I2CM_BAUD * 10)) -#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE -#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2) -#warning Requested I2C baudrate too low, please check -#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF -#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1 -#warning Requested I2C baudrate too high, please check -#define CONF_SERCOM_1_I2CM_BAUD_RATE 1 -#else -#define CONF_SERCOM_1_I2CM_BAUD_RATE \ - ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2)) -#endif -#endif - -#include - -#ifndef CONF_SERCOM_2_USART_ENABLE -#define CONF_SERCOM_2_USART_ENABLE 1 -#endif - -// Basic Configuration - -// Receive buffer enable -// Enable input buffer in SERCOM module -// usart_rx_enable -#ifndef CONF_SERCOM_2_USART_RXEN -#define CONF_SERCOM_2_USART_RXEN 1 -#endif - -// Transmitt buffer enable -// Enable output buffer in SERCOM module -// usart_tx_enable -#ifndef CONF_SERCOM_2_USART_TXEN -#define CONF_SERCOM_2_USART_TXEN 1 -#endif - -// Frame parity -// <0x0=>No parity -// <0x1=>Even parity -// <0x2=>Odd parity -// Parity bit mode for USART frame -// usart_parity -#ifndef CONF_SERCOM_2_USART_PARITY -#define CONF_SERCOM_2_USART_PARITY 0x0 -#endif - -// Character Size -// <0x0=>8 bits -// <0x1=>9 bits -// <0x5=>5 bits -// <0x6=>6 bits -// <0x7=>7 bits -// Data character size in USART frame -// usart_character_size -#ifndef CONF_SERCOM_2_USART_CHSIZE -#define CONF_SERCOM_2_USART_CHSIZE 0x0 -#endif - -// Stop Bit -// <0=>One stop bit -// <1=>Two stop bits -// Number of stop bits in USART frame -// usart_stop_bit -#ifndef CONF_SERCOM_2_USART_SBMODE -#define CONF_SERCOM_2_USART_SBMODE 0 -#endif - -// Baud rate <1-3000000> -// USART baud rate setting -// usart_baud_rate -#ifndef CONF_SERCOM_2_USART_BAUD -#define CONF_SERCOM_2_USART_BAUD 9600 -#endif - -// - -// Advanced configuration -// usart_advanced -#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG -#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0 -#endif - -// Run in stand-by -// Keep the module running in standby sleep mode -// usart_arch_runstdby -#ifndef CONF_SERCOM_2_USART_RUNSTDBY -#define CONF_SERCOM_2_USART_RUNSTDBY 0 -#endif - -// Immediate Buffer Overflow Notification -// Controls when the BUFOVF status bit is asserted -// usart_arch_ibon -#ifndef CONF_SERCOM_2_USART_IBON -#define CONF_SERCOM_2_USART_IBON 0 -#endif - -// Start of Frame Detection Enable -// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) -// usart_arch_sfde -#ifndef CONF_SERCOM_2_USART_SFDE -#define CONF_SERCOM_2_USART_SFDE 0 -#endif - -// Collision Detection Enable -// Collision detection enable -// usart_arch_cloden -#ifndef CONF_SERCOM_2_USART_CLODEN -#define CONF_SERCOM_2_USART_CLODEN 0 -#endif - -// Operating Mode -// <0x0=>USART with external clock -// <0x1=>USART with internal clock -// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. -// usart_arch_clock_mode -#ifndef CONF_SERCOM_2_USART_MODE -#define CONF_SERCOM_2_USART_MODE 0x1 -#endif - -// Sample Rate -// <0x0=>16x arithmetic -// <0x1=>16x fractional -// <0x2=>8x arithmetic -// <0x3=>8x fractional -// <0x3=>3x -// How many over-sampling bits used when samling data state -// usart_arch_sampr -#ifndef CONF_SERCOM_2_USART_SAMPR -#define CONF_SERCOM_2_USART_SAMPR 0x0 -#endif - -// Sample Adjustment -// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) -// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) -// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) -// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) -// Adjust which samples to use for data sampling in asynchronous mode -// usart_arch_sampa -#ifndef CONF_SERCOM_2_USART_SAMPA -#define CONF_SERCOM_2_USART_SAMPA 0x0 -#endif - -// Fractional Part <0-7> -// Fractional part of the baud rate if baud rate generator is in fractional mode -// usart_arch_fractional -#ifndef CONF_SERCOM_2_USART_FRACTIONAL -#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 -#endif - -// Data Order -// <0=>MSB is transmitted first -// <1=>LSB is transmitted first -// Data order of the data bits in the frame -// usart_arch_dord -#ifndef CONF_SERCOM_2_USART_DORD -#define CONF_SERCOM_2_USART_DORD 1 -#endif - -// Does not do anything in UART mode -#define CONF_SERCOM_2_USART_CPOL 0 - -// Encoding Format -// <0=>No encoding -// <1=>IrDA encoded -// usart_arch_enc -#ifndef CONF_SERCOM_2_USART_ENC -#define CONF_SERCOM_2_USART_ENC 0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. -// <0=>Keep running -// <1=>Halt -// usart_arch_dbgstop -#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE -#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 -#endif - -// - -#ifndef CONF_SERCOM_2_USART_CMODE -#define CONF_SERCOM_2_USART_CMODE 0 -#endif - -#ifndef CONF_SERCOM_2_USART_RXPO -#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PA09 */ -#endif - -#ifndef CONF_SERCOM_2_USART_TXPO -#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PA08 */ -#endif - -/* Set correct parity settings in register interface based on PARITY setting */ -#if CONF_SERCOM_2_USART_PARITY == 0 -#define CONF_SERCOM_2_USART_PMODE 0 -#define CONF_SERCOM_2_USART_FORM 0 -#else -#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 -#define CONF_SERCOM_2_USART_FORM 1 -#endif - -// Calculate BAUD register value in UART mode -#if CONF_SERCOM_2_USART_SAMPR == 0 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_2_USART_SAMPR == 1 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) -#endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_2_USART_SAMPR == 2 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_2_USART_SAMPR == 3 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) -#endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_2_USART_SAMPR == 4 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#endif - -// <<< end of configuration section >>> - -#endif // HPL_SERCOM_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h b/atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h deleted file mode 100644 index ab4c48d52..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_sysctrl_config.h +++ /dev/null @@ -1,678 +0,0 @@ -/* Auto-generated config file hpl_sysctrl_config.h */ -#ifndef HPL_SYSCTRL_CONFIG_H -#define HPL_SYSCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#define CONF_DFLL_OPEN_LOOP_MODE 0 -#define CONF_DFLL_CLOSED_LOOP_MODE 1 - -#define CONF_XOSC_STARTUP_TIME_31MCS 0 -#define CONF_XOSC_STARTUP_TIME_61MCS 1 -#define CONF_XOSC_STARTUP_TIME_122MCS 2 -#define CONF_XOSC_STARTUP_TIME_244MCS 3 -#define CONF_XOSC_STARTUP_TIME_488MCS 4 -#define CONF_XOSC_STARTUP_TIME_977MCS 5 -#define CONF_XOSC_STARTUP_TIME_1953MCS 6 -#define CONF_XOSC_STARTUP_TIME_3906MCS 7 -#define CONF_XOSC_STARTUP_TIME_7813MCS 8 -#define CONF_XOSC_STARTUP_TIME_15625MCS 9 -#define CONF_XOSC_STARTUP_TIME_31250MCS 10 -#define CONF_XOSC_STARTUP_TIME_62500MCS 11 -#define CONF_XOSC_STARTUP_TIME_125000MCS 12 -#define CONF_XOSC_STARTUP_TIME_250000MCS 13 -#define CONF_XOSC_STARTUP_TIME_500000MCS 14 -#define CONF_XOSC_STARTUP_TIME_1000000MCS 15 - -#define CONF_OSC_STARTUP_TIME_92MCS 0 -#define CONF_OSC_STARTUP_TIME_122MCS 1 -#define CONF_OSC_STARTUP_TIME_183MCS 2 -#define CONF_OSC_STARTUP_TIME_305MCS 3 -#define CONF_OSC_STARTUP_TIME_549MCS 4 -#define CONF_OSC_STARTUP_TIME_1038MCS 5 -#define CONF_OSC_STARTUP_TIME_2014MCS 6 -#define CONF_OSC_STARTUP_TIME_3967MCS 7 - -#define CONF_XOSC32K_STARTUP_TIME_122MCS 0 -#define CONF_XOSC32K_STARTUP_TIME_1068MCS 1 -#define CONF_XOSC32K_STARTUP_TIME_65592MCS 2 -#define CONF_XOSC32K_STARTUP_TIME_125092MCS 3 -#define CONF_XOSC32K_STARTUP_TIME_500092MCS 4 -#define CONF_XOSC32K_STARTUP_TIME_1000092MCS 5 -#define CONF_XOSC32K_STARTUP_TIME_2000092MCS 6 -#define CONF_XOSC32K_STARTUP_TIME_4000092MCS 7 - -// 8MHz Internal Oscillator Configuration -// Indicates whether configuration for OSC8M is enabled or not -// enable_osc8m -#ifndef CONF_OSC8M_CONFIG -#define CONF_OSC8M_CONFIG 1 -#endif - -// 8MHz Internal Oscillator (OSC8M) Control -// Internal 8M Oscillator Enable -// Indicates whether Internal 8 Mhz Oscillator is enabled or not -// osc8m_arch_enable -#ifndef CONF_OSC8M_ENABLE -#define CONF_OSC8M_ENABLE 1 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not. -// If enabled, the oscillator will only be running when requested by a peripheral. -// If disabled, the oscillator will always be running when enabled. -// osc8m_arch_ondemand -#ifndef CONF_OSC8M_ONDEMAND -#define CONF_OSC8M_ONDEMAND 1 -#endif - -// Run In Standby -// Run In standby Mode -// If this bit is 0: The oscillator is disabled in standby sleep mode. -// If this bit is 1: The oscillator is not stopped in standby sleep mode. -// osc8m_arch_runstdby -#ifndef CONF_OSC8M_RUNSTDBY -#define CONF_OSC8M_RUNSTDBY 0 -#endif - -// Prescaler -// 1 -// 2 -// 4 -// 8 -// Prescaler for Internal 8Mhz OSC -// Default: No Prescaling -// osc8m_presc -#ifndef CONF_OSC8M_PRESC -#define CONF_OSC8M_PRESC SYSCTRL_OSC8M_PRESC_3_Val -#endif - -// Overwrite Default Osc Calibration -// Overwrite Default Osc Calibration -// osc8m_arch_overwrite_calibration -#ifndef CONF_OSC8M_OVERWRITE_CALIBRATION -#define CONF_OSC8M_OVERWRITE_CALIBRATION 0 -#endif - -// Osc Calibration Value <0-65535> -// Set the Oscillator Calibration Value -// Default: 1 -// osc8m_arch_calib -#ifndef CONF_OSC8M_CALIB -#define CONF_OSC8M_CALIB 0 -#endif - -// -// - -// 32kHz Internal Oscillator Configuration -// Indicates whether configuration for OSC32K is enabled or not -// enable_osc32k -#ifndef CONF_OSC32K_CONFIG -#define CONF_OSC32K_CONFIG 0 -#endif - -// 32kHz Internal Oscillator (OSC32K) Control -// Internal 32K Oscillator Enable -// Indicates whether Internal 32K Oscillator is enabled or not -// osc32k_arch_enable -#ifndef CONF_OSC32K_ENABLE -#define CONF_OSC32K_ENABLE 0 -#endif - -// On Demand Control -// Enable On Demand -// If this bit is 0: The oscillator is always on, if enabled. -// If this bit is 1, the oscillator will only be running when requested by a peripheral. -// osc32k_arch_ondemand -#ifndef CONF_OSC32K_ONDEMAND -#define CONF_OSC32K_ONDEMAND 1 -#endif - -// Run In Standby -// Run In standby Mode -// If this bit is 0: The oscillator is disabled in standby sleep mode. -// If this bit is 1: The oscillator is not stopped in standby sleep mode. -// osc32k_arch_runstdby -#ifndef CONF_OSC32K_RUNSTDBY -#define CONF_OSC32K_RUNSTDBY 0 -#endif - -// Enable 32Khz Output -// Enable 32 Khz Output -// osc32k_arch_en32k -#ifndef CONF_OSC32K_EN32K -#define CONF_OSC32K_EN32K 0 -#endif - -// Enable 1K -// Enable 1K -// osc32k_arch_en1k -#ifndef CONF_OSC32K_EN1K -#define CONF_OSC32K_EN1K 0 -#endif - -// Write Lock -// Write Lock -// osc32k_arch_wrtlock -#ifndef CONF_OSC32K_WRTLOCK -#define CONF_OSC32K_WRTLOCK 0 -#endif - -// Start up time for the 32K Oscillator -// 3 Clock Cycles (92us) -// 4 Clock Cycles (122us) -// 6 Clock Cycles (183us) -// 10 Clock Cycles (305us) -// 18 Clock Cycles (549us) -// 34 Clock Cycles (1038us) -// 66 Clock Cycles (2014us) -// 130 Clock Cycles (3967us) -// Start Up Time for the 32K Oscillator -// Default: 10 Clock Cycles (305us) -// osc32k_arch_startup -#ifndef CONF_OSC32K_STARTUP -#define CONF_OSC32K_STARTUP CONF_OSC_STARTUP_TIME_92MCS -#endif - -// Overwrite Default Osc Calibration -// Overwrite Default Osc Calibration -// osc32k_arch_overwrite_calibration -#ifndef CONF_OSC32K_OVERWRITE_CALIBRATION -#define CONF_OSC32K_OVERWRITE_CALIBRATION 0 -#endif - -// Osc Calibration Value <0-65535> -// Set the Oscillator Calibration Value -// Default: 0 -// osc32k_arch_calib -#ifndef CONF_OSC32K_CALIB -#define CONF_OSC32K_CALIB 0 -#endif - -// -// - -// 32kHz External Crystal Oscillator Configuration -// Indicates whether configuration for External 32K Osc is enabled or not -// enable_xosc32k -#ifndef CONF_XOSC32K_CONFIG -#define CONF_XOSC32K_CONFIG 0 -#endif - -// 32kHz External Crystal Oscillator (XOSC32K) Control -// External 32K Oscillator Enable -// Indicates whether External 32K Oscillator is enabled or not -// xosc32k_arch_enable -#ifndef CONF_XOSC32K_ENABLE -#define CONF_XOSC32K_ENABLE 0 -#endif - -// On Demand -// Enable On Demand. -// If this bit is 0: The oscillator is always on, if enabled. -// If this bit is 1: the oscillator will only be running when requested by a peripheral. -// xosc32k_arch_ondemand -#ifndef CONF_XOSC32K_ONDEMAND -#define CONF_XOSC32K_ONDEMAND 1 -#endif - -// Run In Standby -// Run In standby Mode -// If this bit is 0: The oscillator is disabled in standby sleep mode. -// If this bit is 1: The oscillator is not stopped in standby sleep mode. -// xosc32k_arch_runstdby -#ifndef CONF_XOSC32K_RUNSTDBY -#define CONF_XOSC32K_RUNSTDBY 0 -#endif - -// Enable 1K -// Enable 1K -// xosc32k_arch_en1k -#ifndef CONF_XOSC32K_EN1K -#define CONF_XOSC32K_EN1K 0 -#endif - -// Enable 32Khz Output -// Enable 32 Khz Output -// xosc32k_arch_en32k -#ifndef CONF_XOSC32K_EN32K -#define CONF_XOSC32K_EN32K 0 -#endif - -// Enable XTAL -// Enable XTAL -// xosc32k_arch_xtalen -#ifndef CONF_XOSC32K_XTALEN -#define CONF_XOSC32K_XTALEN 0 -#endif - -// Write Lock -// Write Lock -// xosc32k_arch_wrtlock -#ifndef CONF_XOSC32K_WRTLOCK -#define CONF_XOSC32K_WRTLOCK 0 -#endif - -// Automatic Amplitude Control Enable -// Indicates whether Automatic Amplitude Control is Enabled or not -// xosc32k_arch_aampen -#ifndef CONF_XOSC32K_AAMPEN -#define CONF_XOSC32K_AAMPEN 0 -#endif - -// Start up time for the 32K Oscillator -// 122 us -// 1068 us -// 62592 us -// 1125092 us -// 500092 us -// 1000092 us -// 2000092 us -// 4000092 us -// Start Up Time for the 32K Oscillator -// Default: 122 us -// xosc32k_arch_startup -#ifndef CONF_XOSC32K_STARTUP -#define CONF_XOSC32K_STARTUP CONF_XOSC32K_STARTUP_TIME_122MCS -#endif - -// -// - -// External Multipurpose Crystal Oscillator Configuration -// Indicates whether configuration for External Multipurpose Osc is enabled or not -// enable_xosc -#ifndef CONF_XOSC_CONFIG -#define CONF_XOSC_CONFIG 0 -#endif - -// Frequency <400000-32000000> -// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. -// xosc_frequency -#ifndef CONF_XOSC_FREQUENCY -#define CONF_XOSC_FREQUENCY 400000 -#endif - -// External Multipurpose Crystal Oscillator (XOSC) Control -// Enable -// Indicates whether External Multipurpose Oscillator is enabled or not -// xosc_arch_enable -#ifndef CONF_XOSC_ENABLE -#define CONF_XOSC_ENABLE 0 -#endif - -// On Demand -// Enable On Demand -// If this bit is 0: The oscillator is always on, if enabled. -// If this bit is 1: the oscillator will only be running when requested by a peripheral. -// xosc_arch_ondemand -#ifndef CONF_XOSC_ONDEMAND -#define CONF_XOSC_ONDEMAND 1 -#endif - -// Run In Standby -// Run In standby Mode -// If this bit is 0: The oscillator is disabled in standby sleep mode. -// If this bit is 1: The oscillator is not stopped in standby sleep mode. -// xosc_arch_runstdby -#ifndef CONF_XOSC_RUNSTDBY -#define CONF_XOSC_RUNSTDBY 0 -#endif - -// Enable XTAL -// Enable XTAL -// xosc_arch_xtalen -#ifndef CONF_XOSC_XTALEN -#define CONF_XOSC_XTALEN 0 -#endif - -// Automatic Amplitude Control Enable -// Indicates whether Automatic Amplitude Control is Enabled or not -// xosc_arch_ampgc -#ifndef CONF_XOSC_AMPGC -#define CONF_XOSC_AMPGC 0 -#endif - -// Gain of the Oscillator -// 2Mhz -// 4Mhz -// 8Mhz -// 16Mhz -// 30Mhz -// Select the Gain of the oscillator -// xosc_arch_gain -#ifndef CONF_XOSC_GAIN -#define CONF_XOSC_GAIN SYSCTRL_XOSC_GAIN_0_Val -#endif - -// Start up time for the External Oscillator -// 31 us -// 61 us -// 122 us -// 244 us -// 488 us -// 977 us -// 1953 us -// 3906 us -// 7813 us -// 15625 us -// 31250 us -// 62500 us -// 125000 us -// 250000 us -// 500000 us -// 1000000 us -// Start Up Time for the External Oscillator -// Default: 31 us -// xosc_arch_startup -#ifndef CONF_XOSC_STARTUP -#define CONF_XOSC_STARTUP CONF_XOSC_STARTUP_TIME_31MCS -#endif - -// -// - -// 32kHz Ultra Low Power Internal Oscillator Configuration -// Indicates whether configuration for OSCULP32K is enabled or not -// enable_osculp32k -#ifndef CONF_OSCULP32K_CONFIG -#define CONF_OSCULP32K_CONFIG 1 -#endif - -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -// Write Lock -// Locks the OSCULP32K register for future writes to fix the OSCULP32K configuration -// osculp32k_arch_wrtlock -#ifndef CONF_OSCULP32K_WRTLOCK -#define CONF_OSCULP32K_WRTLOCK 0 -#endif - -// Overwrite Default Osc Calibration -// Overwrite Default Osc Calibration -// osculp32k_arch_overwrite_calibration -#ifndef CONF_OSCULP32K_OVERWRITE_CALIBRATION -#define CONF_OSCULP32K_OVERWRITE_CALIBRATION 0 -#endif - -// Osc Calibration Value <0-255> -// Set the Oscillator Calibration Value -// Default: 0 -// osculp32k_arch_calib -#ifndef CONF_OSCULP32K_CALIB -#define CONF_OSCULP32K_CALIB 0 -#endif - -// -// - -// DFLL Configuration -// Indicates whether configuration for DFLL is enabled or not -// enable_dfll48m -#ifndef CONF_DFLL_CONFIG -#define CONF_DFLL_CONFIG 0 -#endif - -// Reference Clock Source -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Select the clock source. -// dfll48m_ref_clock -#ifndef CONF_DFLL_GCLK -#define CONF_DFLL_GCLK GCLK_CLKCTRL_GEN_GCLK4_Val -#endif - -// DFLL Control -// DFLL Enable -// Indicates whether DFLL is enabled or not -// dfll48m_arch_enable -#ifndef CONF_DFLL_ENABLE -#define CONF_DFLL_ENABLE 0 -#endif - -// Wait Lock -// Indicates whether Wait Lock is Enables or not -// dfll48m_arch_waitlock -#ifndef CONF_DFLL_WAITLOCK -#define CONF_DFLL_WAITLOCK 0 -#endif - -// Bypass Coarse Lock -// Indicates whether Bypass coarse lock is enabled or not -// dfll48m_arch_bplckc -#ifndef CONF_DFLL_BPLCKC -#define CONF_DFLL_BPLCKC 0 -#endif - -// Quick Lock Disable -// Quick Lock Disable -// dfll48m_arch_qldis -#ifndef CONF_DFLL_QLDIS -#define CONF_DFLL_QLDIS 0 -#endif - -// Chill Cycle Disable -// Chill Cycle Disable -// dfll48m_arch_ccdis -#ifndef CONF_DFLL_CCDIS -#define CONF_DFLL_CCDIS 0 -#endif - -// On Demand -// Enable On Demand -// If this bit is 0: The DFLL is always on, if enabled. -// If this bit is 1: the DFLL will only be running when requested by a peripheral. -// dfll48m_arch_ondemand -#ifndef CONF_DFLL_ONDEMAND -#define CONF_DFLL_ONDEMAND 1 -#endif - -// Run In Standby -// Run In standby Mode -// If this bit is 0: The DFLL is disabled in standby sleep mode. -// If this bit is 1: The DFLL is not stopped in standby sleep mode. -// dfll48m_arch_runstdby -#ifndef CONF_DFLL_RUNSTDBY -#define CONF_DFLL_RUNSTDBY 0 -#endif - -// USB Clock Recovery Mode -// USB Clock Recovery Mode -// dfll48m_arch_usbcrm -#ifndef CONF_DFLL_USBCRM -#define CONF_DFLL_USBCRM 1 -#endif - -#if CONF_DFLL_USBCRM == 1 -#if CONF_DFLL_QLDIS == 1 -#warning QLDIS must be cleared to speed up the lock phase -#endif -#if CONF_DFLL_CCDIS == 0 -#warning CCDIS should be set to speed up the lock phase -#endif -#endif - -// Lose Lock After Wake -// Lose Lock After Wake -// dfll48m_arch_llaw -#ifndef CONF_DFLL_LLAW -#define CONF_DFLL_LLAW 0 -#endif - -// Stable DFLL Frequency -// Stable DFLL Frequency -// If 0: FINE calibration tracks changes in output frequency. -// If 1: FINE calibration register value will be fixed after a fine lock. -// dfll48m_arch_stable -#ifndef CONF_DFLL_STABLE -#define CONF_DFLL_STABLE 0 -#endif - -// Operating Mode Selection -// Open Loop Mode -// Closed Loop Mode -// Mode -// dfll48m_mode -#ifndef CONF_DFLL_MODE -#define CONF_DFLL_MODE CONF_DFLL_CLOSED_LOOP_MODE -#endif - -// Coarse Maximum Step <0x0-0x1F> -// dfll_arch_cstep -#ifndef CONF_DFLL_CSTEP -#define CONF_DFLL_CSTEP 1 -#endif - -// Fine Maximum Step <0x0-0x3FF> -// dfll_arch_fstep -#ifndef CONF_DFLL_FSTEP -#define CONF_DFLL_FSTEP 1 -#endif - -// DFLL Multiply Factor<0-65535> -// Set the DFLL Multiply Factor -// Default: 0 -// dfll48m_mul -#ifndef CONF_DFLL_MUL -#define CONF_DFLL_MUL 0 -#endif - -// DFLL Calibration Overwrite -// Indicates whether Overwrite Calibration value of DFLL -// dfll48m_arch_calibration -#ifndef CONF_DFLL_OVERWRITE_CALIBRATION -#define CONF_DFLL_OVERWRITE_CALIBRATION 1 -#endif - -// Coarse Value <0x0-0x3F> -// dfll48m_arch_coarse -#ifndef CONF_DFLL_COARSE -#define CONF_DFLL_COARSE (0xa) -#endif - -// Fine Value <0x0-0x3FF> -// dfll48m_arch_fine -#ifndef CONF_DFLL_FINE -#define CONF_DFLL_FINE (0x200) -#endif - -#if CONF_DFLL_OVERWRITE_CALIBRATION == 0 -#define CONF_DEFAULT_CORASE \ - ((FUSES_DFLL48M_COARSE_CAL_Msk & (*((uint32_t *)FUSES_DFLL48M_COARSE_CAL_ADDR))) >> FUSES_DFLL48M_COARSE_CAL_Pos) - -#define CONF_DFLLVAL \ - SYSCTRL_DFLLVAL_COARSE(((CONF_DEFAULT_CORASE) == 0x3F) ? 0x1F : (CONF_DEFAULT_CORASE)) \ - | SYSCTRL_DFLLVAL_FINE(512) - -#else -#define CONF_DFLLVAL SYSCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | SYSCTRL_DFLLVAL_FINE(CONF_DFLL_FINE) - -#endif -// - -// -// - -// DPLL Configuration -// Indicates whether configuration for DPLL is enabled or not -// enable_fdpll96m -#ifndef CONF_DPLL_CONFIG -#define CONF_DPLL_CONFIG 0 -#endif - -// Reference Clock Source -// 32kHz External Crystal Oscillator (XOSC32K) -// External Crystal Oscillator 0.4-32MHz (XOSC) -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Select the clock source. -// fdpll96m_ref_clock -#ifndef CONF_DPLL_GCLK -#define CONF_DPLL_GCLK GCLK_CLKCTRL_GEN_GCLK3_Val -#endif - -#if (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC32K) -#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF0_Val -#elif (CONF_DPLL_GCLK == GCLK_GENCTRL_SRC_XOSC) -#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_REF1_Val -#else -#define CONF_DPLL_REFCLK SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val -#endif - -// DPLL Control -// ON Demand -// Enable On Demand -// If this bit is 0: The DFLL is always on, if enabled. -// If this bit is 1: the DFLL will only be running when requested by a peripheral. -// fdpll96m_arch_ondemand -#ifndef CONF_DPLL_ONDEMAND -#define CONF_DPLL_ONDEMAND 1 -#endif - -// Run In Standby -// Run In standby Mode -// If this bit is 0: The DFLL is disabled in standby sleep mode. -// If this bit is 1: The DFLL is not stopped in standby sleep mode. -// fdpll96m_arch_runstdby -#ifndef CONF_DPLL_RUNSTDBY -#define CONF_DPLL_RUNSTDBY 0 -#endif - -// DPLL Enable -// Indicates whether DPLL is enabled or not -// fdpll96m_arch_enable -#ifndef CONF_DPLL_ENABLE -#define CONF_DPLL_ENABLE 0 -#endif - -// Lock ByPass -// Enabling it makes the CLK_FDPLL96M always running otherwise it will be turned off when lock signal is low -// fdpll96m_arch_lbypass -#ifndef CONF_DPLL_LBYPASS -#define CONF_DPLL_LBYPASS 0 -#endif - -// Clock Divider <0-2047> -// Clock Division Factor (Applicable if reference clock is XOSC) -// fdpll96m_clock_div -#ifndef CONF_DPLL_DIV -#define CONF_DPLL_DIV 0 -#endif - -// DPLL LDRFRAC<0-15> -// Set the fractional part of the frequency multiplier. -// fdpll96m_ldrfrac -#ifndef CONF_DPLL_LDRFRAC -#define CONF_DPLL_LDRFRAC 13 -#endif - -// DPLL LDR <0-4095> -// Set the integer part of the frequency multiplier. -// fdpll96m_ldr -#ifndef CONF_DPLL_LDR -#define CONF_DPLL_LDR 1463 -#endif - -// -// - -#define CONF_DPLL_LTIME SYSCTRL_DPLLCTRLB_LTIME_DEFAULT_Val -#define CONF_DPLL_WUF 0 -#define CONF_DPLL_LPEN 0 -#define CONF_DPLL_FILTER SYSCTRL_DPLLCTRLB_FILTER_DEFAULT_Val - -// <<< end of configuration section >>> - -#endif // HPL_SYSCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_systick_config.h b/atmel-samd/asf4/samd21/config/hpl_systick_config.h deleted file mode 100644 index a7f2f3620..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_systick_config.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Auto-generated config file hpl_systick_config.h */ -#ifndef HPL_SYSTICK_CONFIG_H -#define HPL_SYSTICK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Advanced settings -// SysTick exception request -// Indicates whether the generation of SysTick exception is enabled or not -// systick_arch_tickint -#ifndef CONF_SYSTICK_TICKINT -#define CONF_SYSTICK_TICKINT 0 -#endif -// - -// <<< end of configuration section >>> - -#endif // HPL_SYSTICK_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_tc_config.h b/atmel-samd/asf4/samd21/config/hpl_tc_config.h deleted file mode 100644 index 90e9b0735..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_tc_config.h +++ /dev/null @@ -1,181 +0,0 @@ -/* Auto-generated config file hpl_tc_config.h */ -#ifndef HPL_TC_CONFIG_H -#define HPL_TC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -#ifndef CONF_TC3_ENABLE -#define CONF_TC3_ENABLE 1 -#endif - -// Basic settings - -// Prescaler -// No division -// Divide by 2 -// Divide by 4 -// Divide by 8 -// Divide by 16 -// Divide by 64 -// Divide by 256 -// Divide by 1024 -// This defines the prescaler value -// tc_prescaler -#ifndef CONF_TC3_PRESCALER -#define CONF_TC3_PRESCALER TC_CTRLA_PRESCALER_DIV8_Val -#endif - -// Period Value <0x00000000-0xFFFFFFFF> -// tc_per -#ifndef CONF_TC3_PER -#define CONF_TC3_PER 0x32 -#endif -// - -// PWM Waveform Output settings -// Waveform Period Value (uS) <0x00-0xFFFFFFFF> -// The unit of this value is us. -// tc_arch_wave_per_val -#ifndef CONF_TC3_WAVE_PER_VAL -#define CONF_TC3_WAVE_PER_VAL 0x3e8 -#endif - -// Waveform Duty Value (0.1%) <0x00-0x03E8> -// The unit of this value is 1/1000. -// tc_arch_wave_duty_val -#ifndef CONF_TC3_WAVE_DUTY_VAL -#define CONF_TC3_WAVE_DUTY_VAL 0x1f4 -#endif - -/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ -#if CONF_TC3_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val -#define CONF_TC3_CC0 \ - ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1000000 / (1 << CONF_TC3_PRESCALER) - 1)) -#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) - -#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val -#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 64000000 - 1)) -#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) - -#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val -#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 256000000 - 1)) -#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) - -#elif CONF_TC3_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val -#define CONF_TC3_CC0 ((uint32_t)(((double)CONF_TC3_WAVE_PER_VAL * CONF_GCLK_TC3_FREQUENCY) / 1024000000 - 1)) -#define CONF_TC3_CC1 ((CONF_TC3_CC0 * CONF_TC3_WAVE_DUTY_VAL) / 1000) -#endif - -// - -// Advanced settings -// Mode -// Counter in 16-bit mode -// Counter in 32-bit mode -// These bits mode -// tc_arch_mode -#ifndef CONF_TC3_MODE -#define CONF_TC3_MODE TC_CTRLA_MODE_COUNT16_Val -#endif -// - -// Advanced settings -/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC3_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val - -// Run in standby -// Indicates whether the will continue running in standby sleep mode or not -// tc_arch_runstdby -#ifndef CONF_TC3_RUNSTDBY -#define CONF_TC3_RUNSTDBY 0 -#endif - -// Prescaler and Counter Synchronization Selection -// Reload or reset counter on next GCLK -// Reload or reset counter on next prescaler clock -// Reload or reset counter on next GCLK and reset prescaler counter -// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. -// tc_arch_presync -#ifndef CONF_TC3_PRESCSYNC -#define CONF_TC3_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val -#endif - -/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC3_DIR 0 -//#define CONF_TC3_ONESHOT 0 - -/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC3_INVEN0 0 -//#define CONF_TC3_INVEN1 0 -//#define CONF_TC3_CPTEN0 0 -//#define CONF_TC3_CPTEN1 0 - -// Debug Running Mode -// Indicates whether the Debug Running Mode is enabled or not -// tc_arch_dbgrun -#ifndef CONF_TC3_DBGRUN -#define CONF_TC3_DBGRUN 0 -#endif - -// - -// Event control -// timer_event_control -#ifndef CONF_TC3_EVENT_CONTROL_ENABLE -#define CONF_TC3_EVENT_CONTROL_ENABLE 0 -#endif - -// Overflow/Underflow Event Output -// Generates event for counter overflows/underflows -// tc_arch_ovfeo -#ifndef CONF_TC3_OVFEO -#define CONF_TC3_OVFEO 0 -#endif - -// TC Event Asynchronous input -// Enables Asynchronous input events to the TC -// tc_arch_tcei -#ifndef CONF_TC3_TCEI -#define CONF_TC3_TCEI 0 -#endif - -// TC Inverted Event Input Polarity -// Used to invert the asynchronous input event source -// tc_arch_tceinv -#ifndef CONF_TC3_TCINV -#define CONF_TC3_TCINV 0 -#endif - -// Event Action -// Defines the event action the TC will perform on an event -// Event action disabled -// Start, restart or retrigger TC on event -// Count on event -// Start TC on event -// Period captured in CC0, pulse width in CC1 -// Period captured in CC1, pulse width in CC0 -// tc_arch_evact -#ifndef CONF_TC3_EVACT -#define CONF_TC3_EVACT TC_EVCTRL_EVACT_OFF_Val -#endif - -// Match/Capture channel 0 Event -// Enables the generation of an event for every match or capture on channel 0 -// tc_arch_mceo0 -#ifndef CONF_TC3_MCEO0 -#define CONF_TC3_MCEO0 0 -#endif -// Match/Capture channel 1 Event -// Enables the generation of an event for every match or capture on channel 1 -// tc_arch_mceo1 -#ifndef CONF_TC3_MCEO1 -#define CONF_TC3_MCEO1 0 -#endif - -// - -// <<< end of configuration section >>> - -#endif // HPL_TC_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/hpl_usb_config.h b/atmel-samd/asf4/samd21/config/hpl_usb_config.h deleted file mode 100644 index 73a9fea44..000000000 --- a/atmel-samd/asf4/samd21/config/hpl_usb_config.h +++ /dev/null @@ -1,355 +0,0 @@ -/* Auto-generated config file hpl_usb_config.h */ -#ifndef HPL_USB_CONFIG_H -#define HPL_USB_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#define CONF_USB_N_0 0 -#define CONF_USB_N_1 1 -#define CONF_USB_N_2 2 -#define CONF_USB_N_3 3 -#define CONF_USB_N_4 4 -#define CONF_USB_N_5 5 -#define CONF_USB_N_6 6 -#define CONF_USB_N_7 7 -#define CONF_USB_N_8 8 -#define CONF_USB_N_9 9 -#define CONF_USB_N_10 10 -#define CONF_USB_N_11 11 -#define CONF_USB_N_12 12 -#define CONF_USB_N_13 13 -#define CONF_USB_N_14 14 -#define CONF_USB_N_15 15 - -#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1) -#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1) - -// USB Device HAL Configuration - -// Max number of endpoints supported -// Limits the number of endpoints (described by EP address) can be used in app. -// 1 (EP0 only) -// 2 (EP0 + 1 endpoint) -// 3 (EP0 + 2 endpoints) -// 4 (EP0 + 3 endpoints) -// 5 (EP0 + 4 endpoints) -// 6 (EP0 + 5 endpoints) -// 7 (EP0 + 6 endpoints) -// 8 (EP0 + 7 endpoints) -// Max possible (by "Max Endpoint Number" config) -// usbd_num_ep_sp -#ifndef CONF_USB_D_NUM_EP_SP -#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4 -#endif - -// - -// Max Endpoint Number supported -// Limits the max endpoint number. -// USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1. -// Reduce the value according to specific device design, to cut-off memory usage. -// 0 (only EP0) -// 1 (EP 0x81 or 0x01) -// 2 (EP 0x82 or 0x02) -// 3 (EP 0x83 or 0x03) -// 4 (EP 0x84 or 0x04) -// 5 (EP 0x85 or 0x05) -// 6 (EP 0x86 or 0x06) -// 7 (EP 0x87 or 0x07) -// Max possible (by HW) -// The number of physical endpoints - 1 -// usbd_arch_max_ep_n -#ifndef CONF_USB_D_MAX_EP_N -#define CONF_USB_D_MAX_EP_N CONF_USB_N_2 -#endif - -// USB Speed Limit -// Limits the working speed of the device. -// Full speed -// Low Speed -// usbd_arch_speed -#ifndef CONF_USB_D_SPEED -#define CONF_USB_D_SPEED USB_SPEED_FS -#endif - -// Cache buffer size for EP0 -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time. -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// usb_arch_ep0_cache -#ifndef CONF_USB_EP0_CACHE -#define CONF_USB_EP0_CACHE 64 -#endif - -// Cache configuration EP1 -// Cache buffer size for EP1 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep1_cache -#ifndef CONF_USB_EP1_CACHE -#define CONF_USB_EP1_CACHE 64 -#endif - -// Cache buffer size for EP1 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep1_I_CACHE -#ifndef CONF_USB_EP1_I_CACHE -#define CONF_USB_EP1_I_CACHE 0 -#endif -// - -// Cache configuration EP2 -// Cache buffer size for EP2 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep2_cache -#ifndef CONF_USB_EP2_CACHE -#define CONF_USB_EP2_CACHE 64 -#endif - -// Cache buffer size for EP2 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep2_I_CACHE -#ifndef CONF_USB_EP2_I_CACHE -#define CONF_USB_EP2_I_CACHE 0 -#endif -// - -// Cache configuration EP3 -// Cache buffer size for EP3 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep3_cache -#ifndef CONF_USB_EP3_CACHE -#define CONF_USB_EP3_CACHE 64 -#endif - -// Cache buffer size for EP3 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep3_I_CACHE -#ifndef CONF_USB_EP3_I_CACHE -#define CONF_USB_EP3_I_CACHE 0 -#endif -// - -// Cache configuration EP4 -// Cache buffer size for EP4 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep4_cache -#ifndef CONF_USB_EP4_CACHE -#define CONF_USB_EP4_CACHE 64 -#endif - -// Cache buffer size for EP4 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep4_I_CACHE -#ifndef CONF_USB_EP4_I_CACHE -#define CONF_USB_EP4_I_CACHE 0 -#endif -// - -// Cache configuration EP5 -// Cache buffer size for EP5 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep5_cache -#ifndef CONF_USB_EP5_CACHE -#define CONF_USB_EP5_CACHE 64 -#endif - -// Cache buffer size for EP5 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep5_I_CACHE -#ifndef CONF_USB_EP5_I_CACHE -#define CONF_USB_EP5_I_CACHE 0 -#endif -// - -// Cache configuration EP6 -// Cache buffer size for EP6 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep6_cache -#ifndef CONF_USB_EP6_CACHE -#define CONF_USB_EP6_CACHE 64 -#endif - -// Cache buffer size for EP6 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep6_I_CACHE -#ifndef CONF_USB_EP6_I_CACHE -#define CONF_USB_EP6_I_CACHE 0 -#endif -// - -// Cache configuration EP7 -// Cache buffer size for EP7 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep7_cache -#ifndef CONF_USB_EP7_CACHE -#define CONF_USB_EP7_CACHE 64 -#endif - -// Cache buffer size for EP7 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep7_I_CACHE -#ifndef CONF_USB_EP7_I_CACHE -#define CONF_USB_EP7_I_CACHE 0 -#endif -// - -// <<< end of configuration section >>> - -#endif // HPL_USB_CONFIG_H diff --git a/atmel-samd/asf4/samd21/config/peripheral_clk_config.h b/atmel-samd/asf4/samd21/config/peripheral_clk_config.h deleted file mode 100644 index f3bb927f9..000000000 --- a/atmel-samd/asf4/samd21/config/peripheral_clk_config.h +++ /dev/null @@ -1,369 +0,0 @@ -/* Auto-generated config file peripheral_clk_config.h */ -#ifndef PERIPHERAL_CLK_CONFIG_H -#define PERIPHERAL_CLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// ADC Clock Source -// adc_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Select the clock source for ADC. -#ifndef CONF_GCLK_ADC_SRC -#define CONF_GCLK_ADC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_ADC_FREQUENCY - * \brief ADC's Clock frequency - */ -#ifndef CONF_GCLK_ADC_FREQUENCY -#define CONF_GCLK_ADC_FREQUENCY 1000000 -#endif - -/** - * \def CONF_CPU_FREQUENCY - * \brief CPU's Clock frequency - */ -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 1000000 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM0_CORE_SRC -#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM0_SLOW_SRC -#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY - * \brief SERCOM0's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY -#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 1000000 -#endif - -/** - * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY - * \brief SERCOM0's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 400000 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM1_CORE_SRC -#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM1_SLOW_SRC -#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY - * \brief SERCOM1's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY -#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 1000000 -#endif - -/** - * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY - * \brief SERCOM1's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 400000 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM2_CORE_SRC -#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_CLKCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM2_SLOW_SRC -#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_CLKCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY - * \brief SERCOM2's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY -#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 1000000 -#endif - -/** - * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY - * \brief SERCOM2's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 400000 -#endif - -// RTC Clock Source -// rtc_clk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Select the clock source for RTC. -#ifndef CONF_GCLK_RTC_SRC -#define CONF_GCLK_RTC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_RTC_FREQUENCY - * \brief RTC's Clock frequency - */ -#ifndef CONF_GCLK_RTC_FREQUENCY -#define CONF_GCLK_RTC_FREQUENCY 1000000 -#endif - -// TC Clock Source -// tc_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Select the clock source for TC. -#ifndef CONF_GCLK_TC3_SRC -#define CONF_GCLK_TC3_SRC GCLK_CLKCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_TC3_FREQUENCY - * \brief TC3's Clock frequency - */ -#ifndef CONF_GCLK_TC3_FREQUENCY -#define CONF_GCLK_TC3_FREQUENCY 1000000 -#endif - -// DAC Clock Source -// dac_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Select the clock source for DAC. -#ifndef CONF_GCLK_DAC_SRC -#define CONF_GCLK_DAC_SRC GCLK_CLKCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_DAC_FREQUENCY - * \brief DAC's Clock frequency - */ -#ifndef CONF_GCLK_DAC_FREQUENCY -#define CONF_GCLK_DAC_FREQUENCY 1000000 -#endif - -// USB Clock Source -// usb_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Select the clock source for USB. -#ifndef CONF_GCLK_USB_SRC -#define CONF_GCLK_USB_SRC GCLK_CLKCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_USB_FREQUENCY - * \brief USB's Clock frequency - */ -#ifndef CONF_GCLK_USB_FREQUENCY -#define CONF_GCLK_USB_FREQUENCY 1000000 -#endif - -// <<< end of configuration section >>> - -#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/atmel-samd/asf4/samd21/documentation/usb_device_composite.rst b/atmel-samd/asf4/samd21/documentation/usb_device_composite.rst deleted file mode 100644 index 1d6151cc2..000000000 --- a/atmel-samd/asf4/samd21/documentation/usb_device_composite.rst +++ /dev/null @@ -1,32 +0,0 @@ -==================== -USB Device Composite -==================== - -USB Device Composite is a part of the USB Device Stack library. It provides the support for -combining different USB classes into one USB device application. For more detailed features -or use cases introduction, user can refer to the related class documents. - - -Features --------- -* Combination of different USB classes. - - -Applications ------------- - -* An USB device which is composed by CDC ACM, HID Keyboard,etc. - -Dependencies ------------- - -* USB Device Driver -* USB Device Stack Core -* USB Device CDC -* USB Device HID - - -Limitations ------------ - -N/A diff --git a/atmel-samd/asf4/samd21/documentation/usb_device_core.rst b/atmel-samd/asf4/samd21/documentation/usb_device_core.rst deleted file mode 100644 index fc7018625..000000000 --- a/atmel-samd/asf4/samd21/documentation/usb_device_core.rst +++ /dev/null @@ -1,41 +0,0 @@ -=============== -USB Device Core -=============== - -USB Device Core is a part of the USB Device Stack library. It handles all the requests -during USB Enumeration process and helps upper class driver to be installed successfully -if only the descriptor configuration is correct. For more detailed description about Bus -Enumeration, user can refer to Chapter 9 (USB Device Framework) in Universal Serial Bus -Specification. - -Features --------- -* Initialization/de-initialization -* Enabling/disabling USB device class components -* Data Transfer -* Attaching/detaching control -* Waking up by USB host -* Callbacks management on: - - * SOF event - * USB Device state change - * USB Device request handler - - -Applications ------------- - -N/A - -Dependencies ------------- - -* USB Device Driver -* USB Protocol Core - - -Limitations ------------ - -* It is recommended that at least one device class should run above the USB - device core. diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_cdc.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_cdc.rst deleted file mode 100644 index 3cf414b92..000000000 --- a/atmel-samd/asf4/samd21/documentation/usb_protocol_cdc.rst +++ /dev/null @@ -1,24 +0,0 @@ -================ -USB CDC Protocol -================ - -USB CDC Protocol is a part of the USB Device Stack library. It provides basic -macro definitions and data structures which are compliant with CDC(Communications -Device Class) Specification version 1.2. - - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_core.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_core.rst deleted file mode 100644 index 4d5e01bbf..000000000 --- a/atmel-samd/asf4/samd21/documentation/usb_protocol_core.rst +++ /dev/null @@ -1,40 +0,0 @@ -================= -USB Protocol Core -================= - -USB Protocol Core is a part of the USB Device Stack library. It provides basic -macro definitions, data structures and API functions which are compliant with -USB specification version 2.0.0/2.0.1 for user. - -In addition, it provides interfaces of USB descriptor searching for the upper -layer to use, which is especially helpful in the USB enumeration process. - -Features --------- -* Packaging USB device, configuration, interface, endpoint descriptors. -* Getting the descriptor length or type from an assigned USB descriptor. -* Getting VID, PID value from an assigned USB descriptor. -* Getting the total length of an USB configuration descriptor. -* Finding the next valid descriptor in a given USB descriptor. -* Finding an endpoint descriptor in a given USB descriptor. -* Finding a specific descriptor by an assigned descriptor type. -* Finding a configure descriptor by an assigned configure value. -* Finding a string descriptor by an assigned string index. - - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A - diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_hid.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_hid.rst deleted file mode 100644 index 613c22cec..000000000 --- a/atmel-samd/asf4/samd21/documentation/usb_protocol_hid.rst +++ /dev/null @@ -1,24 +0,0 @@ -================ -USB HID Protocol -================ - -USB HID Protocol is a part of the USB Device Stack library. It provides basic -macro definitions and data structures which are compliant with HID(Human Interface -Device) Specification version 1.11. - - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_hub.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_hub.rst deleted file mode 100644 index d60b0bbfd..000000000 --- a/atmel-samd/asf4/samd21/documentation/usb_protocol_hub.rst +++ /dev/null @@ -1,32 +0,0 @@ -====================== -USB Protocol Hub Class -====================== - -USB Protocol Hub Class is a part of the USB Device Stack library. It provides -basic macro definitions, data structures and API functions which are compliant -with Hub part of USB specification version 2.0.0/2.0.1 for user. - -In addition, it provides interfaces of USB requests filling and input data -analyzing for the upper layer to use. - -Features --------- -* Hub requests filling -* Hub change bitmap analyzing - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A - diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_msc.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_msc.rst deleted file mode 100644 index 6c7df5450..000000000 --- a/atmel-samd/asf4/samd21/documentation/usb_protocol_msc.rst +++ /dev/null @@ -1,25 +0,0 @@ -================ -USB MSC Protocol -================ - -USB MSC Protocol is a part of the USB Device Stack library. It provides basic -macro definitions and data structures which are compliant with Mass Storage -Control/Bulk/Interrupt (CBI) Specification 1.1 and Mass Storage UFI Command -Specification 1.0. - - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A diff --git a/atmel-samd/asf4/samd21/documentation/usb_protocol_vendor.rst b/atmel-samd/asf4/samd21/documentation/usb_protocol_vendor.rst deleted file mode 100644 index e244675a6..000000000 --- a/atmel-samd/asf4/samd21/documentation/usb_protocol_vendor.rst +++ /dev/null @@ -1,24 +0,0 @@ -=================== -USB Vendor Protocol -=================== - -USB Vendor Protocol is a part of the USB Device Stack library. It provides basic -macro definitions which are compliant with Universal Serial Bus Specification -Revision 2.0. - - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A diff --git a/atmel-samd/asf4/samd21/driver_init.c b/atmel-samd/asf4/samd21/driver_init.c deleted file mode 100644 index 5ee0d0ef7..000000000 --- a/atmel-samd/asf4/samd21/driver_init.c +++ /dev/null @@ -1,788 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ - -#include "driver_init.h" -#include -#include -#include -#include -#include -#include -#include - -struct spi_m_sync_descriptor SPI_0; -struct timer_descriptor TIMER_0; - -struct adc_sync_descriptor ADC_0; - -struct flash_descriptor FLASH_0; - -struct i2c_m_sync_desc I2C_0; - -struct usart_sync_descriptor USART_0; - -struct pwm_descriptor PWM_0; - -struct dac_sync_descriptor DAC_0; - -void ADC_0_PORT_init(void) -{ -} - -void ADC_0_CLOCK_init(void) -{ - _pm_enable_bus_clock(PM_BUS_APBC, ADC); - _gclk_enable_channel(ADC_GCLK_ID, CONF_GCLK_ADC_SRC); -} - -void ADC_0_init(void) -{ - ADC_0_CLOCK_init(); - ADC_0_PORT_init(); - adc_sync_init(&ADC_0, ADC, (void *)NULL); -} - -void FLASH_0_CLOCK_init(void) -{ - - _pm_enable_bus_clock(PM_BUS_APBB, NVMCTRL); -} - -void FLASH_0_init(void) -{ - FLASH_0_CLOCK_init(); - flash_init(&FLASH_0, NVMCTRL); -} - -void SPI_0_PORT_init(void) -{ - - // Set pin direction to output - gpio_set_pin_direction(PA04, GPIO_DIRECTION_OUT); - - gpio_set_pin_level(PA04, - // Initial level - // pad_initial_level - // Low - // High - false); - - gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0); - - // Set pin direction to output - gpio_set_pin_direction(PA05, GPIO_DIRECTION_OUT); - - gpio_set_pin_level(PA05, - // Initial level - // pad_initial_level - // Low - // High - false); - - gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1); - - // Set pin direction to input - gpio_set_pin_direction(PA06, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA06, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA06, PINMUX_PA06D_SERCOM0_PAD2); -} - -void SPI_0_CLOCK_init(void) -{ - _pm_enable_bus_clock(PM_BUS_APBC, SERCOM0); - _gclk_enable_channel(SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC); -} - -void SPI_0_init(void) -{ - SPI_0_CLOCK_init(); - spi_m_sync_init(&SPI_0, SERCOM0); - SPI_0_PORT_init(); -} - -void I2C_0_PORT_init(void) -{ - - gpio_set_pin_pull_mode(PA16, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA16, PINMUX_PA16C_SERCOM1_PAD0); - - gpio_set_pin_pull_mode(PA17, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA17, PINMUX_PA17C_SERCOM1_PAD1); -} - -void I2C_0_CLOCK_init(void) -{ - _pm_enable_bus_clock(PM_BUS_APBC, SERCOM1); - _gclk_enable_channel(SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC); - _gclk_enable_channel(SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC); -} - -void I2C_0_init(void) -{ - I2C_0_CLOCK_init(); - i2c_m_sync_init(&I2C_0, SERCOM1); - I2C_0_PORT_init(); -} - -void USART_0_PORT_init(void) -{ - - gpio_set_pin_function(PA08, PINMUX_PA08D_SERCOM2_PAD0); - - gpio_set_pin_function(PA09, PINMUX_PA09D_SERCOM2_PAD1); -} - -void USART_0_CLOCK_init(void) -{ - _pm_enable_bus_clock(PM_BUS_APBC, SERCOM2); - _gclk_enable_channel(SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC); -} - -void USART_0_init(void) -{ - USART_0_CLOCK_init(); - usart_sync_init(&USART_0, SERCOM2, (void *)NULL); - USART_0_PORT_init(); -} - -void delay_driver_init(void) -{ - delay_init(SysTick); -} - -/** - * \brief Timer initialization function - * - * Enables Timer peripheral, clocks and initializes Timer driver - */ -static void TIMER_0_init(void) -{ - _pm_enable_bus_clock(PM_BUS_APBA, RTC); - _gclk_enable_channel(RTC_GCLK_ID, CONF_GCLK_RTC_SRC); - timer_init(&TIMER_0, RTC, _rtc_get_timer()); -} - -void PWM_0_PORT_init(void) -{ -} - -void PWM_0_CLOCK_init(void) -{ - _pm_enable_bus_clock(PM_BUS_APBC, TC3); - _gclk_enable_channel(TC3_GCLK_ID, CONF_GCLK_TC3_SRC); -} - -void PWM_0_init(void) -{ - PWM_0_CLOCK_init(); - PWM_0_PORT_init(); - pwm_init(&PWM_0, TC3, _tc_get_pwm()); -} - -void DAC_0_PORT_init(void) -{ -} - -void DAC_0_CLOCK_init(void) -{ - - _pm_enable_bus_clock(PM_BUS_APBC, DAC); - _gclk_enable_channel(DAC_GCLK_ID, CONF_GCLK_DAC_SRC); -} - -void DAC_0_init(void) -{ - DAC_0_CLOCK_init(); - dac_sync_init(&DAC_0, DAC); - DAC_0_PORT_init(); -} - -void USB_0_PORT_init(void) -{ - - gpio_set_pin_direction(PA24, - // Pin direction - // pad_direction - // Off - // In - // Out - GPIO_DIRECTION_OUT); - - gpio_set_pin_level(PA24, - // Initial level - // pad_initial_level - // Low - // High - false); - - gpio_set_pin_pull_mode(PA24, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA24, - // Pin function - // pad_function - // Auto : use driver pinmux if signal is imported by driver, else turn off function - // Auto - // Off - // A - // B - // C - // D - // E - // F - // G - // H - PINMUX_PA24G_USB_DM); - - gpio_set_pin_direction(PA25, - // Pin direction - // pad_direction - // Off - // In - // Out - GPIO_DIRECTION_OUT); - - gpio_set_pin_level(PA25, - // Initial level - // pad_initial_level - // Low - // High - false); - - gpio_set_pin_pull_mode(PA25, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA25, - // Pin function - // pad_function - // Auto : use driver pinmux if signal is imported by driver, else turn off function - // Auto - // Off - // A - // B - // C - // D - // E - // F - // G - // H - PINMUX_PA25G_USB_DP); -} - -/* The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock - * for low speed and full speed operation. */ -#if (CONF_GCLK_USB_FREQUENCY > (48000000 + 48000000 / 400)) || (CONF_GCLK_USB_FREQUENCY < (48000000 - 48000000 / 400)) -#warning USB clock should be 48MHz ~ 0.25% clock, check your configuration! -#endif - -void USB_0_CLOCK_init(void) -{ - - _pm_enable_bus_clock(PM_BUS_APBB, USB); - _pm_enable_bus_clock(PM_BUS_AHB, USB); - _gclk_enable_channel(USB_GCLK_ID, CONF_GCLK_USB_SRC); -} - -void USB_0_init(void) -{ - USB_0_CLOCK_init(); - usb_d_init(); - USB_0_PORT_init(); -} - -void system_init(void) -{ - init_mcu(); - - // GPIO on PA00 - - // Set pin direction to input - gpio_set_pin_direction(PA00, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA00, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA00, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA01 - - // Set pin direction to input - gpio_set_pin_direction(PA01, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA01, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA01, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA02 - - // Set pin direction to input - gpio_set_pin_direction(PA02, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA02, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA02, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA03 - - // Set pin direction to input - gpio_set_pin_direction(PA03, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA03, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA03, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA07 - - // Set pin direction to input - gpio_set_pin_direction(PA07, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA07, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA07, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA10 - - // Set pin direction to input - gpio_set_pin_direction(PA10, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA10, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA10, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA11 - - // Set pin direction to input - gpio_set_pin_direction(PA11, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA11, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA11, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA12 - - // Set pin direction to input - gpio_set_pin_direction(PA12, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA12, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA12, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA13 - - // Set pin direction to input - gpio_set_pin_direction(PA13, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA13, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA13, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA14 - - // Set pin direction to input - gpio_set_pin_direction(PA14, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA14, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA14, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA15 - - // Set pin direction to input - gpio_set_pin_direction(PA15, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA15, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA15, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA18 - - // Set pin direction to input - gpio_set_pin_direction(PA18, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA18, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA18, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA19 - - // Set pin direction to input - gpio_set_pin_direction(PA19, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA19, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA19, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA20 - - // Set pin direction to input - gpio_set_pin_direction(PA20, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA20, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA20, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA21 - - // Set pin direction to input - gpio_set_pin_direction(PA21, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA21, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA21, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA22 - - // Set pin direction to input - gpio_set_pin_direction(PA22, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA22, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA22, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA23 - - // Set pin direction to input - gpio_set_pin_direction(PA23, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA23, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA23, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA27 - - // Set pin direction to input - gpio_set_pin_direction(PA27, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA27, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA27, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA28 - - // Set pin direction to input - gpio_set_pin_direction(PA28, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA28, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA28, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA30 - - // Set pin direction to input - gpio_set_pin_direction(PA30, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA30, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA30, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PA31 - - // Set pin direction to input - gpio_set_pin_direction(PA31, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA31, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA31, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PB02 - - // Set pin direction to input - gpio_set_pin_direction(PB02, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PB02, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PB02, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PB03 - - // Set pin direction to input - gpio_set_pin_direction(PB03, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PB03, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PB03, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PB08 - - // Set pin direction to input - gpio_set_pin_direction(PB08, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PB08, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PB08, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PB09 - - // Set pin direction to input - gpio_set_pin_direction(PB09, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PB09, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PB09, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PB10 - - // Set pin direction to input - gpio_set_pin_direction(PB10, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PB10, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PB10, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PB11 - - // Set pin direction to input - gpio_set_pin_direction(PB11, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PB11, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PB11, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PB22 - - // Set pin direction to input - gpio_set_pin_direction(PB22, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PB22, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PB22, GPIO_PIN_FUNCTION_OFF); - - // GPIO on PB23 - - // Set pin direction to input - gpio_set_pin_direction(PB23, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PB23, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PB23, GPIO_PIN_FUNCTION_OFF); - - ADC_0_init(); - - FLASH_0_init(); - - SPI_0_init(); - - I2C_0_init(); - - USART_0_init(); - - delay_driver_init(); - - TIMER_0_init(); - - PWM_0_init(); - - DAC_0_init(); - - USB_0_init(); -} diff --git a/atmel-samd/asf4/samd21/driver_init.h b/atmel-samd/asf4/samd21/driver_init.h deleted file mode 100644 index da65d4ff0..000000000 --- a/atmel-samd/asf4/samd21/driver_init.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef DRIVER_INIT_INCLUDED -#define DRIVER_INIT_INCLUDED - -#include "atmel_start_pins.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include - -#include - -#include - -#include -#include -#include -#include - -#include - -#include "hal_usb_device.h" - -extern struct adc_sync_descriptor ADC_0; - -extern struct flash_descriptor FLASH_0; -extern struct spi_m_sync_descriptor SPI_0; - -extern struct i2c_m_sync_desc I2C_0; - -extern struct usart_sync_descriptor USART_0; - -extern struct timer_descriptor TIMER_0; - -extern struct pwm_descriptor PWM_0; - -extern struct dac_sync_descriptor DAC_0; - -void ADC_0_PORT_init(void); -void ADC_0_CLOCK_init(void); -void ADC_0_init(void); - -void FLASH_0_init(void); -void FLASH_0_CLOCK_init(void); - -void SPI_0_PORT_init(void); -void SPI_0_CLOCK_init(void); -void SPI_0_init(void); - -void I2C_0_CLOCK_init(void); -void I2C_0_init(void); -void I2C_0_PORT_init(void); - -void USART_0_PORT_init(void); -void USART_0_CLOCK_init(void); -void USART_0_init(void); - -void delay_driver_init(void); - -void PWM_0_PORT_init(void); -void PWM_0_CLOCK_init(void); -void PWM_0_init(void); - -void DAC_0_PORT_init(void); -void DAC_0_CLOCK_init(void); -void DAC_0_init(void); - -void USB_0_CLOCK_init(void); -void USB_0_init(void); - -/** - * \brief Perform system initialization, initialize pins and clocks for - * peripherals - */ -void system_init(void); - -#ifdef __cplusplus -} -#endif -#endif // DRIVER_INIT_INCLUDED diff --git a/atmel-samd/asf4/samd21/examples/driver_examples.c b/atmel-samd/asf4/samd21/examples/driver_examples.c deleted file mode 100644 index 9fb93dc3e..000000000 --- a/atmel-samd/asf4/samd21/examples/driver_examples.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ - -#include "driver_examples.h" -#include "driver_init.h" -#include "utils.h" - -/** - * Example of using ADC_0 to generate waveform. - */ -void ADC_0_example(void) -{ - uint8_t buffer[2]; - - adc_sync_enable_channel(&ADC_0, 0); - - while (1) { - adc_sync_read_channel(&ADC_0, 0, buffer, 2); - } -} - -static uint8_t src_data[128]; -static uint8_t chk_data[128]; -/** - * Example of using FLASH_0 to read and write buffer. - */ -void FLASH_0_example(void) -{ - uint32_t page_size; - uint16_t i; - - /* Init source data */ - page_size = flash_get_page_size(&FLASH_0); - - for (i = 0; i < page_size; i++) { - src_data[i] = i; - } - - /* Write data to flash */ - flash_write(&FLASH_0, 0x3200, src_data, page_size); - - /* Read data from flash */ - flash_read(&FLASH_0, 0x3200, chk_data, page_size); -} - -/** - * Example of using SPI_0 to write "Hello World" using the IO abstraction. - */ -static uint8_t example_SPI_0[12] = "Hello World!"; - -void SPI_0_example(void) -{ - struct io_descriptor *io; - spi_m_sync_get_io_descriptor(&SPI_0, &io); - - spi_m_sync_enable(&SPI_0); - io_write(io, example_SPI_0, 12); -} - -void I2C_0_example(void) -{ - struct io_descriptor *I2C_0_io; - - i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); - i2c_m_sync_enable(&I2C_0); - i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); - io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); -} - -/** - * Example of using USART_0 to write "Hello World" using the IO abstraction. - */ -void USART_0_example(void) -{ - struct io_descriptor *io; - usart_sync_get_io_descriptor(&USART_0, &io); - usart_sync_enable(&USART_0); - - io_write(io, (uint8_t *)"Hello World!", 12); -} - -void delay_example(void) -{ - delay_ms(5000); -} - -static struct timer_task TIMER_0_task1, TIMER_0_task2; -/** - * Example of using TIMER_0. - */ -static void TIMER_0_task1_cb(const struct timer_task *const timer_task) -{ -} - -static void TIMER_0_task2_cb(const struct timer_task *const timer_task) -{ -} - -void TIMER_0_example(void) -{ - TIMER_0_task1.interval = 100; - TIMER_0_task1.cb = TIMER_0_task1_cb; - TIMER_0_task1.mode = TIMER_TASK_REPEAT; - TIMER_0_task2.interval = 200; - TIMER_0_task2.cb = TIMER_0_task2_cb; - TIMER_0_task2.mode = TIMER_TASK_REPEAT; - - timer_add_task(&TIMER_0, &TIMER_0_task1); - timer_add_task(&TIMER_0, &TIMER_0_task2); - timer_start(&TIMER_0); -} - -/** - * Example of using PWM_0. - */ -void PWM_0_example(void) -{ - pwm_set_parameters(&PWM_0, 10000, 5000); - pwm_enable(&PWM_0); -} - -/** - * Example of using DAC_0 to generate waveform. - */ -void DAC_0_example(void) -{ - uint16_t i = 0; - - dac_sync_enable_channel(&DAC_0, 0); - - for (;;) { - dac_sync_write(&DAC_0, 0, &i, 1); - i = (i + 1) % 1024; - } -} diff --git a/atmel-samd/asf4/samd21/examples/driver_examples.h b/atmel-samd/asf4/samd21/examples/driver_examples.h deleted file mode 100644 index 7a4353b98..000000000 --- a/atmel-samd/asf4/samd21/examples/driver_examples.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef DRIVER_EXAMPLES_H_INCLUDED -#define DRIVER_EXAMPLES_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -void ADC_0_example(void); - -void FLASH_0_example(void); - -void I2C_0_example(void); - -void USART_0_example(void); - -void delay_example(void); - -void PWM_0_example(void); - -void DAC_0_example(void); - -#ifdef __cplusplus -} -#endif -#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/atmel-samd/asf4/samd21/gcc/Makefile b/atmel-samd/asf4/samd21/gcc/Makefile deleted file mode 100644 index 85b5aee2d..000000000 --- a/atmel-samd/asf4/samd21/gcc/Makefile +++ /dev/null @@ -1,286 +0,0 @@ - -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -ifdef SystemRoot - SHELL = cmd.exe - MK_DIR = mkdir -else - ifeq ($(shell uname), Linux) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW32) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW64) - MK_DIR = mkdir -p - endif -endif - -# List the subdirectories for creating object files -SUB_DIRS += \ - \ -hpl/adc \ -hal/src \ -examples \ -hpl/systick \ -hpl/tc \ -usb \ -hpl/dmac \ -usb/class/cdc/device \ -hal/utils/src \ -hpl/rtc \ -usb/class/hid/device \ -hpl/usb \ -samd21a/gcc/gcc \ -hpl/pm \ -hpl/sysctrl \ -hpl/gclk \ -usb/device \ -hpl/dac \ -samd21a/gcc \ -hpl/sercom \ -hpl/nvmctrl \ -hpl/core \ -usb/class/msc/device - -# List the object files -OBJS += \ -hal/src/hal_io.o \ -hpl/systick/hpl_systick.o \ -samd21a/gcc/gcc/startup_samd21.o \ -usb/usb_protocol.o \ -usb/class/hid/device/hiddf_generic.o \ -usb/class/cdc/device/cdcdf_acm.o \ -hal/utils/src/utils_syscalls.o \ -hpl/nvmctrl/hpl_nvmctrl.o \ -usb/class/msc/device/mscdf.o \ -hal/src/hal_spi_m_sync.o \ -hal/src/hal_timer.o \ -hal/src/hal_pwm.o \ -hpl/usb/hpl_usb.o \ -hal/src/hal_i2c_m_sync.o \ -hal/src/hal_delay.o \ -hpl/sysctrl/hpl_sysctrl.o \ -hpl/core/hpl_init.o \ -hal/utils/src/utils_list.o \ -hpl/core/hpl_core_m0plus_base.o \ -hal/utils/src/utils_assert.o \ -hpl/dmac/hpl_dmac.o \ -hpl/pm/hpl_pm.o \ -usb/class/hid/device/hiddf_keyboard.o \ -hal/src/hal_usart_sync.o \ -hpl/dac/hpl_dac.o \ -hpl/gclk/hpl_gclk.o \ -hal/src/hal_flash.o \ -hal/src/hal_init.o \ -hal/src/hal_usb_device.o \ -main.o \ -samd21a/gcc/system_samd21.o \ -hpl/rtc/hpl_rtc.o \ -examples/driver_examples.o \ -driver_init.o \ -hal/src/hal_adc_sync.o \ -hal/src/hal_dac_sync.o \ -hpl/sercom/hpl_sercom.o \ -hal/src/hal_gpio.o \ -usb/class/hid/device/hiddf_mouse.o \ -hal/utils/src/utils_event.o \ -hal/src/hal_sleep.o \ -usb_start.o \ -atmel_start.o \ -usb/device/usbdc.o \ -hpl/tc/hpl_tc.o \ -hal/src/hal_atomic.o \ -hpl/adc/hpl_adc.o - -OBJS_AS_ARGS += \ -"hal/src/hal_io.o" \ -"hpl/systick/hpl_systick.o" \ -"samd21a/gcc/gcc/startup_samd21.o" \ -"usb/usb_protocol.o" \ -"usb/class/hid/device/hiddf_generic.o" \ -"usb/class/cdc/device/cdcdf_acm.o" \ -"hal/utils/src/utils_syscalls.o" \ -"hpl/nvmctrl/hpl_nvmctrl.o" \ -"usb/class/msc/device/mscdf.o" \ -"hal/src/hal_spi_m_sync.o" \ -"hal/src/hal_timer.o" \ -"hal/src/hal_pwm.o" \ -"hpl/usb/hpl_usb.o" \ -"hal/src/hal_i2c_m_sync.o" \ -"hal/src/hal_delay.o" \ -"hpl/sysctrl/hpl_sysctrl.o" \ -"hpl/core/hpl_init.o" \ -"hal/utils/src/utils_list.o" \ -"hpl/core/hpl_core_m0plus_base.o" \ -"hal/utils/src/utils_assert.o" \ -"hpl/dmac/hpl_dmac.o" \ -"hpl/pm/hpl_pm.o" \ -"usb/class/hid/device/hiddf_keyboard.o" \ -"hal/src/hal_usart_sync.o" \ -"hpl/dac/hpl_dac.o" \ -"hpl/gclk/hpl_gclk.o" \ -"hal/src/hal_flash.o" \ -"hal/src/hal_init.o" \ -"hal/src/hal_usb_device.o" \ -"main.o" \ -"samd21a/gcc/system_samd21.o" \ -"hpl/rtc/hpl_rtc.o" \ -"examples/driver_examples.o" \ -"driver_init.o" \ -"hal/src/hal_adc_sync.o" \ -"hal/src/hal_dac_sync.o" \ -"hpl/sercom/hpl_sercom.o" \ -"hal/src/hal_gpio.o" \ -"usb/class/hid/device/hiddf_mouse.o" \ -"hal/utils/src/utils_event.o" \ -"hal/src/hal_sleep.o" \ -"usb_start.o" \ -"atmel_start.o" \ -"usb/device/usbdc.o" \ -"hpl/tc/hpl_tc.o" \ -"hal/src/hal_atomic.o" \ -"hpl/adc/hpl_adc.o" - -# List the dependency files -DEPS := $(OBJS:%.o=%.d) - -DEPS_AS_ARGS += \ -"usb/usb_protocol.d" \ -"samd21a/gcc/gcc/startup_samd21.d" \ -"hal/utils/src/utils_event.d" \ -"hal/src/hal_io.d" \ -"hpl/systick/hpl_systick.d" \ -"usb/class/hid/device/hiddf_generic.d" \ -"hal/utils/src/utils_syscalls.d" \ -"usb/class/cdc/device/cdcdf_acm.d" \ -"usb/class/hid/device/hiddf_mouse.d" \ -"hal/src/hal_i2c_m_sync.d" \ -"hpl/usb/hpl_usb.d" \ -"usb/class/msc/device/mscdf.d" \ -"hpl/nvmctrl/hpl_nvmctrl.d" \ -"hal/src/hal_pwm.d" \ -"hal/src/hal_timer.d" \ -"hal/src/hal_spi_m_sync.d" \ -"hpl/core/hpl_core_m0plus_base.d" \ -"hal/utils/src/utils_list.d" \ -"hpl/dmac/hpl_dmac.d" \ -"hal/utils/src/utils_assert.d" \ -"hal/src/hal_delay.d" \ -"hpl/core/hpl_init.d" \ -"hpl/sysctrl/hpl_sysctrl.d" \ -"hal/src/hal_flash.d" \ -"hpl/gclk/hpl_gclk.d" \ -"hal/src/hal_usb_device.d" \ -"usb_start.d" \ -"hal/src/hal_init.d" \ -"hal/src/hal_usart_sync.d" \ -"usb/class/hid/device/hiddf_keyboard.d" \ -"hpl/dac/hpl_dac.d" \ -"driver_init.d" \ -"hal/src/hal_adc_sync.d" \ -"samd21a/gcc/system_samd21.d" \ -"main.d" \ -"examples/driver_examples.d" \ -"hpl/rtc/hpl_rtc.d" \ -"hal/src/hal_sleep.d" \ -"hpl/sercom/hpl_sercom.d" \ -"hal/src/hal_dac_sync.d" \ -"hal/src/hal_gpio.d" \ -"hal/src/hal_atomic.d" \ -"hpl/tc/hpl_tc.d" \ -"usb/device/usbdc.d" \ -"hpl/pm/hpl_pm.d" \ -"hpl/adc/hpl_adc.d" \ -"atmel_start.d" - -OUTPUT_FILE_NAME :=AtmelStart -QUOTE := " -OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf -OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf - -vpath %.c ../ -vpath %.s ../ -vpath %.S ../ - -# All Target -all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) - -# Linker target - - -$(OUTPUT_FILE_PATH): $(OBJS) - @echo Building target: $@ - @echo Invoking: ARM/GNU Linker - $(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \ --Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m0plus \ - \ - \ --T"../samd21a/gcc/gcc/samd21g18a_flash.ld" \ --L"../samd21a/gcc/gcc" - @echo Finished building target: $@ - - "arm-none-eabi-objcopy" -O binary "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).bin" - "arm-none-eabi-objcopy" -O ihex -R .eeprom -R .fuse -R .lock -R .signature \ - "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).hex" - "arm-none-eabi-objcopy" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma \ - .eeprom=0 --no-change-warnings -O binary "$(OUTPUT_FILE_NAME).elf" \ - "$(OUTPUT_FILE_NAME).eep" || exit 0 - "arm-none-eabi-objdump" -h -S "$(OUTPUT_FILE_NAME).elf" > "$(OUTPUT_FILE_NAME).lss" - "arm-none-eabi-size" "$(OUTPUT_FILE_NAME).elf" - -# Compiler targets - - -%.o: %.c - @echo Building file: $< - @echo ARM/GNU C Compiler - $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAMD21G18A__ -mcpu=cortex-m0plus \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ --MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" - @echo Finished building: $< - -%.o: %.s - @echo Building file: $< - @echo ARM/GNU Assembler - $(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAMD21G18A__ -mcpu=cortex-m0plus \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ --MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" - @echo Finished building: $< - -%.o: %.S - @echo Building file: $< - @echo ARM/GNU Preprocessing Assembler - $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAMD21G18A__ -mcpu=cortex-m0plus \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/nvmctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/sysctrl" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../samd21a/include" \ --MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" - @echo Finished building: $< - -# Detect changes in the dependent files and recompile the respective object files. -ifneq ($(MAKECMDGOALS),clean) -ifneq ($(strip $(DEPS)),) --include $(DEPS) -endif -endif - -$(SUB_DIRS): - $(MK_DIR) "$@" - -clean: - rm -f $(OBJS_AS_ARGS) - rm -f $(OUTPUT_FILE_PATH) - rm -f $(DEPS_AS_ARGS) - rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \ - $(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \ - $(OUTPUT_FILE_NAME).srec diff --git a/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_flash.ld b/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_flash.ld deleted file mode 100644 index 2c94a53ba..000000000 --- a/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_flash.ld +++ /dev/null @@ -1,142 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD21G18A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_sram.ld b/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_sram.ld deleted file mode 100644 index f0462a22d..000000000 --- a/atmel-samd/asf4/samd21/gcc/gcc/samd21g18a_sram.ld +++ /dev/null @@ -1,141 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD21G18A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > ram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ram - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c b/atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c deleted file mode 100644 index 67c95dfe5..000000000 --- a/atmel-samd/asf4/samd21/gcc/gcc/startup_samd21.c +++ /dev/null @@ -1,254 +0,0 @@ -/** - * \file - * - * \brief gcc starttup file for SAMD21 - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "samd21.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M0+ core handlers */ -void NMI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SVC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SYSCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void EIC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void NVMCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void DMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_USB -void USB_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void EVSYS_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SERCOM0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SERCOM1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SERCOM2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SERCOM3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_SERCOM4 -void SERCOM4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_SERCOM5 -void SERCOM5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void TCC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TCC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TCC2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_TC6 -void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC7 -void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_ADC -void ADC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_AC -void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_DAC -void DAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_PTC -void PTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); - -/* Exception Table */ -__attribute__((section(".vectors"), used)) const DeviceVectors exception_table = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void *)(&_estack), - - .pfnReset_Handler = (void *)Reset_Handler, - .pfnNMI_Handler = (void *)NMI_Handler, - .pfnHardFault_Handler = (void *)HardFault_Handler, - .pvReservedM12 = (void *)(0UL), /* Reserved */ - .pvReservedM11 = (void *)(0UL), /* Reserved */ - .pvReservedM10 = (void *)(0UL), /* Reserved */ - .pvReservedM9 = (void *)(0UL), /* Reserved */ - .pvReservedM8 = (void *)(0UL), /* Reserved */ - .pvReservedM7 = (void *)(0UL), /* Reserved */ - .pvReservedM6 = (void *)(0UL), /* Reserved */ - .pfnSVC_Handler = (void *)SVC_Handler, - .pvReservedM4 = (void *)(0UL), /* Reserved */ - .pvReservedM3 = (void *)(0UL), /* Reserved */ - .pfnPendSV_Handler = (void *)PendSV_Handler, - .pfnSysTick_Handler = (void *)SysTick_Handler, - - /* Configurable interrupts */ - .pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */ - .pfnSYSCTRL_Handler = (void *)SYSCTRL_Handler, /* 1 System Control */ - .pfnWDT_Handler = (void *)WDT_Handler, /* 2 Watchdog Timer */ - .pfnRTC_Handler = (void *)RTC_Handler, /* 3 Real-Time Counter */ - .pfnEIC_Handler = (void *)EIC_Handler, /* 4 External Interrupt Controller */ - .pfnNVMCTRL_Handler = (void *)NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */ - .pfnDMAC_Handler = (void *)DMAC_Handler, /* 6 Direct Memory Access Controller */ -#ifdef ID_USB - .pfnUSB_Handler = (void *)USB_Handler, /* 7 Universal Serial Bus */ -#else - .pvReserved7 = (void *)(0UL), /* 7 Reserved */ -#endif - .pfnEVSYS_Handler = (void *)EVSYS_Handler, /* 8 Event System Interface */ - .pfnSERCOM0_Handler = (void *)SERCOM0_Handler, /* 9 Serial Communication Interface 0 */ - .pfnSERCOM1_Handler = (void *)SERCOM1_Handler, /* 10 Serial Communication Interface 1 */ - .pfnSERCOM2_Handler = (void *)SERCOM2_Handler, /* 11 Serial Communication Interface 2 */ - .pfnSERCOM3_Handler = (void *)SERCOM3_Handler, /* 12 Serial Communication Interface 3 */ -#ifdef ID_SERCOM4 - .pfnSERCOM4_Handler = (void *)SERCOM4_Handler, /* 13 Serial Communication Interface 4 */ -#else - .pvReserved13 = (void *)(0UL), /* 13 Reserved */ -#endif -#ifdef ID_SERCOM5 - .pfnSERCOM5_Handler = (void *)SERCOM5_Handler, /* 14 Serial Communication Interface 5 */ -#else - .pvReserved14 = (void *)(0UL), /* 14 Reserved */ -#endif - .pfnTCC0_Handler = (void *)TCC0_Handler, /* 15 Timer Counter Control 0 */ - .pfnTCC1_Handler = (void *)TCC1_Handler, /* 16 Timer Counter Control 1 */ - .pfnTCC2_Handler = (void *)TCC2_Handler, /* 17 Timer Counter Control 2 */ - .pfnTC3_Handler = (void *)TC3_Handler, /* 18 Basic Timer Counter 0 */ - .pfnTC4_Handler = (void *)TC4_Handler, /* 19 Basic Timer Counter 1 */ - .pfnTC5_Handler = (void *)TC5_Handler, /* 20 Basic Timer Counter 2 */ -#ifdef ID_TC6 - .pfnTC6_Handler = (void *)TC6_Handler, /* 21 Basic Timer Counter 3 */ -#else - .pvReserved21 = (void *)(0UL), /* 21 Reserved */ -#endif -#ifdef ID_TC7 - .pfnTC7_Handler = (void *)TC7_Handler, /* 22 Basic Timer Counter 4 */ -#else - .pvReserved22 = (void *)(0UL), /* 22 Reserved */ -#endif -#ifdef ID_ADC - .pfnADC_Handler = (void *)ADC_Handler, /* 23 Analog Digital Converter */ -#else - .pvReserved23 = (void *)(0UL), /* 23 Reserved */ -#endif -#ifdef ID_AC - .pfnAC_Handler = (void *)AC_Handler, /* 24 Analog Comparators */ -#else - .pvReserved24 = (void *)(0UL), /* 24 Reserved */ -#endif -#ifdef ID_DAC - .pfnDAC_Handler = (void *)DAC_Handler, /* 25 Digital Analog Converter */ -#else - .pvReserved25 = (void *)(0UL), /* 25 Reserved */ -#endif -#ifdef ID_PTC - .pfnPTC_Handler = (void *)PTC_Handler, /* 26 Peripheral Touch Controller */ -#else - .pvReserved26 = (void *)(0UL), /* 26 Reserved */ -#endif - .pfnI2S_Handler = (void *)I2S_Handler, /* 27 Inter-IC Sound Interface */ - .pvReserved28 = (void *)(0UL) /* 28 Reserved */ -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *)&_sfixed; - SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); - - /* Change default QOS values to have the best performance and correct USB behaviour */ - SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2; -#if defined(ID_USB) - USB->DEVICE.QOSCTRL.bit.CQOS = 2; - USB->DEVICE.QOSCTRL.bit.DQOS = 2; -#endif - DMAC->QOSCTRL.bit.DQOS = 2; - DMAC->QOSCTRL.bit.FQOS = 2; - DMAC->QOSCTRL.bit.WRBQOS = 2; - - /* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */ - NVMCTRL->CTRLB.bit.MANW = 1; - - /* Initialize the C library */ - //__libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1) - ; -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/atmel-samd/asf4/samd21/gcc/system_samd21.c b/atmel-samd/asf4/samd21/gcc/system_samd21.c deleted file mode 100644 index 274ecccb8..000000000 --- a/atmel-samd/asf4/samd21/gcc/system_samd21.c +++ /dev/null @@ -1,63 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup. - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "samd21.h" - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (1000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} diff --git a/atmel-samd/asf4/samd21/hal/documentation/adc_sync.rst b/atmel-samd/asf4/samd21/hal/documentation/adc_sync.rst deleted file mode 100644 index d189565ad..000000000 --- a/atmel-samd/asf4/samd21/hal/documentation/adc_sync.rst +++ /dev/null @@ -1,74 +0,0 @@ -====================== -ADC Synchronous driver -====================== - -An ADC (Analog-to-Digital Converter) converts analog signals to digital values. -A reference signal with a known voltage level is quantified into equally -sized chunks, each representing a digital value from 0 to the highest number -possible with the bit resolution supported by the ADC. The input voltage -measured by the ADC is compared against these chunks and the chunk with the -closest voltage level defines the digital value that can be used to represent -the analog input voltage level. - -Usually an ADC can operate in either differential or single-ended mode. -In differential mode two signals (V+ and V-) are compared against each other -and the resulting digital value represents the relative voltage level between -V+ and V-. This means that if the input voltage level on V+ is lower than on -V- the digital value is negative, which also means that in differential -mode one bit is lost to the sign. In single-ended mode only V+ is compared -against the reference voltage, and the resulting digital value can only be -positive, but the full bit-range of the ADC can be used. - -Usually multiple resolutions are supported by the ADC, lower resolution can -reduce the conversion time, but lose accuracy. - -Some ADCs has a gain stage on the input lines which can be used to increase the -dynamic range. The default gain value is usually x1, which means that the -conversion range is from 0V to the reference voltage. -Applications can change the gain stage, to increase or reduce the conversion -range. - -The window mode allows the conversion result to be compared to a set of -predefined threshold values. Applications can use callback function to monitor -if the conversion result exceeds predefined threshold value. - -Usually multiple reference voltages are supported by the ADC, both internal and -external with difference voltage levels. The reference voltage have an impact -on the accuracy, and should be selected to cover the full range of the analog -input signal and never less than the expected maximum input voltage. - -There are two conversion modes supported by ADC, single shot and free running. -In single shot mode the ADC only make one conversion when triggered by the -application, in free running mode it continues to make conversion from it -is triggered until it is stopped by the application. When window monitoring, -the ADC should be set to free running mode. - -Features --------- -* Initialization and de-initialization -* Support multiple Conversion Mode, Single or Free run -* Start ADC Conversion -* Read Conversion Result - -Applications ------------- -* Measurement of internal sensor. E.g., MCU internal temperature sensor value. -* Measurement of external sensor. E.g., Temperature, humidity sensor value. -* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave. - -Dependencies ------------- -* ADC hardware - -Concurrency ------------ -N/A - -Limitations ------------ -N/A - -Knows issues and workarounds ----------------------------- -N/A - diff --git a/atmel-samd/asf4/samd21/hal/documentation/dac_sync.rst b/atmel-samd/asf4/samd21/hal/documentation/dac_sync.rst deleted file mode 100644 index b3f322929..000000000 --- a/atmel-samd/asf4/samd21/hal/documentation/dac_sync.rst +++ /dev/null @@ -1,41 +0,0 @@ -====================== -DAC Synchronous driver -====================== - -A DAC (Digital-to-Analog Converter) converts digital value to an analog voltage. -The digital value from 0 to the highest represent the output voltage value. -The digital highest value possible with the bit resolution supported by the -DAC. For example a 10 bit resolution DAC hardware, the highest value is 1024. -The highest output voltage possible with the reference voltage. - -The driver can convert a serials digital value. The pre-defined data should -be an data array. Application can invoke dac_sync_write to start the conversation. - -Features --------- -* Initialization and de-initialization -* Enabling and disabling -* Support for DACs with channels -* Writing buffers with multiple samples to DAC - -Applications ------------- -* Generate audio signals by connecting the DAC output to a speaker -* Generate a reference voltage - -Dependencies ------------- -* DAC hardware - -Concurrency ------------ -N/A - -Limitations ------------ -N/A - -Knows issues and workarounds ----------------------------- -N/A - diff --git a/atmel-samd/asf4/samd21/hal/documentation/flash.rst b/atmel-samd/asf4/samd21/hal/documentation/flash.rst deleted file mode 100644 index fcc86e63f..000000000 --- a/atmel-samd/asf4/samd21/hal/documentation/flash.rst +++ /dev/null @@ -1,52 +0,0 @@ -The Flash Driver -================ - -Flash is a re-programmable memory that retains program and data -storage even with power off. - -User can write or read several bytes from any valid address in a flash. - -As to the erase/lock/unlock command, the input parameter of address should -be a bytes address aligned with the page start, otherwise, the command will fail -to be executed. At the meantime, the number of pages that can be locked or unlocked -at once depends on region size of the flash. User can get the real number -from the function return value which could be different for the different devices. - -Features --------- - -* Initialization/de-initialization -* Writing/Reading bytes -* Locking/Unlocking/Erasing pages -* Notifications about errors or being ready for a new command - -Applications ------------- - -* Mini disk which can retain program and data storage -* Boot loader -* Non volatile storage - -Dependencies ------------- - -The peripheral which controls a re-programmable flash memory. - -Concurrency ------------ - -N/A - -Limitations ------------ - -User should pay attention to set a proper stack size in their application, -since the driver manages a temporary buffer in stack to cache unchanged data -when calling flash write and erase function. -Due to flash memory architecture of SAMD21/D20/L21/L22/C20/C21/D09/D10/D11/R21, -write operation erazes row content before each write. - -Known issues and workarounds ----------------------------- - -N/A diff --git a/atmel-samd/asf4/samd21/hal/documentation/i2c_master_sync.rst b/atmel-samd/asf4/samd21/hal/documentation/i2c_master_sync.rst deleted file mode 100644 index 77b4f6e9c..000000000 --- a/atmel-samd/asf4/samd21/hal/documentation/i2c_master_sync.rst +++ /dev/null @@ -1,87 +0,0 @@ -============================= -I2C Master synchronous driver -============================= - -I2C (Inter-Integrated Circuit) is a two wire serial interface usually used -for on-board low-speed bi-directional communication between controllers and -peripherals. The master device is responsible for initiating and controlling -all transfers on the I2C bus. Only one master device can be active on the I2C -bus at the time, but the master role can be transferred between devices on the -same I2C bus. I2C uses only two bidirectional open-drain lines, usually -designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up -resistors. - -The stop condition is automatically controlled by the driver if the I/O write and -read functions are used, but can be manually controlled by using the -i2c_m_sync_transfer function. - -Often a master accesses different information in the slave by accessing -different registers in the slave. This is done by first sending a message to -the target slave containing the register address, followed by a repeated start -condition (no stop condition between) ending with transferring register data. -This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read -function, but limited to 8-bit register addresses. - -I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in -Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to -stick within the SCL clock frequency range supported by the selected mode. -The requested SCL clock frequency is not validated by the -i2c_m_sync_set_baudrate function against the selected I2C mode. - -Features --------- - - * I2C Master support - * Initialization and de-initialization - * Enabling and disabling - * Run-time bus speed configuration - * Write and read I2C messages - * Slave register access functions (limited to 8-bit address) - * Manual or automatic stop condition generation - * 10- and 7- bit addressing - * I2C Modes supported - +----------------------+-------------------+ - |* Standard/Fast mode | (SCL: 1 - 400kHz) | - +----------------------+-------------------+ - |* Fastmode+ | (SCL: 1 - 1000kHz)| - +----------------------+-------------------+ - |* Highspeed mode | (SCL: 1 - 3400kHz)| - +----------------------+-------------------+ - -Applications ------------- - -* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals -* Data communication between micro controllers -* Controlling displays - -Dependencies ------------- - -* I2C Master capable hardware - -Concurrency ------------ - -N/A - -Limitations ------------ - -General -^^^^^^^ - - * System Managmenet Bus (SMBus) not supported. - * Power Management Bus (PMBus) not supported. - -Clock considerations -^^^^^^^^^^^^^^^^^^^^ - -The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected. - -Known issues and workarounds ----------------------------- - -N/A - - diff --git a/atmel-samd/asf4/samd21/hal/documentation/pwm.rst b/atmel-samd/asf4/samd21/hal/documentation/pwm.rst deleted file mode 100644 index 71785c634..000000000 --- a/atmel-samd/asf4/samd21/hal/documentation/pwm.rst +++ /dev/null @@ -1,53 +0,0 @@ -The PWM Driver(bare-bone) -========================= - -Pulse-width modulation (PWM) is used to create an analog behavior -digitally by controlling the amount of power transferred to the -connected peripheral. This is achieved by controlling the high period -(duty-cycle) of a periodic signal. - -User can change the period or duty cycle whenever PWM is running. The -function pwm_set_parameters is used to configure these two parameters. -Note these are raw register values and the parameter duty_cycle means -the period of first half during one cycle, which should be not beyond -total period value. - -In addition, user can also get multi PWM channels output from different -peripherals at the same time, which is implemented more flexible by the -function pointers. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* Run-time control of PWM duty-cycle and period -* Notifications about errors and one PWM cycle is done - -Applications ------------- - -Motor control, ballast, LED, H-bridge, power converters, and -other types of power control applications. - -Dependencies ------------- - -The peripheral which can perform waveform generation like frequency -generation and pulse-width modulation, such as Timer/Counter. - -Concurrency ------------ - -N/A - -Limitations ------------ - -The current driver doesn't support the features like recoverable, -non-recoverable faults, dithering, dead-time insertion. - -Known issues and workarounds ----------------------------- - -N/A diff --git a/atmel-samd/asf4/samd21/hal/documentation/spi_master_sync.rst b/atmel-samd/asf4/samd21/hal/documentation/spi_master_sync.rst deleted file mode 100644 index 4fbe45e29..000000000 --- a/atmel-samd/asf4/samd21/hal/documentation/spi_master_sync.rst +++ /dev/null @@ -1,51 +0,0 @@ -The SPI Master Synchronous Driver -================================= - -The serial peripheral interface (SPI) is a synchronous serial communication -interface. - -SPI devices communicate in full duplex mode using a master-slave -architecture with a single master. The master device originates the frame for -reading and writing. Multiple slave devices are supported through selection -with individual slave select (SS) lines. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* Control of the following settings: - - * Baudrate - * SPI mode - * Character size - * Data order -* Data transfer: transmission, reception and full-duplex - -Applications ------------- - -Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card, -LCD controller, etc. - -Dependencies ------------- - -SPI master capable hardware - -Concurrency ------------ - -N/A - -Limitations ------------ - -The slave select (SS) is not automatically inserted during read/write/transfer, -user must use I/O to control the devices' SS. - -Known issues and workarounds ----------------------------- - -N/A - diff --git a/atmel-samd/asf4/samd21/hal/documentation/timer.rst b/atmel-samd/asf4/samd21/hal/documentation/timer.rst deleted file mode 100644 index c5ca63d12..000000000 --- a/atmel-samd/asf4/samd21/hal/documentation/timer.rst +++ /dev/null @@ -1,52 +0,0 @@ -============================ -The Timer driver (bare-bone) -============================ - -The Timer driver provides means for delayed and periodical function invocation. - -A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has -been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a -configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically -changes execution delays and periods for all tasks in the timers task queue. - -A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue -and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on -the period set in the task configuration. -In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to -reuse the memory of expired task in the callback. - -Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available. - -Features --------- -* Initialization and de-initialization -* Starting and stopping -* Timer tasks - periodical invocation of functions -* Changing and obtaining of the period of a timer - -Applications ------------- -* Delayed and periodical function execution for middle-ware stacks and applications. - -Dependencies ------------- -* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt. - -Concurrency ------------ -The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during -the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed -until the task adding or removing is complete. - -The task queue is not protected from the access by interrupts not used by the driver. Due to this -it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes -the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver. - -Limitations ------------ -* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts. -* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task. - -Knows issues and workarounds ----------------------------- -Not applicable diff --git a/atmel-samd/asf4/samd21/hal/documentation/usart_sync.rst b/atmel-samd/asf4/samd21/hal/documentation/usart_sync.rst deleted file mode 100644 index 73f76b749..000000000 --- a/atmel-samd/asf4/samd21/hal/documentation/usart_sync.rst +++ /dev/null @@ -1,58 +0,0 @@ -The USART Synchronous Driver -============================ - -The universal synchronous and asynchronous receiver and transmitter -(USART) is usually used to transfer data from one device to the other. - -User can set action for flow control pins by function usart_set_flow_control, -if the flow control is enabled. All the available states are defined in union -usart_flow_control_state. - -Note that user can set state of flow control pins only if automatic support of -the flow control is not supported by the hardware. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* Control of the following settings: - - * Baudrate - * UART or USRT communication mode - * Character size - * Data order - * Flow control -* Data transfer: transmission, reception - -Applications ------------- - -They are commonly used in a terminal application or low-speed communication -between devices. - -Dependencies ------------- - -USART capable hardware. - -Concurrency ------------ - -Write buffer should not be changed while data is being sent. - - -Limitations ------------ - -* The driver does not support 9-bit character size. -* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. -And the SCK pin can't be set directly. Application can use a GCLK output PIN -to generate SCK. For example to communicate with a SMARTCARD with ISO7816 -(F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be -config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. - -Known issues and workarounds ----------------------------- - -N/A diff --git a/atmel-samd/asf4/samd21/hal/documentation/usb_device_async.rst b/atmel-samd/asf4/samd21/hal/documentation/usb_device_async.rst deleted file mode 100644 index 647eec071..000000000 --- a/atmel-samd/asf4/samd21/hal/documentation/usb_device_async.rst +++ /dev/null @@ -1,195 +0,0 @@ -The USB Device Asynchronous Driver -================================== - -Universal Serial Bus (USB) is an industry standard that defines the cables, -connectors and communication protocols used in a bus for connection, -communication, and power supply between computers and electronic devices. - -The USB device driver provides necessary APIs to support USB Device states and -USB data flow. So that the USB Device enumeration, class and vendor support can -be implemented base on it. The driver is asynchronous, which means that all USB -data processing is done in callbacks.. - -To be recognized by a host, a USB device must handle a subset of the USB events. -The USB device should build up control communication to report its descriptors -to the host and accept host's requests. An application or upper stack that uses -the USB device driver should have its descriptors prepared, catch the callbacks, -monitor the control requests and handle them correctly. -Usually, a USB device application that can be enumerated may use the following -sequence: - -* Initialize -* Register callback and handle Reset event, where: - - * Initialize endpoint 0 - * Register callbacks for endpoint 0, where some of the standard requests - defined in Chapter 9, USB specification - (see `USB 2.0 Documents `_) - are handled - - * Setup request handling callback - - * On *GetDeviceDescriptor* request, sends device descriptor - * On *GetConfigurationDescriptor* request, sends configuration descriptors - * On *SetAddress* request sends no data, just goes to status phase - * On *SetConfigure* request initialize and enable other endpoints, sends - no data, just goes to status phase - * Transfer done handling callback - - * On *SetAddress* request apply the new address - * On *SetConfigure* request a global variable can be set to indicates - that the host driver is loaded and device is ready to work - * Enable endpoint 0 -* Enable -* Attach device - -To support USB transfer on endpoints, endpoints information is stored -by the driver internally, including control request data, endpoint status, -callbacks and transfer data pointers. The number of endpoints that the driver -can support is defined through configuration. To optimize RAM usage, the -number of endpoints the driver needs to support should be minimized. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* USB device attachment/detachment -* USB device address control -* USB working speed status -* USB device frame number and micro frame number status -* Sending remote wakeup to host -* Callback management for following USB events: - - * Start of Frame (SOF) - * Other USB events: - - * VBus change - * Reset - * Wakeup - * Linked Power Management (LPM) Suspend - * Suspend - * Error -* Endpoints management: - - * Endpoint initialization/de-initialization - * Endpoint enabling/disabling - * Control endpoint setup request packet - * Data transfer and abort - * Endpoint halt state control - * Endpoint status, including: - - * Endpoint address - * Last transfer result status code - * Last error status code - * Current transfer state - * Transfer size and done count - * Endpoint callback management for endpoint and its transfer events: - - * In case a setup request received on control endpoint - * In case transfer finished with/without error - -Applications ------------- - -USB Device stack, to monitor USB events, handle control requests and process -data. - -Dependencies ------------- - -* USB device capable hardware -* 48MHz clock for low-speed and full-speed and 480MHz clock for high-speed - -Concurrency ------------ - -N/A - -Limitations ------------ - -* When a buffer is used by a USB endpoint to transfer data, it must be kept - unchanged while the transfer is in progress. -* After receiving a request that has no data expected, the transfer function - must be called with data length zero to complete control status phase. - -Known issues and workarounds ----------------------------- - -N/A - -Considerations for D21 USB --------------------------- - -Clocks -^^^^^^ - -DFLL must be used to generate 48MHz clock for USB device with either of the -following mode: - -* USB Clock Recovery Mode - - * Set "DFLL Enable", "Bypass Coarse Lock", "Chill Cycle Disable", - "USB Clock Recovery Mode", "Stable DFLL Frequency" - * Clear "Wait Lock" - * Leave "Operating Mode Selection" to "Closed Loop Mode" - -* Closed Loop Mode - - * Set "DFLL Enable" - * Clear "USB Clock Recovery Mode", "Stable DFLL Frequency" - * Select "Closed Loop Mode" of "Operating Mode Selection" - * Set "DFLL Multiply Factor" to 1464 or 1465 (48000000/32768) - * Select "Reference Clock Source" to use 32768Hz source, e.g., use GCLK1 and - for GCLK1 settings: - - * Set "Generic Clock Generator Enable" - * Select "XOSC32K" of "Generic clock generator 1 source", and for XOSC32K - settings: - - * Set "External 32K Oscillator Enable", "Enable 32KHz Output", - "Enable XTAL" - * Set a right value for "Startup time for the 32K Oscillator", e.g., - 1125092 us - -Endpoints -^^^^^^^^^ - -Each USB device endpoint number supports two endpoint addresses, corresponding -to IN and OUT endpoint. E.g., for endpoint 1, the endpoint IN has address 0x81 -and endpoint OUT has address 0x01. Thus, the possible supported endpoint -addresses are almost two times of max endpoint number (endpoint 0 must be used -as control endpoint instead of dedicated IN and OUT endpoints). - -Buffering and RAM usage optimization -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -When transferring data through USB device endpoints, buffer pointers can be -used to let endpoint get access to the buffer, but there are some limits: - -* For control endpoint there must always be a buffer available to put received - setup packet. -* For IN endpoint (transmit to host) the data must in RAM. -* For OUT endpoint (receive from host) the data pointer must be aligned, and - the data size must be aligned by max endpoint size and not zero. - -The driver has option for each endpoint to allocate internal static buffer as -cache to buffer input/output data, to remove upper limits. The configuration -affects the parameter check of transfer functions, and the RAM usage. - -* For control endpoints, cache buffer must be enabled to fill setup packet. - In addition, to support unaligned OUT packet and IN packet inside flash, the - buffer size must be equal to or larger than max endpoint size. -* For OUT endpoints, if the cache is allocated, it's possible to pass unaligned - buffer address and buffer size to transfer function. Else the transfer - function only accepts aligned buffer with it's size multiple of endpoint - packet size. -* For IN endpoints, if the cache is allocated, it's possible to pass buffer - pointer to internal flash or other memory part other than RAM to the transfer - function. - -To optimize the RAM usage, the configuration of max endpoint number, max number -of endpoints supported and the buffer usage of used input and/or output -endpoints can be adjusted. - diff --git a/atmel-samd/asf4/samd21/hal/include/hal_adc_sync.h b/atmel-samd/asf4/samd21/hal/include/hal_adc_sync.h deleted file mode 100644 index fb4604aa5..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_adc_sync.h +++ /dev/null @@ -1,287 +0,0 @@ -/** - * \file - * - * \brief ADC functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_ADC_SYNC_H_INCLUDED -#define _HAL_ADC_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_adc_sync - * - * @{ - */ - -/** - * \brief ADC descriptor - * - * The ADC descriptor forward declaration. - */ -struct adc_sync_descriptor; - -/** - * \brief ADC descriptor - */ -struct adc_sync_descriptor { - /** ADC device */ - struct _adc_sync_device device; -}; - -/** - * \brief Initialize ADC - * - * This function initializes the given ADC descriptor. - * It checks if the given hardware is not initialized and if the given hardware - * is permitted to be initialized. - * - * \param[out] descr An ADC descriptor to initialize - * \param[in] hw The pointer to hardware instance - * \param[in] func The pointer to a set of functions pointers - * - * \return Initialization status. - */ -int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func); - -/** - * \brief Deinitialize ADC - * - * This function deinitializes the given ADC descriptor. - * It checks if the given hardware is initialized and if the given hardware is - * permitted to be deinitialized. - * - * \param[in] descr An ADC descriptor to deinitialize - * - * \return De-initialization status. - */ -int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr); - -/** - * \brief Enable ADC - * - * Use this function to set the ADC peripheral to enabled state. - * - * \param[in] descr Pointer to the ADC descriptor - * \param[in] channel Channel number - * - * \return Operation status - * - */ -int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel); - -/** - * \brief Disable ADC - * - * Use this function to set the ADC peripheral to disabled state. - * - * \param[in] descr Pointer to the ADC descriptor - * \param[in] channel Channel number - * - * \return Operation status - * - */ -int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel); - -/** - * \brief Read data from ADC - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] channel Channel number - * \param[in] buf A buffer to read data to - * \param[in] length The size of a buffer - * - * \return The number of bytes read. - */ -int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, - const uint16_t length); - -/** - * \brief Set ADC reference source - * - * This function sets ADC reference source. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] reference A reference source to set - * - * \return Status of the ADC reference source setting. - */ -int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference); - -/** - * \brief Set ADC resolution - * - * This function sets ADC resolution. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] resolution A resolution to set - * - * \return Status of the ADC resolution setting. - */ -int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution); - -/** - * \brief Set ADC input source of a channel - * - * This function sets ADC positive and negative input sources. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] pos_input A positive input source to set - * \param[in] neg_input A negative input source to set - * \param[in] channel Channel number - * - * \return Status of the ADC channels setting. - */ -int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel); - -/** - * \brief Set ADC conversion mode - * - * This function sets ADC conversion mode. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] mode A conversion mode to set - * - * \return Status of the ADC conversion mode setting. - */ -int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode); - -/** - * \brief Set ADC differential mode - * - * This function sets ADC differential mode. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] channel Channel number - * \param[in] mode A differential mode to set - * - * \return Status of the ADC differential mode setting. - */ -int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel, - const enum adc_differential_mode mode); - -/** - * \brief Set ADC channel gain - * - * This function sets ADC channel gain. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] channel Channel number - * \param[in] gain A gain to set - * - * \return Status of the ADC gain setting. - */ -int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, - const adc_gain_t gain); - -/** - * \brief Set ADC window mode - * - * This function sets ADC window mode. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] mode A window mode to set - * - * \return Status of the ADC window mode setting. - */ -int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode); - -/** - * \brief Set ADC thresholds - * - * This function sets ADC positive and negative thresholds. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] low_threshold A lower thresholds to set - * \param[in] up_threshold An upper thresholds to set - * - * \return Status of the ADC thresholds setting. - */ -int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold); - -/** - * \brief Retrieve threshold state - * - * This function retrieves ADC threshold state. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[out] state The threshold state - * - * \return The state of ADC thresholds state retrieving. - */ -int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, - adc_threshold_status_t *const state); - -/** - * \brief Check if conversion is complete - * - * This function checks if the ADC has finished the conversion. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] channel Channel number - * - * \return The status of ADC conversion completion checking. - * \retval 1 The conversion is complete - * \retval 0 The conversion is not complete - */ -int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t adc_sync_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#include - -#endif /* _HAL_ADC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_atomic.h b/atmel-samd/asf4/samd21/hal/include/hal_atomic.h deleted file mode 100644 index 8a51b2a96..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_atomic.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * \file - * - * \brief Critical sections related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_ATOMIC_H_INCLUDED -#define _HAL_ATOMIC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_atomic - * - *@{ - */ - -/** - * \brief Type for the register holding global interrupt enable flag - */ -typedef uint32_t hal_atomic_t; - -/** - * \brief Helper macro for entering critical sections - * - * This macro is recommended to be used instead of a direct call - * hal_enterCritical() function to enter critical - * sections. No semicolon is required after the macro. - * - * \section atomic_usage Usage Example - * \code - * CRITICAL_SECTION_ENTER() - * Critical code - * CRITICAL_SECTION_LEAVE() - * \endcode - */ -#define CRITICAL_SECTION_ENTER() \ - { \ - volatile hal_atomic_t __atomic; \ - atomic_enter_critical(&__atomic); - -/** - * \brief Helper macro for leaving critical sections - * - * This macro is recommended to be used instead of a direct call - * hal_leaveCritical() function to leave critical - * sections. No semicolon is required after the macro. - * - * \section atomic_usage Usage Example - * \code - * CRITICAL_SECTION_ENTER() - * Some critical code - * CRITICAL_SECTION_LEAVE() - * \endcode - */ -#define CRITICAL_SECTION_LEAVE() \ - atomic_leave_critical(&__atomic); \ - } - -/** - * \brief Disable interrupts, enter critical section - * - * Disables global interrupts. Supports nested critical sections, - * so that global interrupts are only re-enabled - * upon leaving the outermost nested critical section. - * - * \param[out] atomic The pointer to a variable to store the value of global - * interrupt enable flag - */ -void atomic_enter_critical(hal_atomic_t volatile *atomic); - -/** - * \brief Exit atomic section - * - * Enables global interrupts. Supports nested critical sections, - * so that global interrupts are only re-enabled - * upon leaving the outermost nested critical section. - * - * \param[in] atomic The pointer to a variable, which stores the latest stored - * value of the global interrupt enable flag - */ -void atomic_leave_critical(hal_atomic_t volatile *atomic); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t atomic_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_dac_sync.h b/atmel-samd/asf4/samd21/hal/include/hal_dac_sync.h deleted file mode 100644 index 79c68b2cb..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_dac_sync.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - * \file - * - * \brief DAC functionality declaration. - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef HAL_SYNC_DAC_H_INCLUDED -#define HAL_SYNC_DAC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_dac_sync - * - *@{ - */ - -/** - * \brief DAC synchronous descriptor. - * - * The DAC descriptor forward declaration. - */ -struct dac_sync_descriptor; - -/** - * \brief DAC synchronous channel descriptor. - * - */ -struct dac_sync_channel { - /** Pointer to buffer what to be converted */ - uint16_t *buffer; - /** The length of buffer */ - uint32_t length; -}; - -/** - * \brief DAC synchronous descriptor - */ -struct dac_sync_descriptor { - /** DAC device */ - struct _dac_sync_device device; - /** DAC selected channel */ - struct dac_sync_channel sel_ch[CHANNEL_NUM]; -}; - -/** \brief Initialize the DAC HAL instance and hardware. - * \param[out] descr A DAC descriptor to initialize - * \param[in] hw The pointer to hardware instance - * \return Operation status. - */ -int32_t dac_sync_init(struct dac_sync_descriptor *const descr, void *const hw); - -/** \brief Deinitialize the DAC HAL instance and hardware. - * \param[in] descr Pointer to the HAL DAC descriptor - * \return Operation status. - */ -int32_t dac_sync_deinit(struct dac_sync_descriptor *const descr); - -/** \brief Enable DAC channel. - * \param[in] descr Pointer to the HAL DAC descriptor - * \param[in] ch Channel number - * \return Operation status. - */ -int32_t dac_sync_enable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch); - -/** \brief Disable DAC channel. - * \param[in] descr Pointer to the HAL DAC descriptor - * \param[in] ch Channel number - * \return Operation status. - */ -int32_t dac_sync_disable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch); - -/** \brief DAC converts digital data to analog output. - * \param[in] descr Pointer to the HAL DAC descriptor - * \param[in] ch the Channel selected to output - * \param[in] buffer Pointer to digital data or buffer - * \param[in] length The number of elements in the buffer - * \return Operation status. - */ -int32_t dac_sync_write(struct dac_sync_descriptor *const descr, const uint8_t ch, uint16_t *buffer, uint32_t length); - -/** \brief Get DAC driver version - * - * \return Current driver version. - */ -uint32_t dac_sync_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_DAC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_delay.h b/atmel-samd/asf4/samd21/hal/include/hal_delay.h deleted file mode 100644 index 48fee826f..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_delay.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * \file - * - * \brief HAL delay related functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -#ifndef _HAL_DELAY_H_INCLUDED -#define _HAL_DELAY_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_delay Delay Driver - * - *@{ - */ - -/** - * \brief Initialize Delay driver - * - * \param[in] hw The pointer to hardware instance - */ -void delay_init(void *const hw); - -/** - * \brief Perform delay in us - * - * This function performs delay for the given amount of microseconds. - * - * \param[in] us The amount delay in us - */ -void delay_us(const uint16_t us); - -/** - * \brief Perform delay in ms - * - * This function performs delay for the given amount of milliseconds. - * - * \param[in] ms The amount delay in ms - */ -void delay_ms(const uint16_t ms); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t delay_get_version(void); - -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_flash.h b/atmel-samd/asf4/samd21/hal/include/hal_flash.h deleted file mode 100644 index ffba519de..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_flash.h +++ /dev/null @@ -1,219 +0,0 @@ -/** - * \file - * - * \brief Flash related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_FLASH_H_INCLUDED -#define _HAL_FLASH_H_INCLUDED - -#include - -/** - * \addtogroup doc_driver_hal_flash - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Forward declaration of flash_descriptor. */ -struct flash_descriptor; - -/** The callback types */ -enum flash_cb_type { - /** Callback type for ready to accept a new command */ - FLASH_CB_READY, - /** Callback type for error */ - FLASH_CB_ERROR, - FLASH_CB_N -}; - -/** \brief Prototype of callback on FLASH - * - */ -typedef void (*flash_cb_t)(struct flash_descriptor *const descr); - -/** \brief FLASH HAL callbacks - * - */ -struct flash_callbacks { - /** Callback invoked when ready to accept a new command */ - flash_cb_t cb_ready; - /** Callback invoked when error occurs */ - flash_cb_t cb_error; -}; - -/** \brief FLASH HAL driver struct for asynchronous access - */ -struct flash_descriptor { - /** Pointer to FLASH device instance */ - struct _flash_device dev; - /** Callbacks for asynchronous transfer */ - struct flash_callbacks callbacks; -}; - -/** \brief Initialize the FLASH HAL instance and hardware for callback mode - * - * Initialize FLASH HAL with interrupt mode (uses callbacks). - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] hw Pointer to the hardware base. - * \return Initialize status. - */ -int32_t flash_init(struct flash_descriptor *flash, void *const hw); - -/** \brief Deinitialize the FLASH HAL instance - * - * Abort transfer, disable and reset FLASH, and deinitialize software. - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \return Deinitialze status. - */ -int32_t flash_deinit(struct flash_descriptor *flash); - -/** \brief Writes a number of bytes to a page in the internal Flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address to write into flash - * \param[in] buffer Pointer to a buffer where the content - * will be written to the flash - * \param[in] length Number of bytes to write - * \return Write status. - */ -int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); - -/** \brief Appends a number of bytes to a page in the internal Flash - * - * This functions never erases the flash before writing. - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address to write to flash - * \param[in] buffer Pointer to a buffer with data to write to flash - * \param[in] length Number of bytes to append - * \return Append status. - */ -int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - -/** \brief Reads a number of bytes to a page in the internal Flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] src_addr Source bytes address to read from flash - * \param[out] buffer Pointer to a buffer where the content - * of the read pages will be stored - * \param[in] length Number of bytes to read - * \return Read status. - */ -int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length); - -/** \brief Register a function as FLASH transfer completion callback - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] type Callback type (\ref flash_cb_type). - * \param[in] func Pointer to callback function. - * \retval 0 Success - * \retval -1 Error - */ -int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func); - -/** \brief Execute lock in the internal flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address aligned with page - * start to be locked - * \param[in] page_nums Number of pages to be locked - * - * \return Real locked numbers of pages. - */ -int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); - -/** \brief Execute unlock in the internal flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address aligned with page - * start to be unlocked - * \param[in] page_nums Number of pages to be unlocked - * - * \return Real unlocked numbers of pages. - */ -int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); - -/** \brief Execute erase in the internal flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address aligned with page - * start to be erased - * \param[in] page_nums Number of pages to be erased - * \retval 0 Success - * \retval -1 Error - */ -int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); - -/** - * \brief Get the flash page size - * - * \param[in, out] flash Pointer to the HAL FLASH instance - * - * \return The flash page size - */ -uint32_t flash_get_page_size(struct flash_descriptor *flash); - -/** - * \brief Get the number of flash page - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * - * \return The flash total page numbers - */ -uint32_t flash_get_total_pages(struct flash_descriptor *flash); - -/** \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t flash_get_version(void); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* ifndef _HAL_FLASH_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_gpio.h b/atmel-samd/asf4/samd21/hal/include/hal_gpio.h deleted file mode 100644 index f0e8af8d7..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_gpio.h +++ /dev/null @@ -1,212 +0,0 @@ -/** - * \file - * - * \brief Port - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ -#ifndef _HAL_GPIO_INCLUDED_ -#define _HAL_GPIO_INCLUDED_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Set gpio pull mode - * - * Set pin pull mode, non existing pull modes throws an fatal assert - * - * \param[in] pin The pin number for device - * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin high with internal - * resistor - * GPIO_PULL_UP = Pull pin low with internal resistor - * GPIO_PULL_OFF = Disable pin pull mode - */ -static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) -{ - _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); -} - -/** - * \brief Set pin function - * - * Select which function a pin will be used for - * - * \param[in] pin The pin number for device - * \param[in] function The pin function is given by a 32-bit wide bitfield - * found in the header files for the device - * - */ -static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) -{ - _gpio_set_pin_function(pin, function); -} - -/** - * \brief Set port data direction - * - * Select if the pin data direction is input, output or disabled. - * If disabled state is not possible, this function throws an assert. - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to the - * corresponding pin - * \param[in] direction GPIO_DIRECTION_IN = Data direction in - * GPIO_DIRECTION_OUT = Data direction out - * GPIO_DIRECTION_OFF = Disables the pin - * (low power state) - */ -static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction) -{ - _gpio_set_direction(port, mask, direction); -} - -/** - * \brief Set gpio data direction - * - * Select if the pin data direction is input, output or disabled. - * If disabled state is not possible, this function throws an assert. - * - * \param[in] pin The pin number for device - * \param[in] direction GPIO_DIRECTION_IN = Data direction in - * GPIO_DIRECTION_OUT = Data direction out - * GPIO_DIRECTION_OFF = Disables the pin - * (low power state) - */ -static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) -{ - _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); -} - -/** - * \brief Set port level - * - * Sets output level on the pins defined by the bit mask - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply port level to the corresponding - * pin - * \param[in] level true = Pin levels set to "high" state - * false = Pin levels set to "low" state - */ -static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) -{ - _gpio_set_level(port, mask, level); -} - -/** - * \brief Set gpio level - * - * Sets output level on a pin - * - * \param[in] pin The pin number for device - * \param[in] level true = Pin level set to "high" state - * false = Pin level set to "low" state - */ -static inline void gpio_set_pin_level(const uint8_t pin, const bool level) -{ - _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); -} - -/** - * \brief Toggle out level on pins - * - * Toggle the pin levels on pins defined by bit mask - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding - * pin - */ -static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) -{ - _gpio_toggle_level(port, mask); -} - -/** - * \brief Toggle output level on pin - * - * Toggle the pin levels on pins defined by bit mask - * - * \param[in] pin The pin number for device - */ -static inline void gpio_toggle_pin_level(const uint8_t pin) -{ - _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); -} - -/** - * \brief Get input level on pins - * - * Read the input level on pins connected to a port - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - */ -static inline uint32_t gpio_get_port_level(const enum gpio_port port) -{ - return _gpio_get_level(port); -} - -/** - * \brief Get level on pin - * - * Reads the level on pins connected to a port - * - * \param[in] pin The pin number for device - */ -static inline bool gpio_get_pin_level(const uint8_t pin) -{ - return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); -} -/** - * \brief Get current driver version - */ -uint32_t gpio_get_version(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/atmel-samd/asf4/samd21/hal/include/hal_i2c_m_sync.h b/atmel-samd/asf4/samd21/hal/include/hal_i2c_m_sync.h deleted file mode 100644 index 65741831a..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_i2c_m_sync.h +++ /dev/null @@ -1,254 +0,0 @@ -/** - * \file - * - * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_I2C_M_SYNC_H_INCLUDED -#define _HAL_I2C_M_SYNC_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_i2c_master_sync - * - * @{ - */ - -#define I2C_M_MAX_RETRY 1 - -/** - * \brief I2C descriptor structure, embed i2c_device & i2c_interface - */ -struct i2c_m_sync_desc { - struct _i2c_m_sync_device device; - struct io_descriptor io; - uint16_t slave_addr; -}; - -/** - * \brief Initialize synchronous I2C interface - * - * This function initializes the given I/O descriptor to be used as a - * synchronous I2C interface descriptor. - * It checks if the given hardware is not initialized and if the given hardware - * is permitted to be initialized. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - * \retval -1 The passed parameters were invalid or the interface is already initialized - * \retval 0 The initialization is completed successfully - */ -int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw); - -/** - * \brief Deinitialize I2C interface - * - * This function deinitializes the given I/O descriptor. - * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Uninitialization status. - * \retval -1 The passed parameters were invalid or the interface is already deinitialized - * \retval 0 The de-initialization is completed successfully - */ -int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c); - -/** - * \brief Set the slave device address - * - * This function sets the next transfer target slave I2C device address. - * It takes no effect to any already started access. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] addr The slave address to access - * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN - * - * \return Masked slave address. The mask is a maximum 10-bit address, and 10th - * bit is set if a 10-bit address is used - */ -int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len); - -/** - * \brief Set baudrate - * - * This function sets the I2C device to the specified baudrate. - * It only takes effect when the hardware is disabled. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] clkrate Unused parameter. Should always be 0 - * \param[in] baudrate The baudrate value set to master - * - * \return Whether successfully set the baudrate - * \retval -1 The passed parameters were invalid or the device is already enabled - * \retval 0 The baudrate set is completed successfully - */ -int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Sync version of enable hardware - * - * This function enables the I2C device, and then waits for this enabling operation to be done - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Whether successfully enable the device - * \retval -1 The passed parameters were invalid or the device enable failed - * \retval 0 The hardware enabling is completed successfully - */ -int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c); - -/** - * \brief Sync version of disable hardware - * - * This function disables the I2C device and then waits for this disabling operation to be done - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Whether successfully disable the device - * \retval -1 The passed parameters were invalid or the device disable failed - * \retval 0 The hardware disabling is completed successfully - */ -int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c); - -/** - * \brief Sync version of write command to I2C slave - * - * This function will write the value to a specified register in the I2C slave device and - * then wait for this operation to be done. - * - * The sequence of this routine is - * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] reg The internal address/register of the I2C slave device - * \param[in] buffer The buffer holding data to write to the I2C slave device - * \param[in] length The length (in bytes) to write to the I2C slave device - * - * \return Whether successfully write to the device - * \retval <0 The passed parameters were invalid or write fail - * \retval 0 Writing to register is completed successfully - */ -int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); - -/** - * \brief Sync version of read register value from I2C slave - * - * This function will read a byte value from a specified register in the I2C slave device and - * then wait for this operation to be done. - * - * The sequence of this routine is - * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] reg The internal address/register of the I2C slave device - * \param[in] buffer The buffer to hold the read data from the I2C slave device - * \param[in] length The length (in bytes) to read from the I2C slave device - * - * \return Whether successfully read from the device - * \retval <0 The passed parameters were invalid or read fail - * \retval 0 Reading from register is completed successfully - */ -int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); - -/** - * \brief Sync version of transfer message to/from the I2C slave - * - * This function will transfer a message between the I2C slave and the master. This function will wait for the operation - * to be done. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] msg An i2c_m_msg struct - * - * \return The status of the operation - * \retval 0 Operation completed successfully - * \retval <0 Operation failed - */ -int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg); - -/** - * \brief Sync version of send stop condition on the i2c bus - * - * This function will create a stop condition on the i2c bus to release the bus - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return The status of the operation - * \retval 0 Operation completed successfully - * \retval <0 Operation failed - */ -int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c); - -/** - * \brief Return I/O descriptor for this I2C instance - * - * This function will return a I/O instance for this I2C driver instance - * - * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C - * \param[in] io_descriptor A pointer to an I/O descriptor pointer type - * - * \return Error code - * \retval 0 No error detected - * \retval <0 Error code - */ -int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t i2c_m_sync_get_version(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/atmel-samd/asf4/samd21/hal/include/hal_init.h b/atmel-samd/asf4/samd21/hal/include/hal_init.h deleted file mode 100644 index a970943eb..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_init.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * \file - * - * \brief HAL initialization related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_INIT_H_INCLUDED -#define _HAL_INIT_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_init Init Driver - * - *@{ - */ - -/** - * \brief Initialize the hardware abstraction layer - * - * This function calls the various initialization functions. - * Currently the following initialization functions are supported: - * - System clock initialization - */ -static inline void init_mcu(void) -{ - _init_chip(); -} - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t init_get_version(void); - -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_io.h b/atmel-samd/asf4/samd21/hal/include/hal_io.h deleted file mode 100644 index e8005e3db..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_io.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * \file - * - * \brief I/O related functionality declaration. - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_IO_INCLUDED -#define _HAL_IO_INCLUDED - -/** - * \addtogroup doc_driver_hal_helper_io I/O Driver - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief I/O descriptor - * - * The I/O descriptor forward declaration. - */ -struct io_descriptor; - -/** - * \brief I/O write function pointer type - */ -typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O read function pointer type - */ -typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O descriptor - */ -struct io_descriptor { - io_write_t write; /*! The write function pointer. */ - io_read_t read; /*! The read function pointer. */ -}; - -/** - * \brief I/O write interface - * - * This function writes up to \p length of bytes to a given I/O descriptor. - * It returns the number of bytes actually write. - * - * \param[in] descr An I/O descriptor to write - * \param[in] buf The buffer pointer to story the write data - * \param[in] length The number of bytes to write - * - * \return The number of bytes written - */ -int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O read interface - * - * This function reads up to \p length bytes from a given I/O descriptor, and - * stores it in the buffer pointed to by \p buf. It returns the number of bytes - * actually read. - * - * \param[in] descr An I/O descriptor to read - * \param[in] buf The buffer pointer to story the read data - * \param[in] length The number of bytes to read - * - * \return The number of bytes actually read. This number can be less than the - * requested length. E.g., in a driver that uses ring buffer for - * reception, it may depend on the availability of data in the - * ring buffer. - */ -int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HAL_IO_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_pwm.h b/atmel-samd/asf4/samd21/hal/include/hal_pwm.h deleted file mode 100644 index 29efc4bc4..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -/** - * \file - * - * \brief PWM functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef HAL_PWM_H_INCLUDED -#define HAL_PWM_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_pwm_async - * - *@{ - */ - -/** - * \brief PWM descriptor - * - * The PWM descriptor forward declaration. - */ -struct pwm_descriptor; - -/** - * \brief PWM callback type - */ -typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr); - -/** - * \brief PWM callback types - */ -enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB }; - -/** - * \brief PWM callbacks - */ -struct pwm_callbacks { - pwm_cb_t period; - pwm_cb_t error; -}; - -/** \brief PWM descriptor - */ -struct pwm_descriptor { - /** PWM device */ - struct _pwm_device device; - /** PWM callback structure */ - struct pwm_callbacks pwm_cb; -}; - -/** \brief Initialize the PWM HAL instance and hardware - * - * \param[in] descr Pointer to the HAL PWM descriptor - * \param[in] hw The pointer to hardware instance - * \param[in] func The pointer to a set of functions pointers - * - * \return Operation status. - */ -int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func); - -/** \brief Deinitialize the PWM HAL instance and hardware - * - * \param[in] descr Pointer to the HAL PWM descriptor - * - * \return Operation status. - */ -int32_t pwm_deinit(struct pwm_descriptor *const descr); - -/** \brief PWM output start - * - * \param[in] descr Pointer to the HAL PWM descriptor - * - * \return Operation status. - */ -int32_t pwm_enable(struct pwm_descriptor *const descr); - -/** \brief PWM output stop - * - * \param[in] descr Pointer to the HAL PWM descriptor - * - * \return Operation status. - */ -int32_t pwm_disable(struct pwm_descriptor *const descr); - -/** \brief Register PWM callback - * - * \param[in] descr Pointer to the HAL PWM descriptor - * \param[in] type Callback type - * \param[in] cb A callback function, passing NULL de-registers callback - * - * \return Operation status. - * \retval 0 Success - * \retval -1 Error - */ -int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb); - -/** \brief Change PWM parameter - * - * \param[in] descr Pointer to the HAL PWM descriptor - * \param[in] period Total period of one PWM cycle - * \param[in] duty_cycle Period of PWM first half during one cycle - * - * \return Operation status. - */ -int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, - const pwm_period_t duty_cycle); - -/** \brief Get PWM driver version - * - * \return Current driver version. - */ -uint32_t pwm_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_PWM;_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_sleep.h b/atmel-samd/asf4/samd21/hal/include/hal_sleep.h deleted file mode 100644 index 0a11856b1..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_sleep.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SLEEP_H_INCLUDED -#define _HAL_SLEEP_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_sleep - * - *@{ - */ - -/** - * \brief Set the sleep mode of the device and put the MCU to sleep - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see the data sheet. - * - * \param[in] mode Sleep mode to use - * - * \return The status of a sleep request - * \retval -1 The requested sleep mode was invalid or not available - * \retval 0 The operation completed successfully, returned after leaving the - * sleep - */ -int sleep(const uint8_t mode); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t sleep_get_version(void); -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_spi_m_sync.h b/atmel-samd/asf4/samd21/hal/include/hal_spi_m_sync.h deleted file mode 100644 index 2c630ff09..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_spi_m_sync.h +++ /dev/null @@ -1,220 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SPI_M_SYNC_H_INCLUDED -#define _HAL_SPI_M_SYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup doc_driver_hal_spi_master_sync - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** \brief SPI HAL driver struct for polling mode - * - */ -struct spi_m_sync_descriptor { - /** SPI device instance */ - struct _spi_sync_dev dev; - /** I/O read/write */ - struct io_descriptor io; - /** Flags for HAL driver */ - uint16_t flags; -}; - -/** \brief Initialize SPI HAL instance and hardware for polling mode - * - * Initialize SPI HAL with polling mode. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] hw Pointer to the hardware base. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_INVALID_DATA Error, initialized. - */ -int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw); - -/** \brief Deinitialize the SPI HAL instance and hardware - * - * Abort transfer, disable and reset SPI, deinit software. - * - * \param[in] spi Pointer to the HAL SPI instance. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval <0 Error code. - */ -void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi); - -/** \brief Enable SPI - * - * \param[in] spi Pointer to the HAL SPI instance. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval <0 Error code. - */ -void spi_m_sync_enable(struct spi_m_sync_descriptor *spi); - -/** \brief Disable SPI - * - * \param[in] spi Pointer to the HAL SPI instance. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval <0 Error code. - */ -void spi_m_sync_disable(struct spi_m_sync_descriptor *spi); - -/** \brief Set SPI baudrate - * - * Works if SPI is initialized as master, it sets the baudrate. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] baud_val The target baudrate value - * (see "baudrate calculation" for calculating the value). - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The baudrate is not supported. - */ -int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val); - -/** \brief Set SPI mode - * - * Set the SPI transfer mode (\ref spi_transfer_mode), - * which controls the clock polarity and clock phase: - * - Mode 0: leading edge is rising edge, data sample on leading edge. - * - Mode 1: leading edge is rising edge, data sample on trailing edge. - * - Mode 2: leading edge is falling edge, data sample on leading edge. - * - Mode 3: leading edge is falling edge, data sample on trailing edge. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] mode The mode (0~3). - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The mode is not supported. - */ -int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode); - -/** \brief Set SPI transfer character size in number of bits - * - * The character size (\ref spi_char_size) influence the way the data is - * sent/received. - * For char size <= 8-bit, data is stored byte by byte. - * For char size between 9-bit ~ 16-bit, data is stored in 2-byte length. - * Note that the default and recommended char size is 8-bit since it's - * supported by all system. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] char_size The char size (~16, recommended 8). - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The char size is not supported. - */ -int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size); - -/** \brief Set SPI transfer data order - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] dord The data order: send LSB/MSB first. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The data order is not supported. - */ -int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord); - -/** \brief Perform the SPI data transfer (TX and RX) in polling way - * - * Activate CS, do TX and RX and deactivate CS. It blocks. - * - * \param[in, out] spi Pointer to the HAL SPI instance. - * \param[in] xfer Pointer to the transfer information (\ref spi_xfer). - * - * \retval size Success. - * \retval >=0 Timeout, with number of characters transferred. - * \retval ERR_BUSY SPI is busy - */ -int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer); - -/** - * \brief Return the I/O descriptor for this SPI instance - * - * This function will return an I/O instance for this SPI driver instance. - * - * \param[in] spi An SPI master descriptor, which is used to communicate through - * SPI - * \param[in, out] io A pointer to an I/O descriptor pointer type - * - * \retval ERR_NONE - */ -int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io); - -/** \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t spi_m_sync_get_version(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_timer.h b/atmel-samd/asf4/samd21/hal/include/hal_timer.h deleted file mode 100644 index b5c8f6082..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_timer.h +++ /dev/null @@ -1,216 +0,0 @@ -/** - * \file - * - * \brief Timer task functionality declaration. - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_TIMER_H_INCLUDED -#define _HAL_TIMER_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_timer - * - * @{ - */ - -/** - * \brief Timer mode type - */ -enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT }; - -/** - * \brief Timer task descriptor - * - * The timer task descriptor forward declaration. - */ -struct timer_task; - -/** - * \brief Timer task callback function type - */ -typedef void (*timer_cb_t)(const struct timer_task *const timer_task); - -/** - * \brief Timer task structure - */ -struct timer_task { - struct list_element elem; /*! List element. */ - uint32_t time_label; /*! Absolute timer start time. */ - - uint32_t interval; /*! Number of timer ticks before calling the task. */ - timer_cb_t cb; /*! Function pointer to the task. */ - enum timer_task_mode mode; /*! Task mode: one shot or repeat. */ -}; - -/** - * \brief Timer structure - */ -struct timer_descriptor { - struct _timer_device device; - uint32_t time; - struct list_descriptor tasks; /*! Timer tasks list. */ - volatile uint8_t flags; -}; - -/** - * \brief Initialize timer - * - * This function initializes the given timer. - * It checks if the given hardware is not initialized and if the given hardware - * is permitted to be initialized. - * - * \param[out] descr A timer descriptor to initialize - * \param[in] hw The pointer to the hardware instance - * \param[in] func The pointer to a set of function pointers - * - * \return Initialization status. - */ -int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func); - -/** - * \brief Deinitialize timer - * - * This function deinitializes the given timer. - * It checks if the given hardware is initialized and if the given hardware is - * permitted to be deinitialized. - * - * \param[in] descr A timer descriptor to deinitialize - * - * \return De-initialization status. - */ -int32_t timer_deinit(struct timer_descriptor *const descr); - -/** - * \brief Start timer - * - * This function starts the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to start - * - * \return Timer starting status. - */ -int32_t timer_start(struct timer_descriptor *const descr); - -/** - * \brief Stop timer - * - * This function stops the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to stop - * - * \return Timer stopping status. - */ -int32_t timer_stop(struct timer_descriptor *const descr); - -/** - * \brief Set amount of clock cycles per timer tick - * - * This function sets the amount of clock cycles per timer tick for the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to stop - * \param[in] clock_cycles The amount of clock cycles per tick to set - * - * \return Setting clock cycles amount status. - */ -int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles); - -/** - * \brief Retrieve the amount of clock cycles in a tick - * - * This function retrieves how many clock cycles there are in a single timer tick. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to convert ticks to - * clock cycles - * \param[out] cycles The amount of clock cycles - * - * \return The status of clock cycles retrieving. - */ -int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles); - -/** - * \brief Add timer task - * - * This function adds the given timer task to the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to add task to - * \param[in] task A task to add - * - * \return Timer's task adding status. - */ -int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task); - -/** - * \brief Remove timer task - * - * This function removes the given timer task from the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to remove task from - * \param[in] task A task to remove - * - * \return Timer's task removing status. - */ -int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t timer_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_TIMER_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_usart_sync.h b/atmel-samd/asf4/samd21/hal/include/hal_usart_sync.h deleted file mode 100644 index e2aef748d..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_usart_sync.h +++ /dev/null @@ -1,257 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SYNC_USART_H_INCLUDED -#define _HAL_SYNC_USART_H_INCLUDED - -#include "hal_io.h" -#include - -/** - * \addtogroup doc_driver_hal_usart_sync - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Synchronous USART descriptor - */ -struct usart_sync_descriptor { - struct io_descriptor io; - struct _usart_sync_device device; -}; - -/** - * \brief Initialize USART interface - * - * This function initializes the given I/O descriptor to be used - * as USART interface descriptor. - * It checks if the given hardware is not initialized and - * if the given hardware is permitted to be initialized. - * - * \param[out] descr A USART descriptor which is used to communicate via USART - * \param[in] hw The pointer to hardware instance - * \param[in] func The pointer to as set of functions pointers - * - * \return Initialization status. - */ -int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); - -/** - * \brief Deinitialize USART interface - * - * This function deinitializes the given I/O descriptor. - * It checks if the given hardware is initialized and - * if the given hardware is permitted to be deinitialized. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return De-initialization status. - */ -int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); - -/** - * \brief Enable USART interface - * - * Enables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Enabling status. - */ -int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); - -/** - * \brief Disable USART interface - * - * Disables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Disabling status. - */ -int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); - -/** - * \brief Retrieve I/O descriptor - * - * This function retrieves the I/O descriptor of the given USART descriptor. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] io An I/O descriptor to retrieve - * - * \return The status of the I/O descriptor retrieving. - */ -int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); - -/** - * \brief Specify action for flow control pins - * - * This function sets the action (or state) for the flow control pins - * if the flow control is enabled. - * It sets the state of flow control pins only if the automatic support of - * the flow control is not supported by the hardware. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] state A state to set the flow control pins - * - * \return The status of flow control action setup. - */ -int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, - const union usart_flow_control_state state); - -/** - * \brief Set USART baud rate - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] baud_rate A baud rate to set - * - * \return The status of baud rate setting. - */ -int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); - -/** - * \brief Set USART data order - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] data_order A data order to set - * - * \return The status of data order setting. - */ -int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); - -/** - * \brief Set USART mode - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] mode A mode to set - * - * \return The status of mode setting. - */ -int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); - -/** - * \brief Set USART parity - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] parity A parity to set - * - * \return The status of parity setting. - */ -int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); - -/** - * \brief Set USART stop bits - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] stop_bits Stop bits to set - * - * \return The status of stop bits setting. - */ -int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); - -/** - * \brief Set USART character size - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] size A character size to set - * - * \return The status of character size setting. - */ -int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins - * if the flow control is enabled. - * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case - * if the flow control is done by the hardware - * and the pins state cannot be read out. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] state The state of flow control pins - * - * \return The status of flow control state reading. - */ -int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, - union usart_flow_control_state *const state); - -/** - * \brief Check if the USART transmitter is empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of USART TX empty checking. - * \retval 0 The USART transmitter is not empty - * \retval 1 The USART transmitter is empty - */ -int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); - -/** - * \brief Check if the USART receiver is not empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of USART RX empty checking. - * \retval 1 The USART receiver is not empty - * \retval 0 The USART receiver is empty - */ -int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t usart_sync_get_version(void); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hal_usb_device.h b/atmel-samd/asf4/samd21/hal/include/hal_usb_device.h deleted file mode 100644 index 8b7bd5ec7..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hal_usb_device.h +++ /dev/null @@ -1,305 +0,0 @@ -/** - * \file - * - * \brief SAM USB device HAL - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_USB_DEVICE_H_INCLUDED -#define _HAL_USB_DEVICE_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_usb_device - * - * @{ - */ - -/** USB device endpoint status structure. */ -struct usb_d_ep_status { - /** Endpoint address, including direction. */ - uint8_t ep; - /** Endpoint transfer status code that triggers the callback. - * \ref usb_xfer_code. */ - uint8_t code; - /** Endpoint error, if \c code is \ref USB_TRANS_ERROR. */ - uint8_t error; - /** Transfer state, \ref usb_ep_state. */ - uint8_t state; - /** Transfer count. */ - uint32_t count; - /** Transfer size. */ - uint32_t size; -}; - -/** Prototype function for callback that is invoked on USB device SOF. */ -typedef void (*usb_d_sof_cb_t)(void); - -/** Prototype function for callback that is invoked on USB device events. */ -typedef void (*usb_d_event_cb_t)(const enum usb_event event, const uint32_t param); - -/** USB device callbacks. */ -struct usb_d_callbacks { - /** Callback that is invoked on SOF. */ - usb_d_sof_cb_t sof; - /** Callback that is invoked on USB RESET/WAKEUP/RESUME/SUSPEND. */ - usb_d_event_cb_t event; -}; - -/** Callback that is invoked when setup packet is received. - * Return \c true if request has been handled, or control endpoint will - * stall IN/OUT transactions. - */ -typedef bool (*usb_d_ep_cb_setup_t)(const uint8_t ep, const uint8_t *req); - -/** Callback that is invoked when buffer is done without error, but last packet - * is full size packet without ZLP. - * Return \c true if more data has been requested. - */ -typedef bool (*usb_d_ep_cb_more_t)(const uint8_t ep, const uint32_t count); - -/** Callback that is invoked when all data is finished, including background - * transfer, or error happens. - * In control transfer data stage, return value is checked, - * return \c false if no error happens. - */ -typedef bool (*usb_d_ep_cb_xfer_t)(const uint8_t ep, const enum usb_xfer_code code, void *param); - -/** - * \brief Initialize the USB device driver - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_init(void); - -/** - * \brief Deinitialize the USB device driver - */ -void usb_d_deinit(void); - -/** - * \brief Register the USB device callback - * \param[in] type The callback type to register. - * \param[in] func The callback function, NULL to disable callback. - */ -void usb_d_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func); - -/** - * \brief Enable the USB device driver - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_enable(void); - -/** - * \brief Disable the USB device driver - */ -void usb_d_disable(void); - -/** - * \brief Attach the USB device - */ -void usb_d_attach(void); - -/** - * \brief Detach the USB device - */ -void usb_d_detach(void); - -/** - * \brief Retrieve current USB working speed. - * \return USB Speed. See \ref usb_speed. - */ -enum usb_speed usb_d_get_speed(void); - -/** - * \brief Retrieve current USB frame number. - * \return Frame number. - */ -uint16_t usb_d_get_frame_num(void); - -/** - * \brief Retrieve current USB micro frame number. - * \return Micro frame number inside a frame (0~7). - * 0 if not available (not HS). - */ -uint8_t usb_d_get_uframe_num(void); - -/** - * \brief Set the USB address that is used. - * \param[in] addr The address to set. - */ -void usb_d_set_address(const uint8_t addr); - -/** - * \brief Send remote wakeup to host - * \return Operation status. - */ -void usb_d_send_remotewakeup(void); - -/** - * \brief Initialize the endpoint 0. - * - * Note that endpoint 0 must be initialized as control endpoint. - * - * \param[in] max_pkt_size Max. packet size of EP0. - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_ep0_init(const uint8_t max_pkt_size); - -/** - * \brief Initialize the endpoint. - * - * \param[in] ep The endpoint address. - * \param[in] attr The endpoint attributes. - * \param[in] max_pkt_size Max. packet size of EP0. - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_size); - -/** - * \brief Disable and deinitialize the endpoint. - * \param[in] ep The endpoint address to deinitialize. - */ -void usb_d_ep_deinit(const uint8_t ep); - -/** - * \brief Register the USB device endpoint callback on initialized endpoint. - * - * \param[in] ep The endpoint address. - * \param[in] type The callback type to register. - * \param[in] func The callback function, NULL to disable callback. - */ -void usb_d_ep_register_callback(const uint8_t ep, const enum usb_d_ep_cb_type type, const FUNC_PTR func); - -/** - * \brief Enabled the initialized endpoint. - * - * Setup request will be monitored after enabling a control endpoint. - * - * \param[in] ep The endpoint address. - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_ep_enable(const uint8_t ep); - -/** - * \brief Disable the initialized endpoint. - * \param[in] ep The endpoint address. - */ -void usb_d_ep_disable(const uint8_t ep); - -/** - * \brief Get request data pointer to access received setup request packet - * \param[in] ep The endpoint address. - * \return Pointer to the request data. - * \retval NULL The endpoint is not a control endpoint. - */ -uint8_t *usb_d_ep_get_req(const uint8_t ep); - -/** - * \brief Endpoint transfer. - * - * For control endpoints, start the transfer according to the direction in the bmRequest - * type, and finish with STATUS stage. - * For non-control endpoints, the transfer will be unique direction. Defined by - * bit 8 of the endpoint address. - * - * \param[in] xfer Pointer to the transfer description. - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer); - -/** - * \brief Abort an on-going transfer on a specific endpoint. - * - * \param[in] ep The endpoint address. - */ -void usb_d_ep_abort(const uint8_t ep); - -/** - * \brief Retrieve the endpoint status. - * - * \param[in] ep The endpoint address. - * \param[out] stat Pointer to the buffer to fill the status description. - * - * \return Endpoint status. - * \retval 1 Busy. - * \retval 0 Idle. - * \retval <0 Error code. - */ -int32_t usb_d_ep_get_status(const uint8_t ep, struct usb_d_ep_status *stat); - -/** - * \brief Endpoint halt control. - * - * \param[in] ep The endpoint address. - * \param[in] ctrl Control code (SET/CLEAR/GET). - * - * \return Operation status or HALT state (if \c ctrl is \ref USB_EP_HALT_GET). - */ -int32_t usb_d_ep_halt(const uint8_t ep, const enum usb_ep_halt_ctrl ctrl); - -/** \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t usb_d_get_version(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_USB_DEVICE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_adc_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_adc_async.h deleted file mode 100644 index 31612be00..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_adc_async.h +++ /dev/null @@ -1,274 +0,0 @@ -/** - * \file - * - * \brief ADC related functionality declaration. - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_ADC_ASYNC_H_INCLUDED -#define _HPL_ADC_ASYNC_H_INCLUDED - -/** - * \addtogroup HPL ADC - * - * \section hpl_async_adc_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_adc_sync.h" -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief ADC device structure - * - * The ADC device structure forward declaration. - */ -struct _adc_async_device; - -/** - * \brief ADC callback types - */ -enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB }; - -/** - * \brief ADC interrupt callbacks - */ -struct _adc_async_callbacks { - void (*window_cb)(struct _adc_async_device *device, const uint8_t channel); - void (*error_cb)(struct _adc_async_device *device, const uint8_t channel); -}; - -/** - * \brief ADC channel interrupt callbacks - */ -struct _adc_async_ch_callbacks { - void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data); -}; - -/** - * \brief ADC descriptor device structure - */ -struct _adc_async_device { - struct _adc_async_callbacks adc_async_cb; - struct _adc_async_ch_callbacks adc_async_ch_cb; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize synchronous ADC - * - * This function does low level ADC configuration. - * - * param[in] device The pointer to ADC device instance - * param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw); - -/** - * \brief Deinitialize ADC - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_async_deinit(struct _adc_async_device *const device); - -/** - * \brief Enable ADC peripheral - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel); - -/** - * \brief Disable ADC peripheral - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel); - -/** - * \brief Retrieve ADC conversion data size - * - * \param[in] device The pointer to ADC device instance - * - * \return The data size in bytes - */ -uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device); - -/** - * \brief Check if conversion is done - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * - * \return The status of conversion - * \retval true The conversion is done - * \retval false The conversion is not done - */ -bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel); - -/** - * \brief Make conversion - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_async_convert(struct _adc_async_device *const device); - -/** - * \brief Retrieve the conversion result - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * - * The result value - */ -uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel); - -/** - * \brief Set reference source - * - * \param[in] device The pointer to ADC device instance - * \param[in] reference A reference source to set - */ -void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference); - -/** - * \brief Set resolution - * - * \param[in] device The pointer to ADC device instance - * \param[in] resolution A resolution to set - */ -void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution); - -/** - * \brief Set ADC input source of a channel - * - * \param[in] device The pointer to ADC device instance - * \param[in] pos_input A positive input source to set - * \param[in] neg_input A negative input source to set - * \param[in] channel Channel number - */ -void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel); - -/** - * \brief Set conversion mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A conversion mode to set - */ -void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode); - -/** - * \brief Set differential mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] mode A differential mode to set - */ -void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel, - const enum adc_differential_mode mode); - -/** - * \brief Set gain - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] gain A gain to set - */ -void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain); - -/** - * \brief Set window mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A mode to set - */ -void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode); - -/** - * \brief Set lower threshold - * - * \param[in] device The pointer to ADC device instance - * \param[in] low_threshold A lower threshold to set - * \param[in] up_threshold An upper thresholds to set - */ -void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold); - -/** - * \brief Retrieve threshold state - * - * \param[in] device The pointer to ADC device instance - * \param[out] state The threshold state - */ -void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state); - -/** - * \brief Enable/disable ADC channel interrupt - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] type The type of interrupt to disable/enable if applicable - * \param[in] state Enable or disable - */ -void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel, - const enum _adc_async_callback_type type, const bool state); - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_ADC_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_adc_dma.h b/atmel-samd/asf4/samd21/hal/include/hpl_adc_dma.h deleted file mode 100644 index 40ff158d2..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_adc_dma.h +++ /dev/null @@ -1,253 +0,0 @@ -/** - * \file - * - * \brief ADC related functionality declaration. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_ADC_DMA_H_INCLUDED -#define _HPL_ADC_DMA_H_INCLUDED - -/** - * \addtogroup HPL ADC - * - * \section hpl_dma_adc_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief ADC device structure - * - * The ADC device structure forward declaration. - */ -struct _adc_dma_device; - -/** - * \brief ADC callback types - */ -enum _adc_dma_callback_type { ADC_DMA_DEVICE_COMPLETE_CB, ADC_DMA_DEVICE_ERROR_CB }; - -/** - * \brief ADC interrupt callbacks - */ -struct _adc_dma_callbacks { - void (*complete)(struct _adc_dma_device *device, const uint16_t data); - void (*error)(struct _adc_dma_device *device); -}; - -/** - * \brief ADC descriptor device structure - */ -struct _adc_dma_device { - struct _adc_dma_callbacks adc_dma_cb; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize synchronous ADC - * - * This function does low level ADC configuration. - * - * param[in] device The pointer to ADC device instance - * param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw); - -/** - * \brief Deinitialize ADC - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_dma_deinit(struct _adc_dma_device *const device); - -/** - * \brief Enable ADC peripheral - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel); - -/** - * \brief Disable ADC peripheral - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel); - -/** - * \brief Return address of ADC DMA source - * - * \param[in] device The pointer to ADC device instance - * - * \return ADC DMA source address - */ -uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device); - -/** - * \brief Retrieve ADC conversion data size - * - * \param[in] device The pointer to ADC device instance - * - * \return The data size in bytes - */ -uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device); - -/** - * \brief Check if conversion is done - * - * \param[in] device The pointer to ADC device instance - * - * \return The status of conversion - * \retval true The conversion is done - * \retval false The conversion is not done - */ -bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device); - -/** - * \brief Make conversion - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_dma_convert(struct _adc_dma_device *const device); - -/** - * \brief Set reference source - * - * \param[in] device The pointer to ADC device instance - * \param[in] reference A reference source to set - */ -void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference); - -/** - * \brief Set resolution - * - * \param[in] device The pointer to ADC device instance - * \param[in] resolution A resolution to set - */ -void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution); - -/** - * \brief Set ADC input source of a channel - * - * \param[in] device The pointer to ADC device instance - * \param[in] pos_input A positive input source to set - * \param[in] neg_input A negative input source to set - * \param[in] channel Channel number - */ -void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel); - -/** - * \brief Set conversion mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A conversion mode to set - */ -void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode); - -/** - * \brief Set differential mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] mode A differential mode to set - */ -void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel, - const enum adc_differential_mode mode); - -/** - * \brief Set gain - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] gain A gain to set - */ -void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain); - -/** - * \brief Set window mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A mode to set - */ -void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode); - -/** - * \brief Set thresholds - * - * \param[in] device The pointer to ADC device instance - * \param[in] low_threshold A lower thresholds to set - * \param[in] up_threshold An upper thresholds to set - */ -void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold); - -/** - * \brief Retrieve threshold state - * - * \param[in] device The pointer to ADC device instance - * \param[out] state The threshold state - */ -void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state); - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_ADC_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_adc_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_adc_sync.h deleted file mode 100644 index 84ab01ab3..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_adc_sync.h +++ /dev/null @@ -1,281 +0,0 @@ -/** - * \file - * - * \brief ADC related functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_ADC_SYNC_H_INCLUDED -#define _HPL_ADC_SYNC_H_INCLUDED - -/** - * \addtogroup HPL ADC - * - * \section hpl_adc_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "compiler.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief ADC reference source - */ -typedef uint8_t adc_reference_t; - -/** - * \brief ADC resolution - */ -typedef uint8_t adc_resolution_t; - -/** - * \brief ADC positive input for channel - */ -typedef uint8_t adc_pos_input_t; - -/** - * \brief ADC negative input for channel - */ -typedef uint8_t adc_neg_input_t; - -/** - * \brief ADC threshold - */ -typedef uint16_t adc_threshold_t; - -/** - * \brief ADC gain - */ -typedef uint8_t adc_gain_t; - -/** - * \brief ADC conversion mode - */ -enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN }; - -/** - * \brief ADC differential mode - */ -enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL }; - -/** - * \brief ADC window mode - */ -typedef uint8_t adc_window_mode_t; - -/** - * \brief ADC threshold status - */ -typedef bool adc_threshold_status_t; - -/** - * \brief ADC sync descriptor device structure - */ -struct _adc_sync_device { - void *hw; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize synchronous ADC - * - * This function does low level ADC configuration. - * - * param[in] device The pointer to ADC device instance - * param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize ADC - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_sync_deinit(struct _adc_sync_device *const device); - -/** - * \brief Enable ADC - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel); - -/** - * \brief Disable ADC - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel); - -/** - * \brief Retrieve ADC conversion data size - * - * \param[in] device The pointer to ADC device instance - * - * \return The data size in bytes - */ -uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device); - -/** - * \brief Check if conversion is done - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * - * \return The status of conversion - * \retval true The conversion is done - * \retval false The conversion is not done - */ -bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel); - -/** - * \brief Make conversion - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_sync_convert(struct _adc_sync_device *const device); - -/** - * \brief Retrieve the conversion result - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * - * \return The result value of channel - */ -uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel); - -/** - * \brief Set reference source - * - * \param[in] device The pointer to ADC device instance - * \param[in] reference A reference source to set - */ -void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference); - -/** - * \brief Set resolution - * - * \param[in] device The pointer to ADC device instance - * \param[in] resolution A resolution to set - */ -void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution); - -/** - * \brief Set ADC input source of a channel - * - * \param[in] device The pointer to ADC device instance - * \param[in] pos_input A positive input source to set - * \param[in] neg_input A negative input source to set - * \param[in] channel Channel number - */ -void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel); - -/** - * \brief Set conversion mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A conversion mode to set - */ -void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode); - -/** - * \brief Set differential mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] mode A differential mode to set - */ -void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel, - const enum adc_differential_mode mode); - -/** - * \brief Set gain - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] gain A gain to set - */ -void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain); - -/** - * \brief Set window mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A mode to set - */ -void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode); - -/** - * \brief Set threshold - * - * \param[in] device The pointer to ADC device instance - * \param[in] low_threshold A lower threshold to set - * \param[in] up_threshold An upper thresholds to set - */ -void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold); - -/** - * \brief Retrieve threshold state - * - * \param[in] device The pointer to ADC device instance - * \param[out] state The threshold state - */ -void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_ADC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_calendar.h b/atmel-samd/asf4/samd21/hal/include/hpl_calendar.h deleted file mode 100644 index 9b9002c25..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_calendar.h +++ /dev/null @@ -1,252 +0,0 @@ -/** - * \file - * - * \brief Generic CALENDAR functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_CALENDER_H_INCLUDED -#define _HPL_CALENDER_H_INCLUDED - -#include -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Calendar structure - * - * The Calendar structure forward declaration. - */ -struct calendar_dev; - -/** - * \brief Available mask options for alarms. - * - * Available mask options for alarms. - */ -enum calendar_alarm_option { - /** Alarm disabled. */ - CALENDAR_ALARM_MATCH_DISABLED = 0, - /** Alarm match on second. */ - CALENDAR_ALARM_MATCH_SEC, - /** Alarm match on second and minute. */ - CALENDAR_ALARM_MATCH_MIN, - /** Alarm match on second, minute, and hour. */ - CALENDAR_ALARM_MATCH_HOUR, - /** Alarm match on second, minute, hour, and day. */ - CALENDAR_ALARM_MATCH_DAY, - /** Alarm match on second, minute, hour, day, and month. */ - CALENDAR_ALARM_MATCH_MONTH, - /** Alarm match on second, minute, hour, day, month and year. */ - CALENDAR_ALARM_MATCH_YEAR -}; - -/** - * \brief Available mode for alarms. - */ -enum calendar_alarm_mode { ONESHOT = 1, REPEAT }; -/** - * \brief Prototype of callback on alarm match - */ -typedef void (*calendar_drv_cb_alarm_t)(struct calendar_dev *const dev); - -/** - * \brief Structure of Calendar instance - */ -struct calendar_dev { - /** Pointer to the hardware base */ - void *hw; - /** Alarm match callback */ - calendar_drv_cb_alarm_t callback; - /** IRQ struct */ - struct _irq_descriptor irq; -}; - -/** - * \brief Time struct for calendar - */ -struct calendar_time { - /*range from 0 to 59*/ - uint8_t sec; - /*range from 0 to 59*/ - uint8_t min; - /*range from 0 to 23*/ - uint8_t hour; -}; - -/** - * \brief Time struct for calendar - */ -struct calendar_date { - /*range from 1 to 28/29/30/31*/ - uint8_t day; - /*range from 1 to 12*/ - uint8_t month; - /*absolute year>= 1970(such as 2000)*/ - uint16_t year; -}; - -/** \brief Calendar driver struct - * - */ -struct calendar_descriptor { - struct calendar_dev device; - struct list_descriptor alarms; - /*base date/time = base_year/1/1/0/0/0(year/month/day/hour/min/sec)*/ - uint32_t base_year; - uint8_t flags; -}; - -/** \brief Date&Time struct for calendar - */ -struct calendar_date_time { - struct calendar_time time; - struct calendar_date date; -}; - -/** \brief struct for alarm time - */ -struct _calendar_alarm { - struct calendar_date_time datetime; - uint32_t timestamp; - enum calendar_alarm_option option; - enum calendar_alarm_mode mode; -}; - -/** - * \brief Initialize Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_init(struct calendar_dev *const dev); - -/** - * \brief Deinitialize Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_deinit(struct calendar_dev *const dev); - -/** - * \brief Enable Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_enable(struct calendar_dev *const dev); - -/** - * \brief Disable Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_disable(struct calendar_dev *const dev); -/** - * \brief Set time for calendar - * - * \param[in] dev The pointer to calendar device struct - * \param[in] p_calendar_time Pointer to the time configuration - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_set_time(struct calendar_dev *const dev, struct calendar_time *const p_calendar_time); - -/** - * \brief Set date for calendar - * - * \param[in] dev The pointer to calendar device struct - * \param[in] p_calendar_date Pointer to the date configuration - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_set_date(struct calendar_dev *const dev, struct calendar_date *const p_calendar_date); - -/** - * \brief Get the time for calendar HAL instance and hardware - * Retrieve the time from calendar instance. - * - * \param[in] dev The pointer to calendar device struct - * \param[in] date_time Pointer to value that will be filled with current time - * - * \return Return current counter value - */ -uint32_t _calendar_get_date_time(struct calendar_dev *const dev, struct calendar_date_time *const date_time); - -/** - * \brief Set compare value for calendar - * - * \param[in] dev The pointer to calendar device struct - * \param[in] alarm Pointer to the configuration - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_set_alarm(struct calendar_dev *const dev, struct _calendar_alarm *const alarm); - -/** - * \brief Register callback for calendar alarm - * - * \param[in] dev The pointer to calendar device struct - * \param[in] callback The pointer to callback function - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback); - -/** - * \brief Set calendar IRQ - * - * \param[in] dev The pointer to calendar device struct - */ -void _calendar_set_irq(struct calendar_dev *const dev); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_RTC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_core.h b/atmel-samd/asf4/samd21/hal/include/hpl_core.h deleted file mode 100644 index db448a16a..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_core.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * \file - * - * \brief CPU core related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_CORE_H_INCLUDED -#define _HPL_CORE_H_INCLUDED - -/** - * \addtogroup HPL Core - * - * \section hpl_core_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_core_port.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h deleted file mode 100644 index dc40a47f8..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_dac_async.h +++ /dev/null @@ -1,182 +0,0 @@ -/** - * \file - * - * \brief DAC related functionality declaration. - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_DAC_H_INCLUDED -#define _HPL_DAC_H_INCLUDED - -/** - * \addtogroup hpl__dac__group DAC HPL APIs - * See interface description here: \ref hpl__dac__doc - * - */ - -/**@{*/ - -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DAC hardware Channel Number - */ - -#ifndef CHANNEL_NUM -#define CHANNEL_NUM 1 -#endif - -/** - * \brief DAC callback types - */ -enum _dac_callback_type { DAC_DEVICE_CONVERSION_DONE_CB, DAC_DEVICE_ERROR_CB }; - -/** - * \brief DAC device structure - * - * The DAC device structure forward declaration. - */ -struct _dac_async_device; - -/** - * \brief DAC interrupt handlers structure - */ -struct _dac_callback { - /** Transmit ready(Data Buffer empty) handler */ - void (*tx_ready_cb)(struct _dac_async_device *device, const uint8_t ch); - /** Error handler */ - void (*tx_error_cb)(struct _dac_async_device *device, const uint8_t ch); -}; - -/** - * \brief DAC descriptor device structure. - */ -struct _dac_async_device { - struct _dac_callback dac_cb; /*!< Interrupt handers */ - struct _irq_descriptor irq; /*!< Interrupt descriptor */ - void * hw; /*!< Hardware module instance handler */ -}; - -/** - * \brief Initialize asynchronous DAC. - * - * This function does low level DAC configuration. - * - * \param[in] device The pointer to DAC device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _dac_async_init(struct _dac_async_device *const device, void *const hw); - -/** - * \brief Deinitialize DAC. - * - * \param[in] device The pointer to DAC device instance - */ -void _dac_async_deinit(struct _dac_async_device *const device); - -/** - * \brief Enable DAC Channel. - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - */ -void _dac_async_enable_channel(struct _dac_async_device *const device, const uint8_t ch); - -/** - * \brief Disable DAC Channel. - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - */ -void _dac_async_disable_channel(struct _dac_async_device *const device, const uint8_t ch); - -/** - * \brief Checks if DAC channel is enabled - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - * - * \return true channel is enabled, false otherwise - */ -bool _dac_async_is_channel_enable(struct _dac_async_device *const device, const uint8_t ch); - -/** - * \brief Write DAC data for output. - * - * \param[in] device The pointer to DAC device instance - * \param[in] data Digital data which to be converted - * \param[in] ch The channel selected to output - */ -void _dac_async_write_data(struct _dac_async_device *const device, const uint16_t data, const uint8_t ch); - -/** - * \brief Enable/disable DAC interrupt - * - * param[in] device The pointer to DAC device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _dac_async_set_irq_state(struct _dac_async_device *const device, const enum _dac_callback_type type, - const bool state); - -#ifdef __cplusplus -} -#endif - -/**@}*/ - -/** - * \page hpl__dac__doc DAC HPL Interface Driver - * - * \section hpl__dac__desc DAC HPL Description - * - * The following device can use this HPL driver - * - Atmel | SMART SAM D21 - * - * \section hpl__dac__imple DAC HPL Implements - * - \subpage hpl__dac__hw_module1__doc - */ - -#endif /* _HPL_DAC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h deleted file mode 100644 index a70b3ba64..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_dac_sync.h +++ /dev/null @@ -1,148 +0,0 @@ -/** - * \file - * - * \brief DAC related functionality declaration. - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_DAC_SYNC_H_INCLUDED -#define _HPL_DAC_SYNC_H_INCLUDED - -/** - * \addtogroup hpl__dac__group DAC HPL APIs - * See interface description here: \ref hpl__dac__doc - * - */ - -/**@{*/ - -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DAC hardware Channel Number - */ - -#ifndef CHANNEL_NUM -#define CHANNEL_NUM 1 -#endif - -/** - * \brief DAC sync descriptor device structure. - */ -struct _dac_sync_device { - void *hw; /*!< Hardware module instance handler */ -}; - -/** - * \brief Initialize synchronous DAC. - * - * This function does low level DAC configuration. - * - * \param[in] device The pointer to DAC device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _dac_sync_init(struct _dac_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize DAC. - * - * \param[in] device The pointer to DAC device instance - */ -void _dac_sync_deinit(struct _dac_sync_device *const device); - -/** - * \brief Enable DAC Channel. - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - */ -void _dac_sync_enable_channel(struct _dac_sync_device *const device, const uint8_t ch); - -/** - * \brief Disable DAC Channel. - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - */ -void _dac_sync_disable_channel(struct _dac_sync_device *const device, const uint8_t ch); - -/** - * \brief Checks if DAC channel is enabled - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - * - * \return true channel is enabled, false otherwise - */ -bool _dac_sync_is_channel_enable(struct _dac_sync_device *const device, const uint8_t ch); - -/** - * \brief Write synchronous DAC data for output. - * - * \param[in] device The pointer to DAC device instance - * \param[in] data Digital data which to be converted - * \param[in] ch The channel selected to output - */ -void _dac_sync_write_data(struct _dac_sync_device *const device, const uint16_t data, const uint8_t ch); - -#ifdef __cplusplus -} -#endif - -/**@}*/ - -/** - * \page hpl__dac__doc DAC HPL Interface Driver - * - * \section hpl__dac__desc DAC HPL Description - * - * The following device can use this HPL driver - * - Atmel | SMART SAM D21 - * - * \section hpl__dac__imple DAC HPL Implements - * - \subpage hpl__dac__hw_module1__doc - */ - -#endif /* _HPL_DAC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_delay.h b/atmel-samd/asf4/samd21/hal/include/hpl_delay.h deleted file mode 100644 index 7d2a6f90b..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_delay.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \file - * - * \brief Delay related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_DELAY_H_INCLUDED -#define _HPL_DELAY_H_INCLUDED - -/** - * \addtogroup HPL Delay - * - * \section hpl_delay_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ - -/** - * \brief Initialize delay functionality - * - * \param[in] hw The pointer to hardware instance - */ -void _delay_init(void *const hw); - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - * - * \param[in] us The amount of us to delay for - * - * \return The amount of cycles - */ -uint32_t _get_cycles_for_us(const uint16_t us); - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - * - * \param[in] ms The amount of ms to delay for - * - * \return The amount of cycles - */ -uint32_t _get_cycles_for_ms(const uint16_t ms); - -/** - * \brief Delay loop to delay n number of cycles - * - * \param[in] hw The pointer to hardware instance - * \param[in] cycles The amount of cycles to delay for - */ -void _delay_cycles(void *const hw, uint32_t cycles); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_dma.h b/atmel-samd/asf4/samd21/hal/include/hpl_dma.h deleted file mode 100644 index f8c8cce42..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_dma.h +++ /dev/null @@ -1,167 +0,0 @@ -/** - * \file - * - * \brief DMA related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_DMA_H_INCLUDED -#define _HPL_DMA_H_INCLUDED - -/** - * \addtogroup HPL DMA - * - * \section hpl_dma_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct _dma_resource; - -/** - * \brief DMA callback types - */ -enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; - -/** - * \brief DMA interrupt callbacks - */ -struct _dma_callbacks { - void (*transfer_done)(struct _dma_resource *resource); - void (*error)(struct _dma_resource *resource); -}; - -/** - * \brief DMA resource structure - */ -struct _dma_resource { - struct _dma_callbacks dma_cb; - void * back; -}; - -/** - * \brief Initialize DMA - * - * This function does low level DMA configuration. - * - * \return initialize status - */ -int32_t _dma_init(void); - -/** - * \brief Set destination address - * - * \param[in] channel DMA channel to set destination address for - * \param[in] dst Destination address - * - * \return setting status - */ -int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); - -/** - * \brief Set source address - * - * \param[in] channel DMA channel to set source address for - * \param[in] src Source address - * - * \return setting status - */ -int32_t _dma_set_source_address(const uint8_t channel, const void *const src); - -/** - * \brief Enable/disable source address incrementation during DMA transaction - * - * \param[in] channel DMA channel to set source address for - * \param[in] enable True to enable, false to disable - * - * \return status of operation - */ -int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); - -/** - * \brief Set the amount of data to be transfered per transaction - * - * \param[in] channel DMA channel to set data amount for - * \param[in] amount Data amount - * - * \return status of operation - */ -int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); - -/** - * \brief Trigger DMA transaction on the given channel - * - * \param[in] channel DMA channel to trigger transaction on - * - * \return status of operation - */ -int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); - -/** - * \brief Retrieves DMA resource structure - * - * \param[out] resource The resource to be retrieved - * \param[in] channel DMA channel to retrieve structure for - * - * \return status of operation - */ -int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); - -/** - * \brief Enable/disable DMA interrupt - * - * \param[in] channel DMA channel to enable/disable interrupt for - * \param[in] type The type of interrupt to disable/enable if applicable - * \param[in] state Enable or disable - */ -void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); - -#ifdef __cplusplus -} -#endif - -#endif /* HPL_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_flash.h b/atmel-samd/asf4/samd21/hal/include/hpl_flash.h deleted file mode 100644 index 6a59f757c..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_flash.h +++ /dev/null @@ -1,228 +0,0 @@ -/** - * \file - * - * \brief FLASH related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_FLASH_H_INCLUDED -#define _HPL_FLASH_H_INCLUDED - -/** - * \addtogroup hpl__flash__group FLASH HPL APIs - * - */ - -/**@{*/ - -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief FLASH device structure - * - * The FLASH device structure forward declaration. - */ -struct _flash_device; - -/** The callback types */ -enum _flash_cb_type { FLASH_DEVICE_CB_READY, FLASH_DEVICE_CB_ERROR, FLASH_DEVICE_CB_N }; - -/** - * \brief FLASH interrupt handlers structure - */ -struct _flash_callback { - /** Ready to accept new command handler */ - void (*ready_cb)(struct _flash_device *device); - /** Error handler */ - void (*error_cb)(struct _flash_device *device); -}; - -/** - * \brief FLASH descriptor device structure. - */ -struct _flash_device { - struct _flash_callback flash_cb; /*!< Interrupt handers */ - struct _irq_descriptor irq; /*!< Interrupt descriptor */ - void * hw; /*!< Hardware module instance handler */ -}; - -/** - * \brief Initialize FLASH. - * - * This function does low level FLASH configuration. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialize status. - */ -int32_t _flash_init(struct _flash_device *const device, void *const hw); - -/** - * \brief Deinitialize FLASH. - * - * \param[in] device The pointer to FLASH device instance - */ -void _flash_deinit(struct _flash_device *const device); - -/** - * \brief Reads a number of bytes in the internal Flash. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] src_addr Source bytes address to read from flash - * \param[out] buffer Pointer to a buffer where the content - * of the read page will be stored - * \param[in] length Number of bytes to read - */ -void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length); - -/** - * \brief Writes a number of bytes in the internal Flash. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address to write into flash - * \param[in] buffer Pointer to buffer where the data to - * write is stored - * \param[in] length Number of bytes to write - */ -void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - -/** - * \brief Appends a number of bytes in the internal Flash. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address to write into flash - * \param[in] buffer Pointer to buffer with data to write to flash - * \param[in] length Number of bytes to write - */ -void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - -/** \brief Execute lock in the internal flash - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address aligned with page - * start to be locked - * \param[in] page_nums Number of pages to be locked - * - * \return Real locked numbers of pages. - */ -int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); - -/** \brief Execute unlock in the internal flash - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address aligned with page - * start to be unlocked - * \param[in] page_nums Number of pages to be unlocked - * - * \return Real unlocked numbers of pages. - */ -int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); - -/** \brief check whether the region which is pointed by address - * is locked - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address to check - * - * \return The lock status of assigned address. - */ -bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr); - -/** \brief Execute erase in the internal flash - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address aligned with page - * start to be erased - * \param[in] page_nums Number of pages to be erased - */ -void _flash_erase(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); - -/** - * \brief Get the flash page size. - * - * \param[in] device The pointer to FLASH device instance - * - * \return The flash page size - */ -uint32_t _flash_get_page_size(struct _flash_device *const device); - -/** - * \brief Get the numbers of flash page. - * - * \param[in] device The pointer to FLASH device instance - * - * \return The flash total page numbers - */ -uint32_t _flash_get_total_pages(struct _flash_device *const device); - -/** - * \brief Get the number of wait states for read and write operations. - * - * \param[in] device The pointer to FLASH device instance - * - * \return The number of wait states for read and write operations - */ -uint8_t _flash_get_wait_state(struct _flash_device *const device); - -/** - * \brief Set the number of wait states for read and write operations. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] state The number of wait states - * - */ -void _flash_set_wait_state(struct _flash_device *const device, uint8_t state); - -/** - * \brief Enable/disable Flash interrupt - * - * param[in] device The pointer to Flash device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state); - -#ifdef __cplusplus -} -#endif - -/**@}*/ - -#endif /* _HPL_FLASH_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_gpio.h b/atmel-samd/asf4/samd21/hal/include/hpl_gpio.h deleted file mode 100644 index e1de9c58e..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_gpio.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - * \file - * - * \brief Port related functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_GPIO_H_INCLUDED -#define _HPL_GPIO_H_INCLUDED - -/** - * \addtogroup HPL Port - * - * \section hpl_port_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif -/** - * \brief Macros for the pin and port group, lower 5 - * bits stands for pin number in the group, higher 3 - * bits stands for port group - */ -#define GPIO_PIN(n) (((n)&0x1Fu) << 0) -#define GPIO_PORT(n) ((n) >> 5) -#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) -#define GPIO_PIN_FUNCTION_OFF 0xffffffff - -/** - * \brief PORT pull mode settings - */ -enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; - -/** - * \brief PORT direction settins - */ -enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; - -/** - * \brief PORT group abstraction - */ - -enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Port initialization function - * - * Port initialization function should setup the port module based - * on a static configuration file, this function should normally - * not be called directly, but is a part of hal_init() - */ -void _gpio_init(void); - -/** - * \brief Set direction on port with mask - * - * Set data direction for each pin, or disable the pin - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to the - * corresponding pin - * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input - * and disable input buffer to disable the pin - * GPIO_DIRECTION_IN = set pin direction to input - * and enable input buffer to enable the pin - * GPIO_DIRECTION_OUT = set pin direction to output - * and disable input buffer - */ -static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction); - -/** - * \brief Set output level on port with mask - * - * Sets output state on pin to high or low with pin masking - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to - * the corresponding pin - * \param[in] level true = pin level is set to 1 - * false = pin level is set to 0 - */ -static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); - -/** - * \brief Change output level to the opposite with mask - * - * Change pin output level to the opposite with pin masking - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to - * the corresponding pin - */ -static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); - -/** - * \brief Get input levels on all port pins - * - * Get input level on all port pins, will read IN register if configured to - * input and OUT register if configured as output - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - */ -static inline uint32_t _gpio_get_level(const enum gpio_port port); - -/** - * \brief Set pin pull mode - * - * Set pull mode on a single pin - * - * \notice This function will automatically change pin direction to input - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] pin The pin in the group that pull mode should be selected - * for - * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled - * GPIO_PULL_DOWN = pull resistor on pin will pull pin - * level to ground level - * GPIO_PULL_UP = pull resistor on pin will pull pin - * level to VCC - */ -static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, - const enum gpio_pull_mode pull_mode); - -/** - * \brief Set gpio function - * - * Select which function a gpio is used for - * - * \param[in] gpio The gpio to set function for - * \param[in] function The gpio function is given by a 32-bit wide bitfield - * found in the header files for the device - * - */ -static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); - -#include -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_async.h deleted file mode 100644 index c00d7e733..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_async.h +++ /dev/null @@ -1,215 +0,0 @@ -/** - * \file - * - * \brief I2C Master Hardware Proxy Layer(HPL) declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED -#define _HPL_I2C_M_ASYNC_H_INCLUDED - -#include "hpl_i2c_m_sync.h" -#include "hpl_irq.h" -#include "utils.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c master callback names - */ -enum _i2c_m_async_callback_type { - I2C_M_ASYNC_DEVICE_ERROR, - I2C_M_ASYNC_DEVICE_TX_COMPLETE, - I2C_M_ASYNC_DEVICE_RX_COMPLETE -}; - -struct _i2c_m_async_device; - -typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); -typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); - -/** - * \brief i2c callback pointers structure - */ -struct _i2c_m_async_callback { - _i2c_error_cb_t error; - _i2c_complete_cb_t tx_complete; - _i2c_complete_cb_t rx_complete; -}; - -/** - * \brief i2c device structure - */ -struct _i2c_m_async_device { - struct _i2c_m_service service; - void * hw; - struct _i2c_m_async_callback cb; - struct _irq_descriptor irq; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize I2C in interrupt mode - * - * This function does low level I2C configuration. - * - * \param[in] i2c_dev The pointer to i2c interrupt device structure - * \param[in] hw The pointer to hardware instance - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); - -/** - * \brief Deinitialize I2C in interrupt mode - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Transfer data by I2C - * - * This function does low level I2C data transfer. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] msg The pointer to i2c msg structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); - -/** - * \brief Set baud rate of I2C - * - * This function does low level I2C set baud rate. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] clkrate The clock rate(KHz) input to i2c module - * \param[in] baudrate The demand baud rate(KHz) of i2c module - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Register callback to I2C - * - * This function does low level I2C callback register. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] cb_type The callback type request - * \param[in] func The callback function pointer - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, - FUNC_PTR func); - -/** - * \brief Generate stop condition on the I2C bus - * - * This function will generate a stop condition on the I2C bus - * - * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C - * - * \return Operation status - * \retval 0 Operation executed successfully - * \retval <0 Operation failed - */ -int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Returns the number of bytes left or not used in the I2C message buffer - * - * This function will return the number of bytes left (not written to the bus) or still free - * (not received from the bus) in the message buffer, depending on direction of transmission. - * - * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C - * - * \return Number of bytes or error code - * \retval >0 Positive number indicating bytes left - * \retval 0 Buffer is full/empty depending on direction - * \retval <0 Error code - */ -int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Enable/disable I2C master interrupt - * - * param[in] device The pointer to I2C master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, - const bool state); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_sync.h deleted file mode 100644 index 4a643ee65..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_m_sync.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - * \file - * - * \brief I2C Master Hardware Proxy Layer(HPL) declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_M_SYNC_H_INCLUDED -#define _HPL_I2C_M_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c flags - */ -#define I2C_M_RD 0x0001 /* read data, from slave to master */ -#define I2C_M_BUSY 0x0100 -#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ -#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ -#define I2C_M_FAIL 0x1000 -#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ - -/** - * \brief i2c Return codes - */ -#define I2C_OK 0 /* Operation successful */ -#define I2C_ACK -1 /* Received ACK from device on I2C bus */ -#define I2C_NACK -2 /* Received NACK from device on I2C bus */ -#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ -#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ -#define I2C_ERR_BUS -5 /* Bus error */ -#define I2C_ERR_BUSY -6 /* Device busy */ -#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ - -/** - * \brief i2c I2C Modes - */ -#define I2C_STANDARD_MODE 0x00 -#define I2C_FASTMODE 0x01 -#define I2C_HIGHSPEED_MODE 0x02 - -/** - * \brief i2c master message structure - */ -struct _i2c_m_msg { - uint16_t addr; - volatile uint16_t flags; - int32_t len; - uint8_t * buffer; -}; - -/** - * \brief i2c master service - */ -struct _i2c_m_service { - struct _i2c_m_msg msg; - uint16_t mode; - uint16_t trise; -}; - -/** - * \brief i2c sync master device structure - */ -struct _i2c_m_sync_device { - struct _i2c_m_service service; - void * hw; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize I2C - * - * This function does low level I2C configuration. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] hw The pointer to hardware instance - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); - -/** - * \brief Deinitialize I2C - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Transfer data by I2C - * - * This function does low level I2C data transfer. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] msg The pointer to i2c msg structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); - -/** - * \brief Set baud rate of I2C - * - * This function does low level I2C set baud rate. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] clkrate The clock rate(KHz) input to i2c module - * \param[in] baudrate The demand baud rate(KHz) of i2c module - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Send send condition on the I2C bus - * - * This function will generate a stop condition on the I2C bus - * - * \param[in] i2c_dev The pointer to i2c device struct - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_async.h deleted file mode 100644 index b240478f7..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_async.h +++ /dev/null @@ -1,194 +0,0 @@ -/** - * \file - * - * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED -#define _HPL_I2C_S_ASYNC_H_INCLUDED - -#include "hpl_i2c_s_sync.h" -#include "hpl_irq.h" -#include "utils.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c callback types - */ -enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; - -/** - * \brief Forward declaration of I2C Slave device - */ -struct _i2c_s_async_device; - -/** - * \brief i2c slave callback function type - */ -typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); - -/** - * \brief i2c slave callback pointers structure - */ -struct _i2c_s_async_callback { - void (*error)(struct _i2c_s_async_device *const device); - void (*tx)(struct _i2c_s_async_device *const device); - void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); -}; - -/** - * \brief i2c slave device structure - */ -struct _i2c_s_async_device { - void * hw; - struct _i2c_s_async_callback cb; - struct _irq_descriptor irq; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize asynchronous I2C slave - * - * This function does low level I2C configuration. - * - * \param[in] device The pointer to i2c interrupt device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); - -/** - * \brief Deinitialize asynchronous I2C in interrupt mode - * - * \param[in] device The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); - -/** - * \brief Check if 10-bit addressing mode is on - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Cheking status - * \retval 1 10-bit addressing mode is on - * \retval 0 10-bit addressing mode is off - */ -int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); - -/** - * \brief Set I2C slave address - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] address Address to set - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); - -/** - * \brief Write a byte to the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] data Data to write - */ -void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); - -/** - * \brief Retrieve I2C slave status - * - * \param[in] device The pointer to i2c slave device structure - * - *\return I2C slave status - */ -i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); - -/** - * \brief Abort data transmission - * - * \param[in] device The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); - -/** - * \brief Enable/disable I2C slave interrupt - * - * param[in] device The pointer to I2C slave device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] disable Enable or disable - */ -int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, - const bool disable); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_sync.h deleted file mode 100644 index a0f4fa465..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_i2c_s_sync.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - * \file - * - * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_S_SYNC_H_INCLUDED -#define _HPL_I2C_S_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief I2C Slave status type - */ -typedef uint32_t i2c_s_status_t; - -/** - * \brief i2c slave device structure - */ -struct _i2c_s_sync_device { - void *hw; -}; - -#include - -/** - * \name HPL functions - */ - -/** - * \brief Initialize synchronous I2C slave - * - * This function does low level I2C configuration. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize synchronous I2C slave - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); - -/** - * \brief Check if 10-bit addressing mode is on - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Cheking status - * \retval 1 10-bit addressing mode is on - * \retval 0 10-bit addressing mode is off - */ -int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); - -/** - * \brief Set I2C slave address - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] address Address to set - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); - -/** - * \brief Write a byte to the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] data Data to write - */ -void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); - -/** - * \brief Retrieve I2C slave status - * - * \param[in] device The pointer to i2c slave device structure - * - *\return I2C slave status - */ -i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); - -/** - * \brief Read a byte from the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Data received via I2C interface. - */ -uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); - -/** - * \brief Check if I2C is ready to send next byte - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Status of the ready check. - * \retval true if the I2C is ready to send next byte - * \retval false if the I2C is not ready to send next byte - */ -bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); - -/** - * \brief Check if there is data received by I2C - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Status of the data received check. - * \retval true if the I2C has received a byte - * \retval false if the I2C has not received a byte - */ -bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_init.h b/atmel-samd/asf4/samd21/hal/include/hpl_init.h deleted file mode 100644 index be54600c0..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_init.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - * \file - * - * \brief Init related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_INIT_H_INCLUDED -#define _HPL_INIT_H_INCLUDED - -/** - * \addtogroup HPL Init - * - * \section hpl_init_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initializes clock sources - */ -void _sysctrl_init_sources(void); - -/** - * \brief Initializes Power Manager - */ -void _pm_init(void); - -/** - * \brief Initialize generators - */ -void _gclk_init_generators(void); - -/** - * \brief Initialize 32 kHz clock sources - */ -void _osc32kctrl_init_sources(void); - -/** - * \brief Initialize clock sources - */ -void _oscctrl_init_sources(void); - -/** - * \brief Initialize clock sources that need input reference clocks - */ -void _sysctrl_init_referenced_generators(void); - -/** - * \brief Initialize clock sources that need input reference clocks - */ -void _oscctrl_init_referenced_generators(void); - -/** - * \brief Initialize master clock generator - */ -void _mclk_init(void); - -/** - * \brief Initialize clock generator - */ -void _lpmcu_misc_regs_init(void); - -/** - * \brief Initialize clock generator - */ -void _pmc_init(void); - -/** - * \brief Set performance level - * - * \param[in] level The performance level to set - */ -void _set_performance_level(const uint8_t level); - -/** - * \brief Initialize the chip - */ -void _init_chip(void); - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_irq.h b/atmel-samd/asf4/samd21/hal/include/hpl_irq.h deleted file mode 100644 index 7325b5711..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_irq.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief IRQ related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_IRQ_H_INCLUDED -#define _HPL_IRQ_H_INCLUDED - -/** - * \addtogroup HPL IRQ - * - * \section hpl_irq_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief IRQ descriptor - */ -struct _irq_descriptor { - void (*handler)(void *parameter); - void *parameter; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Retrieve current IRQ number - * - * \return The current IRQ number - */ -uint8_t _irq_get_current(void); - -/** - * \brief Disable the given IRQ - * - * \param[in] n The number of IRQ to disable - */ -void _irq_disable(uint8_t n); - -/** - * \brief Set the given IRQ - * - * \param[in] n The number of IRQ to set - */ -void _irq_set(uint8_t n); - -/** - * \brief Clear the given IRQ - * - * \param[in] n The number of IRQ to clear - */ -void _irq_clear(uint8_t n); - -/** - * \brief Enable the given IRQ - * - * \param[in] n The number of IRQ to enable - */ -void _irq_enable(uint8_t n); - -/** - * \brief Register IRQ handler - * - * \param[in] number The number registered IRQ - * \param[in] irq The pointer to irq handler to register - * - * \return The status of IRQ handler registering - * \retval -1 Passed parameters were invalid - * \retval 0 The registering is completed successfully - */ -void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_missing_features.h b/atmel-samd/asf4/samd21/hal/include/hpl_missing_features.h deleted file mode 100644 index 90fa16be4..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_missing_features.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * \file - * - * \brief Family-dependent missing features expected by HAL - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_MISSING_FEATURES -#define _HPL_MISSING_FEATURES - -#endif /* _HPL_MISSING_FEATURES */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_pwm.h b/atmel-samd/asf4/samd21/hal/include/hpl_pwm.h deleted file mode 100644 index 8deb54cc0..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_pwm.h +++ /dev/null @@ -1,203 +0,0 @@ -/** - * \file - * - * \brief PWM related functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_PWM_H_INCLUDED -#define _HPL_PWM_H_INCLUDED - -/** - * \addtogroup HPL PWM - * - * \section hpl_pwm_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief PWM callback types - */ -enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB }; - -/** - * \brief PWM pulse-width period - */ -typedef uint32_t pwm_period_t; - -/** - * \brief PWM device structure - * - * The PWM device structure forward declaration. - */ -struct _pwm_device; - -/** - * \brief PWM interrupt callbacks - */ -struct _pwm_callback { - void (*pwm_period_cb)(struct _pwm_device *device); - void (*pwm_error_cb)(struct _pwm_device *device); -}; - -/** - * \brief PWM descriptor device structure - */ -struct _pwm_device { - struct _pwm_callback callback; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \brief PWM functions, pointers to low-level functions - */ -struct _pwm_hpl_interface { - int32_t (*init)(struct _pwm_device *const device, void *const hw); - void (*deinit)(struct _pwm_device *const device); - void (*start_pwm)(struct _pwm_device *const device); - void (*stop_pwm)(struct _pwm_device *const device); - void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); - bool (*is_pwm_enabled)(const struct _pwm_device *const device); - pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device); - uint32_t (*pwm_get_duty)(const struct _pwm_device *const device); - void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); -}; -/** - * \brief Initialize TC - * - * This function does low level TC configuration. - * - * \param[in] device The pointer to PWM device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - */ -int32_t _pwm_init(struct _pwm_device *const device, void *const hw); - -/** - * \brief Deinitialize TC - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_deinit(struct _pwm_device *const device); - -/** - * \brief Retrieve offset of the given tc hardware instance - * - * \param[in] device The pointer to PWM device instance - * - * \return The offset of the given tc hardware instance - */ -uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device); - -/** - * \brief Start hardware pwm - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_enable(struct _pwm_device *const device); - -/** - * \brief Stop hardware pwm - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_disable(struct _pwm_device *const device); - -/** - * \brief Set pwm parameter - * - * \param[in] device The pointer to PWM device instance - * \param[in] period Total period of one PWM cycle. - * \param[in] duty_cycle Period of PWM first half during one cycle. - */ -void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); - -/** - * \brief Check if pwm is working - * - * \param[in] device The pointer to PWM device instance - * - * \return Check status. - * \retval true The given pwm is working - * \retval false The given pwm is not working - */ -bool _pwm_is_enabled(const struct _pwm_device *const device); - -/** - * \brief Get pwm waveform period value - * - * \param[in] device The pointer to PWM device instance - * - * \return Period value. - */ -pwm_period_t _pwm_get_period(const struct _pwm_device *const device); - -/** - * \brief Get pwm waveform duty cycle value - * - * \param[in] device The pointer to PWM device instance - * - * \return Duty cycle value - */ -uint32_t _pwm_get_duty(const struct _pwm_device *const device); - -/** - * \brief Enable/disable PWM interrupt - * - * param[in] device The pointer to PWM device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] disable Enable or disable - */ -void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_PWM_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_reset.h b/atmel-samd/asf4/samd21/hal/include/hpl_reset.h deleted file mode 100644 index 7cb48aff0..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_reset.h +++ /dev/null @@ -1,101 +0,0 @@ -/** - * \file - * - * \brief Reset related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_RESET_H_INCLUDED -#define _HPL_RESET_H_INCLUDED - -/** - * \addtogroup HPL Reset - * - * \section hpl_reset_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Reset reason enumeration - * - * The list of possible reset reasons. - */ -enum reset_reason { - RESET_REASON_POR = 1, - RESET_REASON_BOD12 = 2, - RESET_REASON_BOD33 = 4, - RESET_REASON_EXT = 16, - RESET_REASON_WDT = 32, - RESET_REASON_SYST = 64, -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Retrieve the reset reason - * - * Retrieves the reset reason of the last MCU reset. - * - *\return An enum value indicating the reason of the last reset. - */ -enum reset_reason _get_reset_reason(void); - -/** - * \brief Reset MCU - */ -void _reset_mcu(void); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_sleep.h b/atmel-samd/asf4/samd21/hal/include/hpl_sleep.h deleted file mode 100644 index 3bd6a1cb2..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_sleep.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SLEEP_H_INCLUDED -#define _HPL_SLEEP_H_INCLUDED - -/** - * \addtogroup HPL Sleep - * - * \section hpl_sleep_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Set the sleep mode for the device - * - * This function sets the sleep mode for the device. - * For an overview of which systems are disabled in sleep for the different - * sleep modes see datasheet. - * - * \param[in] mode Sleep mode to use - * - * \return the status of a sleep request - * \retval -1 The requested sleep mode was invalid - * \retval 0 The operation completed successfully, sleep mode is set - */ -int32_t _set_sleep_mode(const uint8_t mode); - -/** - * \brief Reset MCU - */ -void _reset_mcu(void); - -/** - * \brief Put MCU to sleep - */ -void _go_to_sleep(void); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi.h deleted file mode 100644 index 14177642f..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_spi.h +++ /dev/null @@ -1,173 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (C) 2014 - 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_H_INCLUDED -#define _HPL_SPI_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief SPI Dummy char is used when reading data from the SPI slave - */ -#define SPI_DUMMY_CHAR 0x1ff - -/** - * \brief SPI message to let driver to process - */ -//@{ -struct spi_msg { - /** Pointer to the output data buffer */ - uint8_t *txbuf; - /** Pointer to the input data buffer */ - uint8_t *rxbuf; - /** Size of the message data in SPI characters */ - uint32_t size; -}; -//@} - -/** - * \brief SPI transfer modes - * SPI transfer mode controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - */ -enum spi_transfer_mode { - /** Leading edge is rising edge, data sample on leading edge. */ - SPI_MODE_0, - /** Leading edge is rising edge, data sample on trailing edge. */ - SPI_MODE_1, - /** Leading edge is falling edge, data sample on leading edge. */ - SPI_MODE_2, - /** Leading edge is falling edge, data sample on trailing edge. */ - SPI_MODE_3 -}; - -/** - * \brief SPI character sizes - * The character size influence the way the data is sent/received. - * For char size <= 8 data is stored byte by byte. - * For char size between 9 ~ 16 data is stored in 2-byte length. - * Note that the default and recommended char size is 8 bit since it's - * supported by all system. - */ -enum spi_char_size { - /** Character size is 8 bit. */ - SPI_CHAR_SIZE_8 = 0, - /** Character size is 9 bit. */ - SPI_CHAR_SIZE_9 = 1, - /** Character size is 10 bit. */ - SPI_CHAR_SIZE_10 = 2, - /** Character size is 11 bit. */ - SPI_CHAR_SIZE_11 = 3, - /** Character size is 12 bit. */ - SPI_CHAR_SIZE_12 = 4, - /** Character size is 13 bit. */ - SPI_CHAR_SIZE_13 = 5, - /** Character size is 14 bit. */ - SPI_CHAR_SIZE_14 = 6, - /** Character size is 15 bit. */ - SPI_CHAR_SIZE_15 = 7, - /** Character size is 16 bit. */ - SPI_CHAR_SIZE_16 = 8 -}; - -/** - * \brief SPI data order - */ -enum spi_data_order { - /** MSB goes first. */ - SPI_DATA_ORDER_MSB_1ST = 0, - /** LSB goes first. */ - SPI_DATA_ORDER_LSB_1ST = 1 -}; - -/** \brief Transfer descriptor for SPI - * Transfer descriptor holds TX and RX buffers - */ -struct spi_xfer { - /** Pointer to data buffer to TX */ - uint8_t *txbuf; - /** Pointer to data buffer to RX */ - uint8_t *rxbuf; - /** Size of data characters to TX & RX */ - uint32_t size; -}; - -/** SPI generic driver. */ -struct spi_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Reference start of sync/async variables */ - uint32_t sync_async_misc[1]; -}; - -/** - * \brief Calculate the baudrate value for hardware to use to set baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] clk Clock frequency (Hz) for baudrate generation. - * \param[in] baud Target baudrate (bps). - * \return Error or baudrate value. - * \retval >0 Baudrate value. - * \retval ERR_INVALID_ARG Calculation fail. - */ -int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_async.h deleted file mode 100644 index b81ef12af..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_spi_async.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * \file - * - * \brief Common SPI related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_ASYNC_H_INCLUDED -#define _HPL_SPI_ASYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Callbacks the SPI driver must offer in async mode - */ -//@{ -/** The callback types */ -enum _spi_async_dev_cb_type { - /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ - SPI_DEV_CB_TX, - /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ - SPI_DEV_CB_RX, - /** Callback type for \ref _spi_async_dev_cb_complete_t. */ - SPI_DEV_CB_COMPLETE, - /** Number of callbacks. */ - SPI_DEV_CB_N -}; - -struct _spi_async_dev; - -/** \brief The prototype for callback on SPI transfer complete. - * If status code is zero, it indicates the normal completion, that is, - * SS deactivation. - * If status code belows zero, it indicates complete. - */ -typedef void (*_spi_async_dev_cb_complete_t)(struct _spi_async_dev *dev, int32_t status); - -/** \brief The prototype for callback on SPI transmit/receive event - * For TX, the callback is invoked when transmit is done or ready to start - * transmit. - * For RX, the callback is invoked when receive is done or ready to read data, - * see \ref _spi_async_dev_read_one_t on data reading. - * Without DMA enabled, the callback is invoked on each character event. - * With DMA enabled, the callback is invoked on DMA buffer done. - */ -typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); - -/** - * \brief The callbacks offered by SPI driver - */ -struct _spi_async_dev_callbacks { - /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ - _spi_async_dev_cb_xfer_t tx; - /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ - _spi_async_dev_cb_xfer_t rx; - /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ - _spi_async_dev_cb_complete_t complete; -}; -//@} - -/** - * \brief SPI async driver - */ -//@{ - -/** SPI driver to support async HAL */ -struct _spi_async_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Data size, number of bytes for each character */ - uint8_t char_size; - /** Dummy byte used in master mode when reading the slave */ - uint16_t dummy_byte; - - /** \brief Pointer to callback functions, ignored for polling mode - * Pointer to the callback functions so that initialize the driver to - * handle interrupts. - */ - struct _spi_async_dev_callbacks callbacks; - /** IRQ instance for SPI device. */ - struct _irq_descriptor irq; -}; -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_dma.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_dma.h deleted file mode 100644 index 3f2088c05..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_spi_dma.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * \file - * - * \brief Common SPI DMA related functionality declaration. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_DMA_H_INCLUDED -#define _HPL_SPI_DMA_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** The callback types */ -enum _spi_dma_dev_cb_type { - /** Callback type for DMA transmit. */ - SPI_DEV_CB_DMA_TX, - /** Callback type for DMA receive. */ - SPI_DEV_CB_DMA_RX, - /** Callback type for DMA error. */ - SPI_DEV_CB_DMA_ERROR, - /** Number of callbacks. */ - SPI_DEV_CB_DMA_N -}; - -struct _spi_dma_dev; - -/** - * \brief The prototype for callback on SPI DMA. - */ -typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource); - -/** - * \brief The callbacks offered by SPI driver - */ -struct _spi_dma_dev_callbacks { - _spi_dma_cb_t tx; - _spi_dma_cb_t rx; - _spi_dma_cb_t error; -}; - -/** SPI driver to support DMA HAL */ -struct _spi_dma_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Pointer to callback functions */ - struct _spi_dma_dev_callbacks callbacks; - /** IRQ instance for SPI device. */ - struct _irq_descriptor irq; - /** DMA resource */ - struct _dma_resource *resource; -}; - -#ifdef __cplusplus -} -#endif - -#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_async.h deleted file mode 100644 index f2d330495..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_async.h +++ /dev/null @@ -1,248 +0,0 @@ -/** - * \file - * - * \brief SPI Slave Async related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED -#define _HPL_SPI_M_ASYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_m_async_dev _spi_async_dev - -#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type - -/** Uses common SPI async device driver complete callback type. */ -#define _spi_m_async_dev_cb_complete_t _spi_async_dev_cb_complete_t - -/** Uses common SPI async device driver transfer callback type. */ -#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t - -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on Slave Select (SS) rising - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_m_async_enable_ss_detect(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); - -/** - * \brief Register the SPI device callback - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, - const FUNC_PTR func); - -/** - * \brief Enable/disable SPI master interrupt - * - * param[in] device The pointer to SPI master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, - const bool state); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_dma.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_dma.h deleted file mode 100644 index 5e676fdc5..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_dma.h +++ /dev/null @@ -1,187 +0,0 @@ -/** - * \file - * - * \brief SPI Master DMA related functionality declaration. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_DMA_H_INCLUDED -#define _HPL_SPI_M_DMA_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI dma device driver. */ -#define _spi_m_dma_dev _spi_dma_dev - -#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type - -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); - -/** - * \brief Register the SPI device callback - * \param[in] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); - -/** \brief Do SPI data transfer (TX & RX) with DMA - * Log the TX & RX buffers and transfer them in background. It never blocks. - * - * \param[in] dev Pointer to the SPI device instance. - * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). - * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). - * \param[in] length spi transfer data length. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy. - */ -int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, - const uint16_t length); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_sync.h deleted file mode 100644 index fff1db4f2..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_spi_m_sync.h +++ /dev/null @@ -1,171 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_SYNC_H_INCLUDED -#define _HPL_SPI_M_SYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_m_sync_dev _spi_sync_dev - -/** - * \brief Initialize SPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); - -/** - * \brief Deinitialize SPI - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); - -/** - * \brief Enable SPI for access without interrupts - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); - -/** - * \brief Transfer the whole message without interrupt - * Transfer the message, it will keep waiting until the message finish or - * error. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] msg Pointer to the message instance to process. - * \return Error or number of characters transferred. - * \retval ERR_BUSY SPI hardware is not ready to start transfer (not - * enabled, busy applying settings, ...). - * \retval SPI_ERR_OVERFLOW Overflow error. - * \retval >=0 Number of characters transferred. - */ -int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_async.h deleted file mode 100644 index aec3c0a6f..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_async.h +++ /dev/null @@ -1,227 +0,0 @@ -/** - * \file - * - * \brief SPI Slave Async related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED -#define _HPL_SPI_S_ASYNC_H_INCLUDED - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_s_async_dev _spi_async_dev - -#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type - -/** Uses common SPI async device driver complete callback type. */ -#define _spi_s_async_dev_cb_complete_t _spi_async_dev_cb_complete_t - -/** Uses common SPI async device driver transfer callback type. */ -#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t - -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on Slave Select (SS) rising - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); - -/** - * \brief Register the SPI device callback - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, - const FUNC_PTR func); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_sync.h deleted file mode 100644 index d42368697..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_spi_s_sync.h +++ /dev/null @@ -1,237 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_S_SYNC_H_INCLUDED -#define _HPL_SPI_S_SYNC_H_INCLUDED - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_s_sync_dev _spi_sync_dev - -/** - * \brief Initialize SPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); - -/** - * \brief Enable SPI for access without interrupts - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retval 0 OK Status - */ -int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); - -/** - * \brief Check if TX ready - * - * \param[in] dev Pointer to the SPI device instance - * - * \return TX ready state - * \retval true TX ready - * \retval false TX not ready - */ -bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if RX character ready - * - * \param[in] dev Pointer to the SPI device instance - * - * \return RX character ready state - * \retval true RX character ready - * \retval false RX character not ready - */ -bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if SS deactiviation detected - * - * \param[in] dev Pointer to the SPI device instance - * - * \return SS deactiviation state - * \retval true SS deactiviation detected - * \retval false SS deactiviation not detected - */ -bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if error is detected - * - * \param[in] dev Pointer to the SPI device instance - * - * \return Error detection state - * \retval true Error detected - * \retval false Error not detected - */ -bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_spi_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_spi_sync.h deleted file mode 100644 index a231a0bb5..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_spi_sync.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * \brief Common SPI related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_SYNC_H_INCLUDED -#define _HPL_SPI_SYNC_H_INCLUDED - -#include -#include - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * \section hpl_spi_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** SPI driver to support sync HAL */ -struct _spi_sync_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Data size, number of bytes for each character */ - uint8_t char_size; - /** Dummy byte used in master mode when reading the slave */ - uint16_t dummy_byte; -}; - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_time_measure.h b/atmel-samd/asf4/samd21/hal/include/hpl_time_measure.h deleted file mode 100644 index 7502a5910..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_time_measure.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - * \file - * - * \brief Time measure related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_TIME_MEASURE_H_INCLUDED -#define _HPL_TIME_MEASURE_H_INCLUDED - -/** - * \addtogroup HPL Time measure - * - * \section hpl_time_measure_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief System time type - */ -typedef uint32_t system_time_t; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize system time module - * - * \param[in] hw The pointer to hardware instance to initialize - */ -void _system_time_init(void *const hw); - -/** - * \brief Deinitialize system time module - * - * \param[in] hw The pointer to hardware instance to initialize - */ -void _system_time_deinit(void *const hw); - -/** - * \brief Get system time - * - * \param[in] hw The pointer to hardware instance to initialize - */ -system_time_t _system_time_get(const void *const hw); - -/** - * \brief Get maximum possible system time - * - * \param[in] hw The pointer to hardware instance to initialize - */ -system_time_t _system_time_get_max_time_value(const void *const hw); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_TIME_MEASURE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_timer.h b/atmel-samd/asf4/samd21/hal/include/hpl_timer.h deleted file mode 100644 index d2434e8c4..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_timer.h +++ /dev/null @@ -1,170 +0,0 @@ -/** - * \file - * - * \brief Timer related functionality declaration. - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_TIMER_H_INCLUDED -#define _HPL_TIMER_H_INCLUDED - -/** - * \addtogroup HPL Timer - * - * \section hpl_timer_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Timer device structure - * - * The Timer device structure forward declaration. - */ -struct _timer_device; - -/** - * \brief Timer interrupt callbacks - */ -struct _timer_callbacks { - void (*period_expired)(struct _timer_device *device); -}; - -/** - * \brief Timer device structure - */ -struct _timer_device { - struct _timer_callbacks timer_cb; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \brief Timer functions, pointers to low-level functions - */ -struct _timer_hpl_interface { - int32_t (*init)(struct _timer_device *const device, void *const hw); - void (*deinit)(struct _timer_device *const device); - void (*start_timer)(struct _timer_device *const device); - void (*stop_timer)(struct _timer_device *const device); - void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); - uint32_t (*get_period)(const struct _timer_device *const device); - bool (*is_timer_started)(const struct _timer_device *const device); - void (*set_timer_irq)(struct _timer_device *const device); -}; -/** - * \brief Initialize TCC - * - * This function does low level TCC configuration. - * - * \param[in] device The pointer to timer device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - */ -int32_t _timer_init(struct _timer_device *const device, void *const hw); - -/** - * \brief Deinitialize TCC - * - * \param[in] device The pointer to timer device instance - */ -void _timer_deinit(struct _timer_device *const device); - -/** - * \brief Start hardware timer - * - * \param[in] device The pointer to timer device instance - */ -void _timer_start(struct _timer_device *const device); - -/** - * \brief Stop hardware timer - * - * \param[in] device The pointer to timer device instance - */ -void _timer_stop(struct _timer_device *const device); - -/** - * \brief Set timer period - * - * \param[in] device The pointer to timer device instance - */ -void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); - -/** - * \brief Retrieve timer period - * - * \param[in] device The pointer to timer device instance - * - * \return Timer period - */ -uint32_t _timer_get_period(const struct _timer_device *const device); - -/** - * \brief Check if timer is running - * - * \param[in] device The pointer to timer device instance - * - * \return Check status. - * \retval true The given timer is running - * \retval false The given timer is not running - */ -bool _timer_is_started(const struct _timer_device *const device); - -/** - * \brief Set timer IRQ - * - * \param[in] device The pointer to timer device instance - */ -void _timer_set_irq(struct _timer_device *const device); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usart.h b/atmel-samd/asf4/samd21/hal/include/hpl_usart.h deleted file mode 100644 index f6235de93..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_usart.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USART_H_INCLUDED -#define _HPL_USART_H_INCLUDED - -/** - * \addtogroup HPL USART SYNC - * - * \section hpl_usart_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART flow control state - */ -union usart_flow_control_state { - struct { - uint8_t cts : 1; - uint8_t rts : 1; - uint8_t unavailable : 1; - uint8_t reserved : 5; - } bit; - uint8_t value; -}; - -/** - * \brief USART baud rate mode - */ -enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; - -/** - * \brief USART data order - */ -enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; - -/** - * \brief USART mode - */ -enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; - -/** - * \brief USART parity - */ -enum usart_parity { - USART_PARITY_EVEN = 0, - USART_PARITY_ODD = 1, - USART_PARITY_NONE = 2, - USART_PARITY_SPACE = 3, - USART_PARITY_MARK = 4 -}; - -/** - * \brief USART stop bits mode - */ -enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; - -/** - * \brief USART character size - */ -enum usart_character_size { - USART_CHARACTER_SIZE_8BITS = 0, - USART_CHARACTER_SIZE_9BITS = 1, - USART_CHARACTER_SIZE_5BITS = 5, - USART_CHARACTER_SIZE_6BITS = 6, - USART_CHARACTER_SIZE_7BITS = 7 -}; - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usart_async.h b/atmel-samd/asf4/samd21/hal/include/hpl_usart_async.h deleted file mode 100644 index 1bcb3da44..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_usart_async.h +++ /dev/null @@ -1,280 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USART_ASYNC_H_INCLUDED -#define _HPL_USART_ASYNC_H_INCLUDED - -/** - * \addtogroup HPL USART - * - * \section hpl_usart_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_usart.h" -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART callback types - */ -enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; - -/** - * \brief USART device structure - * - * The USART device structure forward declaration. - */ -struct _usart_async_device; - -/** - * \brief USART interrupt callbacks - */ -struct _usart_async_callbacks { - void (*tx_byte_sent)(struct _usart_async_device *device); - void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); - void (*tx_done_cb)(struct _usart_async_device *device); - void (*error_cb)(struct _usart_async_device *device); -}; - -/** - * \brief USART descriptor device structure - */ -struct _usart_async_device { - struct _usart_async_callbacks usart_cb; - struct _irq_descriptor irq; - void * hw; -}; -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize asynchronous USART - * - * This function does low level USART configuration. - * - * \param[in] device The pointer to USART device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); - -/** - * \brief Deinitialize USART - * - * This function closes the given USART by disabling its clock. - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_deinit(struct _usart_async_device *const device); - -/** - * \brief Enable usart module - * - * This function will enable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable(struct _usart_async_device *const device); - -/** - * \brief Disable usart module - * - * This function will disable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_disable(struct _usart_async_device *const device); - -/** - * \brief Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); - -/** - * \brief Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); - -/** - * \brief Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); - -/** - * \brief Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); - -/** - * \brief Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); - -/** - * \brief Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); - -/** - * \brief Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); - -/** - * \brief Retrieve usart status - * - * \param[in] device The pointer to USART device instance - */ -uint32_t _usart_async_get_status(const struct _usart_async_device *const device); - -/** - * \brief Write a byte to the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - */ -void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); - -/** - * \brief Check if USART is ready to send next byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART is ready to send next byte - * \retval false if the USART is not ready to send next byte - */ -bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); - -/** - * \brief Set the state of flow control pins - * - * \param[in] device The pointer to USART device instance - * \param[in] state - A state of flow control pins to set - */ -void _usart_async_set_flow_control_state(struct _usart_async_device *const device, - const union usart_flow_control_state state); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins. - * - * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. - */ -union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); - -/** - * \brief Enable data register empty interrupt - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); - -/** - * \brief Enable transmission complete interrupt - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); - -/** - * \brief Retrieve ordinal number of the given USART hardware instance - * - * \param[in] device The pointer to USART device instance - * - * \return The ordinal number of the given USART hardware instance - */ -uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); - -/** - * \brief Enable/disable USART interrupt - * - * param[in] device The pointer to USART device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, - const bool state); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usart_sync.h b/atmel-samd/asf4/samd21/hal/include/hpl_usart_sync.h deleted file mode 100644 index c7881583c..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_usart_sync.h +++ /dev/null @@ -1,253 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SYNC_USART_H_INCLUDED -#define _HPL_SYNC_USART_H_INCLUDED - -/** - * \addtogroup HPL USART SYNC - * - * \section hpl_usart_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART descriptor device structure - */ -struct _usart_sync_device { - void *hw; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize synchronous USART - * - * This function does low level USART configuration. - * - * \param[in] device The pointer to USART device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize USART - * - * This function closes the given USART by disabling its clock. - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_deinit(struct _usart_sync_device *const device); - -/** - * \brief Enable usart module - * - * This function will enable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_enable(struct _usart_sync_device *const device); - -/** - * \brief Disable usart module - * - * This function will disable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_disable(struct _usart_sync_device *const device); - -/** - * \brief Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); - -/** - * \brief Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); - -/** - * \brief Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); - -/** - * \brief Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); - -/** - * \brief Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); - -/** - * \brief Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); - -/** - * \brief Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); - -/** - * \brief Retrieve usart status - * - * \param[in] device The pointer to USART device instance - */ -uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); - -/** - * \brief Write a byte to the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - */ -void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); - -/** - * \brief Read a byte from the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - * - * \return Data received via USART interface. - */ -uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); - -/** - * \brief Check if USART is ready to send next byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART is ready to send next byte - * \retval false if the USART is not ready to send next byte - */ -bool _usart_sync_is_byte_sent(const struct _usart_sync_device *const device); - -/** - * \brief Check if there is data received by USART - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the data received check. - * \retval true if the USART has received a byte - * \retval false if the USART has not received a byte - */ -bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); - -/** - * \brief Set the state of flow control pins - * - * \param[in] device The pointer to USART device instance - * \param[in] state - A state of flow control pins to set - */ -void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, - const union usart_flow_control_state state); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins. - * - * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. - */ -union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); - -/** - * \brief Retrieve ordinal number of the given USART hardware instance - * - * \param[in] device The pointer to USART device instance - * - * \return The ordinal number of the given USART hardware instance - */ -uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usb.h b/atmel-samd/asf4/samd21/hal/include/hpl_usb.h deleted file mode 100644 index d31bd9785..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_usb.h +++ /dev/null @@ -1,281 +0,0 @@ -/** - * \file - * - * \brief SAM USB HPL - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USB_H_INCLUDED -#define _HPL_USB_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** \name USB Spec definitions */ -/*@{*/ - -/** Return 8-bit unsigned USB data. */ -#define USB_GET_U8(addr, offset) (((uint8_t *)(addr))[(offset)]) - -/** Return 16-bit unsigned USB data. */ -#define USB_GET_U16(addr, offset) ((((uint8_t *)(addr))[(offset) + 0] << 0) + (((uint8_t *)(addr))[(offset) + 1] << 8)) - -/** Return 32-bit unsigned USB data. */ -#define USB_GET_U32(addr, offset) \ - ((((uint8_t *)(addr))[(offset) + 0] << 0) + (((uint8_t *)(addr))[(offset) + 1] << 8) \ - + (((uint8_t *)(addr))[(offset) + 2] << 16) \ - + (((uint8_t *)(addr))[(offset) + 3] << 32)) - -/** Offset of bmRequestType in USB request buffer. */ -#define USB_bmRequestType_Offset 0 - -/** Offset of bRequest in USB request buffer. */ -#define USB_bRequest_Offset 1 - -/** Offset of wValue in USB request buffer. */ -#define USB_wValue_Offset 2 - -/** Offset of wIndex in USB request buffer. */ -#define USB_wIndex_Offset 4 - -/** Offset of wLength in USB request buffer. */ -#define USB_wLength_Offset 6 - -/** Get value of bmRequestType from USB request. */ -#define USB_GET_bmRequestType(req) USB_GET_U8((req), USB_bmRequestType_Offset) - -/** Get value of bRequest from USB request. */ -#define USB_GET_bRequest(req) USB_GET_U8((req), USB_bRequest_Offset) - -/** Get value of wValue from USB request. */ -#define USB_GET_wValue(req) USB_GET_U16((req), USB_wValue_Offset) - -/** Get value of wIndex from USB request. */ -#define USB_GET_wIndex(req) USB_GET_U16((req), USB_wIndex_Offset) - -/** Get value of wLength from USB request. */ -#define USB_GET_wLength(req) USB_GET_U16((req), USB_wLength_Offset) - -/** USB request IN indication of bmRequestType. */ -#define USB_REQ_TYPE_IN 0x80u - -/** USB endpoint number mask of bEndpointAddress. */ -#define USB_EP_N_MASK 0x0Fu - -/** USB endpoint direction bit of bEndpointAddress. */ -#define USB_EP_DIR 0x80u - -/** Get USB endpoint direction from endpoint address. */ -#define USB_EP_GET_DIR(ep_addr) ((ep_addr)&USB_EP_DIR) - -/** Get USB endpoint number from endpoint address. */ -#define USB_EP_GET_N(ep_addr) ((ep_addr)&USB_EP_N_MASK) - -/** Transfer type in EP descriptor bmAttributes: Control. */ -#define USB_EP_XTYPE_CTRL 0x0 - -/** Transfer type in EP descriptor bmAttributes: Isochronous. */ -#define USB_EP_XTYPE_ISOCH 0x1 - -/** Transfer type in EP descriptor bmAttributes: Bulk. */ -#define USB_EP_XTYPE_BULK 0x2 - -/** Transfer type in EP descriptor bmAttributes: Interrupt. */ -#define USB_EP_XTYPE_INTERRUPT 0x3 - -/** Transfer type mask in EP descriptor bmAttributes. */ -#define USB_EP_XTYPE_MASK 0x3u - -/*@}*/ - -/** \name USB status codes - *@{ - */ -/** USB operation is done successfully. */ -#define USB_OK 0 -/** USB (endpoint) is busy. */ -#define USB_BUSY 1 -/** USB (endpoint) is halted. */ -#define USB_HALTED 2 - -/** General error. */ -#define USB_ERROR 0x10 -/** Operation is denied by hardware (e.g., syncing). */ -#define USB_ERR_DENIED 0x11 -/** Input parameter error. */ -#define USB_ERR_PARAM 0x12 -/** Functionality is not supported (e.g., initialize endpoint without cache to be control). */ -#define USB_ERR_FUNC 0x13 -/** Re-initialize, re-enable ... */ -#define USB_ERR_REDO 0x14 -/** Not enough resource (memory, endpoints ...). */ -#define USB_ERR_ALLOC_FAIL 0x15 -/*@}*/ - -/** USB speed. */ -enum usb_speed { - /** USB Low Speed. */ - USB_SPEED_LS, - /** USB Full Speed. */ - USB_SPEED_FS, - /** USB High Speed. */ - USB_SPEED_HS, - /** USB Super Speed. */ - USB_SPEED_SS -}; - -/** USB transaction type. */ -enum usb_trans_type { - /** USB SETUP transaction. */ - USB_TRANS_SETUP, - /** USB IN transaction. */ - USB_TRANS_IN, - /** USB OUT transaction. */ - USB_TRANS_OUT -}; - -/** USB events that generates the device callbacks. */ -enum usb_event { - /** USB VBus changed, with parameter as present/not present. */ - USB_EV_VBUS, - /** USB RESET detected on bus. */ - USB_EV_RESET, - /** USB wakeup. */ - USB_EV_WAKEUP, - /** USB LPM suspend, with parameter as \ref usb_lpm_attributes. */ - USB_EV_LPM_SUSPEND, - /** USB suspend. */ - USB_EV_SUSPEND, - /** USB error, with parameter as error code. */ - USB_EV_ERROR, - /** Number of USB event types. */ - USB_EV_N -}; - -/** Control action for USB device endpoint stall. */ -enum usb_ep_stall_ctrl { - /** Clear stall of the endpoint. */ - USB_EP_STALL_CLR, - /** Stall the endpoint. */ - USB_EP_STALL_SET, - /** Return the stall status. */ - USB_EP_STALL_GET -}; - -/** Control action for USB device endpoint halt. */ -enum usb_ep_halt_ctrl { - /** Clear halt of the endpoint. */ - USB_EP_HALT_CLR = USB_EP_STALL_CLR, - /** Stall the endpoint. */ - USB_EP_HALT_SET = USB_EP_STALL_SET, - /** Return the halt status. */ - USB_EP_HALT_GET = USB_EP_STALL_GET -}; - -/** USB transactions status codes. */ -enum usb_trans_code { - /** TX or RX has been done without error. */ - USB_TRANS_DONE, - /** The endpoint is stalled. */ - USB_TRANS_STALL, - /** The endpoint transactions are aborted (cancel, control setup/status). */ - USB_TRANS_ABORT, - /** The endpoint transactions are aborted by reset/disable. */ - USB_TRANS_RESET, - /** Error is reported on the endpoint. */ - USB_TRANS_ERROR -}; - -/** Transfer status codes. */ -enum usb_xfer_code { - /** Transfer is done without error, for ctrl it means status packet done. */ - USB_XFER_DONE, - /** For control transfer only, data stage is done without error. */ - USB_XFER_DATA, - /** Endpoint stall is set. */ - USB_XFER_HALT, - /** Endpoint stall is cleared. */ - USB_XFER_UNHALT, - /** Transfer is aborted. */ - USB_XFER_ABORT, - /** Transfer is aborted because endpoint reset/disable. */ - USB_XFER_RESET, - /** There was an error. */ - USB_XFER_ERROR -}; - -/** USB endpoint errors. */ -enum usb_ep_error { - /** No error. */ - USB_EP_NO_ERROR, - /** CRC error. */ - USB_EP_ERR_CRC, - /** Endpoint transfer overflow. */ - USB_EP_ERR_OVERFLOW, - /** Other endpoint errors. */ - USB_EP_ERR_GENERAL -}; - -/** Endpoint transfer state. */ -enum usb_ep_state { - /** Endpoint is disabled. */ - USB_EP_S_DISABLED, - /** Endpoint is not busy. */ - USB_EP_S_IDLE, - /** Control transfer only, endpoint is transferring setup packet. */ - USB_EP_S_X_SETUP, - /** Endpoint is transferring data. */ - USB_EP_S_X_DATA, - /** Control transfer only, endpoint is in status stage. */ - USB_EP_S_X_STATUS, - /** Endpoint is halted. */ - USB_EP_S_HALTED, - /** Endpoint error. */ - USB_EP_S_ERROR -}; - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_USB_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usb_device.h b/atmel-samd/asf4/samd21/hal/include/hpl_usb_device.h deleted file mode 100644 index 640833f45..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_usb_device.h +++ /dev/null @@ -1,387 +0,0 @@ -/** - * \file - * - * \brief SAM USB HPL - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USB_DEVICE_H_INCLUDED -#define _HPL_USB_DEVICE_H_INCLUDED - -#include -#include "hpl_usb_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** USB Device callback type. */ -enum usb_d_cb_type { - /** USB device SOF callback. */ - USB_D_CB_SOF, - /** USB device events callbacks. */ - USB_D_CB_EVENT, - /** Number of types of USB device callback types. */ - USB_D_CB_N -}; - -/** USB Device endpoint callback type. */ -enum usb_d_ep_cb_type { - /** USB device endpoint setup callback. */ - USB_D_EP_CB_SETUP, - /** USB device endpoint more data callback. */ - USB_D_EP_CB_MORE, - /** USB device endpoint transaction done or error callback. */ - USB_D_EP_CB_XFER, - /** Number of types of USB device endpoint callback types. */ - USB_D_EP_CB_N -}; - -/** Control action for USB device LPM handshake. */ -enum usb_d_lpm_ctrl { - /** No LPM handshake, not supported. */ - USB_D_LPM_DISABLE, - /** ACK the LPM transaction. */ - USB_D_LPM_ACK, - /** NYET the LPM transaction. */ - USB_D_LPM_NYET -}; - -/** - * USB device transfer descriptor. - */ -struct usb_d_transfer { - /** Pointer to data buffer to transfer. - * Note that it's recommended that the buffer is 32-bit aligned since - * some of USB peripheral require this. - */ - uint8_t *buf; - /** Transfer size, in number of bytes. - * Note that it's recommended that the buffer size is 32-bit aligned - * (modeled by 4) since some of USB peripheral require this. - */ - uint32_t size; - /** Endpoint address. */ - uint8_t ep; - /** Append ZLP for IN transfer, wait ZLP for OUT transfer. */ - uint8_t zlp; -}; - -/** USB device transactions status structure. */ -struct usb_d_trans_status { - /** Total data size. */ - uint32_t size; - /** Total transfered data count. */ - uint32_t count; - /** Endpoint address. */ - uint8_t ep; - /** Endpoint type - CTRL/ISO/INT/BULK. */ - uint8_t xtype : 2; - /** Transactions state, busy or not. */ - uint8_t busy : 1; - /** Transactions state, setup received or not. */ - uint8_t setup : 1; - /** Transactions state, stall or not. */ - uint8_t stall : 1; - /** Transactions direction. */ - uint8_t dir : 1; -}; - -/** Prototype function for callback that is invoked on USB device SOF. */ -typedef void (*_usb_d_dev_sof_cb_t)(void); - -/** Prototype function for callback that is invoked on USB device events. */ -typedef void (*_usb_d_dev_event_cb_t)(const enum usb_event, const uint32_t param); - -/** HPL USB device callbacks. */ -struct _usb_d_dev_callbacks { - /** Callback that is invoked on SOF. */ - _usb_d_dev_sof_cb_t sof; - /** Callback that is invoked on USB RESET/WAKEUP/RESUME/SUSPEND. */ - _usb_d_dev_event_cb_t event; -}; - -/** USB device endpoint callbacks. */ -enum usb_d_dev_ep_cb_type { - /** Setup packet is received. */ - USB_D_DEV_EP_CB_SETUP, - /** Try to require more data. */ - USB_D_DEV_EP_CB_MORE, - /** Transaction done OK/ERROR. */ - USB_D_DEV_EP_CB_DONE, - /** Number of device endpoint callbacks. */ - USB_D_DEV_EP_CB_N -}; - -/** - * Callback that is invoked when control SETUP packet has bee received. - * \ref _usb_d_dev_ep_read_req() must be invoked to read setup data, and allow - * IN/OUT transactions on control endpoint. - */ -typedef void (*_usb_d_dev_ep_cb_setup_t)(const uint8_t ep); - -/** Callback that is invoked when buffer is done, but last packet is full size - * packet without ZLP. Return \c true if more data has been requested. */ -typedef bool (*_usb_d_dev_ep_cb_more_t)(const uint8_t ep, const uint32_t transfered); - -/** Callback that is invoked when all data is finished, including background - * transfer, or error happens. */ -typedef void (*_usb_d_dev_ep_cb_done_t)(const uint8_t ep, const int32_t code, const uint32_t transfered); - -/** Callbacks for HPL USB device endpoint. */ -struct _usb_d_dev_ep_callbacks { - /** Callback that is invoked when SETUP packet is received. - * \ref _usb_d_dev_ep_read_req() must be invoked to read setup data, and - * allow IN/OUT transactions on control endpoint. - */ - _usb_d_dev_ep_cb_setup_t setup; - /** Callback that is invoked to check if buffer is NULL and more data is - * required. - * It's called when last packet is full size packet, without - * auto ZLP enabled. - * It could be called when background transfer is still in progress. - */ - _usb_d_dev_ep_cb_more_t more; - /** Callback that is invoked when transaction is done, including background - * transfer, or error occurs. - */ - _usb_d_dev_ep_cb_done_t done; -}; - -/** - * \brief Initialize the USB device instance - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_init(void); - -/** - * \brief Deinitialize the USB device instance - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -void _usb_d_dev_deinit(void); - -/** - * \brief Register callback to handle USB device events - * \param[in] type Callback type. See \ref usb_d_cb_type. - * \param[in] func Pointer to callback function. - * Refer to \ref _usb_d_dev_callbacks for the prototypes. - */ -void _usb_d_dev_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func); - -/** - * \brief Register callback to handle USB device endpoint events - * \param[in] type Callback type. See \ref usb_d_dev_ep_cb_type. - * \param[in] func Pointer to callback function. - * Refer to \ref _usb_d_dev_ep_callbacks for the prototypes. - */ -void _usb_d_dev_register_ep_callback(const enum usb_d_dev_ep_cb_type type, const FUNC_PTR func); - -/** - * \brief Enable the USB device - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_enable(void); - -/** - * \brief Disable the USB device - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_disable(void); - -/** - * \brief Attach the USB device - */ -void _usb_d_dev_attach(void); - -/** - * \brief Detach the USB device - */ -void _usb_d_dev_detach(void); - -/** - * \brief Send the USB device remote wakeup to host - */ -void _usb_d_dev_send_remotewakeup(void); - -/** - * \brief Get the USB device working speed - * \return USB speed. See \ref usb_speed. - */ -enum usb_speed _usb_d_dev_get_speed(void); - -/** - * \brief Set the USB device address - * \param[in] addr Address to be used. - */ -void _usb_d_dev_set_address(const uint8_t addr); - -/** - * \brief Get the USB device address - * \return Address that is used. - */ -uint8_t _usb_d_dev_get_address(void); - -/** - * \brief Get the USB device frame number - * \return The frame number. - */ -uint16_t _usb_d_dev_get_frame_n(void); - -/** - * \brief Get the USB device micro frame number - * \return The micro frame number inside one frame (0~7). - */ -uint8_t _usb_d_dev_get_uframe_n(void); - -/** - * \brief Initialize and enable the USB device default endpoint 0 - * \param[in] max_pkt_siz Max endpoint size. - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_ep0_init(const uint8_t max_pkt_siz); - -/** - * \brief Initialize and enable the USB device endpoint - * \param[in] ep Endpoint address, - * see endpoint descriptor details in USB spec. - * \param[in] attr Endpoint attributes, - * see endpoint descriptor details in USB spec. - * \param[in] max_pkt_siz Endpoint size, - * see endpoint descriptor details in USB spec. - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_ep_init(const uint8_t ep, const uint8_t attr, uint16_t max_pkt_siz); - -/** - * \brief Disable and deinitialize the USB device endpoint - - * \param[in] ep The endpoint to deinitialize. - */ -void _usb_d_dev_ep_deinit(const uint8_t ep); - -/** - * \brief Enable the endpoint - * \param[in] ep The endpoint to enable. - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_ep_enable(const uint8_t ep); - -/** - * \brief Disable the endpoint - * \param[in] ep The endpoint to disable. - */ -void _usb_d_dev_ep_disable(const uint8_t ep); - -/** - * \brief Set/Clear/Get USB device endpoint stall status - * \param[in] ep Endpoint address. - * \param[in] ctrl Operation selector. See \ref usb_ep_stall_ctrl. - * \return Operation result or stall status. - * \retval 0 Success or not stall. - * \retval 1 Endpoint is stalled. - * \retval -1 error. - */ -int32_t _usb_d_dev_ep_stall(const uint8_t ep, const enum usb_ep_stall_ctrl ctrl); - -/** - * \brief Read setup request data from specific endpoint - * \param[in] ep Endpoint address. - * \param[out] req_buf Pointer to buffer to locate the setup packet. - * \return Number of bytes or error code. - * \retval <0 error code. - * \retval 0 No setup packet ready for read. - * \retval >0 Size of bytes read, and ready to start IN/OUT. Note that if - * this number is over 8, only first 8 bytes will be copied. - */ -int32_t _usb_d_dev_ep_read_req(const uint8_t ep, uint8_t *req_buf); - -/** - * \brief Start USB device transfer - * - * On different USB peripheral hardware the transaction buffer address and size - * may have different constraints. E.g., some hardware may require input address - * 32-bit aligned, and input size 32-bit aligned. Refer to the corresponding - * hardware usage reference documents. - * The constraints are checked in implementation, with error code returned. - * - * \param[in] trans Pointer to the transaction description. - * \return Operation result status. - * \retval 1 Busy. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_ep_trans(const struct usb_d_transfer *trans); - -/** - * \brief Abort pending USB device transaction on specific endpoint - * \param[in] ep Endpoint address to abort. - */ -void _usb_d_dev_ep_abort(const uint8_t ep); - -/** - * \brief Retrieve endpoint status. - * \param[in] ep Endpoint address. - * \param[out] stat Pointer to buffer to fill status description. - * \return Status. - * \retval 2 Packet writing. - * \retval 1 Busy. - * \retval 0 Ready. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_ep_get_status(const uint8_t ep, struct usb_d_trans_status *stat); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_USB_DEVICE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_usb_host.h b/atmel-samd/asf4/samd21/hal/include/hpl_usb_host.h deleted file mode 100644 index ee48ecc3a..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_usb_host.h +++ /dev/null @@ -1,628 +0,0 @@ -/** - * \file - * - * \brief SAM USB host HPL - * - * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USB_HOST_H_INCLUDED -#define _HPL_USB_HOST_H_INCLUDED - -#include -#include -#include "hpl_usb_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** Driver version */ -#define USB_H_VERSION 0x00000001 - -/** - * @brief USB HCD callback types - */ -enum usb_h_cb_type { - /** SOF generated */ - USB_H_CB_SOF, - /** Root Hub change detected */ - USB_H_CB_ROOTHUB_CHANGE, - /** Number of USB HCD callback types */ - USB_H_CB_N -}; - -/** - * @brief USB HCD resource strategy - */ -enum usb_h_rsc_strategy { - /** Normal resource allocation, e.g., - * 1 bank for interrupt endpoint, - * 2 bank for bulk endpoint and normal iso endpoint, - * 3 bank for iso high bandwidth endpoint. - */ - USB_H_RSC_NORMAL = false, - /** Minimal resource allocation, e.g., only 1 bank for bulk endpoints */ - USB_H_RSC_MINIMAL = true -}; - -/** - * @brief USB HCD pipe states - */ -enum usb_h_pipe_state { - /** Pipe is free to allocate */ - USB_H_PIPE_S_FREE = 0x00, - /** Pipe is in configuration */ - USB_H_PIPE_S_CFG = 0x01, - /** Pipe is allocated and idle */ - USB_H_PIPE_S_IDLE = 0x02, - /** Pipe in control setup stage */ - USB_H_PIPE_S_SETUP = 0x03, - /** Pipe in data IN stage */ - USB_H_PIPE_S_DATI = 0x05, - /** Pipe in data OUT stage */ - USB_H_PIPE_S_DATO = 0x06, - /** Pipe in data IN ZLP stage */ - USB_H_PIPE_S_ZLPI = 0x07, - /** Pipe in data OUT ZLP stage */ - USB_H_PIPE_S_ZLPO = 0x08, - /** Pipe in control status IN stage */ - USB_H_PIPE_S_STATI = 0x09, - /** Pipe in control status OUT stage */ - USB_H_PIPE_S_STATO = 0x0A, - /** Taken by physical pipe (in process) */ - USB_H_PIPE_S_TAKEN = 0x10 -}; - -/** - * @brief USB HCD status code - */ -enum usb_h_status { - /** OK */ - USB_H_OK = ERR_NONE, - /** Busy */ - USB_H_BUSY = ERR_BUSY, - /** Denied */ - USB_H_DENIED = ERR_DENIED, - /** Timeout */ - USB_H_TIMEOUT = ERR_TIMEOUT, - /** Abort */ - USB_H_ABORT = ERR_ABORTED, - /** Stall protocol */ - USB_H_STALL = ERR_PROTOCOL, - /** Transfer reset by pipe re-configure */ - USB_H_RESET = ERR_REQ_FLUSHED, - /** Argument error */ - USB_H_ERR_ARG = ERR_INVALID_ARG, - /** Operation not supported */ - USB_H_ERR_UNSP_OP = ERR_UNSUPPORTED_OP, - /** No resource */ - USB_H_ERR_NO_RSC = ERR_NO_RESOURCE, - /** Not initialized */ - USB_H_ERR_NOT_INIT = ERR_NOT_INITIALIZED, - /** Some general error */ - USB_H_ERR = ERR_IO -}; - -/** Forward declare for pipe structure */ -struct usb_h_pipe; - -/** Forward declare for driver descriptor structure */ -struct usb_h_desc; - -/** - * \brief Prototyping USB HCD callback of SOF - */ -typedef void (*usb_h_cb_sof_t)(struct usb_h_desc *drv); - -/** - * \brief Prototyping USB HCD callback of root hub changing. - * According to the bitmap size, max port number is 31. - */ -typedef void (*usb_h_cb_roothub_t)(struct usb_h_desc *drv, uint8_t port, uint8_t ftr); - -/** - * Prototyping USB HCD callback of pipe transfer done. - * For control pipe, it's forced to call even if there is no transfer - * in progress, since the pipe size could be changed at run time. - */ -typedef void (*usb_h_pipe_cb_xfer_t)(struct usb_h_pipe *pipe); - -/** Access to max packet size of a pipe */ -#define usb_h_pipe_max_pkt_size(p) (p->max_pkt_size) - -/** Access to device address of a pipe */ -#define usb_h_pipe_dev_addr(p) (p->dev) - -/** Access to endpoint address of a pipe */ -#define usb_h_pipe_ep_addr(p) (p->ep) - -/** Access to state of a pipe */ -#define usb_h_pipe_state(p) (p->x.general.state) - -/** Access to status of a pipe */ -#define usb_h_pipe_status(p) (p->x.general.status) - -/** - * @brief USB Host Controller device structure - */ -struct usb_h_desc { - /** Pointer to hardware base */ - void *hw; - /** Pointer to private data for Host Controller driver */ - void *prvt; - /** Interrupt handling descriptor */ - struct _irq_descriptor irq; - /** Callback of SOF */ - usb_h_cb_sof_t sof_cb; - /** Callback of root hub change */ - usb_h_cb_roothub_t rh_cb; -#if CONF_USB_H_INST_OWNER_SP - /** Extension for the driver owner (upper layer user) */ - void *owner; -#endif -}; - -/** - * @brief Transfer descriptor for control transfer - * - * Timing in USB 2.0 spec.: - * - 9.2.6.1 : USB sets an upper limit of 5 seconds as the upper limit for any - * command to be processed. - * - 9.2.6.3 : if a device receives a SetAddress() request, the device must be - * able to complete processing of the request and be able to - * successfully complete the Status stage of the request within - * 50 ms. - * After successful completion of the Status stage, the device is - * allowed a SetAddress() recovery interval of 2 ms. At the end of - * this interval, the device must be able to accept Setup packets - * addressed to the new address. - * - 9.2.6.4 : For standard device requests that require no Data stage, a device - * must be able to complete the request and be able to successfully - * complete the Status stage of the request within 50 ms of receipt - * of the request. This limitation applies to requests to the - * device, interface, or endpoint. - * For standard device requests that require data stage transfer to - * the host, the device must be able to return the first data packet - * to the host within 500 ms of receipt of the request. For - * subsequent data packets, if any, the device must be able to - * return them within 500 ms of successful completion of the - * transmission of the previous packet. The device must then be - * able to successfully complete the status stage within 50 ms after - * returning the last data packet. - * For standard device requests that require a data stage transfer - * to the device, the 5-second limit applies. - * - 9.2.6.5 : Unless specifically exempted in the class document, all - * class-specific requests must meet the timing limitations for - * standard device requests. - * - * Conclusion: - * 1. Whole request with data: 5 seconds - * 2. Whole request without data: 50 ms - * 3. Data packets: 500 ms - */ -struct usb_h_ctrl_xfer { - /** Pointer to transfer data */ - uint8_t *data; - /** Pointer to setup packet */ - uint8_t *setup; - /** Expected transfer size */ - uint16_t size; - /** Transfer count */ - uint16_t count; - /** Timeout for request, -1 if disable timeout */ - int16_t req_timeout; - /** Timeout between packets - * (500ms for data and 50ms for status), -1 if disabled */ - int16_t pkt_timeout; - /** Packet size during transfer (<= allocate max packet size) */ - uint16_t pkt_size; - - /** Transfer state */ - uint8_t state; - /** Last transfer status */ - int8_t status; -}; - -/** - * @brief Transfer descriptor for bulk / interrupt / iso transfer - */ -struct usb_h_bulk_int_iso_xfer { - /** Expected transfer size */ - uint32_t size; - /** Transfer count */ - uint32_t count; - /** Pointer to transfer data */ - uint8_t *data; - /** Reserved */ - uint16_t reserved[3]; - - /** Transfer state */ - uint8_t state; - /** Last transfer status */ - int8_t status; -}; - -/** - * @brief Transfer descriptor for periodic high bandwidth transfer - */ -struct usb_h_high_bw_xfer { - /** Expected transfer size */ - uint32_t size; - /** Transfer count */ - uint32_t count; - /** Pointer to transfer data */ - uint8_t *data; - /** Micro frame packet sizes */ - uint16_t pkt_size[3]; - - /** Transfer state */ - uint8_t state; - /** Last transfer status */ - int8_t status; -}; - -/** - * @brief General transfer descriptor - */ -struct usb_h_xfer { - /** Reserved for different transfer */ - union { - uint16_t u16[9]; - uint8_t u8[18]; - } reserved; - /** Transfer state */ - uint8_t state; - /** Last transfer status */ - int8_t status; -}; - -/** - * @brief USB Host Controller Driver Pipe structure - */ -struct usb_h_pipe { - /** Pointer to the USB Host Controller Driver */ - struct usb_h_desc *hcd; - /** Pointer to the callback for transfer done */ - usb_h_pipe_cb_xfer_t done; -#if CONF_USB_H_INST_OWNER_SP - /** Pointer to the pipe owner */ - void *owner; -#endif - - /** Endpoint max packet size (bits 10..0) */ - uint16_t max_pkt_size; - /** Device address */ - uint8_t dev; - /** Endpoint address */ - uint8_t ep; - - /** Endpoint interval */ - uint8_t interval; - /** Endpoint type: Control, Isochronous, Bulk or Interrupt */ - uint8_t type; - /** Current toggle (driver dependent) */ - uint8_t toggle; - /** Endpoint number of banks (HW dependent) */ - uint8_t bank : 2; - /** Transfer speed (HW dependent) */ - uint8_t speed : 2; - /** High bandwidth periodic out */ - uint8_t high_bw_out : 1; - /** Uses DMA (on transfer) */ - uint8_t dma : 1; - /** Transfer ZLP support */ - uint8_t zlp : 1; - /** Transfer periodic */ - uint8_t periodic_start : 1; - - /** Transfer status */ - union { - /** General transfer info */ - struct usb_h_xfer general; - /** Control transfer status */ - struct usb_h_ctrl_xfer ctrl; - /** Bulk interrupt iso transfer status */ - struct usb_h_bulk_int_iso_xfer bii; - /** Periodic high bandwidth transfer status */ - struct usb_h_high_bw_xfer hbw; - } x; -}; - -/** - * @brief USB HCD Initialization - * - * @param drv Pointer to the HCD driver instance - * @param[in] hw Pointer to hardware base - * @param[in] prvt The private driver data (implement specific) - * - * @return Operation result status - * @retval ERR_DENIED Hardware has been enabled - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_init(struct usb_h_desc *drv, void *hw, void *prvt); - -/** - * @brief USB HCD de-initialization - * - * @param drv The driver - */ -void _usb_h_deinit(struct usb_h_desc *drv); - -/** - * @brief USB HCD enable - * - * @param drv The driver - */ -void _usb_h_enable(struct usb_h_desc *drv); - -/** - * @brief USB HCD disable - * - * @param drv The driver - */ -void _usb_h_disable(struct usb_h_desc *drv); - -/** - * @brief Register callbacks for USB HCD - * - * @param drv The driver - * @param[in] type The callback type - * @param[in] cb The callback function entry - * - * @return Operation result status - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_register_callback(struct usb_h_desc *drv, enum usb_h_cb_type type, FUNC_PTR cb); - -/** - * @brief Return current frame number - * - * @param drv The driver - * - * @return current frame number - */ -uint16_t _usb_h_get_frame_n(struct usb_h_desc *drv); - -/** - * @brief Return current micro frame number - * - * @param drv The driver - * - * @return current micro frame number - */ -uint8_t _usb_h_get_microframe_n(struct usb_h_desc *drv); - -/** - * @brief Suspend the USB bus - * - * @param drv The driver - */ -void _usb_h_suspend(struct usb_h_desc *drv); - -/** - * @brief Resume the USB bus - * - * @param drv The driver - */ -void _usb_h_resume(struct usb_h_desc *drv); - -/* Root hub related APIs */ - -/** - * \brief Reset the root hub port - * - * \param[in,out] drv Pointer to the USB HCD driver - * \param[in] port Root hub port, ignored if there is only one port - */ -void _usb_h_rh_reset(struct usb_h_desc *drv, uint8_t port); - -/** - * \brief Suspend the root hub port - * - * \param[in,out] drv Pointer to the USB HCD driver - * \param[in] port Root hub port, ignored if there is only one port - */ -void _usb_h_rh_suspend(struct usb_h_desc *drv, uint8_t port); - -/** - * \brief Resume the root hub port - * - * \param[in,out] drv Pointer to the USB HCD driver - * \param[in] port Root hub port, ignored if there is only one port - */ -void _usb_h_rh_resume(struct usb_h_desc *drv, uint8_t port); - -/** - * \brief Root hub or port feature status check - * - * Check USB Spec. for hub status and feature selectors. - * - * \param[in] drv Pointer to the USB HCD driver - * \param[in] port Set to 0 to get hub status, otherwise to get port status - * \param[in] ftr Hub feature/status selector - * (0: connection, 2: suspend, 4: reset, 9: LS, 10: HS) - * - * \return \c true if the status bit is 1 - */ -bool _usb_h_rh_check_status(struct usb_h_desc *drv, uint8_t port, uint8_t ftr); - -/* Pipe transfer functions */ - -/** - * @brief Allocate a pipe for USB host communication - * - * @param drv The USB HCD driver - * @param[in] dev The device address - * @param[in] ep The endpoint address - * @param[in] max_pkt_size The endpoint maximum packet size - * @param[in] attr The endpoint attribute - * @param[in] interval The endpoint interval - * (bInterval of USB Endpoint Descriptor) - * @param[in] speed The transfer speed of the endpoint - * @param[in] minimum_rsc Minimum the resource usage, \sa usb_h_rsc_strategy - * - * @return Pointer to allocated pipe structure instance - * @retval NULL allocation fail - */ -struct usb_h_pipe *_usb_h_pipe_allocate(struct usb_h_desc *drv, uint8_t dev, uint8_t ep, uint16_t max_pkt_size, - uint8_t attr, uint8_t interval, uint8_t speed, bool minimum_rsc); - -/** - * @brief Free an allocated pipe - * - * @param pipe The pipe - * - * @return Operation result status - * @retval ERR_BUSY Pipe is busy, use \ref _usb_h_pipe_abort to abort - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_pipe_free(struct usb_h_pipe *pipe); - -/** - * @brief Modify parameters of an allocated control pipe - * - * @param pipe The pipe - * @param[in] dev The device address - * @param[in] ep The endpoint address - * @param[in] max_pkt_size The maximum packet size, must be equal or - * less than allocated size - * @param[in] speed The working speed - * - * @return Operation result status - * @retval ERR_NOT_INITIALIZED Pipe is not allocated - * @retval ERR_BUSY Pipe is busy transferring - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_UNSUPPORTED_OP Pipe is not control pipe - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_pipe_set_control_param(struct usb_h_pipe *pipe, uint8_t dev, uint8_t ep, uint16_t max_pkt_size, - uint8_t speed); - -/** - * @brief Register transfer callback on a pipe - * - * @param pipe The pipe - * @param[in] cb Transfer callback function - * - * @return Operation result status - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_pipe_register_callback(struct usb_h_pipe *pipe, usb_h_pipe_cb_xfer_t cb); - -/** - * @brief Issue a control transfer (request) on a pipe - * - * \note When there is data stage, timeout between data packets is 500ms, the - * timeout between last data packet and the status packet is 50ms. - * - * @param pipe The pipe - * @param[in] setup Pointer to the setup packet - * @param[in,out] data Pointer to the data buffer - * @param[in] length The data length - * @param[in] timeout Timeout for whole request in ms - * - * @return Operation result status - * @retval ERR_NOT_INITIALIZED Pipe is not allocated - * @retval ERR_BUSY Pipe is busy transferring - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_UNSUPPORTED_OP Pipe is not control pipe - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_control_xfer(struct usb_h_pipe *pipe, uint8_t *setup, uint8_t *data, uint16_t length, int16_t timeout); - -/** - * @brief Issue a bulk / interrupt / iso transfer on a pipe - * - * @param pipe The pipe - * @param[in,out] data Pointer to the data buffer - * @param[in] length The data length - * @param[in] auto_zlp Auto append ZLP for OUT - * - * @return Operation result status - * @retval ERR_NOT_INITIALIZED Pipe is not allocated - * @retval ERR_BUSY Pipe is busy transferring - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_UNSUPPORTED_OP Pipe is control pipe - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_bulk_int_iso_xfer(struct usb_h_pipe *pipe, uint8_t *data, uint32_t length, bool auto_zlp); - -/** - * @brief Issue a periodic high bandwidth output on a pipe - * - * @param pipe The pipe - * @param[in,out] data Pointer to the data buffer - * @param[in] length The data length - * @param[in] trans_pkt_size The transaction packet sizes in a micro frame, - * 0 to use endpoint max packet size - * - * @return Operation result status - * @retval ERR_NOT_INITIALIZED Pipe is not allocated - * @retval ERR_BUSY Pipe is busy transferring - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_UNSUPPORTED_OP Pipe is not high bandwidth periodic pipe, or - * DMA feature not enabled, or - * high bandwidth not enabled - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_high_bw_out(struct usb_h_pipe *pipe, uint8_t *data, uint32_t length, uint16_t trans_pkt_size[3]); - -/** - * @brief Check if pipe is busy transferring - * - * @param pipe The pipe - * - * @return \c true if pipe is busy - */ -bool _usb_h_pipe_is_busy(struct usb_h_pipe *pipe); - -/** - * @brief Abort pending transfer on a pipe - * - * @param pipe The pipe - */ -void _usb_h_pipe_abort(struct usb_h_pipe *pipe); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_USB_HOST_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/include/hpl_user_area.h b/atmel-samd/asf4/samd21/hal/include/hpl_user_area.h deleted file mode 100644 index b5c419bff..000000000 --- a/atmel-samd/asf4/samd21/hal/include/hpl_user_area.h +++ /dev/null @@ -1,133 +0,0 @@ -/** - * \file - * - * \brief Special user data area access - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USER_DATA_H_INCLUDED -#define _HPL_USER_DATA_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Read data from user data area - * - * The user data area could be the area that stores user data that is not erased - * with the flash contents, e.g., - * - NVM Software Calibration Area of SAM D/L/C family - * - User Signature of SAM E/S/V 70 - * - * \param[in] base The base address of the user area - * \param[in] offset The byte offset of the data to be read inside the area - * \param[out] buf Pointer to buffer to place the read data - * \param[in] size Size of data in number of bytes - * - * \return Operation status or bytes read. - * \retval ERR_NONE Data read successfully - * \retval ERR_UNSUPPORTED_OP base address not in any supported user area - * \retval ERR_BAD_ADDRESS offset not in right area - * \retval ERR_INVALID_ARG offset and size exceeds the right area - */ -int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, const uint32_t size); - -/** - * \brief Read no more than 32 bits data from user data area - * - * When reading bits, the bitfield can cross 32-bis boundaries. - * - * \param[in] base The base address of the user area - * \param[in] bit_offset Offset in number of bits - * \param[in] n_bits Number of bits to read - * \return data read, assert if anything wrong (address not in user area - * offset, size error, etc.). - */ -uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits); - -/** - * \brief Write data to user data area - * - * The user data area could be the area that stores user data that is not erased - * with the flash contents, e.g., - * - NVM Software Calibration Area of SAM D/L/C family - * - User Signature of SAM E/S/V 70 - * - * When assigned offset and size exceeds the data area, error is reported. - * - * \param[out] base The base address of the user area - * \param[in] offset The offset of the data to be written inside the area - * \param[in] buf Pointer to buffer to place the written data - * \param[in] size Size of data in number of bytes - * - * \return Operation status or bytes writting. - * \retval ERR_NONE Data written successfully - * \retval ERR_UNSUPPORTED_OP base address not in any supported user area - * \retval ERR_DENIED Security bit is set - * \retval ERR_BAD_ADDRESS offset not in right area - * \retval ERR_INVALID_ARG offset and size exceeds the right area - */ -int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size); - -/** - * \brief Write no more than 32 bits data to user data area - * - * When writting bits, the bitfield can cross 32-bis boundaries. - * - * \param[out] base The base address of the user area - * \param[in] bit_offset Offset in number of bits - * \param[in] bits The data content - * \param[in] n_bits Number of bits to write - * \return Operation result - * \retval ERR_NONE Data written successfully - * \retval ERR_UNSUPPORTED_OP base address not in any supported user area - * \retval ERR_DENIED Security bit is set - * \retval ERR_BAD_ADDRESS offset not in right area - * \retval ERR_INVALID_ARG offset and size exceeds the right area - */ -int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_USER_DATA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/src/hal_adc_sync.c b/atmel-samd/asf4/samd21/hal/src/hal_adc_sync.c deleted file mode 100644 index 9c7c3ab52..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_adc_sync.c +++ /dev/null @@ -1,254 +0,0 @@ -/** - * \file - * - * \brief ADC functionality implementation. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * \brief Indicates HAL being compiled. Must be defined before including. - */ -#define _COMPILING_HAL - -#include "hal_adc_sync.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Maximum amount of ADC interface instances - */ -#define MAX_ADC_AMOUNT ADC_INST_NUM - -/** - * \brief Initialize ADC - */ -int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func) -{ - ASSERT(descr && hw); - - return _adc_sync_init(&descr->device, hw); -} - -/** - * \brief Deinitialize ADC - */ -int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr) -{ - ASSERT(descr); - _adc_sync_deinit(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Enable ADC - */ -int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel) -{ - ASSERT(descr); - _adc_sync_enable_channel(&descr->device, channel); - - return ERR_NONE; -} - -/** - * \brief Disable ADC - */ -int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel) -{ - ASSERT(descr); - _adc_sync_disable_channel(&descr->device, channel); - return ERR_NONE; -} - -/* - * \brief Read data from ADC - */ -int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, - const uint16_t length) -{ - uint8_t data_size; - uint16_t offset = 0; - - ASSERT(descr && buffer && length); - data_size = _adc_sync_get_data_size(&descr->device); - ASSERT(!(length % data_size)); - - do { - uint16_t result; - _adc_sync_convert(&descr->device); - - while (!_adc_sync_is_channel_conversion_done(&descr->device, channel)) - ; - - result = _adc_sync_read_channel_data(&descr->device, channel); - buffer[offset] = result; - if (1 < data_size) { - buffer[offset + 1] = result >> 8; - } - offset += data_size; - } while (offset < length); - - return offset; -} - -/** - * \brief Set ADC reference source - */ -int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference) -{ - ASSERT(descr); - _adc_sync_set_reference_source(&descr->device, reference); - - return ERR_NONE; -} - -/** - * \brief Set ADC resolution - */ -int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution) -{ - ASSERT(descr); - _adc_sync_set_resolution(&descr->device, resolution); - - return ERR_NONE; -} - -/** - * \brief Set ADC input source of a channel - */ -int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel) -{ - ASSERT(descr); - _adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel); - - return ERR_NONE; -} - -/** - * \brief Set ADC thresholds - */ -int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold) -{ - ASSERT(descr); - _adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold); - - return ERR_NONE; -} - -/** - * \brief Set ADC gain - */ -int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain) -{ - ASSERT(descr); - _adc_sync_set_channel_gain(&descr->device, channel, gain); - - return ERR_NONE; -} - -/** - * \brief Set ADC conversion mode - */ -int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode) -{ - ASSERT(descr); - _adc_sync_set_conversion_mode(&descr->device, mode); - - return ERR_NONE; -} - -/** - * \brief Set ADC differential mode - */ -int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel, - const enum adc_differential_mode mode) -{ - ASSERT(descr); - _adc_sync_set_channel_differential_mode(&descr->device, channel, mode); - - return ERR_NONE; -} - -/** - * \brief Set ADC window mode - */ -int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode) -{ - ASSERT(descr); - _adc_sync_set_window_mode(&descr->device, mode); - - return ERR_NONE; -} - -/** - * \brief Retrieve threshold state - */ -int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state) -{ - ASSERT(descr && state); - _adc_sync_get_threshold_state(&descr->device, state); - - return ERR_NONE; -} - -/** - * \brief Check if conversion is complete - */ -int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel) -{ - ASSERT(descr); - return _adc_sync_is_channel_conversion_done(&descr->device, channel); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t adc_sync_get_version(void) -{ - return DRIVER_VERSION; -} - -//@} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_atomic.c b/atmel-samd/asf4/samd21/hal/src/hal_atomic.c deleted file mode 100644 index 82a11e2bd..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_atomic.c +++ /dev/null @@ -1,76 +0,0 @@ -/** - * \file - * - * \brief Critical sections related functionality implementation. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_atomic.h" - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Disable interrupts, enter critical section - */ -void atomic_enter_critical(hal_atomic_t volatile *atomic) -{ - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); -} - -/** - * \brief Exit atomic section - */ -void atomic_leave_critical(hal_atomic_t volatile *atomic) -{ - __DMB(); - __set_PRIMASK(*atomic); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t atomic_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_dac_sync.c b/atmel-samd/asf4/samd21/hal/src/hal_dac_sync.c deleted file mode 100644 index a56e6aef7..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_dac_sync.c +++ /dev/null @@ -1,141 +0,0 @@ -/** - * \file - * - * \brief DAC functionality implementation. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_dac_sync.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Initialize the DAC HAL instance and hardware. - */ -int32_t dac_sync_init(struct dac_sync_descriptor *const descr, void *const hw) -{ - uint8_t i; - int32_t rc; - - ASSERT(descr && hw); - - rc = _dac_sync_init(&descr->device, hw); - if (rc) { - return rc; - } - - for (i = 0; i < CHANNEL_NUM; i++) { - descr->sel_ch[i].buffer = NULL; - descr->sel_ch[i].length = 0; - } - - return ERR_NONE; -} - -/** - * \brief Deinitialize the DAC HAL instance and hardware - */ -int32_t dac_sync_deinit(struct dac_sync_descriptor *const descr) -{ - ASSERT(descr); - - _dac_sync_deinit(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Enable DAC channel - */ -int32_t dac_sync_enable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch) -{ - ASSERT(descr && (ch < CHANNEL_NUM)); - - _dac_sync_enable_channel(&descr->device, ch); - - return ERR_NONE; -} - -/** - * \brief Disable DAC channel - */ -int32_t dac_sync_disable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch) -{ - ASSERT(descr && (ch < CHANNEL_NUM)); - - _dac_sync_disable_channel(&descr->device, ch); - - return ERR_NONE; -} - -/** - * \brief DAC convert digital data to analog output - */ -int32_t dac_sync_write(struct dac_sync_descriptor *descr, const uint8_t ch, uint16_t *buffer, uint32_t length) -{ - ASSERT(descr && (ch < CHANNEL_NUM) && buffer && length); - - /* check whether channel is enable */ - if (!_dac_sync_is_channel_enable(&descr->device, ch)) { - return ERR_NOT_READY; - } - - descr->sel_ch[ch].buffer = buffer; - descr->sel_ch[ch].length = length; - - while (descr->sel_ch[ch].length) { - _dac_sync_write_data(&descr->device, *(descr->sel_ch[ch].buffer), ch); - descr->sel_ch[ch].buffer++; - descr->sel_ch[ch].length--; - } - - return ERR_NONE; -} - -/** - * \brief Get DAC driver version - */ -uint32_t dac_sync_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_delay.c b/atmel-samd/asf4/samd21/hal/src/hal_delay.c deleted file mode 100644 index ce963db00..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_delay.c +++ /dev/null @@ -1,90 +0,0 @@ -/** - * \file - * - * \brief HAL delay related functionality implementation. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include "hal_delay.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief The pointer to a hardware instance used by the driver. - */ -static void *hardware; - -/** - * \brief Initialize Delay driver - */ -void delay_init(void *const hw) -{ - _delay_init(hardware = hw); -} - -/** - * \brief Perform delay in us - */ -void delay_us(const uint16_t us) -{ - _delay_cycles(hardware, _get_cycles_for_us(us)); -} - -/** - * \brief Perform delay in ms - */ -void delay_ms(const uint16_t ms) -{ - _delay_cycles(hardware, _get_cycles_for_ms(ms)); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t delay_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_flash.c b/atmel-samd/asf4/samd21/hal/src/hal_flash.c deleted file mode 100644 index 165d46d89..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_flash.c +++ /dev/null @@ -1,330 +0,0 @@ -/** - * \file - * - * \brief Flash functionality implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_flash.h" -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -static void flash_ready(struct _flash_device *device); -static void flash_error(struct _flash_device *device); - -static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr); - -/** - * \brief Initialize the FLASH HAL instance and hardware for callback mode. - */ -int32_t flash_init(struct flash_descriptor *flash, void *const hw) -{ - int32_t rc; - - ASSERT(flash && hw); - - rc = _flash_init(&flash->dev, hw); - if (rc) { - return rc; - } - - flash->dev.flash_cb.ready_cb = flash_ready; - flash->dev.flash_cb.error_cb = flash_error; - - return ERR_NONE; -} - -/** - * \brief Deinitialize the FLASH HAL instance. - */ -int32_t flash_deinit(struct flash_descriptor *flash) -{ - ASSERT(flash); - - _flash_deinit(&flash->dev); - - return ERR_NONE; -} - -/** - * \brief Reads a number of bytes to a page in the internal Flash - */ -int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length) -{ - ASSERT(flash && buffer && length); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - - /* Check if the address is valid */ - if ((src_addr > page_size * total_pages) || (src_addr + length > page_size * total_pages)) { - return ERR_BAD_ADDRESS; - } - - _flash_read(&flash->dev, src_addr, buffer, length); - - return ERR_NONE; -} - -/** - * \brief Updates several bytes to the internal Flash - */ -int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) -{ - ASSERT(flash && buffer && length); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - - /* Check if the address is valid */ - if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { - return ERR_BAD_ADDRESS; - } - - if (_flash_is_locked(&flash->dev, dst_addr)) { - return ERR_DENIED; - } - - _flash_write(&flash->dev, dst_addr, buffer, length); - - return ERR_NONE; -} - -/** - * \brief Appends a number of bytes to a page in the internal Flash - */ -int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length) -{ - ASSERT(flash && buffer && length); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - - /* Check if the address is valid */ - if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { - return ERR_BAD_ADDRESS; - } - - if (_flash_is_locked(&flash->dev, dst_addr)) { - return ERR_DENIED; - } - - _flash_append(&flash->dev, dst_addr, buffer, length); - - return ERR_NONE; -} - -/** - * \brief Execute erase in the internal flash - */ -int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) -{ - ASSERT(flash && page_nums); - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - int32_t rc; - - rc = flash_is_address_aligned(flash, dst_addr); - if (rc) { - return rc; - } - - if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { - return ERR_INVALID_ARG; - } - - _flash_erase(&flash->dev, dst_addr, page_nums); - - return ERR_NONE; -} - -/** - * \brief Register a function as FLASH transfer completion callback - */ -int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func) -{ - ASSERT(flash); - - switch (type) { - case FLASH_CB_READY: - flash->callbacks.cb_ready = func; - break; - - case FLASH_CB_ERROR: - flash->callbacks.cb_error = func; - break; - - default: - return ERR_INVALID_ARG; - } - - _flash_set_irq_state(&flash->dev, (enum _flash_cb_type)type, NULL != func); - - return ERR_NONE; -} - -/** - * \brief Execute lock in the internal flash - */ -int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) -{ - ASSERT(flash && page_nums); - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - int32_t rc; - - rc = flash_is_address_aligned(flash, dst_addr); - if (rc) { - return rc; - } - - if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { - return ERR_INVALID_ARG; - } - - return _flash_lock(&flash->dev, dst_addr, page_nums); -} - -/** - * \brief Execute unlock in the internal flash - */ -int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) -{ - ASSERT(flash && page_nums); - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - int32_t rc; - - rc = flash_is_address_aligned(flash, dst_addr); - if (rc) { - return rc; - } - - if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { - return ERR_INVALID_ARG; - } - - return _flash_unlock(&flash->dev, dst_addr, page_nums); -} - -/** - * \brief Get the flash page size. - */ -uint32_t flash_get_page_size(struct flash_descriptor *flash) -{ - ASSERT(flash); - return _flash_get_page_size(&flash->dev); -} - -/** - * \brief Get the numbers of flash page. - */ -uint32_t flash_get_total_pages(struct flash_descriptor *flash) -{ - ASSERT(flash); - return _flash_get_total_pages(&flash->dev); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t flash_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \internal check the address whether it is aligned - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] flash_addr address to be check in flash - * - * \return whether it is valid - * \retval 0 Valid. - * \retval -1 Error, invalid. - */ -static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr) -{ - ASSERT(flash); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - - /* Check if the read address not aligned to the start of a page */ - if (flash_addr & (page_size - 1)) { - return ERR_BAD_ADDRESS; - } - return ERR_NONE; -} - -/** - * \internal Ready for a new flash command - * - * \param[in] device The pointer to flash device structure - */ -static void flash_ready(struct _flash_device *device) -{ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wcast-align" - struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); - #pragma GCC diagnostic pop - if (descr->callbacks.cb_ready) { - descr->callbacks.cb_ready(descr); - } -} - -/** - * \internal Error occurs in flash command - * - * \param[in] device The pointer to flash device structure - */ -static void flash_error(struct _flash_device *device) -{ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wcast-align" - struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); - #pragma GCC diagnostic pop - if (descr->callbacks.cb_error) { - descr->callbacks.cb_error(descr); - } -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_gpio.c b/atmel-samd/asf4/samd21/hal/src/hal_gpio.c deleted file mode 100644 index 319726290..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_gpio.c +++ /dev/null @@ -1,54 +0,0 @@ -/** - * \file - * - * \brief Port - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_gpio.h" - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -uint32_t gpio_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_i2c_m_sync.c b/atmel-samd/asf4/samd21/hal/src/hal_i2c_m_sync.c deleted file mode 100644 index 7fa26ac7f..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_i2c_m_sync.c +++ /dev/null @@ -1,268 +0,0 @@ -/** - * \file - * - * \brief I/O I2C related functionality implementation. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Sync version of I2C I/O read - */ -static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n) -{ - struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = n; - msg.flags = I2C_M_STOP | I2C_M_RD; - msg.buffer = buf; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret) { - return ret; - } - - return n; -} - -/** - * \brief Sync version of I2C I/O write - */ -static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) -{ - struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = n; - msg.flags = I2C_M_STOP; - msg.buffer = (uint8_t *)buf; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret) { - return ret; - } - - return n; -} - -/** - * \brief Sync version of i2c initialize - */ -int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) -{ - int32_t init_status; - ASSERT(i2c); - - init_status = _i2c_m_sync_init(&i2c->device, hw); - if (init_status) { - return init_status; - } - - /* Init I/O */ - i2c->io.read = i2c_m_sync_read; - i2c->io.write = i2c_m_sync_write; - - return ERR_NONE; -} - -/** - * \brief deinitialize - */ -int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c) -{ - int32_t status; - ASSERT(i2c); - - status = _i2c_m_sync_deinit(&i2c->device); - if (status) { - return status; - } - - i2c->io.read = NULL; - i2c->io.write = NULL; - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c enable - */ -int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c) -{ - return _i2c_m_sync_enable(&i2c->device); -} - -/** - * \brief Sync version of i2c disable - */ -int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c) -{ - return _i2c_m_sync_disable(&i2c->device); -} - -/** - * \brief Sync version of i2c set slave address - */ -int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len) -{ - return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN); -} - -/** - * \brief Sync version of i2c set baudrate - */ -int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate) -{ - return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate); -} - -/** - * \brief Sync version of i2c write command - */ -int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) -{ - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = 1; - msg.flags = 0; - msg.buffer = ® - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - msg.flags = I2C_M_STOP; - msg.buffer = buffer; - msg.len = length; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c read command - */ -int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) -{ - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = 1; - msg.flags = 0; - msg.buffer = ® - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - msg.flags = I2C_M_STOP | I2C_M_RD; - msg.buffer = buffer; - msg.len = length; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c transfer command - */ -int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg) -{ - return _i2c_m_sync_transfer(&i2c->device, msg); -} - -/** - * \brief Sync version of i2c send stop condition command - */ -int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c) -{ - return _i2c_m_sync_send_stop(&i2c->device); -} - -/** - * \brief Retrieve I/O descriptor - */ -int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io) -{ - *io = &i2c->io; - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t i2c_m_sync_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_init.c b/atmel-samd/asf4/samd21/hal/src/hal_init.c deleted file mode 100644 index bdcf2a409..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_init.c +++ /dev/null @@ -1,57 +0,0 @@ -/** - * \file - * - * \brief HAL initialization related functionality implementation. - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_init.h" - -/** - * \brief Driver version - */ -#define HAL_INIT_VERSION 0x00000001u - -/** - * \brief Retrieve the current driver version - */ -uint32_t init_get_version(void) -{ - return HAL_INIT_VERSION; -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_io.c b/atmel-samd/asf4/samd21/hal/src/hal_io.c deleted file mode 100644 index 52638d9b0..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_io.c +++ /dev/null @@ -1,73 +0,0 @@ -/** - * \file - * - * \brief I/O functionality implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -uint32_t io_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \brief I/O write interface - */ -int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) -{ - ASSERT(io_descr && buf); - return io_descr->write(io_descr, buf, length); -} - -/** - * \brief I/O read interface - */ -int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) -{ - ASSERT(io_descr && buf); - return io_descr->read(io_descr, buf, length); -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_pwm.c b/atmel-samd/asf4/samd21/hal/src/hal_pwm.c deleted file mode 100644 index 2b9d2606f..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_pwm.c +++ /dev/null @@ -1,169 +0,0 @@ -/** - * \file - * - * \brief PWM functionality implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_pwm.h" -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -static void pwm_period_expired(struct _pwm_device *device); -static void pwm_detect_fault(struct _pwm_device *device); - -/** - * \brief Initialize pwm - */ -int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func) -{ - ASSERT(descr && hw); - _pwm_init(&descr->device, hw); - descr->device.callback.pwm_period_cb = pwm_period_expired; - descr->device.callback.pwm_error_cb = pwm_detect_fault; - return ERR_NONE; -} - -/** - * \brief Deinitialize pwm - */ -int32_t pwm_deinit(struct pwm_descriptor *const descr) -{ - ASSERT(descr); - _pwm_deinit(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Start pwm - */ -int32_t pwm_enable(struct pwm_descriptor *const descr) -{ - ASSERT(descr); - if (_pwm_is_enabled(&descr->device)) { - return ERR_DENIED; - } - _pwm_enable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Stop pwm - */ -int32_t pwm_disable(struct pwm_descriptor *const descr) -{ - ASSERT(descr); - if (!_pwm_is_enabled(&descr->device)) { - return ERR_DENIED; - } - _pwm_disable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Register PWM callback - */ -int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb) -{ - switch (type) { - case PWM_PERIOD_CB: - descr->pwm_cb.period = cb; - break; - - case PWM_ERROR_CB: - descr->pwm_cb.error = cb; - break; - - default: - return ERR_INVALID_ARG; - } - ASSERT(descr); - _pwm_set_irq_state(&descr->device, (enum _pwm_callback_type)type, NULL != cb); - return ERR_NONE; -} - -/** - * \brief Change PWM parameter - */ -int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, const pwm_period_t duty_cycle) -{ - ASSERT(descr); - _pwm_set_param(&descr->device, period, duty_cycle); - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t pwm_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \internal Process interrupts caused by period experied - */ -static void pwm_period_expired(struct _pwm_device *device) -{ - struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device); - - if (descr->pwm_cb.period) { - descr->pwm_cb.period(descr); - } -} - -/** - * \internal Process interrupts caused by pwm fault - */ -static void pwm_detect_fault(struct _pwm_device *device) -{ - struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device); - - if (descr->pwm_cb.error) { - descr->pwm_cb.error(descr); - } -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_sleep.c b/atmel-samd/asf4/samd21/hal/src/hal_sleep.c deleted file mode 100644 index 2d1aadd67..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_sleep.c +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality implementation. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_sleep.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Set the sleep mode of the device and put the MCU to sleep - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see the data sheet. - * - * \param[in] mode Sleep mode to use - * - * \return The status of a sleep request - * \retval -1 The requested sleep mode was invalid or not available - * \retval 0 The operation completed successfully, returned after leaving the - * sleep - */ -int sleep(const uint8_t mode) -{ - if (ERR_NONE != _set_sleep_mode(mode)) - return ERR_INVALID_ARG; - - _go_to_sleep(); - - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version - */ -uint32_t sleep_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_spi_m_sync.c b/atmel-samd/asf4/samd21/hal/src/hal_spi_m_sync.c deleted file mode 100644 index 8ceaa9a4a..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_spi_m_sync.c +++ /dev/null @@ -1,212 +0,0 @@ -/** - * \file - * - * \brief I/O SPI related functionality implementation. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_spi_m_sync.h" -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Driver version - */ -#define SPI_M_SYNC_DRIVER_VERSION 0x00000001u - -#define SPI_DEACTIVATE_NEXT 0x8000 - -static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length); -static int32_t _spi_m_sync_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length); - -int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw) -{ - int32_t rc = 0; - - ASSERT(spi && hw); - - spi->dev.prvt = (void *)hw; - - rc = _spi_m_sync_init(&spi->dev, hw); - if (rc < 0) { - return rc; - } - - spi->flags = SPI_DEACTIVATE_NEXT; - spi->io.read = _spi_m_sync_io_read; - spi->io.write = _spi_m_sync_io_write; - - return ERR_NONE; -} - -void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi) -{ - ASSERT(spi); - - _spi_m_sync_deinit(&spi->dev); -} - -void spi_m_sync_enable(struct spi_m_sync_descriptor *spi) -{ - ASSERT(spi); - - _spi_m_sync_enable(&spi->dev); -} - -void spi_m_sync_disable(struct spi_m_sync_descriptor *spi) -{ - ASSERT(spi); - - _spi_m_sync_disable(&spi->dev); -} - -int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val) -{ - ASSERT(spi); - - return _spi_m_sync_set_baudrate(&spi->dev, baud_val); -} - -int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode) -{ - ASSERT(spi); - - return _spi_m_sync_set_mode(&spi->dev, mode); -} - -int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size) -{ - ASSERT(spi); - - return _spi_m_sync_set_char_size(&spi->dev, char_size); -} - -int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord) -{ - ASSERT(spi); - - return _spi_m_sync_set_data_order(&spi->dev, dord); -} - -/** \brief Do SPI read in polling way - * For SPI master, activate CS, do send 0xFFs and read data, deactivate CS. - * - * It blocks until all data read or error. - * - * \param[in, out] spi Pointer to the HAL SPI instance. - * \param[out] buf Pointer to the buffer to store read data. - * \param[in] size Size of the data in number of characters. - * \return Operation status. - * \retval size Success. - * \retval >=0 Time out, with number of characters read. - */ -static int32_t _spi_m_sync_io_read(struct io_descriptor *io, uint8_t *buf, const uint16_t length) -{ - ASSERT(io); - - struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); - struct spi_xfer xfer; - - xfer.rxbuf = buf; - xfer.txbuf = 0; - xfer.size = length; - - return spi_m_sync_transfer(spi, &xfer); -} - -/** \brief Do SPI data write in polling way - * For SPI master, activate CS, do buffer send and deactivate CS. The data back - * is discarded. - * - * The data read back is discarded. - * - * It blocks until all data sent or error. - * - * \param[in, out] spi Pointer to the HAL SPI instance. - * \param[in] p_xfer Pointer to the transfer information (\ref spi_transfer). - * \return Operation status. - * \retval size Success. - * \retval >=0 Timeout, with number of characters transferred. - */ -static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length) -{ - ASSERT(io); - - struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); - struct spi_xfer xfer; - - xfer.rxbuf = 0; - xfer.txbuf = (uint8_t *)buf; - xfer.size = length; - - return spi_m_sync_transfer(spi, &xfer); -} - -int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer) -{ - struct spi_msg msg; - - ASSERT(spi && p_xfer); - - msg.txbuf = p_xfer->txbuf; - msg.rxbuf = p_xfer->rxbuf; - msg.size = p_xfer->size; - - return _spi_m_sync_trans(&spi->dev, &msg); -} - -int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io) -{ - ASSERT(spi && io); - *io = &spi->io; - return 0; -} - -uint32_t spi_m_sync_get_version(void) -{ - return SPI_M_SYNC_DRIVER_VERSION; -} - -#ifdef __cplusplus -} -#endif diff --git a/atmel-samd/asf4/samd21/hal/src/hal_timer.c b/atmel-samd/asf4/samd21/hal/src/hal_timer.c deleted file mode 100644 index 08e096a1b..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_timer.c +++ /dev/null @@ -1,263 +0,0 @@ -/** - * \file - * - * \brief Timer functionality implementation. - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_timer.h" -#include -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Timer flags - */ -#define TIMER_FLAG_QUEUE_IS_TAKEN 1 -#define TIMER_FLAG_INTERRUPT_TRIGERRED 2 - -static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time); -static void timer_process_counted(struct _timer_device *device); - -/** - * \brief Initialize timer - */ -int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func) -{ - ASSERT(descr && hw); - _timer_init(&descr->device, hw); - descr->time = 0; - descr->device.timer_cb.period_expired = timer_process_counted; - - return ERR_NONE; -} - -/** - * \brief Deinitialize timer - */ -int32_t timer_deinit(struct timer_descriptor *const descr) -{ - ASSERT(descr); - _timer_deinit(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Start timer - */ -int32_t timer_start(struct timer_descriptor *const descr) -{ - ASSERT(descr); - if (_timer_is_started(&descr->device)) { - return ERR_DENIED; - } - _timer_start(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Stop timer - */ -int32_t timer_stop(struct timer_descriptor *const descr) -{ - ASSERT(descr); - if (!_timer_is_started(&descr->device)) { - return ERR_DENIED; - } - _timer_stop(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Set amount of clock cycler per timer tick - */ -int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles) -{ - ASSERT(descr); - _timer_set_period(&descr->device, clock_cycles); - - return ERR_NONE; -} - -/** - * \brief Add timer task - */ -int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task) -{ - ASSERT(descr && task); - - descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; - if (is_list_element(&descr->tasks, task)) { - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - ASSERT(false); - return ERR_ALREADY_INITIALIZED; - } - task->time_label = descr->time; - timer_add_timer_task(&descr->tasks, task, descr->time); - - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { - CRITICAL_SECTION_ENTER() - descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; - _timer_set_irq(&descr->device); - CRITICAL_SECTION_LEAVE() - } - - return ERR_NONE; -} - -/** - * \brief Remove timer task - */ -int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task) -{ - ASSERT(descr && task); - - descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; - if (!is_list_element(&descr->tasks, task)) { - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - ASSERT(false); - return ERR_NOT_FOUND; - } - list_delete_element(&descr->tasks, task); - - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { - CRITICAL_SECTION_ENTER() - descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; - _timer_set_irq(&descr->device); - CRITICAL_SECTION_LEAVE() - } - - return ERR_NONE; -} - -/** - * \brief Retrieve the amount of clock cycles in a tick - */ -int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles) -{ - ASSERT(descr && cycles); - *cycles = _timer_get_period(&descr->device); - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t timer_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \internal Insert a timer task into sorted timer's list - * - * \param[in] head The pointer to the head of timer task list - * \param[in] task The pointer to task to add - * \param[in] time Current timer time - */ -static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) -{ - struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); - - if (!head) { - list_insert_as_head(list, new_task); - return; - } - - for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { - uint32_t time_left; - - if (it->time_label <= time) { - time_left = it->interval - (time - it->time_label); - } else { - time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; - } - if (time_left >= new_task->interval) - break; - prev = it; - } - - if (it == head) { - list_insert_as_head(list, new_task); - } else { - list_insert_after(prev, new_task); - } -} - -/** - * \internal Process interrupts - */ -static void timer_process_counted(struct _timer_device *device) -{ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wcast-align" - struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); - #pragma GCC diagnostic pop - struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); - uint32_t time = ++timer->time; - - if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { - timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; - return; - } - - while (it && ((time - it->time_label) >= it->interval)) { - struct timer_task *tmp = it; - - list_remove_head(&timer->tasks); - if (TIMER_TASK_REPEAT == tmp->mode) { - tmp->time_label = time; - timer_add_timer_task(&timer->tasks, tmp, time); - } - it = (struct timer_task *)list_get_head(&timer->tasks); - - tmp->cb(tmp); - } -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_usart_sync.c b/atmel-samd/asf4/samd21/hal/src/hal_usart_sync.c deleted file mode 100644 index ccc832db8..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_usart_sync.c +++ /dev/null @@ -1,285 +0,0 @@ -/** - * \file - * - * \brief I/O USART related functionality implementation. - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_usart_sync.h" -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); -static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -/** - * \brief Initialize usart interface - */ -int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) -{ - int32_t init_status; - ASSERT(descr && hw); - init_status = _usart_sync_init(&descr->device, hw); - if (init_status) { - return init_status; - } - - descr->io.read = usart_sync_read; - descr->io.write = usart_sync_write; - - return ERR_NONE; -} - -/** - * \brief Uninitialize usart interface - */ -int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_deinit(&descr->device); - - descr->io.read = NULL; - descr->io.write = NULL; - - return ERR_NONE; -} - -/** - * \brief Enable usart interface - */ -int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_enable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Disable usart interface - */ -int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_disable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Retrieve I/O descriptor - */ -int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) -{ - ASSERT(descr && io); - - *io = &descr->io; - return ERR_NONE; -} - -/** - * \brief Specify action for flow control pins - */ -int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, - const union usart_flow_control_state state) -{ - ASSERT(descr); - _usart_sync_set_flow_control_state(&descr->device, state); - - return ERR_NONE; -} - -/** - * \brief Set usart baud rate - */ -int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) -{ - ASSERT(descr); - _usart_sync_set_baud_rate(&descr->device, baud_rate); - - return ERR_NONE; -} - -/** - * \brief Set usart data order - */ -int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) -{ - ASSERT(descr); - _usart_sync_set_data_order(&descr->device, data_order); - - return ERR_NONE; -} - -/** - * \brief Set usart mode - */ -int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) -{ - ASSERT(descr); - _usart_sync_set_mode(&descr->device, mode); - - return ERR_NONE; -} - -/** - * \brief Set usart parity - */ -int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) -{ - ASSERT(descr); - _usart_sync_set_parity(&descr->device, parity); - - return ERR_NONE; -} - -/** - * \brief Set usart stop bits - */ -int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) -{ - ASSERT(descr); - _usart_sync_set_stop_bits(&descr->device, stop_bits); - - return ERR_NONE; -} - -/** - * \brief Set usart character size - */ -int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) -{ - ASSERT(descr); - _usart_sync_set_character_size(&descr->device, size); - - return ERR_NONE; -} - -/** - * \brief Retrieve the state of flow control pins - */ -int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, - union usart_flow_control_state *const state) -{ - ASSERT(descr && state); - *state = _usart_sync_get_flow_control_state(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Check if the usart transmitter is empty - */ -int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - return _usart_sync_is_byte_sent(&descr->device); -} - -/** - * \brief Check if the usart receiver is not empty - */ -int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - return _usart_sync_is_byte_received(&descr->device); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t usart_sync_get_version(void) -{ - return DRIVER_VERSION; -} - -/* - * \internal Write the given data to usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf Data to write to usart - * \param[in] length The number of bytes to write - * - * \return The number of bytes written. - */ -static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) -{ - uint32_t offset = 0; - struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); - - ASSERT(io_descr && buf && length); - while (!_usart_sync_is_byte_sent(&descr->device)) - ; - do { - _usart_sync_write_byte(&descr->device, buf[offset]); - while (!_usart_sync_is_byte_sent(&descr->device)) - ; - } while (++offset < length); - - return (int32_t)offset; -} - -/* - * \internal Read data from usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf A buffer to read data to - * \param[in] length The size of a buffer - * - * \return The number of bytes read. - */ -static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) -{ - uint32_t offset = 0; - struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); - - ASSERT(io_descr && buf && length); - do { - while (!_usart_sync_is_byte_received(&descr->device)) - ; - buf[offset] = _usart_sync_read_byte(&descr->device); - } while (++offset < length); - - return (int32_t)offset; -} diff --git a/atmel-samd/asf4/samd21/hal/src/hal_usb_device.c b/atmel-samd/asf4/samd21/hal/src/hal_usb_device.c deleted file mode 100644 index 08ad12a30..000000000 --- a/atmel-samd/asf4/samd21/hal/src/hal_usb_device.c +++ /dev/null @@ -1,602 +0,0 @@ -/** - * \file - * - * \brief SAM USB device HAL - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_usb_device.h" -#include "hal_atomic.h" - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** USB device HAL driver version. */ -#define USB_D_VERSION 0x00000001u - -/** - * Endpoint callbacks for data transfer. - */ -struct usb_d_ep_callbacks { - /** Callback that is invoked when setup packet is received. */ - usb_d_ep_cb_setup_t req; - /** Callback invoked when buffer is done, but last packet is full size - * packet without ZLP. Return \c true if new transfer has been submitted. - */ - usb_d_ep_cb_more_t more; - /** Callback invoked when transfer is finished/halted/aborted or error - * occurs. - */ - usb_d_ep_cb_xfer_t xfer; -}; - -/** - * Endpoint transfer descriptor header. - */ -struct usb_ep_xfer_hdr { - /** Transfer type, reuse \ref usb_ep_type. */ - uint8_t type; - /** Endpoint address. */ - uint8_t ep; - /** Endpoint state. */ - uint8_t state; - /** Last status code. */ - uint8_t status; -}; - -/** - * Transfer descriptor. - */ -struct usb_ep_xfer { - /** General transfer descriptor. */ - struct usb_ep_xfer_hdr hdr; - /** Pointer to data buffer. */ - uint8_t *buf; - /** Transfer size. */ - uint32_t size; - /** Control request packet. */ - uint8_t req[8]; -}; - -/** - * USB device endpoint descriptor. - */ -struct usb_d_ep { - /** On-going transfer on the endpoint. */ - struct usb_ep_xfer xfer; - /** Endpoint callbacks. */ - struct usb_d_ep_callbacks callbacks; -}; - -/** - * USB device HAL driver descriptor. - */ -struct usb_d_descriptor { - /** USB device endpoints. */ - struct usb_d_ep ep[CONF_USB_D_NUM_EP_SP]; -}; - -/** The USB HAL driver descriptor instance. */ -static struct usb_d_descriptor usb_d_inst; - -/** \brief Find the endpoint. - * \param[in] ep Endpoint address. - * \return Index of endpoint descriptor. - * \retval >=0 The index. - * \retval <0 Not found (endpoint is not initialized). - */ -static int8_t _usb_d_find_ep(const uint8_t ep) -{ - int8_t i; - for (i = 0; i < CONF_USB_D_NUM_EP_SP; i++) { - if (usb_d_inst.ep[i].xfer.hdr.ep == ep) { - return i; - } - if (usb_d_inst.ep[i].xfer.hdr.type == USB_EP_XTYPE_CTRL - && (ep & USB_EP_N_MASK) == usb_d_inst.ep[i].xfer.hdr.ep) { - return i; - } - } - return -1; -} - -/** - * \brief Start transactions - * \param[in] ep Endpoint address. - * \param[in] dir Endpoint transfer direction. - * \param[in] buf Pointer to transfer buffer. - * \param[in] size Transfer size. - * \param[in] zlp Auto append ZLP for IN, or wait ZLP for OUT. - */ -static inline int32_t _usb_d_trans(const uint8_t ep, const bool dir, const uint8_t *buf, const uint32_t size, - const uint8_t zlp) -{ - struct usb_d_transfer trans - = {(uint8_t *)buf, size, dir ? (uint8_t)(ep | USB_EP_DIR) : (uint8_t)(ep & USB_EP_N_MASK), zlp}; - - return _usb_d_dev_ep_trans(&trans); -} - -/** - * \brief Dummy callback that returns false - * \param[in] unused0 Unused parameter. - * \param[in] unused1 Unused parameter. - * \param[in] unused2 Unused parameter. - * \return Always \c false. - */ -static bool usb_d_dummy_cb_false(uint32_t unused0, uint32_t unused1, uint32_t unused2) -{ - (void)unused0; - (void)unused1; - (void)unused2; - return false; -} - -/** - * \brief Callback invoked when SETUP packet is ready - * \param[in] ep Endpoint number with transfer direction on bit 8. - */ -static void usb_d_cb_trans_setup(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - uint8_t * req = ept->xfer.req; - - uint8_t n = _usb_d_dev_ep_read_req(ep, req); - if (n != 8) { - _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); - _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_SET); - return; - } - - _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); - _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_CLR); - ept->xfer.hdr.state = USB_EP_S_IDLE; - if (!ept->callbacks.req(ep, req)) { - ept->xfer.hdr.state = USB_EP_S_HALTED; - _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); - _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_SET); - } -} - -/** - * \brief Callback invoked when request more data - * \param[in] ep Endpoint number with transfer direction on bit 8. - * \param[in] transfered Number of bytes transfered. - */ -static bool usb_d_cb_trans_more(const uint8_t ep, const uint32_t transfered) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - if (ept->xfer.hdr.state == USB_EP_S_X_DATA) { - return ept->callbacks.more(ep, transfered); - } - return false; -} - -/** - * \brief Handles the case that control endpoint transactions are done - * \param[in,out] ept Pointer to endpoint information. - */ -static inline void usb_d_ctrl_trans_done(struct usb_d_ep *ept) -{ - uint8_t state = ept->xfer.hdr.state; - bool req_dir = USB_GET_bmRequestType(ept->xfer.req) & USB_REQ_TYPE_IN; - - if (state == USB_EP_S_X_DATA) { - /* Data stage -> Status stage */ - bool err = ept->callbacks.xfer(ept->xfer.hdr.ep, USB_XFER_DATA, ept->xfer.req); - if (err) { - ept->xfer.hdr.state = USB_EP_S_HALTED; - ept->xfer.hdr.status = USB_XFER_HALT; - _usb_d_dev_ep_stall(req_dir ? ept->xfer.hdr.ep : (ept->xfer.hdr.ep | USB_EP_DIR), USB_EP_STALL_SET); - } else { - ept->xfer.hdr.state = USB_EP_S_X_STATUS; - _usb_d_trans(ept->xfer.hdr.ep, !req_dir, NULL, 0, 1); - } - } else { - /* Status stage done */ - ept->callbacks.xfer(ept->xfer.hdr.ep, USB_XFER_DONE, ept->xfer.req); - ept->xfer.hdr.state = USB_EP_S_X_SETUP; - } -} - -/** - * Callback when USB transactions are finished. - */ -static void _usb_d_cb_trans_done(const uint8_t ep, const int32_t code, const uint32_t transferred) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - - if (code == USB_TRANS_DONE) { - ept->xfer.hdr.status = USB_XFER_DONE; - if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { - usb_d_ctrl_trans_done(ept); - return; - } - ept->xfer.hdr.state = USB_EP_S_IDLE; - } else if (code == USB_TRANS_STALL) { - ept->xfer.hdr.status = USB_XFER_HALT; - if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { - ept->xfer.hdr.state = USB_EP_S_X_SETUP; - _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); - } else { - ept->xfer.hdr.state = USB_EP_S_HALTED; - } - } else if (code == USB_TRANS_ABORT) { - ept->xfer.hdr.status = USB_XFER_ABORT; - if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { - ept->xfer.hdr.state = USB_EP_S_X_SETUP; - return; - } - ept->xfer.hdr.state = USB_EP_S_IDLE; - } else if (code == USB_TRANS_RESET) { - ept->xfer.hdr.state = USB_EP_S_DISABLED; - ept->xfer.hdr.status = USB_XFER_RESET; - } else { - ept->xfer.hdr.state = USB_EP_S_ERROR; - ept->xfer.hdr.status = USB_XFER_ERROR; - } - - ept->callbacks.xfer(ep, (enum usb_xfer_code)ept->xfer.hdr.status, (void *)transferred); -} - -int32_t usb_d_init(void) -{ - int32_t rc = _usb_d_dev_init(); - uint8_t i; - if (rc < 0) { - return rc; - } - memset(usb_d_inst.ep, 0x00, sizeof(struct usb_d_ep) * CONF_USB_D_NUM_EP_SP); - for (i = 0; i < CONF_USB_D_NUM_EP_SP; i++) { - usb_d_inst.ep[i].xfer.hdr.ep = 0xFF; - usb_d_inst.ep[i].callbacks.req = (usb_d_ep_cb_setup_t)usb_d_dummy_cb_false; - usb_d_inst.ep[i].callbacks.more = (usb_d_ep_cb_more_t)usb_d_dummy_cb_false; - usb_d_inst.ep[i].callbacks.xfer = (usb_d_ep_cb_xfer_t)usb_d_dummy_cb_false; - } - /* Handles device driver endpoint callbacks to build transfer. */ - _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_SETUP, (FUNC_PTR)usb_d_cb_trans_setup); - _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_MORE, (FUNC_PTR)usb_d_cb_trans_more); - _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_DONE, (FUNC_PTR)_usb_d_cb_trans_done); - return ERR_NONE; -} - -void usb_d_deinit(void) -{ - _usb_d_dev_deinit(); -} - -void usb_d_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func) -{ - /* Directly uses device driver callback. */ - _usb_d_dev_register_callback(type, func); -} - -int32_t usb_d_enable(void) -{ - return _usb_d_dev_enable(); -} - -void usb_d_disable(void) -{ - _usb_d_dev_disable(); -} - -void usb_d_attach(void) -{ - _usb_d_dev_attach(); -} - -void usb_d_detach(void) -{ - _usb_d_dev_detach(); -} - -enum usb_speed usb_d_get_speed(void) -{ - return _usb_d_dev_get_speed(); -} - -uint16_t usb_d_get_frame_num(void) -{ - return _usb_d_dev_get_frame_n(); -} - -uint8_t usb_d_get_uframe_num(void) -{ - return _usb_d_dev_get_uframe_n(); -} - -void usb_d_set_address(const uint8_t addr) -{ - _usb_d_dev_set_address(addr); -} - -void usb_d_send_remotewakeup(void) -{ - _usb_d_dev_send_remotewakeup(); -} - -int32_t usb_d_ep0_init(const uint8_t max_pkt_size) -{ - return usb_d_ep_init(0, USB_EP_XTYPE_CTRL, max_pkt_size); -} - -int32_t usb_d_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_size) -{ - int32_t rc; - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - if (ep_index >= 0) { - return -USB_ERR_REDO; - } else { - ep_index = _usb_d_find_ep(0xFF); - if (ep_index < 0) { - return -USB_ERR_ALLOC_FAIL; - } - ept = &usb_d_inst.ep[ep_index]; - } - rc = _usb_d_dev_ep_init(ep, attr, max_pkt_size); - if (rc < 0) { - return rc; - } - ept->xfer.hdr.ep = ep; - ept->xfer.hdr.type = attr & USB_EP_XTYPE_MASK; - return ERR_NONE; -} - -void usb_d_ep_deinit(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - if (ep_index < 0) { - return; - } - _usb_d_dev_ep_deinit(ep); - ept->xfer.hdr.ep = 0xFF; -} - -int32_t usb_d_ep_enable(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - int32_t rc; - if (ep_index < 0) { - return -USB_ERR_PARAM; - } - ept->xfer.hdr.state = (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) ? USB_EP_S_X_SETUP : USB_EP_S_IDLE; - rc = _usb_d_dev_ep_enable(ep); - if (rc < 0) { - ept->xfer.hdr.state = USB_EP_S_DISABLED; - } - return rc; -} - -void usb_d_ep_disable(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - if (ep_index < 0) { - return; - } - _usb_d_dev_ep_disable(ep); - ept->xfer.hdr.state = USB_EP_S_DISABLED; -} - -uint8_t *usb_d_ep_get_req(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - if (ep_index < 0) { - return NULL; - } - return usb_d_inst.ep[ep_index].xfer.req; -} - -int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer) -{ - int8_t ep_index = _usb_d_find_ep(xfer->ep); - struct usb_d_ep * ept = &usb_d_inst.ep[ep_index]; - bool dir = USB_EP_GET_DIR(xfer->ep), zlp = xfer->zlp; - uint32_t len = xfer->size; - int32_t rc; - volatile uint8_t state; - volatile hal_atomic_t flags; - - if (ep_index < 0) { - return -USB_ERR_PARAM; - } - - atomic_enter_critical(&flags); - state = ept->xfer.hdr.state; - if (state == USB_EP_S_IDLE) { - ept->xfer.hdr.state = USB_EP_S_X_DATA; - atomic_leave_critical(&flags); - } else { - atomic_leave_critical(&flags); - switch (state) { - case USB_EP_S_HALTED: - return USB_HALTED; - case USB_EP_S_ERROR: - return -USB_ERROR; - case USB_EP_S_DISABLED: - return -USB_ERR_FUNC; - default: /* USB_EP_S_X_xxxx */ - return USB_BUSY; - } - } - - if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { - uint16_t req_len = USB_GET_wLength(ept->xfer.req); - /* SETUP without data: ZLP IN as status. */ - if (req_len == 0) { - dir = true; - len = 0; - zlp = true; - ept->xfer.hdr.state = USB_EP_S_X_STATUS; - } else { - dir = (USB_GET_bmRequestType(ept->xfer.req) & USB_REQ_TYPE_IN); - /* Data length not exceed requested. */ - if (len > req_len) { - len = req_len; - } - if (dir) { - /* Setup -> In */ - zlp = (req_len > len); - } else { - zlp = false; - } - } - } - - rc = _usb_d_trans(xfer->ep, dir, xfer->buf, len, zlp); - return rc; -} - -void usb_d_ep_abort(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - if (ep_index < 0) { - return; - } - _usb_d_dev_ep_abort(ep); - ept->xfer.hdr.state = USB_EP_S_IDLE; - ept->xfer.hdr.status = USB_XFER_ABORT; -} - -int32_t usb_d_ep_get_status(const uint8_t ep, struct usb_d_ep_status *stat) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep * ept = &usb_d_inst.ep[ep_index]; - struct usb_d_trans_status tmp; - uint8_t state = ept->xfer.hdr.state; - if (ep_index < 0) { - return -USB_ERR_PARAM; - } - if (stat) { - /* Check transaction status if transferring data. */ - _usb_d_dev_ep_get_status(ep, &tmp); - stat->ep = ep; - stat->state = state; - stat->code = ept->xfer.hdr.status; - stat->count = tmp.count; - stat->size = tmp.size; - } - switch (state) { - case USB_EP_S_IDLE: - return USB_OK; - case USB_EP_S_HALTED: - return USB_HALTED; - case USB_EP_S_ERROR: - return -USB_ERROR; - case USB_EP_S_DISABLED: - return -USB_ERR_FUNC; - default: - /* Busy */ - return USB_BUSY; - } -} - -static inline int32_t _usb_d_ep_halt_clr(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - int32_t rc; - if (ep_index < 0) { - return -USB_ERR_PARAM; - } - if (_usb_d_dev_ep_stall(ep, USB_EP_STALL_GET)) { - rc = _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); - if (rc < 0) { - return rc; - } - ept->xfer.hdr.state = USB_EP_S_IDLE; - ept->xfer.hdr.status = USB_XFER_UNHALT; - ept->callbacks.xfer(ep, USB_XFER_UNHALT, NULL); - } - return ERR_NONE; -} - -int32_t usb_d_ep_halt(const uint8_t ep, const enum usb_ep_halt_ctrl ctrl) -{ - if (ctrl == USB_EP_HALT_CLR) { - return _usb_d_ep_halt_clr(ep); - } else if (ctrl == USB_EP_HALT_SET) { - return _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); - } else { - return _usb_d_dev_ep_stall(ep, USB_EP_STALL_GET); - } -} - -void usb_d_ep_register_callback(const uint8_t ep, const enum usb_d_ep_cb_type type, const FUNC_PTR func) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - FUNC_PTR f = func ? (FUNC_PTR)func : (FUNC_PTR)usb_d_dummy_cb_false; - if (ep_index < 0) { - return; - } - switch (type) { - case USB_D_EP_CB_SETUP: - ept->callbacks.req = (usb_d_ep_cb_setup_t)f; - break; - case USB_D_EP_CB_MORE: - ept->callbacks.more = (usb_d_ep_cb_more_t)f; - break; - case USB_D_EP_CB_XFER: - ept->callbacks.xfer = (usb_d_ep_cb_xfer_t)f; - break; - default: - break; - } -} - -uint32_t usb_d_get_version(void) -{ - return USB_D_VERSION; -} - -#ifdef __cplusplus -} -#endif diff --git a/atmel-samd/asf4/samd21/hal/utils/include/compiler.h b/atmel-samd/asf4/samd21/hal/utils/include/compiler.h deleted file mode 100644 index 3cd654f53..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/compiler.h +++ /dev/null @@ -1,28 +0,0 @@ -/****************************************************************************** - * compiler.h - * - * Created: 05.05.2014 - * Author: N. Fomin -******************************************************************************/ - -#ifndef _COMPILER_H -#define _COMPILER_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -#ifndef _UNIT_TEST_ -#include "parts.h" -#endif -#include "err_codes.h" - -#ifdef __cplusplus -} -#endif - -#endif /* _COMPILER_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/err_codes.h b/atmel-samd/asf4/samd21/hal/utils/include/err_codes.h deleted file mode 100644 index ebc80e58b..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/err_codes.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file - * - * \brief Error code definitions. - * - * This file defines various status codes returned by functions, - * indicating success or failure as well as what kind of failure. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef ERROR_CODES_H_INCLUDED -#define ERROR_CODES_H_INCLUDED - -#define ERR_NONE 0 -#define ERR_INVALID_DATA -1 -#define ERR_NO_CHANGE -2 -#define ERR_ABORTED -3 -#define ERR_BUSY -4 -#define ERR_SUSPEND -5 -#define ERR_IO -6 -#define ERR_REQ_FLUSHED -7 -#define ERR_TIMEOUT -8 -#define ERR_BAD_DATA -9 -#define ERR_NOT_FOUND -10 -#define ERR_UNSUPPORTED_DEV -11 -#define ERR_NO_MEMORY -12 -#define ERR_INVALID_ARG -13 -#define ERR_BAD_ADDRESS -14 -#define ERR_BAD_FORMAT -15 -#define ERR_BAD_FRQ -16 -#define ERR_DENIED -17 -#define ERR_ALREADY_INITIALIZED -18 -#define ERR_OVERFLOW -19 -#define ERR_NOT_INITIALIZED -20 -#define ERR_SAMPLERATE_UNAVAILABLE -21 -#define ERR_RESOLUTION_UNAVAILABLE -22 -#define ERR_BAUDRATE_UNAVAILABLE -23 -#define ERR_PACKET_COLLISION -24 -#define ERR_PROTOCOL -25 -#define ERR_PIN_MUX_INVALID -26 -#define ERR_UNSUPPORTED_OP -27 -#define ERR_NO_RESOURCE -28 -#define ERR_NOT_READY -29 -#define ERR_FAILURE -30 -#define ERR_WRONG_LENGTH -31 - -#endif diff --git a/atmel-samd/asf4/samd21/hal/utils/include/events.h b/atmel-samd/asf4/samd21/hal/utils/include/events.h deleted file mode 100644 index 13c1d62db..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/events.h +++ /dev/null @@ -1,64 +0,0 @@ -/** -* \file -* -* \brief Events declaration. -* -* Copyright (C) 2015 Atmel Corporation. All rights reserved. -* -* \asf_license_start -* -* \page License -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of Atmel may not be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* 4. This software may only be redistributed and used in connection with an -* Atmel microcontroller product. -* -* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -* HOWEVER CAUSEsD AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -* \asf_license_stop -* -*/ - -#ifndef _EVENTS_H_INCLUDED -#define _EVENTS_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * \brief List of events. Must start with 0, be unique and follow numerical order. - */ -#define EVENT_IS_READY_TO_SLEEP_ID 0 -#define EVENT_PREPARE_TO_SLEEP_ID 1 -#define EVENT_WOKEN_UP_ID 2 - -#ifdef __cplusplus -} -#endif - -#endif /* _EVENTS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/parts.h b/atmel-samd/asf4/samd21/hal/utils/include/parts.h deleted file mode 100644 index 4ba71d65e..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/parts.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief Atmel part identification macros - * - * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef ATMEL_PARTS_H -#define ATMEL_PARTS_H - -#include "samd21.h" - -#include "hri_d21.h" - -#endif /* ATMEL_PARTS_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils.h b/atmel-samd/asf4/samd21/hal/utils/include/utils.h deleted file mode 100644 index 1cc588ad7..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/utils.h +++ /dev/null @@ -1,364 +0,0 @@ -/** - * \file - * - * \brief Different macros. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef UTILS_H_INCLUDED -#define UTILS_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_utils_macro - * - * @{ - */ - -/** - * \brief Retrieve pointer to parent structure - */ -#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) - -/** - * \brief Retrieve array size - */ -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) - -/** - * \brief Emit the compiler pragma \a arg. - * - * \param[in] arg The pragma directive as it would appear after \e \#pragma - * (i.e. not stringified). - */ -#define COMPILER_PRAGMA(arg) _Pragma(#arg) - -/** - * \def COMPILER_PACK_SET(alignment) - * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. - */ -#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) - -/** - * \def COMPILER_PACK_RESET() - * \brief Set default alignment for subsequent struct and union definitions. - */ -#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) - -/** - * \brief Set aligned boundary. - */ -#if defined __GNUC__ -#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#elif defined __ICCARM__ -#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) -#elif defined __CC_ARM -#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#endif - -/** - * \brief Flash located data macros - */ -#if defined __GNUC__ -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#elif defined __ICCARM__ -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#elif defined __CC_ARM -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#endif - -/** - * \brief Optimization - */ -#if defined __GNUC__ -#define OPTIMIZE_HIGH __attribute__((optimize(s))) -#elif defined __CC_ARM -#define OPTIMIZE_HIGH _Pragma("O3") -#elif defined __ICCARM__ -#define OPTIMIZE_HIGH _Pragma("optimize=high") -#endif - -/** - * \brief RAM located function attribute - */ -#if defined(__CC_ARM) /* Keil ?Vision 4 */ -#define RAMFUNC __attribute__((section(".ramfunc"))) -#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ -#define RAMFUNC __ramfunc -#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ -#define RAMFUNC __attribute__((section(".ramfunc"))) -#endif - -/** - * \brief No-init section. - * Place a data object or a function in a no-init section. - */ -#if defined(__CC_ARM) -#define NO_INIT(a) __attribute__((zero_init)) -#elif defined(__ICCARM__) -#define NO_INIT(a) __no_init -#elif defined(__GNUC__) -#define NO_INIT(a) __attribute__((section(".no_init"))) -#endif - -/** - * \brief Set user-defined section. - * Place a data object or a function in a user-defined section. - */ -#if defined(__CC_ARM) -#define COMPILER_SECTION(a) __attribute__((__section__(a))) -#elif defined(__ICCARM__) -#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) -#elif defined(__GNUC__) -#define COMPILER_SECTION(a) __attribute__((__section__(a))) -#endif - -/** - * \brief Define WEAK attribute. - */ -#if defined(__CC_ARM) /* Keil ?Vision 4 */ -#define WEAK __attribute__((weak)) -#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ -#define WEAK __weak -#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ -#define WEAK __attribute__((weak)) -#endif - -/** - * \brief Pointer to function - */ -typedef void (*FUNC_PTR)(void); - -#define LE_BYTE0(a) ((uint8_t)(a)) -#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) -#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) -#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) - -#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) -#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) - -/** \name Zero-Bit Counting - * - * Under GCC, __builtin_clz and __builtin_ctz behave like macros when - * applied to constant expressions (values known at compile time), so they are - * more optimized than the use of the corresponding assembly instructions and - * they can be used as constant expressions e.g. to initialize objects having - * static storage duration, and like the corresponding assembly instructions - * when applied to non-constant expressions (values unknown at compile time), so - * they are more optimized than an assembly periphrasis. Hence, clz and ctz - * ensure a possible and optimized behavior for both constant and non-constant - * expressions. - * - * @{ */ - -/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the leading zero bits. - * - * \return The count of leading zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -#define clz(u) __builtin_clz(u) -#else -#define clz(u) \ - (((u) == 0) \ - ? 32 \ - : ((u) & (1ul << 31)) ? 0 : ((u) & (1ul << 30)) ? 1 : ((u) & (1ul << 29)) \ - ? 2 \ - : ((u) & (1ul << 28)) \ - ? 3 \ - : ((u) & (1ul << 27)) \ - ? 4 \ - : ((u) & (1ul << 26)) \ - ? 5 \ - : ((u) & (1ul << 25)) ? 6 \ - : ((u) & (1ul << 24)) ? 7 : ((u) & (1ul << 23)) ? 8 : ((u) & (1ul << 22)) ? 9 : ((u) & (1ul << 21)) ? 10 : ((u) & (1ul << 20)) ? 11 : (( \ - u) \ - & (1ul \ - << 19)) \ - ? 12 \ - : ((u) \ - & (1ul \ - << 18)) \ - ? 13 \ - : ( \ - (u) \ - & (1ul \ - << 17)) \ - ? 14 \ - : ((u) & (1ul << 16)) ? 15 \ - : ((u) \ - & (1ul \ - << 15)) \ - ? 16 \ - : ((u) & (1ul << 14)) ? 17 \ - : ((u) & (1ul << 13)) ? 18 : ((u) & (1ul << 12)) ? 19 : ((u) & (1ul << 11)) ? 20 \ - : ((u) \ - & (1ul \ - << 10)) \ - ? 21 \ - : ((u) & (1ul << 9)) ? 22 \ - : ((u) & (1ul << 8)) ? 23 : ((u) \ - & (1ul \ - << 7)) \ - ? 24 \ - : ((u) & (1ul << 6)) ? 25 : ((u) & (1ul << 5)) ? 26 : ((u) & (1ul << 4)) ? 27 : ((u) & (1ul << 3)) ? 28 : ((u) \ - & (1ul \ - << 2)) \ - ? 29 \ - : ((u) & (1ul << 1)) ? 30 \ - : 31) -#endif - -/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the trailing zero bits. - * - * \return The count of trailing zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -#define ctz(u) __builtin_ctz(u) -#else -#define ctz(u) \ - ( \ - (u) & (1ul << 0) \ - ? 0 \ - : (u) & (1ul << 1) \ - ? 1 \ - : (u) & (1ul << 2) \ - ? 2 \ - : (u) & (1ul << 3) \ - ? 3 \ - : (u) & (1ul << 4) \ - ? 4 \ - : (u) & (1ul << 5) \ - ? 5 \ - : (u) & (1ul << 6) \ - ? 6 \ - : (u) & (1ul << 7) \ - ? 7 \ - : (u) & (1ul << 8) \ - ? 8 \ - : (u) & (1ul << 9) ? 9 \ - : (u) & (1ul << 10) \ - ? 10 \ - : (u) & (1ul << 11) \ - ? 11 \ - : (u) & (1ul << 12) \ - ? 12 \ - : (u) & (1ul << 13) \ - ? 13 \ - : (u) & (1ul \ - << 14) \ - ? 14 \ - : (u) & (1ul \ - << 15) \ - ? 15 \ - : (u) & (1ul << 16) ? 16 : (u) & (1ul << 17) ? 17 : (u) & (1ul << 18) ? 18 : (u) & (1ul << 19) ? 19 : (u) & (1ul << 20) ? 20 : (u) \ - & (1ul \ - << 21) \ - ? 21 \ - : (u) & (1ul << 22) ? 22 : (u) \ - & (1ul << 23) \ - ? 23 \ - : (u) & (1ul << 24) ? 24 \ - : (u) & (1ul << 25) ? 25 \ - : (u) & (1ul << 26) ? 26 : (u) & (1ul \ - << 27) \ - ? 27 \ - : (u) & (1ul \ - << 28) \ - ? 28 \ - : (u) & (1ul << 29) ? 29 \ - : (u) & (1ul << 30) ? 30 : ( \ - u) & (1ul << 31) \ - ? 31 \ - : 32) -#endif -/** @} */ - -/** - * \brief Counts the number of bits in a mask (no more than 32 bits) - * \param[in] mask Mask of which to count the bits. - */ -#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) - -/** - * \brief Retrieve the start position of bits mask (no more than 32 bits) - * \param[in] mask Mask of which to retrieve the start position. - */ -#define pos_of_mask(mask) ctz(mask) - -/** - * \brief Return division result of a/b and round up the result to the closest - * number divisible by "b" - */ -#define round_up(a, b) (((a)-1) / (b) + 1) - -/** - * \brief Get the minimum of x and y - */ -#define min(x, y) ((x) > (y) ? (y) : (x)) - -/** - * \brief Get the maximum of x and y - */ -#define max(x, y) ((x) > (y) ? (x) : (y)) - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* UTILS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_assert.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_assert.h deleted file mode 100644 index ae679e7a3..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/utils_assert.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * \file - * - * \brief Asserts related functionality. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _ASSERT_H_INCLUDED -#define _ASSERT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#ifndef USE_SIMPLE_ASSERT -//# define USE_SIMPLE_ASSERT -#endif - -/** - * \brief Assert macro - * - * This macro is used to throw asserts. It can be mapped to different function - * based on debug level. - * - * \param[in] condition A condition to be checked; - * assert is thrown if the given condition is false - */ -#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) - -#ifdef DEBUG - -#ifdef USE_SIMPLE_ASSERT -#define ASSERT_IMPL(condition, file, line) \ - if (!(condition)) \ - __asm("BKPT #0"); -#else -#define ASSERT_IMPL(condition, file, line) asf_assert((condition), file, line) -#endif - -#else /* DEBUG */ - -#ifdef USE_SIMPLE_ASSERT -#define ASSERT_IMPL(condition, file, line) ((void)0) -#else -#define ASSERT_IMPL(condition, file, line) ((void)0) -#endif - -#endif /* DEBUG */ - -/** - * \brief Assert function - * - * This function is used to throw asserts. - * - * \param[in] condition A condition to be checked; assert is thrown if the given - * condition is false - * \param[in] file File name - * \param[in] line Line number - */ -void asf_assert(const bool condition, const char *const file, const int line); - -#ifdef __cplusplus -} -#endif -#endif /* _ASSERT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_decrement_macro.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_decrement_macro.h deleted file mode 100644 index b53c5da8c..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/utils_decrement_macro.h +++ /dev/null @@ -1,319 +0,0 @@ -/** - * \file - * - * \brief Decrement macro. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_DECREMENT_MACRO_H -#define _UTILS_DECREMENT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Compile time decrement, result value is entire integer literal - * - * \param[in] val - value to be decremented - */ -#define DEC_VALUE(val) DEC_##val - -// Preprocessor increment implementation -#define DEC_256 255 -#define DEC_255 254 -#define DEC_254 253 -#define DEC_253 252 -#define DEC_252 251 -#define DEC_251 250 -#define DEC_250 249 -#define DEC_249 248 -#define DEC_248 247 -#define DEC_247 246 -#define DEC_246 245 -#define DEC_245 244 -#define DEC_244 243 -#define DEC_243 242 -#define DEC_242 241 -#define DEC_241 240 -#define DEC_240 239 -#define DEC_239 238 -#define DEC_238 237 -#define DEC_237 236 -#define DEC_236 235 -#define DEC_235 234 -#define DEC_234 233 -#define DEC_233 232 -#define DEC_232 231 -#define DEC_231 230 -#define DEC_230 229 -#define DEC_229 228 -#define DEC_228 227 -#define DEC_227 226 -#define DEC_226 225 -#define DEC_225 224 -#define DEC_224 223 -#define DEC_223 222 -#define DEC_222 221 -#define DEC_221 220 -#define DEC_220 219 -#define DEC_219 218 -#define DEC_218 217 -#define DEC_217 216 -#define DEC_216 215 -#define DEC_215 214 -#define DEC_214 213 -#define DEC_213 212 -#define DEC_212 211 -#define DEC_211 210 -#define DEC_210 209 -#define DEC_209 208 -#define DEC_208 207 -#define DEC_207 206 -#define DEC_206 205 -#define DEC_205 204 -#define DEC_204 203 -#define DEC_203 202 -#define DEC_202 201 -#define DEC_201 200 -#define DEC_200 199 -#define DEC_199 198 -#define DEC_198 197 -#define DEC_197 196 -#define DEC_196 195 -#define DEC_195 194 -#define DEC_194 193 -#define DEC_193 192 -#define DEC_192 191 -#define DEC_191 190 -#define DEC_190 189 -#define DEC_189 188 -#define DEC_188 187 -#define DEC_187 186 -#define DEC_186 185 -#define DEC_185 184 -#define DEC_184 183 -#define DEC_183 182 -#define DEC_182 181 -#define DEC_181 180 -#define DEC_180 179 -#define DEC_179 178 -#define DEC_178 177 -#define DEC_177 176 -#define DEC_176 175 -#define DEC_175 174 -#define DEC_174 173 -#define DEC_173 172 -#define DEC_172 171 -#define DEC_171 170 -#define DEC_170 169 -#define DEC_169 168 -#define DEC_168 167 -#define DEC_167 166 -#define DEC_166 165 -#define DEC_165 164 -#define DEC_164 163 -#define DEC_163 162 -#define DEC_162 161 -#define DEC_161 160 -#define DEC_160 159 -#define DEC_159 158 -#define DEC_158 157 -#define DEC_157 156 -#define DEC_156 155 -#define DEC_155 154 -#define DEC_154 153 -#define DEC_153 152 -#define DEC_152 151 -#define DEC_151 150 -#define DEC_150 149 -#define DEC_149 148 -#define DEC_148 147 -#define DEC_147 146 -#define DEC_146 145 -#define DEC_145 144 -#define DEC_144 143 -#define DEC_143 142 -#define DEC_142 141 -#define DEC_141 140 -#define DEC_140 139 -#define DEC_139 138 -#define DEC_138 137 -#define DEC_137 136 -#define DEC_136 135 -#define DEC_135 134 -#define DEC_134 133 -#define DEC_133 132 -#define DEC_132 131 -#define DEC_131 130 -#define DEC_130 129 -#define DEC_129 128 -#define DEC_128 127 -#define DEC_127 126 -#define DEC_126 125 -#define DEC_125 124 -#define DEC_124 123 -#define DEC_123 122 -#define DEC_122 121 -#define DEC_121 120 -#define DEC_120 119 -#define DEC_119 118 -#define DEC_118 117 -#define DEC_117 116 -#define DEC_116 115 -#define DEC_115 114 -#define DEC_114 113 -#define DEC_113 112 -#define DEC_112 111 -#define DEC_111 110 -#define DEC_110 109 -#define DEC_109 108 -#define DEC_108 107 -#define DEC_107 106 -#define DEC_106 105 -#define DEC_105 104 -#define DEC_104 103 -#define DEC_103 102 -#define DEC_102 101 -#define DEC_101 100 -#define DEC_100 99 -#define DEC_99 98 -#define DEC_98 97 -#define DEC_97 96 -#define DEC_96 95 -#define DEC_95 94 -#define DEC_94 93 -#define DEC_93 92 -#define DEC_92 91 -#define DEC_91 90 -#define DEC_90 89 -#define DEC_89 88 -#define DEC_88 87 -#define DEC_87 86 -#define DEC_86 85 -#define DEC_85 84 -#define DEC_84 83 -#define DEC_83 82 -#define DEC_82 81 -#define DEC_81 80 -#define DEC_80 79 -#define DEC_79 78 -#define DEC_78 77 -#define DEC_77 76 -#define DEC_76 75 -#define DEC_75 74 -#define DEC_74 73 -#define DEC_73 72 -#define DEC_72 71 -#define DEC_71 70 -#define DEC_70 69 -#define DEC_69 68 -#define DEC_68 67 -#define DEC_67 66 -#define DEC_66 65 -#define DEC_65 64 -#define DEC_64 63 -#define DEC_63 62 -#define DEC_62 61 -#define DEC_61 60 -#define DEC_60 59 -#define DEC_59 58 -#define DEC_58 57 -#define DEC_57 56 -#define DEC_56 55 -#define DEC_55 54 -#define DEC_54 53 -#define DEC_53 52 -#define DEC_52 51 -#define DEC_51 50 -#define DEC_50 49 -#define DEC_49 48 -#define DEC_48 47 -#define DEC_47 46 -#define DEC_46 45 -#define DEC_45 44 -#define DEC_44 43 -#define DEC_43 42 -#define DEC_42 41 -#define DEC_41 40 -#define DEC_40 39 -#define DEC_39 38 -#define DEC_38 37 -#define DEC_37 36 -#define DEC_36 35 -#define DEC_35 34 -#define DEC_34 33 -#define DEC_33 32 -#define DEC_32 31 -#define DEC_31 30 -#define DEC_30 29 -#define DEC_29 28 -#define DEC_28 27 -#define DEC_27 26 -#define DEC_26 25 -#define DEC_25 24 -#define DEC_24 23 -#define DEC_23 22 -#define DEC_22 21 -#define DEC_21 20 -#define DEC_20 19 -#define DEC_19 18 -#define DEC_18 17 -#define DEC_17 16 -#define DEC_16 15 -#define DEC_15 14 -#define DEC_14 13 -#define DEC_13 12 -#define DEC_12 11 -#define DEC_11 10 -#define DEC_10 9 -#define DEC_9 8 -#define DEC_8 7 -#define DEC_7 6 -#define DEC_6 5 -#define DEC_5 4 -#define DEC_4 3 -#define DEC_3 2 -#define DEC_2 1 -#define DEC_1 0 - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_DECREMENT_MACRO_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_event.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_event.h deleted file mode 100644 index 48d9c88d5..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/utils_event.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - * \file - * - * \brief Events declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_EVENT_H_INCLUDED -#define _UTILS_EVENT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * \brief The maximum amount of events - */ -#define EVENT_MAX_AMOUNT 8 - -/** - * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the - * closest number divisible by 8. - */ -#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) - -/** - * \brief The type of event ID. IDs should start with 0 and be in numerical order. - */ -typedef uint8_t event_id_t; - -/** - * \brief The type of returned parameter. This type is big enough to contain - * pointer to data on any platform. - */ -typedef uintptr_t event_data_t; - -/** - * \brief The type of returned parameter. This type is big enough to contain - * pointer to data on any platform. - */ -typedef void (*event_cb_t)(event_id_t id, event_data_t data); - -/** - * \brief Event structure - */ -struct event { - struct list_element elem; /*! The pointer to next event */ - uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ - event_cb_t cb; /*! Callback to be called when an event occurs */ -}; - -/** - * \brief Subscribe to event - * - * \param[in] event The pointer to event structure - * \param[in] id The event ID to subscribe to - * \param[in] cb The callback function to call when the given event occurs - * - * \return The status of subscription - */ -int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); - -/** - * \brief Remove event from subscription - * - * \param[in] event The pointer to event structure - * \param[in] id The event ID to remove subscription from - * - * \return The status of subscription removing - */ -int32_t event_unsubscribe(struct event *const event, const event_id_t id); - -/** - * \brief Post event - * - * \param[in] id The event ID to post - * \param[in] data The event data to be passed to event subscribers - */ -void event_post(const event_id_t id, const event_data_t data); - -#ifdef __cplusplus -} -#endif - -#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_increment_macro.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_increment_macro.h deleted file mode 100644 index 9bbc63ff3..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/utils_increment_macro.h +++ /dev/null @@ -1,318 +0,0 @@ -/** - * \file - * - * \brief Increment macro. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_INCREMENT_MACRO_H -#define _UTILS_INCREMENT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Compile time increment, result value is entire integer literal - * - * \param[in] val - value to be incremented (254 max) - */ -#define INC_VALUE(val) SP_INC_##val - -// Preprocessor increment implementation -#define SP_INC_0 1 -#define SP_INC_1 2 -#define SP_INC_2 3 -#define SP_INC_3 4 -#define SP_INC_4 5 -#define SP_INC_5 6 -#define SP_INC_6 7 -#define SP_INC_7 8 -#define SP_INC_8 9 -#define SP_INC_9 10 -#define SP_INC_10 11 -#define SP_INC_11 12 -#define SP_INC_12 13 -#define SP_INC_13 14 -#define SP_INC_14 15 -#define SP_INC_15 16 -#define SP_INC_16 17 -#define SP_INC_17 18 -#define SP_INC_18 19 -#define SP_INC_19 20 -#define SP_INC_20 21 -#define SP_INC_21 22 -#define SP_INC_22 23 -#define SP_INC_23 24 -#define SP_INC_24 25 -#define SP_INC_25 26 -#define SP_INC_26 27 -#define SP_INC_27 28 -#define SP_INC_28 29 -#define SP_INC_29 30 -#define SP_INC_30 31 -#define SP_INC_31 32 -#define SP_INC_32 33 -#define SP_INC_33 34 -#define SP_INC_34 35 -#define SP_INC_35 36 -#define SP_INC_36 37 -#define SP_INC_37 38 -#define SP_INC_38 39 -#define SP_INC_39 40 -#define SP_INC_40 41 -#define SP_INC_41 42 -#define SP_INC_42 43 -#define SP_INC_43 44 -#define SP_INC_44 45 -#define SP_INC_45 46 -#define SP_INC_46 47 -#define SP_INC_47 48 -#define SP_INC_48 49 -#define SP_INC_49 50 -#define SP_INC_50 51 -#define SP_INC_51 52 -#define SP_INC_52 53 -#define SP_INC_53 54 -#define SP_INC_54 55 -#define SP_INC_55 56 -#define SP_INC_56 57 -#define SP_INC_57 58 -#define SP_INC_58 59 -#define SP_INC_59 60 -#define SP_INC_60 61 -#define SP_INC_61 62 -#define SP_INC_62 63 -#define SP_INC_63 64 -#define SP_INC_64 65 -#define SP_INC_65 66 -#define SP_INC_66 67 -#define SP_INC_67 68 -#define SP_INC_68 69 -#define SP_INC_69 70 -#define SP_INC_70 71 -#define SP_INC_71 72 -#define SP_INC_72 73 -#define SP_INC_73 74 -#define SP_INC_74 75 -#define SP_INC_75 76 -#define SP_INC_76 77 -#define SP_INC_77 78 -#define SP_INC_78 79 -#define SP_INC_79 80 -#define SP_INC_80 81 -#define SP_INC_81 82 -#define SP_INC_82 83 -#define SP_INC_83 84 -#define SP_INC_84 85 -#define SP_INC_85 86 -#define SP_INC_86 87 -#define SP_INC_87 88 -#define SP_INC_88 89 -#define SP_INC_89 90 -#define SP_INC_90 91 -#define SP_INC_91 92 -#define SP_INC_92 93 -#define SP_INC_93 94 -#define SP_INC_94 95 -#define SP_INC_95 96 -#define SP_INC_96 97 -#define SP_INC_97 98 -#define SP_INC_98 99 -#define SP_INC_99 100 -#define SP_INC_100 101 -#define SP_INC_101 102 -#define SP_INC_102 103 -#define SP_INC_103 104 -#define SP_INC_104 105 -#define SP_INC_105 106 -#define SP_INC_106 107 -#define SP_INC_107 108 -#define SP_INC_108 109 -#define SP_INC_109 110 -#define SP_INC_110 111 -#define SP_INC_111 112 -#define SP_INC_112 113 -#define SP_INC_113 114 -#define SP_INC_114 115 -#define SP_INC_115 116 -#define SP_INC_116 117 -#define SP_INC_117 118 -#define SP_INC_118 119 -#define SP_INC_119 120 -#define SP_INC_120 121 -#define SP_INC_121 122 -#define SP_INC_122 123 -#define SP_INC_123 124 -#define SP_INC_124 125 -#define SP_INC_125 126 -#define SP_INC_126 127 -#define SP_INC_127 128 -#define SP_INC_128 129 -#define SP_INC_129 130 -#define SP_INC_130 131 -#define SP_INC_131 132 -#define SP_INC_132 133 -#define SP_INC_133 134 -#define SP_INC_134 135 -#define SP_INC_135 136 -#define SP_INC_136 137 -#define SP_INC_137 138 -#define SP_INC_138 139 -#define SP_INC_139 140 -#define SP_INC_140 141 -#define SP_INC_141 142 -#define SP_INC_142 143 -#define SP_INC_143 144 -#define SP_INC_144 145 -#define SP_INC_145 146 -#define SP_INC_146 147 -#define SP_INC_147 148 -#define SP_INC_148 149 -#define SP_INC_149 150 -#define SP_INC_150 151 -#define SP_INC_151 152 -#define SP_INC_152 153 -#define SP_INC_153 154 -#define SP_INC_154 155 -#define SP_INC_155 156 -#define SP_INC_156 157 -#define SP_INC_157 158 -#define SP_INC_158 159 -#define SP_INC_159 160 -#define SP_INC_160 161 -#define SP_INC_161 162 -#define SP_INC_162 163 -#define SP_INC_163 164 -#define SP_INC_164 165 -#define SP_INC_165 166 -#define SP_INC_166 167 -#define SP_INC_167 168 -#define SP_INC_168 169 -#define SP_INC_169 170 -#define SP_INC_170 171 -#define SP_INC_171 172 -#define SP_INC_172 173 -#define SP_INC_173 174 -#define SP_INC_174 175 -#define SP_INC_175 176 -#define SP_INC_176 177 -#define SP_INC_177 178 -#define SP_INC_178 179 -#define SP_INC_179 180 -#define SP_INC_180 181 -#define SP_INC_181 182 -#define SP_INC_182 183 -#define SP_INC_183 184 -#define SP_INC_184 185 -#define SP_INC_185 186 -#define SP_INC_186 187 -#define SP_INC_187 188 -#define SP_INC_188 189 -#define SP_INC_189 190 -#define SP_INC_190 191 -#define SP_INC_191 192 -#define SP_INC_192 193 -#define SP_INC_193 194 -#define SP_INC_194 195 -#define SP_INC_195 196 -#define SP_INC_196 197 -#define SP_INC_197 198 -#define SP_INC_198 199 -#define SP_INC_199 200 -#define SP_INC_200 201 -#define SP_INC_201 202 -#define SP_INC_202 203 -#define SP_INC_203 204 -#define SP_INC_204 205 -#define SP_INC_205 206 -#define SP_INC_206 207 -#define SP_INC_207 208 -#define SP_INC_208 209 -#define SP_INC_209 210 -#define SP_INC_210 211 -#define SP_INC_211 212 -#define SP_INC_212 213 -#define SP_INC_213 214 -#define SP_INC_214 215 -#define SP_INC_215 216 -#define SP_INC_216 217 -#define SP_INC_217 218 -#define SP_INC_218 219 -#define SP_INC_219 220 -#define SP_INC_220 221 -#define SP_INC_221 222 -#define SP_INC_222 223 -#define SP_INC_223 224 -#define SP_INC_224 225 -#define SP_INC_225 226 -#define SP_INC_226 227 -#define SP_INC_227 228 -#define SP_INC_228 229 -#define SP_INC_229 230 -#define SP_INC_230 231 -#define SP_INC_231 232 -#define SP_INC_232 233 -#define SP_INC_233 234 -#define SP_INC_234 235 -#define SP_INC_235 236 -#define SP_INC_236 237 -#define SP_INC_237 238 -#define SP_INC_238 239 -#define SP_INC_239 240 -#define SP_INC_240 241 -#define SP_INC_241 242 -#define SP_INC_242 243 -#define SP_INC_243 244 -#define SP_INC_244 245 -#define SP_INC_245 246 -#define SP_INC_246 247 -#define SP_INC_247 248 -#define SP_INC_248 249 -#define SP_INC_249 250 -#define SP_INC_250 251 -#define SP_INC_251 252 -#define SP_INC_252 253 -#define SP_INC_253 254 -#define SP_INC_254 255 - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_list.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_list.h deleted file mode 100644 index 8d049ff1b..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/utils_list.h +++ /dev/null @@ -1,174 +0,0 @@ -/** - * \file - * - * \brief List declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_LIST_H_INCLUDED -#define _UTILS_LIST_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_utils_list - * - * @{ - */ - -#include - -/** - * \brief List element type - */ -struct list_element { - struct list_element *next; -}; - -/** - * \brief List head type - */ -struct list_descriptor { - struct list_element *head; -}; - -/** - * \brief Reset list - * - * \param[in] list The pointer to a list descriptor - */ -static inline void list_reset(struct list_descriptor *const list) -{ - list->head = NULL; -} - -/** - * \brief Retrieve list head - * - * \param[in] list The pointer to a list descriptor - * - * \return A pointer to the head of the given list or NULL if the list is - * empty - */ -static inline void *list_get_head(const struct list_descriptor *const list) -{ - return (void *)list->head; -} - -/** - * \brief Retrieve next list head - * - * \param[in] list The pointer to a list element - * - * \return A pointer to the next list element or NULL if there is not next - * element - */ -static inline void *list_get_next_element(const void *const element) -{ - return element ? ((struct list_element *)element)->next : NULL; -} - -/** - * \brief Insert an element as list head - * - * \param[in] list The pointer to a list element - * \param[in] element An element to insert to the given list - */ -void list_insert_as_head(struct list_descriptor *const list, void *const element); - -/** - * \brief Insert an element after the given list element - * - * \param[in] after An element to insert after - * \param[in] element Element to insert to the given list - */ -void list_insert_after(void *const after, void *const element); - -/** - * \brief Insert an element at list end - * - * \param[in] after An element to insert after - * \param[in] element Element to insert to the given list - */ -void list_insert_at_end(struct list_descriptor *const list, void *const element); - -/** - * \brief Check whether an element belongs to a list - * - * \param[in] list The pointer to a list - * \param[in] element An element to check - * - * \return The result of checking - * \retval true If the given element is an element of the given list - * \retval false Otherwise - */ -bool is_list_element(const struct list_descriptor *const list, const void *const element); - -/** - * \brief Removes list head - * - * This function removes the list head and sets the next element after the list - * head as a new list head. - * - * \param[in] list The pointer to a list - * - * \return The pointer to the new list head of NULL if the list head is NULL - */ -void *list_remove_head(struct list_descriptor *const list); - -/** - * \brief Removes the list element - * - * \param[in] list The pointer to a list - * \param[in] element An element to remove - * - * \return The result of element removing - * \retval true The given element is removed from the given list - * \retval false The given element is not an element of the given list - */ -bool list_delete_element(struct list_descriptor *const list, const void *const element); - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_recursion_macro.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_recursion_macro.h deleted file mode 100644 index fcc625cd9..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/utils_recursion_macro.h +++ /dev/null @@ -1,79 +0,0 @@ -/** - * \file - * - * \brief Recursion macro. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_RECURSION_MACRO_H -#define _UTILS_RECURSION_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * \brief Macro recursion - * - * \param[in] macro Macro to be repeated recursively - * \param[in] arg A recursive threshold, building on this to decline by times - * defined with parameter n - * \param[in] n The number of repetitious calls to macro - */ -#define RECURSION_MACRO(macro, arg, n) RECURSION_MACRO_I(macro, arg, n) - -/* - * \brief Second level is needed to get integer literal from "n" if it is - * defined as macro - */ -#define RECURSION_MACRO_I(macro, arg, n) RECURSION##n(macro, arg) - -#define RECURSION0(macro, arg) -#define RECURSION1(macro, arg) RECURSION0(macro, DEC_VALUE(arg)) macro(arg, 0) -#define RECURSION2(macro, arg) RECURSION1(macro, DEC_VALUE(arg)) macro(arg, 1) -#define RECURSION3(macro, arg) RECURSION2(macro, DEC_VALUE(arg)) macro(arg, 2) -#define RECURSION4(macro, arg) RECURSION3(macro, DEC_VALUE(arg)) macro(arg, 3) -#define RECURSION5(macro, arg) RECURSION4(macro, DEC_VALUE(arg)) macro(arg, 4) - -#ifdef __cplusplus -} -#endif - -#include -#endif /* _UTILS_RECURSION_MACRO_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/include/utils_repeat_macro.h b/atmel-samd/asf4/samd21/hal/utils/include/utils_repeat_macro.h deleted file mode 100644 index aeed75d5c..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/include/utils_repeat_macro.h +++ /dev/null @@ -1,332 +0,0 @@ -/** - * \file - * - * \brief Repeat macro. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_REPEAT_MACRO_H -#define _UTILS_REPEAT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * \brief Sequently repeates specified macro for n times (255 max). - * - * Specified macro shall have two arguments: macro(arg, i) - * arg - user defined argument, which have the same value for all iterations. - * i - iteration number; numbering begins from zero and increments on each - * iteration. - * - * \param[in] macro - macro to be repeated - * \param[in] arg - user defined argument for repeated macro - * \param[in] n - total number of iterations (255 max) - */ -#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) - -/* - * \brief Second level is needed to get integer literal from "n" if it is - * defined as macro - */ -#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) - -#define REPEAT1(macro, arg, n) macro(arg, n) -#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) -#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) -#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) -#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) -#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) -#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) -#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) -#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) -#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) -#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) -#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) -#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) -#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) -#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) -#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) -#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) -#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) -#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) -#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) -#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) -#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) -#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) -#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) -#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) -#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) -#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) -#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) -#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) -#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) -#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) -#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) -#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) -#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) -#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) -#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) -#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) -#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) -#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) -#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) -#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) -#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) -#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) -#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) -#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) -#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) -#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) -#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) -#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) -#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) -#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) -#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) -#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) -#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) -#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) -#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) -#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) -#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) -#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) -#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) -#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) -#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) -#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) -#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) -#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) -#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) -#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) -#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) -#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) -#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) -#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) -#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) -#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) -#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) -#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) -#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) -#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) -#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) -#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) -#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) -#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) -#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) -#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) -#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) -#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) -#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) -#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) -#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) -#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) -#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) -#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) -#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) -#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) -#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) -#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) -#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) -#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) -#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) -#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) -#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) -#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) -#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) -#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) -#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) -#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) -#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) -#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) -#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) -#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) -#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) -#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) -#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) -#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) -#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) -#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) -#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) -#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) -#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) -#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) -#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) -#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) -#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) -#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) -#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) -#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) -#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) -#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) -#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) -#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) -#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) -#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) -#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) -#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) -#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) -#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) -#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) -#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) -#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) -#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) -#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) -#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) -#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) -#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) -#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) -#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) -#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) -#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) -#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) -#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) -#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) -#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) -#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) -#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) -#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) -#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) -#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) -#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) -#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) -#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) -#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) -#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) -#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) -#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) -#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) -#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) -#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) -#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) -#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) -#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) -#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) -#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) -#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) -#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) -#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) -#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) -#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) -#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) -#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) -#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) -#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) -#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) -#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) -#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) -#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) -#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) -#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) -#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) -#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) -#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) -#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) -#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) -#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) -#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) -#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) -#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) -#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) -#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) -#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) -#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) -#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) -#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) -#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) -#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) -#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) -#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) -#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) -#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) -#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) -#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) -#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) -#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) -#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) -#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) -#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) -#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) -#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) -#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) -#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) -#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) -#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) -#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) -#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) -#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) -#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) -#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) -#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) -#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) -#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) -#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) -#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) -#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) -#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) -#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) -#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) -#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) -#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) -#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) -#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) -#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) -#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) -#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) -#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) -#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) -#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) -#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) -#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) -#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) -#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) -#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) -#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) -#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) -#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) -#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) -#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) -#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) - -#ifdef __cplusplus -} -#endif - -#include -#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/atmel-samd/asf4/samd21/hal/utils/src/utils_assert.c b/atmel-samd/asf4/samd21/hal/utils/src/utils_assert.c deleted file mode 100644 index 9fe56827c..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/src/utils_assert.c +++ /dev/null @@ -1,56 +0,0 @@ -/** - * \file - * - * \brief Asserts related functionality. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUFDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include - -/** - * \brief Assert function - */ -void assert(const bool condition, const char *const file, const int line) -{ - if (!(condition)) { - __asm("BKPT #0"); - } - (void)file; - (void)line; -} diff --git a/atmel-samd/asf4/samd21/hal/utils/src/utils_event.c b/atmel-samd/asf4/samd21/hal/utils/src/utils_event.c deleted file mode 100644 index ab4e9eb3f..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/src/utils_event.c +++ /dev/null @@ -1,135 +0,0 @@ -/** - * \file - * - * \brief Events implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSEsD AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) - -static struct list_descriptor events; -static uint8_t subscribed[EVENT_MASK_SIZE]; - -int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - - ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); - - if (event->mask[position] & mask) { - return ERR_NO_CHANGE; /* Already subscribed */ - } - - if (!is_list_element(&events, event)) { - memset(event->mask, 0, EVENT_MASK_SIZE); - list_insert_as_head(&events, event); - } - event->cb = cb; - event->mask[position] |= mask; - - subscribed[position] |= mask; - - return ERR_NONE; -} - -int32_t event_unsubscribe(struct event *const event, const event_id_t id) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - const struct event *current; - uint8_t i; - - ASSERT(event && (id < EVENT_MAX_AMOUNT)); - - if (!(event->mask[position] & mask)) { - return ERR_NO_CHANGE; /* Already unsubscribed */ - } - - event->mask[position] &= ~mask; - - /* Check if there are more subscribers */ - for ((current = (const struct event *)list_get_head(&events)); current; - current = (const struct event *)list_get_next_element(current)) { - if (current->mask[position] & mask) { - break; - } - } - if (!current) { - subscribed[position] &= ~mask; - } - - /* Remove event from the list. Can be unsave, document it! */ - for (i = 0; i < ARRAY_SIZE(event->mask); i++) { - if (event->mask[i]) { - return ERR_NONE; - } - } - list_delete_element(&events, event); - - return ERR_NONE; -} - -void event_post(const event_id_t id, const event_data_t data) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - const struct event *current; - - ASSERT((id < EVENT_MAX_AMOUNT)); - - if (!(subscribed[position] & mask)) { - return; /* No subscribers */ - } - - /* Find all subscribers */ - for ((current = (const struct event *)list_get_head(&events)); current; - current = (const struct event *)list_get_next_element(current)) { - if (current->mask[position] & mask) { - current->cb(id, data); - } - } -} diff --git a/atmel-samd/asf4/samd21/hal/utils/src/utils_list.c b/atmel-samd/asf4/samd21/hal/utils/src/utils_list.c deleted file mode 100644 index eaf5f3410..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/src/utils_list.c +++ /dev/null @@ -1,146 +0,0 @@ -/** - * \file - * - * \brief List functionality implementation. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Check whether element belongs to list - */ -bool is_list_element(const struct list_descriptor *const list, const void *const element) -{ - struct list_element *it; - for (it = list->head; it; it = it->next) { - if (it == element) { - return true; - } - } - - return false; -} - -/** - * \brief Insert an element as list head - */ -void list_insert_as_head(struct list_descriptor *const list, void *const element) -{ - ASSERT(!is_list_element(list, element)); - - ((struct list_element *)element)->next = list->head; - list->head = (struct list_element *)element; -} - -/** - * \brief Insert an element after the given list element - */ -void list_insert_after(void *const after, void *const element) -{ - ((struct list_element *)element)->next = ((struct list_element *)after)->next; - ((struct list_element *)after)->next = (struct list_element *)element; -} - -/** - * \brief Insert an element at list end - */ -void list_insert_at_end(struct list_descriptor *const list, void *const element) -{ - struct list_element *it = list->head; - - ASSERT(!is_list_element(list, element)); - - if (!list->head) { - list->head = (struct list_element *)element; - ((struct list_element *)element)->next = NULL; - return; - } - - while (it->next) { - it = it->next; - } - it->next = (struct list_element *)element; - ((struct list_element *)element)->next = NULL; -} - -/** - * \brief Removes list head - */ -void *list_remove_head(struct list_descriptor *const list) -{ - if (list->head) { - struct list_element *tmp = list->head; - - list->head = list->head->next; - return (void *)tmp; - } - - return NULL; -} - -/** - * \brief Removes list element - */ -bool list_delete_element(struct list_descriptor *const list, const void *const element) -{ - if (!element) { - return false; - } - - if (list->head == element) { - list->head = list->head->next; - return true; - } else { - struct list_element *it = list->head; - - while (it && it->next != element) { - it = it->next; - } - if (it) { - it->next = ((struct list_element *)element)->next; - return true; - } - } - - return false; -} - -//@} diff --git a/atmel-samd/asf4/samd21/hal/utils/src/utils_syscalls.c b/atmel-samd/asf4/samd21/hal/utils/src/utils_syscalls.c deleted file mode 100644 index 7adad249a..000000000 --- a/atmel-samd/asf4/samd21/hal/utils/src/utils_syscalls.c +++ /dev/null @@ -1,162 +0,0 @@ -/** - * \file - * - * \brief Syscalls for SAM0 (GCC). - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#undef errno -extern int errno; -extern int _end; - -extern caddr_t _sbrk(int incr); -extern int link(char *old, char *_new); -extern int _close(int file); -extern int _fstat(int file, struct stat *st); -extern int _isatty(int file); -extern int _lseek(int file, int ptr, int dir); -extern void _exit(int status); -extern void _kill(int pid, int sig); -extern int _getpid(void); - -/** - * \brief Replacement of C library of _sbrk - */ -extern caddr_t _sbrk(int incr) -{ - static unsigned char *heap = NULL; - unsigned char * prev_heap; - - if (heap == NULL) { - heap = (unsigned char *)&_end; - } - prev_heap = heap; - - heap += incr; - - return (caddr_t)prev_heap; -} - -/** - * \brief Replacement of C library of link - */ -extern int link(char *old, char *_new) -{ - (void)old, (void)_new; - return -1; -} - -/** - * \brief Replacement of C library of _close - */ -extern int _close(int file) -{ - (void)file; - return -1; -} - -/** - * \brief Replacement of C library of _fstat - */ -extern int _fstat(int file, struct stat *st) -{ - (void)file; - st->st_mode = S_IFCHR; - - return 0; -} - -/** - * \brief Replacement of C library of _isatty - */ -extern int _isatty(int file) -{ - (void)file; - return 1; -} - -/** - * \brief Replacement of C library of _lseek - */ -extern int _lseek(int file, int ptr, int dir) -{ - (void)file, (void)ptr, (void)dir; - return 0; -} - -/** - * \brief Replacement of C library of _exit - */ -extern void _exit(int status) -{ - printf("Exiting with status %d.\n", status); - - for (;;) - ; -} - -/** - * \brief Replacement of C library of _kill - */ -extern void _kill(int pid, int sig) -{ - (void)pid, (void)sig; - return; -} - -/** - * \brief Replacement of C library of _getpid - */ -extern int _getpid(void) -{ - return -1; -} - -#ifdef __cplusplus -} -#endif diff --git a/atmel-samd/asf4/samd21/hpl/adc/hpl_adc.c b/atmel-samd/asf4/samd21/hpl/adc/hpl_adc.c deleted file mode 100644 index 7f2e9fca1..000000000 --- a/atmel-samd/asf4/samd21/hpl/adc/hpl_adc.c +++ /dev/null @@ -1,761 +0,0 @@ -/** - * \file - * - * \brief SAM Analog Digital Converter - * - * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include -#include -#include - -#define ADC_CONFIGURATION(n) \ - { \ - (n), (CONF_ADC_##n##_RUNSTDBY << ADC_CTRLA_RUNSTDBY_Pos) | (CONF_ADC_##n##_ENABLE << ADC_CTRLA_ENABLE_Pos), \ - (CONF_ADC_##n##_REFCOMP << ADC_REFCTRL_REFCOMP_Pos) | ADC_REFCTRL_REFSEL(CONF_ADC_##n##_REFSEL), \ - ADC_AVGCTRL_ADJRES(CONF_ADC_##n##_ADJRES) | ADC_AVGCTRL_SAMPLENUM(CONF_ADC_##n##_SAMPLENUM), \ - ADC_SAMPCTRL_SAMPLEN(CONF_ADC_##n##_SAMPLEN), \ - ADC_CTRLB_PRESCALER(CONF_ADC_##n##_PRESCALER) | (CONF_ADC_##n##_RESSEL << ADC_CTRLB_RESSEL_Pos) \ - | (CONF_ADC_##n##_CORREN << ADC_CTRLB_CORREN_Pos) | (CONF_ADC_##n##_FREERUN << ADC_CTRLB_FREERUN_Pos) \ - | (CONF_ADC_##n##_LEFTADJ << ADC_CTRLB_LEFTADJ_Pos) \ - | (CONF_ADC_##n##_DIFFMODE << ADC_CTRLB_DIFFMODE_Pos), \ - CONF_ADC_##n##_WINMODE, \ - ADC_INPUTCTRL_GAIN(CONF_ADC_##n##_GAIN) | ADC_INPUTCTRL_INPUTOFFSET(CONF_ADC_##n##_INPUTOFFSET) \ - | ADC_INPUTCTRL_INPUTSCAN(CONF_ADC_##n##_INPUTSCAN) \ - | (CONF_ADC_##n##_MUXNEG << ADC_INPUTCTRL_MUXNEG_Pos) \ - | (CONF_ADC_##n##_MUXPOS << ADC_INPUTCTRL_MUXPOS_Pos), \ - (CONF_ADC_##n##_WINMONEO << ADC_EVCTRL_WINMONEO_Pos) \ - | (CONF_ADC_##n##_RESRDYEO << ADC_EVCTRL_RESRDYEO_Pos) \ - | (CONF_ADC_##n##_SYNCEI << ADC_EVCTRL_SYNCEI_Pos) \ - | (CONF_ADC_##n##_STARTEI << ADC_EVCTRL_STARTEI_Pos), \ - CONF_ADC_##n##_WINLT, CONF_ADC_##n##_WINUT, ADC_GAINCORR_GAINCORR(CONF_ADC_##n##_GAINCORR), \ - ADC_OFFSETCORR_OFFSETCORR(CONF_ADC_##n##_OFFSETCORR), (CONF_ADC_##n##_DBGRUN << ADC_DBGCTRL_DBGRUN_Pos), \ - } - -/** - * \brief ADC configuration type - */ -struct adc_configuration { - uint8_t number; - hri_adc_ctrla_reg_t ctrl_a; - hri_adc_refctrl_reg_t ref_ctrl; - hri_adc_avgctrl_reg_t avg_ctrl; - hri_adc_sampctrl_reg_t samp_ctrl; - hri_adc_ctrlb_reg_t ctrl_b; - hri_adc_winctrl_reg_t win_ctrl; - hri_adc_inputctrl_reg_t input_ctrl; - hri_adc_evctrl_reg_t ev_ctrl; - hri_adc_winlt_reg_t win_lt; - hri_adc_winut_reg_t win_ut; - hri_adc_gaincorr_reg_t gain_corr; - hri_adc_offsetcorr_reg_t offset_corr; - hri_adc_dbgctrl_reg_t dbg_ctrl; -}; - -#define ADC_AMOUNT (CONF_ADC_0_ENABLE) - -/** - * \brief Array of ADC configurations - */ -static struct adc_configuration _adcs[] = { -#if CONF_ADC_0_ENABLE == 1 - ADC_CONFIGURATION(0), -#endif -}; - -/*!< Pointer to hpl device */ -static struct _adc_async_device *_adc_dev = NULL; - -static void _adc_set_resolution(void *const hw, const adc_resolution_t resolution); -static void _adc_set_conversion_mode(void *const hw, const enum adc_conversion_mode mode); -static void _adc_set_channel_differential_mode(void *const hw, const uint8_t channel, - const enum adc_differential_mode mode); - -/** - * \brief Retrieve ordinal number of the given adc hardware instance - */ -static uint8_t _adc_get_hardware_index(const void *const hw) -{ - (void)hw; - return 0; -} - -/** \brief Return the pointer to register settings of specific ADC - * \param[in] hw_addr The hardware register base address. - * \return Pointer to register settings of specific ADC. - */ -static uint8_t _adc_get_regs(const uint32_t hw_addr) -{ - uint8_t n = _adc_get_hardware_index((const void *)hw_addr); - uint8_t i; - - for (i = 0; i < sizeof(_adcs) / sizeof(struct adc_configuration); i++) { - if (_adcs[i].number == n) { - return i; - } - } - - ASSERT(false); - return 0; -} - -/** - * \brief Retrieve IRQ number for the given hardware instance - */ -static uint8_t _adc_get_irq_num(const struct _adc_async_device *const device) -{ - (void)device; - return ADC_IRQn; -} - -/** - * \brief Initialize ADC - * - * \param[in] hw The pointer to hardware instance - * \param[in] i The number of hardware instance - */ -static int32_t _adc_init(void *const hw, const uint8_t i) -{ - ASSERT(hw == ADC); - - hri_adc_wait_for_sync(hw); - if (hri_adc_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_adc_set_CTRLA_SWRST_bit(hw); - hri_adc_wait_for_sync(hw); - - hri_adc_write_REFCTRL_reg(hw, _adcs[i].ref_ctrl); - hri_adc_write_AVGCTRL_reg(hw, _adcs[i].avg_ctrl); - hri_adc_write_SAMPCTRL_reg(hw, _adcs[i].samp_ctrl); - hri_adc_write_EVCTRL_reg(hw, _adcs[i].ev_ctrl); - hri_adc_write_GAINCORR_reg(hw, _adcs[i].gain_corr); - hri_adc_write_OFFSETCORR_reg(hw, _adcs[i].offset_corr); - hri_adc_write_DBGCTRL_reg(hw, _adcs[i].dbg_ctrl); - hri_adc_write_CTRLB_reg(hw, _adcs[i].ctrl_b); - hri_adc_write_INPUTCTRL_reg(hw, _adcs[i].input_ctrl); - hri_adc_write_WINCTRL_reg(hw, _adcs[i].win_ctrl); - hri_adc_write_WINLT_reg(hw, _adcs[i].win_lt); - hri_adc_write_WINUT_reg(hw, _adcs[i].win_ut); - hri_adc_write_CTRLA_reg(hw, _adcs[i].ctrl_a); - - return ERR_NONE; -} - -/** - * \brief De-initialize ADC - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _adc_deinit(void *const hw) -{ - hri_adc_clear_CTRLA_ENABLE_bit(hw); - hri_adc_set_CTRLA_SWRST_bit(hw); -} - -/** - * \brief Initialize ADC - */ -int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw) -{ - ASSERT(device); - - device->hw = hw; - - return _adc_init(hw, _adc_get_regs((uint32_t)hw)); -} - -/** - * \brief Initialize ADC - */ -int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _adc_init(hw, _adc_get_regs((uint32_t)hw)); - if (init_status) { - return init_status; - } - device->hw = hw; - _adc_dev = device; - - NVIC_DisableIRQ(ADC_IRQn); - NVIC_ClearPendingIRQ(ADC_IRQn); - NVIC_EnableIRQ(ADC_IRQn); - - return ERR_NONE; -} - -/** - * \brief Initialize ADC - */ -int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw) -{ - ASSERT(device); - - device->hw = hw; - - return _adc_init(hw, _adc_get_regs((uint32_t)hw)); -} - -/** - * \brief De-initialize ADC - */ -void _adc_sync_deinit(struct _adc_sync_device *const device) -{ - _adc_deinit(device->hw); -} - -/** - * \brief De-initialize ADC - */ -void _adc_async_deinit(struct _adc_async_device *const device) -{ - NVIC_DisableIRQ(_adc_get_irq_num(device)); - NVIC_ClearPendingIRQ(_adc_get_irq_num(device)); - - _adc_deinit(device->hw); -} - -/** - * \brief De-initialize ADC - */ -void _adc_dma_deinit(struct _adc_dma_device *const device) -{ - _adc_deinit(device->hw); -} - -/** - * \brief Enable ADC - */ -void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Enable ADC - */ -void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Enable ADC - */ -void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable ADC - */ -void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable ADC - */ -void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable ADC - */ -void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Return address of ADC DMA source - */ -uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device) -{ - return (uint32_t) & (((Adc *)(device->hw))->RESULT.reg); -} - -/** - * \brief Retrieve ADC conversion data size - */ -uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device) -{ - return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; -} - -/** - * \brief Retrieve ADC conversion data size - */ -uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device) -{ - return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; -} - -/** - * \brief Retrieve ADC conversion data size - */ -uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device) -{ - return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; -} - -/** - * \brief Check if conversion is done - */ -bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel) -{ - (void)channel; - - return hri_adc_get_interrupt_RESRDY_bit(device->hw); -} - -/** - * \brief Check if conversion is done - */ -bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel) -{ - (void)channel; - - return hri_adc_get_interrupt_RESRDY_bit(device->hw); -} - -/** - * \brief Check if conversion is done - */ -bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device) -{ - return hri_adc_get_interrupt_RESRDY_bit(device->hw); -} - -/** - * \brief Make conversion - */ -void _adc_sync_convert(struct _adc_sync_device *const device) -{ - hri_adc_set_SWTRIG_START_bit(device->hw); -} - -/** - * \brief Make conversion - */ -void _adc_async_convert(struct _adc_async_device *const device) -{ - hri_adc_set_SWTRIG_START_bit(device->hw); -} - -/** - * \brief Make conversion - */ -void _adc_dma_convert(struct _adc_dma_device *const device) -{ - hri_adc_set_SWTRIG_START_bit(device->hw); -} - -/** - * \brief Retrieve the conversion result - */ -uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel) -{ - (void)channel; - - return hri_adc_read_RESULT_reg(device->hw); -} - -/** - * \brief Retrieve the conversion result - */ -uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel) -{ - (void)channel; - - return hri_adc_read_RESULT_reg(device->hw); -} - -/** - * \brief Set reference source - */ -void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference) -{ - hri_adc_write_REFCTRL_REFSEL_bf(device->hw, reference); -} - -/** - * \brief Set reference source - */ -void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference) -{ - hri_adc_write_REFCTRL_REFSEL_bf(device->hw, reference); -} - -/** - * \brief Set reference source - */ -void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference) -{ - hri_adc_write_REFCTRL_REFSEL_bf(device->hw, reference); -} - -/** - * \brief Set resolution - */ -void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution) -{ - _adc_set_resolution(device->hw, resolution); -} - -/** - * \brief Set resolution - */ -void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution) -{ - _adc_set_resolution(device->hw, resolution); -} - -/** - * \brief Set resolution - */ -void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution) -{ - hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution); -} - -/** - * \brief Set channels input sources - */ -void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel) -{ - (void)channel; - - hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); - hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); -} - -/** - * \brief Set channels input sources - */ -void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel) -{ - (void)channel; - - hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); - hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); -} - -/** - * \brief Set channels input source - */ -void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel) -{ - (void)channel; - - hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); - hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); -} - -/** - * \brief Set thresholds - */ -void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold) -{ - hri_adc_write_WINLT_reg(device->hw, low_threshold); - hri_adc_write_WINUT_reg(device->hw, up_threshold); -} - -/** - * \brief Set threshold - */ -void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold) -{ - hri_adc_write_WINLT_reg(device->hw, low_threshold); - hri_adc_write_WINUT_reg(device->hw, up_threshold); -} - -/** - * \brief Set thresholds - */ -void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold) -{ - hri_adc_write_WINLT_reg(device->hw, low_threshold); - hri_adc_write_WINUT_reg(device->hw, up_threshold); -} - -/** - * \brief Set gain - */ -void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain) -{ - (void)channel; - - hri_adc_write_INPUTCTRL_GAIN_bf(device->hw, gain); -} - -/** - * \brief Set gain - */ -void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain) -{ - (void)channel; - - hri_adc_write_INPUTCTRL_GAIN_bf(device->hw, gain); -} - -/** - * \brief Set gain - */ -void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain) -{ - (void)channel; - - hri_adc_write_INPUTCTRL_GAIN_bf(device->hw, gain); -} - -/** - * \brief Set conversion mode - */ -void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode) -{ - _adc_set_conversion_mode(device->hw, mode); -} - -/** - * \brief Set conversion mode - */ -void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode) -{ - _adc_set_conversion_mode(device->hw, mode); -} - -/** - * \brief Set conversion mode - */ -void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode) -{ - _adc_set_conversion_mode(device->hw, mode); -} - -/** - * \brief Set differential mode - */ -void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel, - const enum adc_differential_mode mode) -{ - _adc_set_channel_differential_mode(device->hw, channel, mode); -} - -/** - * \brief Set differential mode - */ -void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel, - const enum adc_differential_mode mode) -{ - _adc_set_channel_differential_mode(device->hw, channel, mode); -} - -/** - * \brief Set differential mode - */ -void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel, - const enum adc_differential_mode mode) -{ - (void)channel; - - _adc_set_channel_differential_mode(device->hw, channel, mode); -} - -/** - * \brief Set window mode - */ -void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode) -{ - hri_adc_write_WINCTRL_WINMODE_bf(device->hw, mode); -} - -/** - * \brief Set window mode - */ -void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode) -{ - hri_adc_write_WINCTRL_WINMODE_bf(device->hw, mode); -} - -/** - * \brief Set window mode - */ -void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode) -{ - hri_adc_write_WINCTRL_WINMODE_bf(device->hw, mode); -} - -/** - * \brief Retrieve threshold state - */ -void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state) -{ - *state = hri_adc_get_interrupt_WINMON_bit(device->hw); -} - -/** - * \brief Retrieve threshold state - */ -void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state) -{ - *state = hri_adc_get_interrupt_WINMON_bit(device->hw); -} - -/** - * \brief Retrieve threshold state - */ -void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state) -{ - *state = hri_adc_get_interrupt_WINMON_bit(device->hw); -} - -/** - * \brief Enable/disable ADC interrupt - * - * param[in] device The pointer to ADC device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel, - const enum _adc_async_callback_type type, const bool state) -{ - (void)channel; - - void *const hw = device->hw; - - if (ADC_ASYNC_DEVICE_MONITOR_CB == type) { - hri_adc_write_INTEN_WINMON_bit(hw, state); - } else if (ADC_ASYNC_DEVICE_ERROR_CB == type) { - hri_adc_write_INTEN_OVERRUN_bit(hw, state); - } else if (ADC_ASYNC_DEVICE_CONVERT_CB == type) { - hri_adc_write_INTEN_RESRDY_bit(hw, state); - } -} - -/** - * \brief SetADC resolution - * - * \param[in] hw The pointer to hardware instance - * \param[in] resolution The resolution to set - */ -static void _adc_set_resolution(void *const hw, const adc_resolution_t resolution) -{ - bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw); - - hri_adc_clear_CTRLA_ENABLE_bit(hw); - hri_adc_write_CTRLB_RESSEL_bf(hw, resolution); - - if (enabled) { - hri_adc_set_CTRLA_ENABLE_bit(hw); - } -} - -/** - * \brief SetADC resolution - * - * \param[in] hw The pointer to hardware instance - * \param[in] mode The mode to set - */ -static void _adc_set_conversion_mode(void *const hw, const enum adc_conversion_mode mode) -{ - bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw); - - hri_adc_clear_CTRLA_ENABLE_bit(hw); - hri_adc_clear_CTRLB_FREERUN_bit(hw); - if (ADC_CONVERSION_MODE_FREERUN == mode) { - hri_adc_set_CTRLB_FREERUN_bit(hw); - } - - if (enabled) { - hri_adc_set_CTRLA_ENABLE_bit(hw); - } -} - -/** - * \brief SetADC resolution - * - * \param[in] hw The pointer to hardware instance - * \param[in] mode The mode to set - */ -static void _adc_set_channel_differential_mode(void *const hw, const uint8_t channel, - const enum adc_differential_mode mode) -{ - (void)channel; - bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw); - - hri_adc_clear_CTRLA_ENABLE_bit(hw); - hri_adc_clear_CTRLB_DIFFMODE_bit(hw); - if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) { - hri_adc_set_CTRLB_DIFFMODE_bit(hw); - } - - if (enabled) { - hri_adc_set_CTRLA_ENABLE_bit(hw); - } -} diff --git a/atmel-samd/asf4/samd21/hpl/adc/hpl_adc_base.h b/atmel-samd/asf4/samd21/hpl/adc/hpl_adc_base.h deleted file mode 100644 index 2f9a333c9..000000000 --- a/atmel-samd/asf4/samd21/hpl/adc/hpl_adc_base.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * \file - * - * \brief ADC related functionality declaration. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_ADC_ADC_H_INCLUDED -#define _HPL_ADC_ADC_H_INCLUDED - -#include -#include - -/** - * \addtogroup HPL ADC - * - * \section hpl_adc_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ - -/** - * \brief Retrieve ADC helper functions - * - * \return A pointer to set of ADC helper functions - */ -void *_adc_get_adc_sync(void); -void *_adc_get_adc_async(void); - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_UART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/core/hpl_core_m0plus_base.c b/atmel-samd/asf4/samd21/hpl/core/hpl_core_m0plus_base.c deleted file mode 100644 index 8b2ecbff3..000000000 --- a/atmel-samd/asf4/samd21/hpl/core/hpl_core_m0plus_base.c +++ /dev/null @@ -1,210 +0,0 @@ -/** - * \file - * - * \brief Core related functionality implementation. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include -#include -#ifndef _UNIT_TEST_ -#include -#endif -#include -#include - -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 1000000 -#endif - -#if CONF_CPU_FREQUENCY < 1000 -#define CPU_FREQ_POWER 3 -#elif CONF_CPU_FREQUENCY < 10000 -#define CPU_FREQ_POWER 4 -#elif CONF_CPU_FREQUENCY < 100000 -#define CPU_FREQ_POWER 5 -#elif CONF_CPU_FREQUENCY < 1000000 -#define CPU_FREQ_POWER 6 -#elif CONF_CPU_FREQUENCY < 10000000 -#define CPU_FREQ_POWER 7 -#elif CONF_CPU_FREQUENCY < 100000000 -#define CPU_FREQ_POWER 8 -#endif - -/** - * \brief The array of interrupt handlers - */ -struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; - -/** - * \brief Reset MCU - */ -void _reset_mcu(void) -{ - NVIC_SystemReset(); -} - -/** - * \brief Put MCU to sleep - */ -void _go_to_sleep(void) -{ - __DSB(); - __WFI(); -} - -/** - * \brief Retrieve current IRQ number - */ -uint8_t _irq_get_current(void) -{ - return (uint8_t)__get_IPSR() - 16; -} - -/** - * \brief Disable the given IRQ - */ -void _irq_disable(uint8_t n) -{ - NVIC_DisableIRQ((IRQn_Type)n); -} - -/** - * \brief Set the given IRQ - */ -void _irq_set(uint8_t n) -{ - NVIC_SetPendingIRQ((IRQn_Type)n); -} - -/** - * \brief Clear the given IRQ - */ -void _irq_clear(uint8_t n) -{ - NVIC_ClearPendingIRQ((IRQn_Type)n); -} - -/** - * \brief Enable the given IRQ - */ -void _irq_enable(uint8_t n) -{ - NVIC_EnableIRQ((IRQn_Type)n); -} - -/** - * \brief Register IRQ handler - */ -void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) -{ - ASSERT(n < PERIPH_COUNT_IRQn); - - _irq_table[n] = irq; -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Default_Handler(void) -{ - while (1) { - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - */ -static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) -{ - switch (power) { - case 8: - return (us * (freq / 100000) - 1) / 10 + 1; - case 7: - return (us * (freq / 10000) - 1) / 100 + 1; - case 6: - return (us * (freq / 1000) - 1) / 1000 + 1; - case 5: - return (us * (freq / 100) - 1) / 10000 + 1; - case 4: - return (us * (freq / 10) - 1) / 100000 + 1; - default: - return (us * freq - 1) / 1000000 + 1; - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - */ -uint32_t _get_cycles_for_us(const uint16_t us) -{ - return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - */ -static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) -{ - switch (power) { - case 8: - return (ms * (freq / 100000)) * 100; - case 7: - return (ms * (freq / 10000)) * 10; - case 6: - return (ms * (freq / 1000)); - case 5: - return (ms * (freq / 100) - 1) / 10 + 1; - case 4: - return (ms * (freq / 10) - 1) / 100 + 1; - default: - return (ms * freq - 1) / 1000 + 1; - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - */ -uint32_t _get_cycles_for_ms(const uint16_t ms) -{ - return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); -} diff --git a/atmel-samd/asf4/samd21/hpl/core/hpl_core_port.h b/atmel-samd/asf4/samd21/hpl/core/hpl_core_port.h deleted file mode 100644 index b068af839..000000000 --- a/atmel-samd/asf4/samd21/hpl/core/hpl_core_port.h +++ /dev/null @@ -1,71 +0,0 @@ -/** - * \file - * - * \brief Core related functionality implementation. - * - * Copyright (C) 2015 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_CORE_PORT_H_INCLUDED -#define _HPL_CORE_PORT_H_INCLUDED - -#include - -/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR - * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), - * there will be assembling errors. - * So the following things are not included for assembling. - */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) - -#ifndef _UNIT_TEST_ -#include -#endif - -/** - * \brief Check if it's in ISR handling - * \return \c true if it's in ISR - */ -static inline bool _is_in_isr(void) -{ - return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); -} - -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/core/hpl_init.c b/atmel-samd/asf4/samd21/hpl/core/hpl_init.c deleted file mode 100644 index e567b5d22..000000000 --- a/atmel-samd/asf4/samd21/hpl/core/hpl_init.c +++ /dev/null @@ -1,69 +0,0 @@ -/** - * \file - * - * \brief HPL initialization related functionality implementation. - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -#include -#include - -/** - * \brief Initialize the hardware abstraction layer - */ -void _init_chip(void) -{ - hri_nvmctrl_set_CTRLB_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); - - _pm_init(); - _sysctrl_init_sources(); - _gclk_init_generators(); - _sysctrl_init_referenced_generators(); - -#if CONF_DMAC_ENABLE - _pm_enable_bus_clock(PM_BUS_AHB, DMAC); - _pm_enable_bus_clock(PM_BUS_APBB, DMAC); - _dma_init(); -#endif -} diff --git a/atmel-samd/asf4/samd21/hpl/dac/hpl_dac.c b/atmel-samd/asf4/samd21/hpl/dac/hpl_dac.c deleted file mode 100644 index 2896b0eee..000000000 --- a/atmel-samd/asf4/samd21/hpl/dac/hpl_dac.c +++ /dev/null @@ -1,248 +0,0 @@ - -/** -* \file -* -* \brief SAM Digital to Analog Converter -* -* Copyright (C) 2016 -2017 Atmel Corporation. All rights reserved. -* -* \asf_license_start -* -* \page License -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of Atmel may not be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* 4. This software may only be redistributed and used in connection with an -* Atmel microcontroller product. -* -* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMIT ED TO, PROCUREMENT OF SUBSTITUTE GOODS -* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -* \asf_license_stop -* -*/ - -#include -#include -#include -#include - -/** \conf INTERNAL */ -static int32_t _dac_init(void *const hw); -static inline void _dac_deinit(void *const hw); -/** \endcond */ - -/** - * \brief DAC configuration type - */ -struct dac_configuration { - hri_dac_ctrla_reg_t ctrla; /*!< Control A Register */ - hri_dac_ctrlb_reg_t ctrlb; /*!< Control B Register */ - hri_dac_evctrl_reg_t ev_ctrl; /*!< Event Control Register */ -}; - -/** - * \brief Array of DAC configurations - */ -static struct dac_configuration _dac = { - (CONF_DAC_RUNSTDBY << DAC_CTRLA_RUNSTDBY_Pos), - (CONF_DAC_REFSEL << DAC_CTRLB_REFSEL_Pos) | (CONF_DAC_BDWP << DAC_CTRLB_BDWP_Pos) - | (CONF_DAC_VPD << DAC_CTRLB_VPD_Pos) - | (CONF_DAC_LEFTADJ << DAC_CTRLB_LEFTADJ_Pos) - | (CONF_DAC_IOEN << DAC_CTRLB_IOEN_Pos) - | (CONF_DAC_EOEN << DAC_CTRLB_EOEN_Pos), - (CONF_DAC_EMPTYEO << DAC_EVCTRL_EMPTYEO_Pos) | (CONF_DAC_STARTEI << DAC_EVCTRL_STARTEI_Pos), -}; - -/*!< Pointer to hpl device */ -static struct _dac_async_device *_dac_dev = NULL; - -/** - * \brief Initialize synchronous DAC - */ -int32_t _dac_sync_init(struct _dac_sync_device *const device, void *const hw) -{ - ASSERT(device); - - device->hw = hw; - - return _dac_init(device->hw); -} - -/** - * \brief Initialize DAC - * - * param[in] hw The pointer to DAC hardware instance - */ -static int32_t _dac_init(void *const hw) -{ - hri_dac_wait_for_sync(hw); - - if (hri_dac_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_dac_set_CTRLA_SWRST_bit(hw); - hri_dac_wait_for_sync(hw); - - hri_dac_write_EVCTRL_reg(hw, _dac.ev_ctrl); - hri_dac_write_CTRLB_reg(hw, _dac.ctrlb); - hri_dac_write_CTRLA_reg(hw, _dac.ctrla); - return ERR_NONE; -} - -/** - * \brief De-initialize DAC - * - * param[in] hw The pointer to DAC hardware instance - */ -static inline void _dac_deinit(void *const hw) -{ - hri_dac_clear_CTRLA_ENABLE_bit(hw); - hri_dac_set_CTRLA_SWRST_bit(hw); -} - -/** - * \brief Initialize DAC - */ -int32_t _dac_async_init(struct _dac_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _dac_init(hw); - if (init_status) { - return init_status; - } - device->hw = hw; - - _dac_dev = device; - NVIC_DisableIRQ(DAC_IRQn); - NVIC_ClearPendingIRQ(DAC_IRQn); - NVIC_EnableIRQ(DAC_IRQn); - - return ERR_NONE; -} - -/** - * \brief De-initialize DAC - */ -void _dac_sync_deinit(struct _dac_sync_device *const device) -{ - _dac_deinit(device->hw); -} - -/** - * \brief De-initialize DAC - */ -void _dac_async_deinit(struct _dac_async_device *const device) -{ - NVIC_DisableIRQ(DAC_IRQn); - - _dac_deinit(device->hw); -} - -/** - * \brief Enable DAC Channel - */ -void _dac_sync_enable_channel(struct _dac_sync_device *const device, const uint8_t ch) -{ - (void)ch; - hri_dac_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Enable DAC Channel - */ -void _dac_async_enable_channel(struct _dac_async_device *const device, const uint8_t ch) -{ - (void)ch; - hri_dac_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable DAC Channel - */ -void _dac_sync_disable_channel(struct _dac_sync_device *const device, const uint8_t ch) -{ - (void)ch; - hri_dac_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable DAC Channel - */ -void _dac_async_disable_channel(struct _dac_async_device *const device, const uint8_t ch) -{ - (void)ch; - hri_dac_clear_CTRLA_ENABLE_bit(device->hw); -} - -bool _dac_sync_is_channel_enable(struct _dac_sync_device *const device, const uint8_t ch) -{ - (void)ch; - return hri_dac_get_CTRLA_ENABLE_bit(device->hw); -} - -bool _dac_async_is_channel_enable(struct _dac_async_device *const device, const uint8_t ch) -{ - (void)ch; - return hri_dac_get_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief write synchronous DAC data for output - */ -void _dac_sync_write_data(struct _dac_sync_device *const device, const uint16_t data, const uint8_t ch) -{ - (void)ch; - hri_dac_write_DATA_reg(device->hw, data); -} - -/** - * \brief write DAC data for output - */ -void _dac_async_write_data(struct _dac_async_device *const device, const uint16_t data, const uint8_t ch) -{ - (void)ch; - hri_dac_write_DATABUF_reg(device->hw, data); -} - -/** - * \brief Enable/disable DAC interrupt - * - * param[in] device The pointer to DAC device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _dac_async_set_irq_state(struct _dac_async_device *const device, const enum _dac_callback_type type, - const bool state) -{ - void *hw = device->hw; - - if (DAC_DEVICE_CONVERSION_DONE_CB == type) { - hri_dac_write_INTEN_EMPTY_bit(hw, state); - } else if (DAC_DEVICE_ERROR_CB == type) { - hri_dac_write_INTEN_UNDERRUN_bit(hw, state); - } -} diff --git a/atmel-samd/asf4/samd21/hpl/dmac/hpl_dmac.c b/atmel-samd/asf4/samd21/hpl/dmac/hpl_dmac.c deleted file mode 100644 index 5af9abaf3..000000000 --- a/atmel-samd/asf4/samd21/hpl/dmac/hpl_dmac.c +++ /dev/null @@ -1,226 +0,0 @@ - -/** - * \file - * - * \brief Generic DMAC related functionality. - * - * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include -#include - -#if CONF_DMAC_ENABLE - -/* Section containing first descriptors for all DMAC channels */ -COMPILER_ALIGNED(16) -static DmacDescriptor _descriptor_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; - -/* Section containing current descriptors for all DMAC channels */ -COMPILER_ALIGNED(16) -static DmacDescriptor _write_back_section[DMAC_CH_NUM] SECTION_DMAC_DESCRIPTOR; - -/* Array containing callbacks for DMAC channels */ -static struct _dma_resource _resources[DMAC_CH_NUM]; - -/* This macro DMAC configuration */ -#define DMAC_CHANNEL_CFG(i, n) \ - {(CONF_DMAC_ENABLE_##n << DMAC_CHCTRLA_ENABLE_Pos), \ - DMAC_CHCTRLB_TRIGACT(CONF_DMAC_TRIGACT_##n) | DMAC_CHCTRLB_TRIGSRC(CONF_DMAC_TRIGSRC_##n) \ - | DMAC_CHCTRLB_LVL(CONF_DMAC_LVL_##n) \ - | (CONF_DMAC_EVOE_##n << DMAC_CHCTRLB_EVOE_Pos) \ - | (CONF_DMAC_EVIE_##n << DMAC_CHCTRLB_EVIE_Pos) \ - | DMAC_CHCTRLB_EVACT(CONF_DMAC_EVACT_##n), \ - DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ - | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) \ - | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ - | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) \ - | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ - | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, - -/* DMAC channel configuration */ -struct dmac_channel_cfg { - uint8_t ctrla; - uint32_t ctrlb; - uint16_t btctrl; -}; - -/* DMAC channel configurations */ -const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; - -/** - * \brief Initialize DMAC - */ -int32_t _dma_init(void) -{ - uint8_t i = 0; - - hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); - hri_dmac_clear_CTRL_CRCENABLE_bit(DMAC); - hri_dmac_set_CHCTRLA_SWRST_bit(DMAC); - - hri_dmac_write_CTRL_reg(DMAC, - (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) - | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) - | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); - hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); - - hri_dmac_write_PRICTRL0_reg(DMAC, - DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) - | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) - | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) - | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) - | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) - | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) - | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); - hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); - hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); - - for (; i < DMAC_CH_NUM; i++) { - hri_dmac_write_CHID_reg(DMAC, i); - - hri_dmac_write_CHCTRLB_reg(DMAC, _cfgs[i].ctrlb); - hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); - } - - NVIC_DisableIRQ(DMAC_IRQn); - NVIC_ClearPendingIRQ(DMAC_IRQn); - NVIC_EnableIRQ(DMAC_IRQn); - - hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); - - return ERR_NONE; -} - -/** - * \brief Enable/disable DMA interrupt - */ -void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) -{ - hri_dmac_write_CHID_reg(DMAC, channel); - - if (DMA_TRANSFER_COMPLETE_CB == type) { - hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, state); - } else if (DMA_TRANSFER_ERROR_CB == type) { - hri_dmac_write_CHINTEN_TERR_bit(DMAC, state); - } -} - -int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) -{ - hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); - - return ERR_NONE; -} - -int32_t _dma_set_source_address(const uint8_t channel, const void *const src) -{ - hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); - - return ERR_NONE; -} - -int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) -{ - hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); - - return ERR_NONE; -} - -int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) -{ - uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); - uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); - - if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { - hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); - } - - address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); - - if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { - hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); - } - - hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); - - return ERR_NONE; -} - -int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) -{ - hri_dmac_write_CHID_reg(DMAC, channel); - hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); - hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC); - if (software_trigger) { - hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); - } - - return ERR_NONE; -} - -int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) -{ - *resource = &_resources[channel]; - - return ERR_NONE; -} - -/** - * \internal DMAC interrupt handler - */ -void DMAC_Handler(void) -{ - uint8_t channel = hri_dmac_read_INTPEND_ID_bf(DMAC); - struct _dma_resource *tmp_resource = &_resources[channel]; - - hri_dmac_write_CHID_reg(DMAC, channel); - - if (hri_dmac_get_CHINTFLAG_TERR_bit(DMAC)) { - hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC); - tmp_resource->dma_cb.error(tmp_resource); - } else if (hri_dmac_get_CHINTFLAG_TCMPL_bit(DMAC)) { - hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC); - tmp_resource->dma_cb.transfer_done(tmp_resource); - } -} - -#endif /* CONF_DMAC_ENABLE */ diff --git a/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk.c b/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk.c deleted file mode 100644 index 1012da0a2..000000000 --- a/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk.c +++ /dev/null @@ -1,162 +0,0 @@ -/** - * \file - * - * \brief Generic Clock Controller v210 related functionality. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Initializes generators - - */ -void _gclk_init_generators(void) -{ -#if CONF_GCLK_GEN_0_GENEN == 1 - hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_0_DIV) | GCLK_GENDIV_ID(0)); - hri_gclk_write_GENCTRL_reg(GCLK, - (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_0_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_0_SRC - | GCLK_GENCTRL_ID(0)); -#endif -#if CONF_GCLK_GEN_1_GENEN == 1 - hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_1_DIV) | GCLK_GENDIV_ID(1)); - hri_gclk_write_GENCTRL_reg(GCLK, - (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_1_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_1_SRC - | GCLK_GENCTRL_ID(1)); -#endif -#if CONF_GCLK_GEN_2_GENEN == 1 - hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_2_DIV) | GCLK_GENDIV_ID(2)); - hri_gclk_write_GENCTRL_reg(GCLK, - (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_2_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_2_SRC - | GCLK_GENCTRL_ID(2)); -#endif -#if CONF_GCLK_GEN_3_GENEN == 1 - hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_3_DIV) | GCLK_GENDIV_ID(3)); - hri_gclk_write_GENCTRL_reg(GCLK, - (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_3_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_3_SRC - | GCLK_GENCTRL_ID(3)); -#endif -#if CONF_GCLK_GEN_4_GENEN == 1 - hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_4_DIV) | GCLK_GENDIV_ID(4)); - hri_gclk_write_GENCTRL_reg(GCLK, - (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_4_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_4_SRC - | GCLK_GENCTRL_ID(4)); -#endif -#if CONF_GCLK_GEN_5_GENEN == 1 - hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_5_DIV) | GCLK_GENDIV_ID(5)); - hri_gclk_write_GENCTRL_reg(GCLK, - (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_5_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_5_SRC - | GCLK_GENCTRL_ID(5)); -#endif -#if CONF_GCLK_GEN_6_GENEN == 1 - hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_6_DIV) | GCLK_GENDIV_ID(6)); - hri_gclk_write_GENCTRL_reg(GCLK, - (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_6_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_6_SRC - | GCLK_GENCTRL_ID(6)); -#endif -#if CONF_GCLK_GEN_7_GENEN == 1 - hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_7_DIV) | GCLK_GENDIV_ID(7)); - hri_gclk_write_GENCTRL_reg(GCLK, - (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_7_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_7_SRC - | GCLK_GENCTRL_ID(7)); -#endif -#if defined(CONF_GCLK_GEN_8_GENEN) && CONF_GCLK_GEN_8_GENEN == 1 - hri_gclk_write_GENDIV_reg(GCLK, GCLK_GENDIV_DIV(CONF_GCLK_GEN_8_DIV) | GCLK_GENDIV_ID(8)); - hri_gclk_write_GENCTRL_reg(GCLK, - (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_8_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_8_SRC - | GCLK_GENCTRL_ID(8)); -#endif -} diff --git a/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk_base.h b/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk_base.h deleted file mode 100644 index 6451647f5..000000000 --- a/atmel-samd/asf4/samd21/hpl/gclk/hpl_gclk_base.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * \file - * - * \brief Generic Clock Controller. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_GCLK_H_INCLUDED -#define _HPL_GCLK_H_INCLUDED - -#include -#ifdef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup gclk_group GCLK Hardware Proxy Layer - * - * \section gclk_hpl_rev Revision History - * - v0.0.0.1 Initial Commit - * - *@{ - */ - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Enable clock on the given channel with the given clock source - * - * This function maps the given clock source to the given clock channel - * and enables channel. - * - * \param[in] channel The channel to enable clock for - * \param[in] source The clock source for the given channel - */ -static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) -{ - - hri_gclk_write_CLKCTRL_reg(GCLK, - GCLK_CLKCTRL_ID(channel) | GCLK_CLKCTRL_GEN(source) | (1 << GCLK_CLKCTRL_CLKEN_Pos)); -} - -//@} -/**@}*/ -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/nvmctrl/hpl_nvmctrl.c b/atmel-samd/asf4/samd21/hpl/nvmctrl/hpl_nvmctrl.c deleted file mode 100644 index 3e751e3d5..000000000 --- a/atmel-samd/asf4/samd21/hpl/nvmctrl/hpl_nvmctrl.c +++ /dev/null @@ -1,684 +0,0 @@ - -/** -* \file -* -* \brief Non-Volatile Memory Controller -* -* Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. -* -* \asf_license_start -* -* \page License -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of Atmel may not be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* 4. This software may only be redistributed and used in connection with an -* Atmel microcontroller product. -* -* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMIT ED TO, PROCUREMENT OF SUBSTITUTE GOODS -* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -* \asf_license_stop -* -*/ - -#include -#include -#include -#include -#include -#include - -#define NVM_MEMORY ((volatile uint16_t *)FLASH_ADDR) - -/** - * \brief NVM configuration type - */ -struct nvm_configuration { - hri_nvmctrl_ctrlb_reg_t ctrlb; /*!< Control B Register */ -}; - -/** - * \brief Array of NVM configurations - */ -static struct nvm_configuration _nvm - = {(CONF_NVM_CACHE << NVMCTRL_CTRLB_CACHEDIS_Pos) | (CONF_NVM_READ_MODE << NVMCTRL_CTRLB_READMODE_Pos) - | (CONF_NVM_SLEEPPRM << NVMCTRL_CTRLB_SLEEPPRM_Pos)}; - -/*!< Pointer to hpl device */ -static struct _flash_device *_nvm_dev = NULL; - -static void _flash_erase_row(void *const hw, const uint32_t dst_addr); -static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size); - -/** - * \brief Initialize NVM - */ -int32_t _flash_init(struct _flash_device *const device, void *const hw) -{ - ASSERT(device && (hw == NVMCTRL)); - uint32_t ctrlb; - - device->hw = hw; - ctrlb = _nvm.ctrlb & ~(NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW); - ctrlb |= hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk | NVMCTRL_CTRLB_MANW); - hri_nvmctrl_write_CTRLB_reg(device->hw, ctrlb); - - _nvm_dev = device; - NVIC_DisableIRQ(NVMCTRL_IRQn); - NVIC_ClearPendingIRQ(NVMCTRL_IRQn); - NVIC_EnableIRQ(NVMCTRL_IRQn); - return ERR_NONE; -} - -/** - * \brief De-initialize NVM - */ -void _flash_deinit(struct _flash_device *const device) -{ - device->hw = NULL; - NVIC_DisableIRQ(NVMCTRL_IRQn); -} - -/** - * \brief Get the flash page size. - */ -uint32_t _flash_get_page_size(struct _flash_device *const device) -{ - (void)device; - return (uint32_t)NVMCTRL_PAGE_SIZE; -} - -/** - * \brief Get the numbers of flash page. - */ -uint32_t _flash_get_total_pages(struct _flash_device *const device) -{ - (void)device; - return (uint32_t)FLASH_NB_OF_PAGES; -} - -/** - * \brief Get the number of wait states for read and write operations. - */ -uint8_t _flash_get_wait_state(struct _flash_device *const device) -{ - return hri_nvmctrl_get_CTRLB_reg(device->hw, NVMCTRL_CTRLB_RWS_Msk); -} - -/** - * \brief Set the number of wait states for read and write operations. - */ -void _flash_set_wait_state(struct _flash_device *const device, uint8_t state) -{ - hri_nvmctrl_write_CTRLB_RWS_bf(device->hw, state); -} - -/** - * \brief Reads a number of bytes to a page in the internal Flash. - */ -void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length) -{ - uint32_t nvm_address = src_addr / 2; - uint32_t i; - uint16_t data; - - /* Check if the module is busy */ - while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { - /* Wait until this module isn't busy */ - } - - /* Clear flags */ - hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); - - /* Check whether byte address is word-aligned*/ - if (src_addr % 2) { - data = NVM_MEMORY[nvm_address++]; - buffer[0] = data >> 8; - i = 1; - } else { - i = 0; - } - - /* NVM _must_ be accessed as a series of 16-bit words, perform manual copy - * to ensure alignment */ - while (i < length) { - data = NVM_MEMORY[nvm_address++]; - buffer[i] = (data & 0xFF); - if (i < (length - 1)) { - buffer[i + 1] = (data >> 8); - } - i += 2; - } -} - -/** - * \brief Writes a number of bytes to a page in the internal Flash. - */ -void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length) -{ - uint8_t tmp_buffer[NVMCTRL_ROW_PAGES][NVMCTRL_PAGE_SIZE]; - uint32_t row_start_addr, row_end_addr; - uint32_t i, j, k; - uint32_t wr_start_addr = dst_addr; - - do { - row_start_addr = wr_start_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); - row_end_addr = row_start_addr + NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE - 1; - - /* store the erase data into temp buffer before write */ - for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { - _flash_read(device, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); - } - - /* temp buffer update */ - j = (wr_start_addr - row_start_addr) / NVMCTRL_PAGE_SIZE; - k = wr_start_addr - row_start_addr - j * NVMCTRL_PAGE_SIZE; - while ((wr_start_addr <= row_end_addr) && (length > 0)) { - tmp_buffer[j][k] = *buffer; - k = (k + 1) % NVMCTRL_PAGE_SIZE; - if (0 == k) { - j++; - } - wr_start_addr++; - buffer++; - length--; - } - - /* erase row before write */ - _flash_erase_row(device->hw, row_start_addr); - - /* write buffer to flash */ - for (i = 0; i < NVMCTRL_ROW_PAGES; i++) { - _flash_program(device->hw, row_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); - } - - } while (row_end_addr < (wr_start_addr + length - 1)); -} - -/** - * \brief Appends a number of bytes in the internal Flash. - */ -void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length) -{ - uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1); - uint32_t size; - uint32_t offset = 0; - - if (dst_addr != page_start_addr) { - /* Need to write some data to the end of a page */ - size = min(length, NVMCTRL_PAGE_SIZE - (dst_addr - page_start_addr)); - _flash_program(device->hw, dst_addr, buffer, size); - page_start_addr += NVMCTRL_PAGE_SIZE; - offset += size; - } - - while (offset < length) { - size = min(length - offset, NVMCTRL_PAGE_SIZE); - _flash_program(device->hw, page_start_addr, buffer + offset, size); - page_start_addr += NVMCTRL_PAGE_SIZE; - offset += size; - } -} - -/** - * \brief Execute erase in the internal flash - */ -void _flash_erase(struct _flash_device *const device, uint32_t dst_addr, uint32_t page_nums) -{ - uint8_t tmp_buffer[NVMCTRL_PAGE_SIZE]; - uint32_t row_start_addr; - uint32_t i; - - row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); - - memset(tmp_buffer, 0xFF, NVMCTRL_PAGE_SIZE); - - /* when address is not aligned with row start address */ - if (dst_addr != row_start_addr) { - row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE; - for (i = 0; i < NVMCTRL_ROW_PAGES - 1; i++) { - _flash_write(device, dst_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); - if (--page_nums == 0) { - return; - } - dst_addr += NVMCTRL_PAGE_SIZE; - if (dst_addr == row_start_addr) { - break; - } - } - } - - while (page_nums >= NVMCTRL_ROW_PAGES) { - _flash_erase_row(device->hw, row_start_addr); - row_start_addr += NVMCTRL_ROW_PAGES * NVMCTRL_PAGE_SIZE; - page_nums -= NVMCTRL_ROW_PAGES; - } - - if (page_nums != 0) { - for (i = 0; i < page_nums; i++) { - _flash_write(device, row_start_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); - row_start_addr += NVMCTRL_PAGE_SIZE; - } - } -} - -/** - * \brief Execute lock in the internal flash - */ -int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) -{ - uint32_t region_pages; - uint32_t row_start_addr; - - region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); - row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); - - if ((page_nums != region_pages) || (dst_addr != row_start_addr)) { - return ERR_INVALID_ARG; - } - - while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { - /* Wait until this module isn't busy */ - } - - /* Clear flags */ - hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); - - hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2); - hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_LR | NVMCTRL_CTRLA_CMDEX_KEY); - - return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); -} - -/** - * \brief Execute unlock in the internal flash - */ -int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) -{ - uint32_t region_pages; - uint32_t row_start_addr; - - region_pages = (uint32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); - row_start_addr = dst_addr & ~((NVMCTRL_PAGE_SIZE * NVMCTRL_ROW_PAGES) - 1); - - if ((page_nums != region_pages) || (dst_addr != row_start_addr)) { - return ERR_INVALID_ARG; - } - - while (!hri_nvmctrl_get_interrupt_READY_bit(device->hw)) { - /* Wait until this module isn't busy */ - } - - /* Clear flags */ - hri_nvmctrl_clear_STATUS_reg(device->hw, NVMCTRL_STATUS_MASK); - - hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr / 2); - hri_nvmctrl_write_CTRLA_reg(device->hw, NVMCTRL_CTRLA_CMD_UR | NVMCTRL_CTRLA_CMDEX_KEY); - - return (int32_t)NVMCTRL_FLASH_SIZE / (16 * NVMCTRL_PAGE_SIZE); -} - -/** - * \brief check whether the region which is pointed by address - */ -bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr) -{ - uint16_t region_id; - - /* Get region for given page */ - region_id = dst_addr / (NVMCTRL_FLASH_SIZE / 16); - - return !(hri_nvmctrl_get_LOCK_reg(device->hw, 1 << region_id)); -} - -/** - * \brief Enable/disable Flash interrupt - */ -void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state) -{ - ASSERT(device); - - if (FLASH_DEVICE_CB_READY == type) { - hri_nvmctrl_write_INTEN_READY_bit(device->hw, state); - } else if (FLASH_DEVICE_CB_ERROR == type) { - hri_nvmctrl_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \internal erase a row in flash - * \param[in] hw The pointer to hardware instance - * \param[in] dst_addr Destination page address to erase - */ -static void _flash_erase_row(void *const hw, const uint32_t dst_addr) -{ - while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - /* Clear flags */ - hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); - - /* Set address and command */ - hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2); - hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_ER | NVMCTRL_CTRLA_CMDEX_KEY); -} - -/** - * \internal write a page in flash - * \param[in] hw The pointer to hardware instance - * \param[in] dst_addr Destination page address to write - * \param[in] buffer Pointer to buffer where the data to - * write is stored - * \param[in] size The size of data to write to a page - */ -static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size) -{ - ASSERT(!(dst_addr % 2)); - - uint32_t nvm_address = dst_addr / 2; - uint16_t i, data; - - while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY); - - while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - /* Clear flags */ - hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); - - for (i = 0; i < size; i += 2) { - data = buffer[i]; - if (i < NVMCTRL_PAGE_SIZE - 1) { - data |= (buffer[i + 1] << 8); - } - NVM_MEMORY[nvm_address++] = data; - } - - while (!hri_nvmctrl_get_interrupt_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - hri_nvmctrl_write_ADDR_reg(hw, dst_addr / 2); - hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_WP | NVMCTRL_CTRLA_CMDEX_KEY); -} - -/** - * \internal NVM interrupt handler - */ -void NVMCTRL_Handler(void) -{ - void *const hw = _nvm_dev->hw; - - if (hri_nvmctrl_get_interrupt_READY_bit(hw)) { - hri_nvmctrl_clear_interrupt_READY_bit(hw); - if (NULL != _nvm_dev->flash_cb.ready_cb) { - _nvm_dev->flash_cb.ready_cb(_nvm_dev); - } - } else if (hri_nvmctrl_get_interrupt_ERROR_bit(hw)) { - hri_nvmctrl_clear_interrupt_ERROR_bit(hw); - if (NULL != _nvm_dev->flash_cb.error_cb) { - _nvm_dev->flash_cb.error_cb(_nvm_dev); - } - } -} - -/* -The NVM User Row contains calibration data that are automatically read at device -power on. -The NVM User Row can be read at address 0x804000. -*/ -#ifndef _NVM_USER_ROW_BASE -#define _NVM_USER_ROW_BASE 0x804000 -#endif -#define _NVM_USER_ROW_N_BITS 64 -#define _NVM_USER_ROW_N_BYTES (_NVM_USER_ROW_N_BITS / 8) -#define _NVM_USER_ROW_END (((uint8_t *)_NVM_USER_ROW_BASE) + _NVM_USER_ROW_N_BYTES - 1) -#define _IS_NVM_USER_ROW(b) \ - (((uint8_t *)(b) >= (uint8_t *)(_NVM_USER_ROW_BASE)) && ((uint8_t *)(b) <= (uint8_t *)(_NVM_USER_ROW_END))) -#define _IN_NVM_USER_ROW(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_USER_ROW_END)) - -/* -The NVM Software Calibration Area can be read at address 0x806020. -The NVM Software Calibration Area can not be written. -*/ -#ifndef _NVM_SW_CALIB_AREA_BASE -#define _NVM_SW_CALIB_AREA_BASE 0x806020 -#endif -#define _NVM_SW_CALIB_AREA_N_BITS 128 -#define _NVM_SW_CALIB_AREA_N_BYTES (_NVM_SW_CALIB_AREA_N_BITS / 8) -#define _NVM_SW_CALIB_AREA_END (((uint8_t *)_NVM_SW_CALIB_AREA_BASE) + _NVM_SW_CALIB_AREA_N_BYTES - 1) -#define _IS_NVM_SW_CALIB_AREA(b) \ - (((uint8_t *)(b) >= (uint8_t *)_NVM_SW_CALIB_AREA_BASE) && ((uint8_t *)(b) <= (uint8_t *)_NVM_SW_CALIB_AREA_END)) -#define _IN_NVM_SW_CALIB_AREA(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_SW_CALIB_AREA_END)) - -/** - * \internal Read left aligned data bits - * \param[in] base Base address for the data - * \param[in] bit_offset Offset for the bitfield start - * \param[in] n_bits Number of bits in the bitfield - */ -static inline uint32_t _user_area_read_l32_bits(const volatile uint32_t *base, const uint32_t bit_offset, - const uint8_t n_bits) -{ - return base[bit_offset >> 5] & ((1 << n_bits) - 1); -} - -/** - * \internal Read right aligned data bits - * \param[in] base Base address for the data - * \param[in] bit_offset Offset for the bitfield start - * \param[in] n_bits Number of bits in the bitfield - */ -static inline uint32_t _user_area_read_r32_bits(const volatile uint32_t *base, const uint32_t bit_offset, - const uint8_t n_bits) -{ - return (base[bit_offset >> 5] >> (bit_offset & 0x1F)) & ((1 << n_bits) - 1); -} - -int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, uint32_t size) -{ - ASSERT(buf); - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - if (!_IN_NVM_USER_ROW(base, offset)) { - return ERR_BAD_ADDRESS; - } - /* Cut off if request too many bytes */ - if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { - return ERR_INVALID_ARG; - } - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - if (!_IN_NVM_SW_CALIB_AREA(base, offset)) { - return ERR_BAD_ADDRESS; - } - /* Cut off if request too many bytes */ - if (!_IN_NVM_SW_CALIB_AREA(base, offset + size - 1)) { - return ERR_INVALID_ARG; - } - } else { - return ERR_UNSUPPORTED_OP; - } - - /* Copy data */ - memcpy(buf, ((uint8_t *)base) + offset, size); - return ERR_NONE; -} - -uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits) -{ - volatile uint32_t *mem_base = (volatile uint32_t *)base; - uint32_t l_off, l_bits; - uint32_t r_off, r_bits; - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - ASSERT(_IN_NVM_USER_ROW(base, bit_offset >> 3) && _IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)); - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - ASSERT(_IN_NVM_SW_CALIB_AREA(base, bit_offset >> 3) - && _IN_NVM_SW_CALIB_AREA(base, (bit_offset + n_bits - 1) >> 3)); - } else { - ASSERT(false); - } - - /* Since the bitfield can cross 32-bits boundaries, - * left and right bits are read from 32-bit aligned address - * and then combined together. */ - l_off = bit_offset & (~(32 - 1)); - r_off = l_off + 32; - l_bits = 32 - (bit_offset & (32 - 1)); - if (n_bits > l_bits) { - r_bits = n_bits - l_bits; - } else { - l_bits = n_bits; - r_bits = 0; - } - return _user_area_read_r32_bits(mem_base, bit_offset, l_bits) - + (_user_area_read_l32_bits(mem_base, r_off, r_bits) << l_bits); -} - -/** \internal Write 64-bit user row - * \param[in] _row Pointer to 64-bit user row data. - */ -static int32_t _user_row_write_exec(const uint32_t *_row) -{ - Nvmctrl *hw = NVMCTRL; - uint32_t ctrlb = hri_nvmctrl_read_CTRLB_reg(NVMCTRL); - - /* Denie if Security Bit is set */ - if (hri_nvmctrl_get_STATUS_reg(hw, NVMCTRL_STATUS_SB)) { - return ERR_DENIED; - } - - /* Do Save */ - - /* - Prepare. */ - while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { - /* Wait until this module isn't busy */ - } - hri_nvmctrl_clear_STATUS_reg(hw, NVMCTRL_STATUS_MASK); - hri_nvmctrl_set_CTRLB_MANW_bit(hw); - - /* - Erase AUX row. */ - hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)_NVM_USER_ROW_BASE); - hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_EAR | NVMCTRL_CTRLA_CMDEX_KEY); - while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { - /* Wait until this module isn't busy */ - } - - /* - Page buffer clear & write. */ - hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_PBC | NVMCTRL_CTRLA_CMDEX_KEY); - while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { - /* Wait until this module isn't busy */ - } - *((uint32_t *)NVMCTRL_AUX0_ADDRESS) = _row[0]; - *(((uint32_t *)NVMCTRL_AUX0_ADDRESS) + 1) = _row[1]; - - /* - Write AUX row. */ - hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)_NVM_USER_ROW_BASE); - hri_nvmctrl_write_CTRLA_reg(hw, NVMCTRL_CTRLA_CMD_WAP | NVMCTRL_CTRLA_CMDEX_KEY); - while (!hri_nvmctrl_get_INTFLAG_reg(hw, NVMCTRL_INTFLAG_READY)) { - /* Wait until this module isn't busy */ - } - - /* Restore CTRLB */ - hri_nvmctrl_write_CTRLB_reg(NVMCTRL, ctrlb); - - return ERR_NONE; -} - -int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size) -{ - uint32_t _row[2]; /* Copy of user row. */ - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - if (!_IN_NVM_USER_ROW(base, offset)) { - return ERR_BAD_ADDRESS; - } else if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { - return ERR_INVALID_ARG; - } - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - return ERR_DENIED; - } else { - return ERR_UNSUPPORTED_OP; - } - - memcpy(_row, base, 8); /* Store previous data. */ - memcpy((uint8_t *)_row + offset, buf, size); /* Modify with buf data. */ - - return _user_row_write_exec(_row); -} - -int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits) -{ - uint32_t _row[2]; /* Copy of user row. */ - uint32_t l_off, l_bits; - uint32_t r_off, r_bits; - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - if (!_IN_NVM_USER_ROW(base, bit_offset >> 3)) { - return ERR_BAD_ADDRESS; - } else if (!_IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)) { - return ERR_INVALID_ARG; - } - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - return ERR_DENIED; - } else { - return ERR_UNSUPPORTED_OP; - } - - /* Since the bitfield can cross 32-bits boundaries, - * left and right bits are splitted for 32-bit aligned address - * and then saved. */ - l_off = bit_offset & (~(32 - 1)); - r_off = l_off + 32; - l_bits = 32 - (bit_offset & (32 - 1)); - if (n_bits > l_bits) { - r_bits = n_bits - l_bits; - } else { - l_bits = n_bits; - r_bits = 0; - } - - memcpy(_row, base, 8); /* Store previous data. */ - if (l_bits) { - uint32_t l_mask = ((1 << l_bits) - 1) << (bit_offset & (32 - 1)); - _row[bit_offset >> 5] &= ~l_mask; - _row[bit_offset >> 5] |= (bits << (bit_offset & (32 - 1))) & l_mask; - } - if (r_bits) { - uint32_t r_mask = (1 << r_bits) - 1; - _row[r_off >> 5] &= ~r_mask; - _row[r_off >> 5] |= bits >> l_bits; - } - return _user_row_write_exec(_row); -} diff --git a/atmel-samd/asf4/samd21/hpl/pm/hpl_pm.c b/atmel-samd/asf4/samd21/hpl/pm/hpl_pm.c deleted file mode 100644 index 2df1169d0..000000000 --- a/atmel-samd/asf4/samd21/hpl/pm/hpl_pm.c +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * \brief SAM Power manager - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include -#include - -/** - * \brief Retrieve the reset reason - */ -enum reset_reason _get_reset_reason(void) -{ - return (enum reset_reason)hri_pm_read_RCAUSE_reg(PM); -} - -/** - * \brief Set the sleep mode for the device - */ -int32_t _set_sleep_mode(const uint8_t mode) -{ - switch (mode) { - case 0: - case 1: - case 2: - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - PM->SLEEP.reg = mode; - return ERR_NONE; - case 3: - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - return ERR_NONE; - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Power Manager Init - */ -void _pm_init(void) -{ - hri_pm_set_CPUSEL_CPUDIV_bf(PM, CONF_CPU_DIV); - hri_pm_set_APBASEL_APBADIV_bf(PM, CONF_APBA_DIV); - hri_pm_set_APBBSEL_APBBDIV_bf(PM, CONF_APBB_DIV); - hri_pm_set_APBCSEL_APBCDIV_bf(PM, CONF_APBC_DIV); -} diff --git a/atmel-samd/asf4/samd21/hpl/pm/hpl_pm_base.h b/atmel-samd/asf4/samd21/hpl/pm/hpl_pm_base.h deleted file mode 100644 index 3f308b426..000000000 --- a/atmel-samd/asf4/samd21/hpl/pm/hpl_pm_base.h +++ /dev/null @@ -1,213 +0,0 @@ -/** - * \file - * - * \brief SAM Power manager - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distributionn. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifndef _HPL_PM_BASE_H_INCLUDED -#define _HPL_PM_BASE_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * \addtogroup pm_group PM Low Level Driver Helpers - * - * \section pm_helpers_rev Revision History - * - v0.0.0.1 Initial Commit - * - *@{ - */ - -/** - * \brief Power Manager buses - */ -enum _pm_bus { PM_BUS_AHB, PM_BUS_APBA, PM_BUS_APBB, PM_BUS_APBC }; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Retrieve AHB index - * - * \param[in] module Module to get index for - * - * \return index of the given module if succeeds, ERR_INVALID_ARG otherwise - */ -static inline int32_t _pm_get_ahb_index(const void *const module) -{ - if ((uint32_t)module == (uint32_t)PM_BUS_APBA) { - return 0; - } else if ((uint32_t)module == (uint32_t)PM_BUS_APBB) { - return 1; - } else if ((uint32_t)module == (uint32_t)PM_BUS_APBC) { - return 2; - } - if ((uint32_t)module == (uint32_t)DSU) { - return 3; - } else if ((uint32_t)module == (uint32_t)NVMCTRL) { - return 4; - } else if ((uint32_t)module == (uint32_t)DMAC) { - return 5; - } -#ifdef USB - else if ((uint32_t)module == (uint32_t)USB) { - return 6; - } -#endif - - return ERR_INVALID_ARG; -} - -/** - * \brief Retrieve APBB index - * - * \param[in] module Module to get index for - * - * \return index of the given module if succeeds, ERR_INVALID_ARG otherwise - */ -static inline int32_t _pm_get_apbb_index(const void *const module) -{ - if ((uint32_t)module == (uint32_t)PAC1) { - return 0; - } else if ((uint32_t)module == (uint32_t)DSU) { - return 1; - } else if ((uint32_t)module == (uint32_t)NVMCTRL) { - return 2; - } - if ((uint32_t)module == (uint32_t)PORT) { - return 3; - } else if ((uint32_t)module == (uint32_t)DMAC) { - return 4; - } -#ifdef USB - else if ((uint32_t)module == (uint32_t)USB) { - return 5; - } -#endif - - return ERR_INVALID_ARG; -} - -/** - * \brief Enable clock on the given bus for the given hardware module - * - * This function enables clock on the given bus for the given hardware module. - * For an overview of available buses and hardware modules see datasheet. - * - * \param[in] bus A bus to enable clock on - * \param[in] module A hardware module to enable clock for - */ -static inline void _pm_enable_bus_clock(const enum _pm_bus bus, const void *const module) -{ - uint32_t peripheral = ((uint32_t)module & 0x0000ff00) >> 10; - - switch (bus) { - case PM_BUS_AHB: - if (_pm_get_ahb_index(module) >= 0) { - peripheral = (uint32_t)_pm_get_ahb_index(module); - PM->AHBMASK.reg |= 1 << peripheral; - } - break; - case PM_BUS_APBA: - PM->APBAMASK.reg |= 1 << peripheral; - break; - case PM_BUS_APBB: - if (_pm_get_apbb_index(module) >= 0) { - peripheral = (uint32_t)_pm_get_apbb_index(module); - PM->APBBMASK.reg |= 1 << peripheral; - } - break; - case PM_BUS_APBC: - PM->APBCMASK.reg |= 1 << peripheral; - break; - default: - ASSERT(false); - break; - } -} - -/** - * \brief Disable clock on the given bus for the given hardware module - * - * This function disables clock on the given bus for the given hardware module. - * For an overview of available buses and hardware modules see datasheet. - * - * \param[in] bus A bus to disable clock on - * \param[in] module A hardware module to disable clock for - */ -static inline void _pm_disable_bus_clock(const enum _pm_bus bus, const void *const module) -{ - uint32_t peripheral = ((uint32_t)module & 0x0000ff00) >> 10; - - switch (bus) { - case PM_BUS_AHB: - if (_pm_get_ahb_index(module) >= 0) { - peripheral = (uint32_t)_pm_get_ahb_index(module); - PM->AHBMASK.reg &= ~(1 << peripheral); - } - break; - case PM_BUS_APBA: - PM->APBAMASK.reg &= ~(1 << peripheral); - break; - case PM_BUS_APBB: - if (_pm_get_apbb_index(module) >= 0) { - peripheral = (uint32_t)_pm_get_apbb_index(module); - PM->APBBMASK.reg &= ~(1 << peripheral); - } - break; - case PM_BUS_APBC: - PM->APBCMASK.reg &= ~(1 << peripheral); - break; - default: - ASSERT(false); - break; - } -} - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/port/hpl_gpio_base.h b/atmel-samd/asf4/samd21/hpl/port/hpl_gpio_base.h deleted file mode 100644 index 6ff4dcaa9..000000000 --- a/atmel-samd/asf4/samd21/hpl/port/hpl_gpio_base.h +++ /dev/null @@ -1,172 +0,0 @@ -/** - * \file - * - * \brief SAM PORT. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#include -#include -#include - -/** - * \brief Set direction on port with mask - */ -static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction) -{ - switch (direction) { - case GPIO_DIRECTION_OFF: - hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg( - PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); - break; - - case GPIO_DIRECTION_IN: - hri_port_clear_DIR_reg(PORT_IOBUS, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg(PORT, - port, - PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN - | ((mask & 0xffff0000) >> 16)); - break; - - case GPIO_DIRECTION_OUT: - hri_port_set_DIR_reg(PORT_IOBUS, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg( - PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); - break; - - default: - ASSERT(false); - } -} - -/** - * \brief Set output level on port with mask - */ -static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) -{ - if (level) { - hri_port_set_OUT_reg(PORT_IOBUS, port, mask); - } else { - hri_port_clear_OUT_reg(PORT_IOBUS, port, mask); - } -} - -/** - * \brief Change output level to the opposite with mask - */ -static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) -{ - hri_port_toggle_OUT_reg(PORT_IOBUS, port, mask); -} - -/** - * \brief Get input levels on all port pins - */ -static inline uint32_t _gpio_get_level(const enum gpio_port port) -{ - uint32_t tmp; - - CRITICAL_SECTION_ENTER(); - - uint32_t dir_tmp = hri_port_read_DIR_reg(PORT_IOBUS, port); - - tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; - tmp |= hri_port_read_OUT_reg(PORT_IOBUS, port) & dir_tmp; - - CRITICAL_SECTION_LEAVE(); - - return tmp; -} - -/** - * \brief Set pin pull mode - */ -static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, - const enum gpio_pull_mode pull_mode) -{ - switch (pull_mode) { - case GPIO_PULL_OFF: - hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); - break; - - case GPIO_PULL_UP: - hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); - hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); - hri_port_set_OUT_reg(PORT_IOBUS, port, 1U << pin); - break; - - case GPIO_PULL_DOWN: - hri_port_clear_DIR_reg(PORT_IOBUS, port, 1U << pin); - hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); - hri_port_clear_OUT_reg(PORT_IOBUS, port, 1U << pin); - break; - - default: - ASSERT(false); - break; - } -} - -/** - * \brief Set gpio pin function - */ -static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) -{ - uint8_t port = GPIO_PORT(gpio); - uint8_t pin = GPIO_PIN(gpio); - - if (function == GPIO_PIN_FUNCTION_OFF) { - hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); - - } else { - hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); - - if (pin & 1) { - // Odd numbered pin - hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); - } else { - // Even numbered pin - hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); - } - } -} diff --git a/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc.c b/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc.c deleted file mode 100644 index 80fca2b5b..000000000 --- a/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc.c +++ /dev/null @@ -1,201 +0,0 @@ -/** - * \file - * - * \brief RTC Driver (Calendar Mode) - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hpl_calendar.h" -#include "hpl_timer.h" -#include -#include - -/*!< Pointer to hpl device */ - -static struct _timer_device *_rtc_dev = NULL; - -/** - * \brief Initialize Timer - */ -int32_t _timer_init(struct _timer_device *const dev, void *const hw) -{ - ASSERT(dev); - - uint16_t register_value; - dev->hw = hw; - - hri_rtcmode0_write_CTRL_reg(dev->hw, RTC_MODE0_CTRL_SWRST); - hri_rtcmode0_wait_for_sync(dev->hw); - - /* Set mode 0 */ - register_value = RTC_MODE0_CTRL_MODE(0); - - /* Set prescaler */ - register_value |= RTC_MODE0_CTRL_PRESCALER(CONF_RTC_PRESCALER); - - /* clear counter on compare/timer match */ - register_value |= RTC_MODE0_CTRL_MATCHCLR; - - hri_rtcmode0_write_CTRL_reg(dev->hw, register_value); - - hri_rtcmode0_write_COMP_COMP_bf(dev->hw, 0, CONF_RTC_COMP_VAL); - hri_rtcmode0_set_INTEN_CMP0_bit(dev->hw); - -/* set event control */ -#if CONF_RTC_EVENT_CONTROL_ENABLE == 1 - hri_rtcmode0_write_EVCTRL_reg(dev->hw, - (CONF_RTC_PEREO0 << RTC_MODE0_EVCTRL_PEREO0_Pos) - | (CONF_RTC_PEREO1 << RTC_MODE0_EVCTRL_PEREO1_Pos) - | (CONF_RTC_PEREO2 << RTC_MODE0_EVCTRL_PEREO2_Pos) - | (CONF_RTC_PEREO3 << RTC_MODE0_EVCTRL_PEREO3_Pos) - | (CONF_RTC_PEREO4 << RTC_MODE0_EVCTRL_PEREO4_Pos) - | (CONF_RTC_PEREO5 << RTC_MODE0_EVCTRL_PEREO5_Pos) - | (CONF_RTC_PEREO6 << RTC_MODE0_EVCTRL_PEREO6_Pos) - | (CONF_RTC_PEREO7 << RTC_MODE0_EVCTRL_PEREO7_Pos) - | (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) - | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos)); -#endif - - _rtc_dev = dev; - - return ERR_NONE; -} - -/** - * \brief De-initialize Timer - */ -void _timer_deinit(struct _timer_device *const dev) -{ - ASSERT(dev && dev->hw); - - NVIC_DisableIRQ(RTC_IRQn); - - hri_rtcmode0_write_CTRL_reg(dev->hw, RTC_MODE0_CTRL_SWRST); -} - -/** - * \brief Start hardware timer - */ -void _timer_start(struct _timer_device *const dev) -{ - ASSERT(dev && dev->hw); - - NVIC_EnableIRQ(RTC_IRQn); - hri_rtcmode0_write_COUNT_COUNT_bf(dev->hw, 0); - hri_rtcmode0_wait_for_sync(dev->hw); - hri_rtcmode0_set_CTRL_ENABLE_bit(dev->hw); -} - -/** - * \brief Stop hardware timer - */ -void _timer_stop(struct _timer_device *const dev) -{ - ASSERT(dev && dev->hw); - - hri_rtcmode0_clear_CTRL_ENABLE_bit(dev->hw); -} - -/** - * \brief Set timer period - */ -void _timer_set_period(struct _timer_device *const dev, const uint32_t clock_cycles) -{ - hri_rtcmode0_write_COMP_COMP_bf(dev->hw, 0, clock_cycles); -} - -/** - * \brief Retrieve timer period - */ -uint32_t _timer_get_period(const struct _timer_device *const dev) -{ - return hri_rtcmode0_read_COMP_COMP_bf(dev->hw, 0); -} - -/** - * \brief Check if timer is running - */ -bool _timer_is_started(const struct _timer_device *const dev) -{ - return hri_rtcmode0_get_CTRL_ENABLE_bit(dev->hw); -} - -/** - * \brief Set timer IRQ - */ -void _timer_set_irq(struct _timer_device *const dev) -{ - (void)dev; -} - -/** - * \brief RTC Timer interrupt handler - * - * \param[in] p The pointer to calendar device struct - */ -static void _rtc_timer_interrupt_handler(struct _timer_device *dev) -{ - /* Read and mask interrupt flag register */ - uint16_t flag = hri_rtcmode0_read_INTFLAG_reg(dev->hw); - - if (flag & RTC_MODE0_INTFLAG_CMP0) { - if (dev->timer_cb.period_expired) { - dev->timer_cb.period_expired(dev); - } - - /* Clear interrupt flag */ - hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw); - } -} - -/** - * \brief Retrieve timer helper functions - */ -struct _timer_hpl_interface *_rtc_get_timer(void) -{ - return NULL; -} - -/** - * \brief Rtc interrupt handler - */ -void RTC_Handler(void) -{ - _rtc_timer_interrupt_handler(_rtc_dev); -} diff --git a/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc_base.h b/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc_base.h deleted file mode 100644 index bbcf242b9..000000000 --- a/atmel-samd/asf4/samd21/hpl/rtc/hpl_rtc_base.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * \file - * - * \brief RTC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distributionn. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifndef _HPL_RTC2_V200_H_INCLUDED -#define _HPL_RTC2_V200_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Retrieve timer helper functions - * - * \return A pointer to set of timer helper functions - */ -struct _timer_hpl_interface *_rtc_get_timer(void); - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_RTC2_V200_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/sercom/hpl_sercom.c b/atmel-samd/asf4/samd21/hpl/sercom/hpl_sercom.c deleted file mode 100644 index e9898b1d9..000000000 --- a/atmel-samd/asf4/samd21/hpl/sercom/hpl_sercom.c +++ /dev/null @@ -1,2897 +0,0 @@ - -/** - * \file - * - * \brief SAM Serial Communication Interface - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONF_SERCOM_0_USART_ENABLE -#define CONF_SERCOM_0_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_USART_ENABLE -#define CONF_SERCOM_1_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_USART_ENABLE -#define CONF_SERCOM_2_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_USART_ENABLE -#define CONF_SERCOM_3_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_USART_ENABLE -#define CONF_SERCOM_4_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_USART_ENABLE -#define CONF_SERCOM_5_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_USART_ENABLE -#define CONF_SERCOM_6_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_USART_ENABLE -#define CONF_SERCOM_7_USART_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as USART. */ -#define SERCOM_USART_AMOUNT \ - (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ - + CONF_SERCOM_4_USART_ENABLE \ - + CONF_SERCOM_5_USART_ENABLE \ - + CONF_SERCOM_6_USART_ENABLE \ - + CONF_SERCOM_7_USART_ENABLE) - -/** - * \brief Macro is used to fill usart configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define SERCOM_CONFIGURATION(n) \ - { \ - n, SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ - | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ - | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ - | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ - | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ - | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ - | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ - | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ - | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ - | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ - SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ - | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ - | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ - | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ - | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ - | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ - (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ - CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ - } - -/** - * \brief SERCOM USART configuration type - */ -struct usart_configuration { - uint8_t number; - hri_sercomusart_ctrla_reg_t ctrl_a; - hri_sercomusart_ctrlb_reg_t ctrl_b; - hri_sercomusart_baud_reg_t baud; - uint8_t fractional; - hri_sercomusart_rxpl_reg_t rxpl; - hri_sercomusart_dbgctrl_reg_t debug_ctrl; -}; - -#if SERCOM_USART_AMOUNT < 1 -/** Dummy array to pass compiling. */ -static struct usart_configuration _usarts[1] = {{0}}; -#else -/** - * \brief Array of SERCOM USART configurations - */ -static struct usart_configuration _usarts[] = { -#if CONF_SERCOM_0_USART_ENABLE == 1 - SERCOM_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_USART_ENABLE == 1 - SERCOM_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_USART_ENABLE == 1 - SERCOM_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_USART_ENABLE == 1 - SERCOM_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_USART_ENABLE == 1 - SERCOM_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_USART_ENABLE == 1 - SERCOM_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_USART_ENABLE == 1 - SERCOM_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_USART_ENABLE == 1 - SERCOM_CONFIGURATION(7), -#endif -}; -#endif - -static uint8_t _get_sercom_index(const void *const hw); -static uint8_t _sercom_get_irq_num(const void *const hw); -static void _sercom_init_irq_param(const void *const hw, void *dev); -static uint8_t _sercom_get_hardware_index(const void *const hw); - -static int32_t _usart_init(void *const hw); -static inline void _usart_deinit(void *const hw); -static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); -static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); -static void _usart_set_data_order(void *const hw, const enum usart_data_order order); -static void _usart_set_mode(void *const hw, const enum usart_mode mode); -static void _usart_set_parity(void *const hw, const enum usart_parity parity); -static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); -static void _usart_set_character_size(void *const hw, const enum usart_character_size size); - -/** - * \brief Initialize synchronous SERCOM USART - */ -int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) -{ - ASSERT(device); - - device->hw = hw; - - return _usart_init(hw); -} - -/** - * \brief Initialize asynchronous SERCOM USART - */ -int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _usart_init(hw); - if (init_status) { - return init_status; - } - device->hw = hw; - _sercom_init_irq_param(hw, (void *)device); - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - return ERR_NONE; -} - -/** - * \brief De-initialize SERCOM USART - */ -void _usart_sync_deinit(struct _usart_sync_device *const device) -{ - _usart_deinit(device->hw); -} - -/** - * \brief De-initialize SERCOM USART - */ -void _usart_async_deinit(struct _usart_async_device *const device) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); - _usart_deinit(device->hw); -} - -/** - * \brief Calculate baud rate register value - */ -uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); -} - -/** - * \brief Calculate baud rate register value - */ -uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); -} - -/** - * \brief Enable SERCOM module - */ -void _usart_sync_enable(struct _usart_sync_device *const device) -{ - hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Enable SERCOM module - */ -void _usart_async_enable(struct _usart_async_device *const device) -{ - hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable SERCOM module - */ -void _usart_sync_disable(struct _usart_sync_device *const device) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable SERCOM module - */ -void _usart_async_disable(struct _usart_async_device *const device) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Set baud rate - */ -void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) -{ - _usart_set_baud_rate(device->hw, baud_rate); -} - -/** - * \brief Set baud rate - */ -void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) -{ - _usart_set_baud_rate(device->hw, baud_rate); -} - -/** - * \brief Set data order - */ -void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) -{ - _usart_set_data_order(device->hw, order); -} - -/** - * \brief Set data order - */ -void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) -{ - _usart_set_data_order(device->hw, order); -} - -/** - * \brief Set mode - */ -void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) -{ - _usart_set_mode(device->hw, mode); -} - -/** - * \brief Set mode - */ -void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) -{ - _usart_set_mode(device->hw, mode); -} - -/** - * \brief Set parity - */ -void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) -{ - _usart_set_parity(device->hw, parity); -} - -/** - * \brief Set parity - */ -void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) -{ - _usart_set_parity(device->hw, parity); -} - -/** - * \brief Set stop bits mode - */ -void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) -{ - _usart_set_stop_bits(device->hw, stop_bits); -} - -/** - * \brief Set stop bits mode - */ -void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) -{ - _usart_set_stop_bits(device->hw, stop_bits); -} - -/** - * \brief Set character size - */ -void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) -{ - _usart_set_character_size(device->hw, size); -} - -/** - * \brief Set character size - */ -void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) -{ - _usart_set_character_size(device->hw, size); -} - -/** - * \brief Retrieve SERCOM usart status - */ -uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_read_STATUS_reg(device->hw); -} - -/** - * \brief Retrieve SERCOM usart status - */ -uint32_t _usart_async_get_status(const struct _usart_async_device *const device) -{ - return hri_sercomusart_read_STATUS_reg(device->hw); -} - -/** - * \brief Write a byte to the given SERCOM USART instance - */ -void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) -{ - hri_sercomusart_write_DATA_reg(device->hw, data); -} - -/** - * \brief Write a byte to the given SERCOM USART instance - */ -void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) -{ - hri_sercomusart_write_DATA_reg(device->hw, data); -} - -/** - * \brief Read a byte from the given SERCOM USART instance - */ -uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_read_DATA_reg(device->hw); -} - -/** - * \brief Check if USART is ready to send next byte - */ -bool _usart_sync_is_byte_sent(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_DRE_bit(device->hw); -} - -/** - * \brief Check if USART is ready to send next byte - */ -bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) -{ - return hri_sercomusart_get_interrupt_DRE_bit(device->hw); -} - -/** - * \brief Check if there is data received by USART - */ -bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_RXC_bit(device->hw); -} - -/** - * \brief Set the state of flow control pins - */ -void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, - const union usart_flow_control_state state) -{ - (void)device; - (void)state; -} - -/** - * \brief Set the state of flow control pins - */ -void _usart_async_set_flow_control_state(struct _usart_async_device *const device, - const union usart_flow_control_state state) -{ - (void)device; - (void)state; -} - -/** - * \brief Retrieve the state of flow control pins - */ -union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) -{ - (void)device; - union usart_flow_control_state state; - - state.value = 0; - state.bit.unavailable = 1; - return state; -} - -/** - * \brief Retrieve the state of flow control pins - */ -union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) -{ - (void)device; - union usart_flow_control_state state; - - state.value = 0; - state.bit.unavailable = 1; - return state; -} - -/** - * \brief Enable data register empty interrupt - */ -void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) -{ - hri_sercomusart_set_INTEN_DRE_bit(device->hw); -} - -/** - * \brief Enable transmission complete interrupt - */ -void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) -{ - hri_sercomusart_set_INTEN_TXC_bit(device->hw); -} - -/** - * \brief Retrieve ordinal number of the given sercom hardware instance - */ -static uint8_t _sercom_get_hardware_index(const void *const hw) -{ -#ifdef _UNIT_TEST_ - return ((uint32_t)hw - (uint32_t)SERCOM0) / sizeof(Sercom); -#endif - -#if defined __SAML21E18B__ || defined __ATSAML21E18B__ || defined __SAML21G18B__ || defined __ATSAML21G18B__ \ - || defined __SAML21J18B__ || defined __ATSAML21J18B__ || defined __ATSAMR30G18A__ || defined __ATSAMR30E18A__ - if ((uint32_t)SERCOM5 == (uint32_t)hw) { - return 5; - } -#endif - - return ((uint32_t)hw - (uint32_t)SERCOM0) >> 10; -} - -/** - * \brief Retrieve ordinal number of the given SERCOM USART hardware instance - */ -uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) -{ - return _sercom_get_hardware_index(device->hw); -} - -/** - * \brief Retrieve ordinal number of the given SERCOM USART hardware instance - */ -uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) -{ - return _sercom_get_hardware_index(device->hw); -} - -/** - * \brief Enable/disable USART interrupt - */ -void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, - const bool state) -{ - ASSERT(device); - - if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { - hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); - hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); - } else if (USART_ASYNC_RX_DONE == type) { - hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); - } else if (USART_ASYNC_ERROR == type) { - hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - - * \return The ordinal number of the given sercom hardware instance - */ -static uint8_t _get_sercom_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_usarts); i++) { - if (_usarts[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return 0; -} - -/** - * \brief Init irq param with the given sercom hardware instance - */ -static void _sercom_init_irq_param(const void *const hw, void *dev) -{ -} - -/** - * \internal Initialize SERCOM USART - * - * \param[in] hw The pointer to hardware instance - * - * \return The status of initialization - */ -static int32_t _usart_init(void *const hw) -{ - uint8_t i = _get_sercom_index(hw); - - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - if (hri_sercomusart_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_sercomusart_set_CTRLA_SWRST_bit(hw); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - - hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); - hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); - if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { - ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; - ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; - } else { - hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); - } - - hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); - hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); - - return ERR_NONE; -} - -/** - * \internal De-initialize SERCOM USART - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _usart_deinit(void *const hw) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - hri_sercomusart_set_CTRLA_SWRST_bit(hw); -} - -/** - * \internal Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate SERCOM clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { - return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; - } - - if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { - return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); - } - - if (USART_BAUDRATE_SYNCH == mode) { - return clock_rate / baud / 2 - 1; - } - - return 0; -} - -/** - * \internal Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_BAUD_reg(hw, baud_rate); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -static void _usart_set_data_order(void *const hw, const enum usart_data_order order) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLA_DORD_bit(hw, order); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -static void _usart_set_mode(void *const hw, const enum usart_mode mode) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -static void _usart_set_parity(void *const hw, const enum usart_parity parity) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - - if (USART_PARITY_NONE != parity) { - hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); - } else { - hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); - } - - hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -static void _usart_set_character_size(void *const hw, const enum usart_character_size size) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); - CRITICAL_SECTION_LEAVE() - - if (enabled) { - hri_sercomusart_set_CTRLA_ENABLE_bit(hw); - } -} - -/* Sercom I2C implementation */ - -#ifndef CONF_SERCOM_0_I2CM_ENABLE -#define CONF_SERCOM_0_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_I2CM_ENABLE -#define CONF_SERCOM_1_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_I2CM_ENABLE -#define CONF_SERCOM_2_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_I2CM_ENABLE -#define CONF_SERCOM_3_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_I2CM_ENABLE -#define CONF_SERCOM_4_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_I2CM_ENABLE -#define CONF_SERCOM_5_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_I2CM_ENABLE -#define CONF_SERCOM_6_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_I2CM_ENABLE -#define CONF_SERCOM_7_I2CM_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as I2C Master. */ -#define SERCOM_I2CM_AMOUNT \ - (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ - + CONF_SERCOM_4_I2CM_ENABLE \ - + CONF_SERCOM_5_I2CM_ENABLE \ - + CONF_SERCOM_6_I2CM_ENABLE \ - + CONF_SERCOM_7_I2CM_ENABLE) - -/** - * \brief Macro is used to fill i2cm configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define I2CM_CONFIGURATION(n) \ - { \ - (n), (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ - | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ - | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ - SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ - CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ - } - -#define ERROR_FLAG (1 << 7) -#define SB_FLAG (1 << 1) -#define MB_FLAG (1 << 0) - -#define CMD_STOP 0x3 -#define I2C_IDLE 0x1 -#define I2C_SM 0x0 -#define I2C_FM 0x1 -#define I2C_HS 0x2 -#define TEN_ADDR_FRAME 0x78 -#define TEN_ADDR_MASK 0x3ff -#define SEVEN_ADDR_MASK 0x7f - -/** - * \brief SERCOM I2CM configuration type - */ -struct i2cm_configuration { - uint8_t number; - hri_sercomi2cm_ctrla_reg_t ctrl_a; - hri_sercomi2cm_ctrlb_reg_t ctrl_b; - hri_sercomi2cm_baud_reg_t baud; - hri_sercomi2cm_dbgctrl_reg_t dbgctrl; - uint16_t trise; - uint32_t clk; /* SERCOM peripheral clock frequency */ -}; - -static inline void _i2c_m_enable_implementation(void *hw); -static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); - -#if SERCOM_I2CM_AMOUNT < 1 -/** Dummy array to pass compiling. */ -static struct i2cm_configuration _i2cms[1] = {{0}}; -#else -/** - * \brief Array of SERCOM I2CM configurations - */ -static struct i2cm_configuration _i2cms[] = { -#if CONF_SERCOM_0_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(7), -#endif -}; -#endif - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - - * \return The ordinal number of the given sercom hardware instance - */ -static int8_t _get_i2cm_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { - if (_i2cms[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return -1; -} - -static inline void _sercom_i2c_send_stop(void *const hw) -{ - hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); -} - -/** - * \brief SERCOM I2CM analyze hardware status and transfer next byte - */ -static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) -{ - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); - - if (flags & MB_FLAG) { - /* tx error */ - if (status & SERCOM_I2CM_STATUS_ARBLOST) { - hri_sercomi2cm_clear_interrupt_MB_bit(hw); - msg->flags |= I2C_M_FAIL; - msg->flags &= ~I2C_M_BUSY; - - if (status & SERCOM_I2CM_STATUS_BUSERR) { - return I2C_ERR_BUS; - } - - return I2C_ERR_BAD_ADDRESS; - } else { - if (status & SERCOM_I2CM_STATUS_RXNACK) { - - /* Slave rejects to receive more data */ - if (msg->len > 0) { - msg->flags |= I2C_M_FAIL; - } - - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - - return I2C_NACK; - } - - if (msg->flags & I2C_M_TEN) { - hri_sercomi2cm_write_ADDR_reg(hw, - ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - msg->flags &= ~I2C_M_TEN; - - return I2C_OK; - } - - if (msg->len == 0) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - } else { - hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); - msg->buffer++; - msg->len--; - } - - return I2C_OK; - } - } else if (flags & SB_FLAG) { - if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { - msg->len--; - - /* last byte, send nack */ - if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } - - if (msg->len == 0) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - } - - /* Accessing DATA.DATA auto-triggers I2C bus operations. - * The operation performed depends on the state of - * CTRLB.ACKACT, CTRLB.SMEN - **/ - *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); - } else { - hri_sercomi2cm_clear_interrupt_SB_bit(hw); - return I2C_NACK; - } - - hri_sercomi2cm_clear_interrupt_SB_bit(hw); - } - - return I2C_OK; -} - -/** - * \brief Enable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - _i2c_m_enable_implementation(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Disable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** - * \brief Set baudrate of master - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] clkrate The clock rate of i2c master, in KHz - * \param[in] baudrate The baud rate desired for i2c master, in KHz - */ -int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) -{ - uint32_t tmp; - void * hw = i2c_dev->hw; - - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - - tmp = _get_i2cm_index(hw); - clkrate = _i2cms[tmp].clk / 1000; - - if (i2c_dev->service.mode == I2C_STANDARD_MODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_FASTMODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { - tmp = (clkrate - 2 * baudrate) / (2 * baudrate); - hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); - } else { - /* error baudrate */ - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Retrieve IRQ number for the given hardware instance - */ -static uint8_t _sercom_get_irq_num(const void *const hw) -{ - return SERCOM0_IRQn + _sercom_get_hardware_index(hw); -} - -/** - * \brief Initialize sercom i2c module to use in async mode - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) -{ - int32_t init_status; - - ASSERT(i2c_dev); - - i2c_dev->hw = hw; - - init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); - if (init_status) { - return init_status; - } - - _sercom_init_irq_param(hw, (void *)i2c_dev); - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - return ERR_NONE; -} - -/** - * \brief Deinitialize sercom i2c module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); - hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Transfer the slave address to bus, which will start the transfer - * - * \param[in] i2c_dev The pointer to i2c device - */ -static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) -{ - void * hw = i2c_dev->hw; - struct _i2c_m_msg *msg = &i2c_dev->service.msg; - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - - ASSERT(i2c_dev); - - if (msg->len == 1 && sclsm) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } else { - hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); - } - - /* ten bit address */ - if (msg->addr & I2C_M_TEN) { - if (msg->flags & I2C_M_RD) { - msg->flags |= I2C_M_TEN; - } - - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } else { - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } - - return ERR_NONE; -} - -/** - * \brief Transfer data specified by msg - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] msg The pointer to i2c message - * - * \return Transfer status. - * \retval 0 Transfer success - * \retval <0 Transfer fail, return the error code - */ -int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) -{ - int ret; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - ASSERT(msg); - - if (msg->len == 0) { - return ERR_NONE; - } - - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return ERR_BUSY; - } - - msg->flags |= I2C_M_BUSY; - i2c_dev->service.msg = *msg; - - ret = _sercom_i2c_send_address(i2c_dev); - - if (ret) { - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Set callback to be called in interrupt handler - * - * \param[in] i2c_dev The pointer to master i2c device - * \param[in] type The callback type - * \param[in] func The callback function pointer - */ -int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, - FUNC_PTR func) -{ - switch (type) { - case I2C_M_ASYNC_DEVICE_ERROR: - i2c_dev->cb.error = (_i2c_error_cb_t)func; - break; - case I2C_M_ASYNC_DEVICE_TX_COMPLETE: - i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; - break; - case I2C_M_ASYNC_DEVICE_RX_COMPLETE: - i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; - break; - default: - /* error */ - break; - } - - return ERR_NONE; -} - -/** - * \brief Set stop condition on I2C - * - * \param i2c_dev Pointer to master i2c device - * - * \return Operation status - * \retval I2C_OK Operation was successfull - */ -int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - _sercom_i2c_send_stop(hw); - - return I2C_OK; -} - -/** - * \brief Get number of bytes left in transfer buffer - * - * \param i2c_dev Pointer to i2c master device - * - * \return Bytes left in buffer - * \retval =>0 Bytes left in buffer - */ -int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) -{ - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return i2c_dev->service.msg.len; - } - - return 0; -} - -/** - * \brief Initialize sercom i2c module to use in sync mode - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) -{ - ASSERT(i2c_dev); - - i2c_dev->hw = hw; - - return _i2c_m_sync_init_impl(&i2c_dev->service, hw); -} - -/** - * \brief Deinitialize sercom i2c module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); - hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Enable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - _i2c_m_enable_implementation(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Disable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** - * \brief Set baudrate of master - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] clkrate The clock rate of i2c master, in KHz - * \param[in] baudrate The baud rate desired for i2c master, in KHz - */ -int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) -{ - uint32_t tmp; - void * hw = i2c_dev->hw; - - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - - tmp = _get_i2cm_index(hw); - clkrate = _i2cms[tmp].clk / 1000; - - if (i2c_dev->service.mode == I2C_STANDARD_MODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_FASTMODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { - tmp = (clkrate - 2 * baudrate) / (2 * baudrate); - hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); - } else { - /* error baudrate */ - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Enable/disable I2C master interrupt - */ -void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, - const bool state) -{ - if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { - hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); - hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); - } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { - hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \brief Wait for bus response - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] flags Store the hardware response - * - * \return Bus response status. - * \retval 0 Bus response status OK - * \retval <0 Bus response fail - */ -inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) -{ - uint32_t timeout = 65535; - void * hw = i2c_dev->hw; - - do { - *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); - - if (timeout-- == 0) { - return I2C_ERR_BUS; - } - } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); - - return I2C_OK; -} - -/** - * \brief Send the slave address to bus, which will start the transfer - * - * \param[in] i2c_dev The pointer to i2c device - */ -static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) -{ - void * hw = i2c_dev->hw; - struct _i2c_m_msg *msg = &i2c_dev->service.msg; - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - uint32_t flags; - - ASSERT(i2c_dev); - - if (msg->len == 1 && sclsm) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } else { - hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); - } - - /* ten bit address */ - if (msg->addr & I2C_M_TEN) { - if (msg->flags & I2C_M_RD) { - msg->flags |= I2C_M_TEN; - } - - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } else { - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } - - _sercom_i2c_sync_wait_bus(i2c_dev, &flags); - return _sercom_i2c_sync_analyse_flags(hw, flags, msg); -} - -/** - * \brief Transfer data specified by msg - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] msg The pointer to i2c message - * - * \return Transfer status. - * \retval 0 Transfer success - * \retval <0 Transfer fail or partial fail, return the error code - */ -int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) -{ - uint32_t flags; - int ret; - void * hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - ASSERT(msg); - - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return I2C_ERR_BUSY; - } - - msg->flags |= I2C_M_BUSY; - i2c_dev->service.msg = *msg; - - ret = _sercom_i2c_sync_send_address(i2c_dev); - - if (ret) { - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - while (i2c_dev->service.msg.flags & I2C_M_BUSY) { - ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); - - if (ret) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); - } - - return ret; -} - -int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - _sercom_i2c_send_stop(hw); - - return I2C_OK; -} - -static inline void _i2c_m_enable_implementation(void *const hw) -{ - int timeout = 65535; - - ASSERT(hw); - - /* Enable interrupts */ - hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); - - while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { - timeout--; - - if (timeout <= 0) { - hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); - } - } -} - -static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) -{ - uint8_t i = _get_i2cm_index(hw); - - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - /* Check if module is enabled. */ - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_sercomi2cm_set_CTRLA_SWRST_bit(hw); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - - hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); - hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); - hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); - - service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); - - service->trise = _i2cms[i].trise; - - return ERR_NONE; -} - -/* SERCOM I2C slave */ - -#ifndef CONF_SERCOM_0_I2CS_ENABLE -#define CONF_SERCOM_0_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_I2CS_ENABLE -#define CONF_SERCOM_1_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_I2CS_ENABLE -#define CONF_SERCOM_2_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_I2CS_ENABLE -#define CONF_SERCOM_3_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_I2CS_ENABLE -#define CONF_SERCOM_4_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_I2CS_ENABLE -#define CONF_SERCOM_5_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_I2CS_ENABLE -#define CONF_SERCOM_6_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_I2CS_ENABLE -#define CONF_SERCOM_7_I2CS_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as I2C Slave. */ -#define SERCOM_I2CS_AMOUNT \ - (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ - + CONF_SERCOM_4_I2CS_ENABLE \ - + CONF_SERCOM_5_I2CS_ENABLE \ - + CONF_SERCOM_6_I2CS_ENABLE \ - + CONF_SERCOM_7_I2CS_ENABLE) - -/** - * \brief Macro is used to fill I2C slave configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define I2CS_CONFIGURATION(n) \ - { \ - n, SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ - | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ - | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ - | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ - | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ - SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ - (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ - | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ - | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ - | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ - } - -/** - * \brief Macro to check 10-bit addressing - */ -#define I2CS_7BIT_ADDRESSING_MASK 0x7F - -static int32_t _i2c_s_init(void *const hw); -static int8_t _get_i2c_s_index(const void *const hw); -static inline void _i2c_s_deinit(void *const hw); -static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); - -/** - * \brief SERCOM I2C slave configuration type - */ -struct i2cs_configuration { - uint8_t number; - hri_sercomi2cs_ctrla_reg_t ctrl_a; - hri_sercomi2cs_ctrlb_reg_t ctrl_b; - hri_sercomi2cs_addr_reg_t address; -}; - -#if SERCOM_I2CS_AMOUNT < 1 -/** Dummy array for compiling. */ -static struct i2cs_configuration _i2css[1] = {{0}}; -#else -/** - * \brief Array of SERCOM I2C slave configurations - */ -static struct i2cs_configuration _i2css[] = { -#if CONF_SERCOM_0_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(5), -#endif -}; -#endif - -/** - * \brief Initialize synchronous I2C slave - */ -int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) -{ - int32_t status; - - ASSERT(device); - - status = _i2c_s_init(hw); - if (status) { - return status; - } - device->hw = hw; - - return ERR_NONE; -} - -/** - * \brief Initialize asynchronous I2C slave - */ -int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _i2c_s_init(hw); - if (init_status) { - return init_status; - } - - device->hw = hw; - _sercom_init_irq_param(hw, (void *)device); - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - return ERR_NONE; -} - -/** - * \brief Deinitialize synchronous I2C - */ -int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) -{ - _i2c_s_deinit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Deinitialize asynchronous I2C - */ -int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); - _i2c_s_deinit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable I2C module - */ -int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable I2C module - */ -int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Disable I2C module - */ -int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Disable I2C module - */ -int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Check if 10-bit addressing mode is on - */ -int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); -} - -/** - * \brief Check if 10-bit addressing mode is on - */ -int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) -{ - return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); -} - -/** - * \brief Set I2C slave address - */ -int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) -{ - return _i2c_s_set_address(device->hw, address); -} - -/** - * \brief Set I2C slave address - */ -int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) -{ - return _i2c_s_set_address(device->hw, address); -} - -/** - * \brief Write a byte to the given I2C instance - */ -void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) -{ - hri_sercomi2cs_write_DATA_reg(device->hw, data); -} - -/** - * \brief Write a byte to the given I2C instance - */ -void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) -{ - hri_sercomi2cs_write_DATA_reg(device->hw, data); -} - -/** - * \brief Read a byte from the given I2C instance - */ -uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_read_DATA_reg(device->hw); -} - -/** - * \brief Check if I2C is ready to send next byt - */ -bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); -} - -/** - * \brief Check if there is data received by I2C - */ -bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); -} - -/** - * \brief Retrieve I2C slave status - */ -i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_read_STATUS_reg(device->hw); -} - -/** - * \brief Retrieve I2C slave status - */ -i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) -{ - return hri_sercomi2cs_read_STATUS_reg(device->hw); -} - -/** - * \brief Abort data transmission - */ -int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable/disable I2C slave interrupt - */ -int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, - const bool state) -{ - ASSERT(device); - - if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { - hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); - } else if (I2C_S_DEVICE_ERROR == type) { - hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); - } - - return ERR_NONE; -} - -/** - * \internal Initalize i2c slave hardware - * - * \param[in] p The pointer to hardware instance - * - *\ return status of initialization - */ -static int32_t _i2c_s_init(void *const hw) -{ - int8_t i = _get_i2c_s_index(hw); - if (i == -1) { - return ERR_INVALID_ARG; - } - - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_CTRLA_SWRST); - if (hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_CTRLA_SWRST); - - hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); - hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); - hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); - - return ERR_NONE; -} - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - * - * \return The ordinal number of the given sercom hardware instance - */ -static int8_t _get_i2c_s_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_i2css); i++) { - if (_i2css[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return -1; -} - -/** - * \internal De-initialize i2c slave - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _i2c_s_deinit(void *const hw) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); -} - -/** - * \internal De-initialize i2c slave - * - * \param[in] hw The pointer to hardware instance - * \param[in] address Address to set - */ -static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) -{ - bool enabled; - - enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); - CRITICAL_SECTION_LEAVE() - - if (enabled) { - hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); - } - - return ERR_NONE; -} - -/* Sercom SPI implementation */ - -#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE -#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) -#endif - -#define SPI_DEV_IRQ_MODE 0x8000 - -#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) -#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) - -COMPILER_PACK_SET(1) -/** Initialization configuration of registers. */ -struct sercomspi_regs_cfg { - uint32_t ctrla; - uint32_t ctrlb; - uint32_t addr; - uint8_t baud; - uint8_t dbgctrl; - uint16_t dummy_byte; - uint8_t n; -}; -COMPILER_PACK_RESET() - -/** Build configuration from header macros. */ -#define SERCOMSPI_REGS(n) \ - { \ - ((CONF_SERCOM_##n##_SPI_DORD) | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ - | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ - | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ - | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) \ - | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ - | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ - | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ - | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ - ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ - | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ - | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ - | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ - | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ - | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ - (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ - | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ - ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ - (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ - CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ - n /* sercom number */ \ - } - -#ifndef CONF_SERCOM_0_SPI_ENABLE -#define CONF_SERCOM_0_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_SPI_ENABLE -#define CONF_SERCOM_1_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_SPI_ENABLE -#define CONF_SERCOM_2_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_SPI_ENABLE -#define CONF_SERCOM_3_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_SPI_ENABLE -#define CONF_SERCOM_4_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_SPI_ENABLE -#define CONF_SERCOM_5_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_SPI_ENABLE -#define CONF_SERCOM_6_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_SPI_ENABLE -#define CONF_SERCOM_7_SPI_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as SPI */ -#define SERCOM_SPI_AMOUNT \ - (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ - + CONF_SERCOM_4_SPI_ENABLE \ - + CONF_SERCOM_5_SPI_ENABLE \ - + CONF_SERCOM_6_SPI_ENABLE \ - + CONF_SERCOM_7_SPI_ENABLE) - -#if SERCOM_SPI_AMOUNT < 1 -/** Dummy array for compiling. */ -static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; -#else -/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ -static const struct sercomspi_regs_cfg sercomspi_regs[] = { -#if CONF_SERCOM_0_SPI_ENABLE - SERCOMSPI_REGS(0), -#endif -#if CONF_SERCOM_1_SPI_ENABLE - SERCOMSPI_REGS(1), -#endif -#if CONF_SERCOM_2_SPI_ENABLE - SERCOMSPI_REGS(2), -#endif -#if CONF_SERCOM_3_SPI_ENABLE - SERCOMSPI_REGS(3), -#endif -#if CONF_SERCOM_4_SPI_ENABLE - SERCOMSPI_REGS(4), -#endif -#if CONF_SERCOM_5_SPI_ENABLE - SERCOMSPI_REGS(5), -#endif -#if CONF_SERCOM_6_SPI_ENABLE - SERCOMSPI_REGS(6), -#endif -#if CONF_SERCOM_7_SPI_ENABLE - SERCOMSPI_REGS(7), -#endif -}; -#endif - -/** \internal De-initialize SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return De-initialization status - */ -static int32_t _spi_deinit(void *const hw) -{ - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - hri_sercomspi_set_CTRLA_SWRST_bit(hw); - - return ERR_NONE; -} - -/** \internal Enable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Enabling status - */ -static int32_t _spi_sync_enable(void *const hw) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - hri_sercomspi_set_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** \internal Enable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Enabling status - */ -static int32_t _spi_async_enable(void *const hw) -{ - _spi_sync_enable(hw); - NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - return ERR_NONE; -} - -/** \internal Disable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Disabling status - */ -static int32_t _spi_sync_disable(void *const hw) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** \internal Disable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Disabling status - */ -static int32_t _spi_async_disable(void *const hw) -{ - _spi_sync_disable(hw); - hri_sercomspi_clear_INTEN_reg( - hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI mode - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] mode The mode to set - * - * \return Setting mode status - */ -static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) -{ - uint32_t ctrla; - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { - return ERR_BUSY; - } - - ctrla = hri_sercomspi_read_CTRLA_reg(hw); - ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); - ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; - hri_sercomspi_write_CTRLA_reg(hw, ctrla); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI baudrate - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * - * \return Setting baudrate status - */ -static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - hri_sercomspi_write_BAUD_reg(hw, baud_val); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI char size - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * \param[out] size Stored char size - * - * \return Setting char size status - */ -static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) -{ - /* Only 8-bit or 9-bit accepted */ - if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { - return ERR_INVALID_ARG; - } - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { - return ERR_BUSY; - } - - hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); - *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI data order - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * - * \return Setting data order status - */ -static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) -{ - uint32_t ctrla; - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - ctrla = hri_sercomspi_read_CTRLA_reg(hw); - - if (dord == SPI_DATA_ORDER_LSB_1ST) { - ctrla |= SERCOM_SPI_CTRLA_DORD; - } else { - ctrla &= ~SERCOM_SPI_CTRLA_DORD; - } - hri_sercomspi_write_CTRLA_reg(hw, ctrla); - - return ERR_NONE; -} - -/** \brief Load SERCOM registers to init for SPI master mode - * The settings will be applied with default master mode, unsupported things - * are ignored. - * \param[in, out] hw Pointer to the hardware register base. - * \param[in] regs Pointer to register configuration values. - */ -static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) -{ - ASSERT(hw && regs); - hri_sercomspi_write_CTRLA_reg( - hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); - hri_sercomspi_write_CTRLB_reg( - hw, - (regs->ctrlb - & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) - | (SERCOM_SPI_CTRLB_RXEN)); - hri_sercomspi_write_BAUD_reg(hw, regs->baud); - hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); -} - -/** \brief Load SERCOM registers to init for SPI slave mode - * The settings will be applied with default slave mode, unsupported things - * are ignored. - * \param[in, out] hw Pointer to the hardware register base. - * \param[in] regs Pointer to register configuration values. - */ -static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) -{ - ASSERT(hw && regs); - hri_sercomspi_write_CTRLA_reg( - hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); - hri_sercomspi_write_CTRLB_reg(hw, - (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) - | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); - hri_sercomspi_write_ADDR_reg(hw, regs->addr); - hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); - while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) - ; -} - -/** \brief Return the pointer to register settings of specific SERCOM - * \param[in] hw_addr The hardware register base address. - * \return Pointer to register settings of specific SERCOM. - */ -static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) -{ - uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); - uint8_t i; - - for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { - if (sercomspi_regs[i].n == n) { - return &sercomspi_regs[i]; - } - } - - return NULL; -} - -int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) -{ - const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); - - ASSERT(dev && hw); - - if (regs == NULL) { - return ERR_INVALID_ARG; - } - - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - if (hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_sercomspi_set_CTRLA_SWRST_bit(hw); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - dev->prvt = hw; - - if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { - _spi_load_regs_slave(hw, regs); - } else { - _spi_load_regs_master(hw, regs); - } - - /* Load character size from default hardware configuration */ - dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; - - dev->dummy_byte = regs->dummy_byte; - - return ERR_NONE; -} - -int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) -{ - return _spi_m_sync_init(dev, hw); -} - -int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) -{ - struct _spi_async_dev *spid = dev; - /* Do hardware initialize. */ - int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); - - if (rc < 0) { - return rc; - } - - _sercom_init_irq_param(hw, (void *)dev); - /* Initialize callbacks: must use them */ - spid->callbacks.complete = NULL; - spid->callbacks.rx = NULL; - spid->callbacks.tx = NULL; - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - - return ERR_NONE; -} - -int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) -{ - return _spi_m_async_init(dev, hw); -} - -int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - - return _spi_deinit(dev->prvt); -} - -int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - - return _spi_deinit(dev->prvt); -} - -int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) -{ - return _spi_deinit(dev->prvt); -} - -int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) -{ - return _spi_deinit(dev->prvt); -} - -int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_enable(dev->prvt); -} - -int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_enable(dev->prvt); -} - -int32_t _spi_m_async_enable(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_enable(dev->prvt); -} - -int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_enable(dev->prvt); -} - -int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_disable(dev->prvt); -} - -int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_disable(dev->prvt); -} - -int32_t _spi_m_async_disable(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_disable(dev->prvt); -} - -int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_disable(dev->prvt); -} - -int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) -{ - int32_t rc; - ASSERT(dev); - - /* Not accept 0es */ - if (clk == 0 || baud == 0) { - return ERR_INVALID_ARG; - } - - /* Check baudrate range of current assigned clock */ - if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { - return ERR_INVALID_ARG; - } - - rc = ((clk >> 1) / baud) - 1; - return rc; -} - -int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_baudrate(dev->prvt, baud_val); -} - -int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_baudrate(dev->prvt, baud_val); -} - -int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -/** Wait until SPI bus idle. */ -static inline void _spi_wait_bus_idle(void *const hw) -{ - while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { - ; - } - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); -} - -/** Holds run time information for message sync transaction. */ -struct _spi_trans_ctrl { - /** Pointer to transmitting data buffer. */ - uint8_t *txbuf; - /** Pointer to receiving data buffer. */ - uint8_t *rxbuf; - /** Count number of data transmitted. */ - uint32_t txcnt; - /** Count number of data received. */ - uint32_t rxcnt; - /** Data character size. */ - uint8_t char_size; -}; - -/** Check interrupt flag of RXC and update transaction runtime information. */ -static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) -{ - uint32_t data; - - if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { - return false; - } - - data = hri_sercomspi_read_DATA_reg(hw); - - if (ctrl->rxbuf) { - *ctrl->rxbuf++ = (uint8_t)data; - - if (ctrl->char_size > 1) { - *ctrl->rxbuf++ = (uint8_t)(data >> 8); - } - } - - ctrl->rxcnt++; - - return true; -} - -/** Check interrupt flag of DRE and update transaction runtime information. */ -static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, - uint16_t dummy) -{ - uint32_t data; - - if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { - return; - } - - if (ctrl->txbuf) { - data = *ctrl->txbuf++; - - if (ctrl->char_size > 1) { - data |= (*ctrl->txbuf) << 8; - ctrl->txbuf++; - } - } else { - data = dummy; - } - - ctrl->txcnt++; - hri_sercomspi_write_DATA_reg(hw, data); -} - -/** Check interrupt flag of ERROR and update transaction runtime information. */ -static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) -{ - if (SERCOM_SPI_INTFLAG_ERROR & iflag) { - hri_sercomspi_clear_STATUS_reg(hw, ~0); - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); - return ERR_OVERFLOW; - } - - return ERR_NONE; -} - -int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) -{ - void * hw = dev->prvt; - int32_t rc = 0; - struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; - - ASSERT(dev && hw); - - /* If settings are not applied (pending), we can not go on */ - if (hri_sercomspi_is_syncing( - hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { - return ERR_BUSY; - } - - /* SPI must be enabled to start synchronous transfer */ - if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { - return ERR_NOT_INITIALIZED; - } - - for (;;) { - uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); - - if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { - /* In master mode, do not start next byte before previous byte received - * to make better output waveform */ - if (ctrl.rxcnt >= ctrl.txcnt) { - _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); - } - } - - rc = _spi_err_check(iflag, hw); - - if (rc < 0) { - break; - } - if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { - rc = ctrl.txcnt; - break; - } - } - /* Wait until SPI bus idle */ - _spi_wait_bus_idle(hw); - - return rc; -} - -int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (state) { - hri_sercomspi_set_INTEN_DRE_bit(hw); - } else { - hri_sercomspi_clear_INTEN_DRE_bit(hw); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_tx(dev, state); -} - -int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) -{ - void *hw = dev->prvt; - - ASSERT(dev); - ASSERT(hw); - - if (state) { - hri_sercomspi_set_INTEN_RXC_bit(hw); - } else { - hri_sercomspi_clear_INTEN_RXC_bit(hw); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_rx(dev, state); -} - -int32_t _spi_m_async_enable_ss_detect(struct _spi_async_dev *dev, bool state) -{ - ASSERT(dev && dev->prvt); - - if (state) { - hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); - } else { - hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_ss_detect(dev, state); -} - -int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, - const FUNC_PTR func) -{ - typedef void (*func_t)(void); - struct _spi_async_dev *spid = dev; - - ASSERT(dev && (cb_type < SPI_DEV_CB_N)); - - func_t *p_ls = (func_t *)&spid->callbacks; - p_ls[cb_type] = (func_t)func; - - return ERR_NONE; -} - -int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, - const FUNC_PTR func) -{ - return _spi_m_async_register_callback(dev, cb_type, func); -} - -bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); -} - -bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); -} - -bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); - return true; - } - return false; -} - -bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { - hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); - return true; - } - return false; -} - -/** - * \brief Enable/disable SPI master interrupt - * - * param[in] device The pointer to SPI master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, - const bool state) -{ - ASSERT(device); - - if (SPI_DEV_CB_COMPLETE == type) { - hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); - } -} diff --git a/atmel-samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c b/atmel-samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c deleted file mode 100644 index fb0156082..000000000 --- a/atmel-samd/asf4/samd21/hpl/sysctrl/hpl_sysctrl.c +++ /dev/null @@ -1,265 +0,0 @@ -/** - * \file - * - * \brief SAM System Controller. - * - * Copyright (C) 2015 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Initializes clock generators - * - * All GCLK generators are running when this function returns. - */ -void _sysctrl_init_sources(void) -{ - void * hw = (void *)SYSCTRL; - uint16_t calib; - -#if CONF_XOSC32K_CONFIG == 1 - hri_sysctrl_write_XOSC32K_reg(hw, - (CONF_XOSC32K_WRTLOCK << SYSCTRL_XOSC32K_WRTLOCK_Pos) - | SYSCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) - | (CONF_XOSC32K_RUNSTDBY << SYSCTRL_XOSC32K_RUNSTDBY_Pos) - | (CONF_XOSC32K_AAMPEN << SYSCTRL_XOSC32K_AAMPEN_Pos) - | (CONF_XOSC32K_EN1K << SYSCTRL_XOSC32K_EN1K_Pos) - | (CONF_XOSC32K_EN32K << SYSCTRL_XOSC32K_EN32K_Pos) - | (CONF_XOSC32K_XTALEN << SYSCTRL_XOSC32K_XTALEN_Pos) - | (CONF_XOSC32K_ENABLE << SYSCTRL_XOSC32K_ENABLE_Pos)); -#endif - -#if CONF_XOSC_CONFIG == 1 - hri_sysctrl_write_XOSC_reg(hw, - SYSCTRL_XOSC_STARTUP(CONF_XOSC_STARTUP) | (CONF_XOSC_AMPGC << SYSCTRL_XOSC_AMPGC_Pos) - | SYSCTRL_XOSC_GAIN(CONF_XOSC_GAIN) - | (CONF_XOSC_RUNSTDBY << SYSCTRL_XOSC_RUNSTDBY_Pos) - | (CONF_XOSC_XTALEN << SYSCTRL_XOSC_XTALEN_Pos) - | (CONF_XOSC_ENABLE << SYSCTRL_XOSC_ENABLE_Pos)); -#endif - -#if CONF_OSC8M_CONFIG == 1 - calib = hri_sysctrl_read_OSC8M_CALIB_bf(hw); - - hri_sysctrl_write_OSC8M_reg(hw, - SYSCTRL_OSC8M_FRANGE(hri_sysctrl_read_OSC8M_FRANGE_bf(hw)) | -#if CONF_OSC8M_OVERWRITE_CALIBRATION == 1 - SYSCTRL_OSC8M_CALIB(CONF_OSC8M_CALIB) | -#else - SYSCTRL_OSC8M_CALIB(calib) | -#endif - SYSCTRL_OSC8M_PRESC(CONF_OSC8M_PRESC) - | (CONF_OSC8M_RUNSTDBY << SYSCTRL_OSC8M_RUNSTDBY_Pos) - | (CONF_OSC8M_ENABLE << SYSCTRL_OSC8M_ENABLE_Pos)); -#endif - -#if CONF_OSC32K_CONFIG == 1 - /* OSC32K calibration value at bit 44:38 of memory 0x00806020 */ - calib = (*((uint32_t *)0x00806024) & 0x0001FC0) >> 6; - - hri_sysctrl_write_OSC32K_reg(hw, -#if CONF_OSC32K_OVERWRITE_CALIBRATION == 1 - SYSCTRL_OSC32K_CALIB(CONF_OSC32K_CALIB) | -#else - SYSCTRL_OSC32K_CALIB(calib) | -#endif - (CONF_OSC32K_WRTLOCK << SYSCTRL_OSC32K_WRTLOCK_Pos) - | SYSCTRL_OSC32K_STARTUP(CONF_OSC32K_STARTUP) - | (CONF_OSC32K_RUNSTDBY << SYSCTRL_OSC32K_RUNSTDBY_Pos) - | (CONF_OSC32K_EN1K << SYSCTRL_OSC32K_EN1K_Pos) - | (CONF_OSC32K_EN32K << SYSCTRL_OSC32K_EN32K_Pos) - | (1 << SYSCTRL_OSC32K_ENABLE_Pos)); -#else - /* Enable OSC32K anyway since GCLK configuration may need it to sync */ - hri_sysctrl_set_OSC32K_ENABLE_bit(hw); -#endif - -#if CONF_OSCULP32K_CONFIG == 1 - hri_sysctrl_write_OSCULP32K_reg(hw, -#if CONF_OSC32K_OVERWRITE_CALIBRATION == 1 - SYSCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) | -#else - SYSCTRL_OSCULP32K_CALIB(calib) | -#endif - (CONF_OSC32K_WRTLOCK << SYSCTRL_OSCULP32K_WRTLOCK_Pos)); -#endif - -#if CONF_XOSC32K_CONFIG == 1 -#if CONF_XOSC32K_ENABLE == 1 - while (!hri_sysctrl_get_PCLKSR_XOSC32KRDY_bit(hw)) - ; -#endif -#if CONF_XOSC32K_ONDEMAND == 1 - hri_sysctrl_set_XOSC32K_ONDEMAND_bit(hw); -#endif -#endif - -#if CONF_XOSC_CONFIG == 1 -#if CONF_XOSC_ENABLE == 1 - while (!hri_sysctrl_get_PCLKSR_XOSCRDY_bit(hw)) - ; -#endif -#if CONF_XOSC_ONDEMAND == 1 - hri_sysctrl_set_XOSC_ONDEMAND_bit(hw); -#endif -#endif - -#if CONF_OSC32K_CONFIG == 1 -#if CONF_OSC32K_ENABLE == 1 - while (!hri_sysctrl_get_PCLKSR_OSC32KRDY_bit(hw)) - ; -#endif -#if CONF_OSC32K_ONDEMAND == 1 - hri_sysctrl_set_OSC32K_ONDEMAND_bit(hw); -#endif -#endif - -#if CONF_OSC8M_CONFIG == 1 -#if CONF_OSC8M_ENABLE == 1 - while (!hri_sysctrl_get_PCLKSR_OSC8MRDY_bit(hw)) - ; -#endif -#if CONF_OSC8M_ONDEMAND == 1 - hri_sysctrl_set_OSC8M_ONDEMAND_bit(hw); -#endif -#endif - - (void)calib, (void)hw; -} - -void _sysctrl_init_referenced_generators(void) -{ - void *hw = (void *)SYSCTRL; - -#if CONF_DFLL_CONFIG == 1 - -#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != CONF_DFLL_OPEN_LOOP_MODE - hri_gclk_write_CLKCTRL_reg(GCLK, - GCLK_CLKCTRL_ID(0) | GCLK_CLKCTRL_GEN(CONF_DFLL_GCLK) | (1 << GCLK_CLKCTRL_CLKEN_Pos)); -#endif - - hri_sysctrl_write_DFLLCTRL_reg(hw, SYSCTRL_DFLLCTRL_ENABLE); - while (!hri_sysctrl_get_PCLKSR_DFLLRDY_bit(hw)) - ; - - hri_sysctrl_write_DFLLMUL_reg(hw, - SYSCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | SYSCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) - | SYSCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); - hri_sysctrl_write_DFLLVAL_reg(hw, CONF_DFLLVAL); - - hri_sysctrl_dfllctrl_reg_t tmp = - - (CONF_DFLL_WAITLOCK << SYSCTRL_DFLLCTRL_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << SYSCTRL_DFLLCTRL_BPLCKC_Pos) - | (CONF_DFLL_QLDIS << SYSCTRL_DFLLCTRL_QLDIS_Pos) | (CONF_DFLL_CCDIS << SYSCTRL_DFLLCTRL_CCDIS_Pos) - | (CONF_DFLL_RUNSTDBY << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos) | (CONF_DFLL_USBCRM << SYSCTRL_DFLLCTRL_USBCRM_Pos) - | (CONF_DFLL_LLAW << SYSCTRL_DFLLCTRL_LLAW_Pos) | (CONF_DFLL_STABLE << SYSCTRL_DFLLCTRL_STABLE_Pos) - | (CONF_DFLL_MODE << SYSCTRL_DFLLCTRL_MODE_Pos) | (CONF_DFLL_ENABLE << SYSCTRL_DFLLCTRL_ENABLE_Pos); - - hri_sysctrl_write_DFLLCTRL_reg(hw, tmp); -#endif - -#if CONF_DPLL_CONFIG == 1 -#if CONF_DPLL_REFCLK == SYSCTRL_DPLLCTRLB_REFCLK_GCLK_Val - hri_gclk_write_CLKCTRL_reg(GCLK, - GCLK_CLKCTRL_ID(1) | GCLK_CLKCTRL_GEN(CONF_DPLL_GCLK) | (1 << GCLK_CLKCTRL_CLKEN_Pos)); -#endif - - hri_sysctrl_write_DPLLCTRLA_reg(hw, - (CONF_DPLL_RUNSTDBY << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos) - | (CONF_DPLL_ENABLE << SYSCTRL_DPLLCTRLA_ENABLE_Pos)); - hri_sysctrl_write_DPLLRATIO_reg( - hw, SYSCTRL_DPLLRATIO_LDRFRAC(CONF_DPLL_LDRFRAC) | SYSCTRL_DPLLRATIO_LDR(CONF_DPLL_LDR)); - hri_sysctrl_write_DPLLCTRLB_reg(hw, - SYSCTRL_DPLLCTRLB_DIV(CONF_DPLL_DIV) - | (CONF_DPLL_LBYPASS << SYSCTRL_DPLLCTRLB_LBYPASS_Pos) - | SYSCTRL_DPLLCTRLB_LTIME(CONF_DPLL_LTIME) - | SYSCTRL_DPLLCTRLB_REFCLK(CONF_DPLL_REFCLK) - | (CONF_DPLL_WUF << SYSCTRL_DPLLCTRLB_WUF_Pos) - | (CONF_DPLL_LPEN << SYSCTRL_DPLLCTRLB_LPEN_Pos) - | SYSCTRL_DPLLCTRLB_FILTER(CONF_DPLL_FILTER)); -#endif - -#if CONF_DFLL_CONFIG == 1 -#if CONF_DFLL_ENABLE == 1 - if (hri_sysctrl_get_DFLLCTRL_MODE_bit(hw)) { - -#if CONF_DFLL_USBCRM == 0 - hri_sysctrl_pclksr_reg_t status_mask - = SYSCTRL_PCLKSR_DFLLRDY | SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC; -#else - hri_sysctrl_pclksr_reg_t status_mask = SYSCTRL_PCLKSR_DFLLRDY; -#endif - - while (hri_sysctrl_get_PCLKSR_reg(hw, status_mask) != status_mask) - ; - } else { - while (!hri_sysctrl_get_PCLKSR_DFLLRDY_bit(hw)) - ; - } -#endif -#if CONF_DFLL_ONDEMAND == 1 - hri_sysctrl_set_DFLLCTRL_ONDEMAND_bit(hw); -#endif -#endif - -#if CONF_DPLL_CONFIG == 1 -#if CONF_DPLL_ENABLE == 1 - while (!(hri_sysctrl_get_DPLLSTATUS_ENABLE_bit(hw) || hri_sysctrl_get_DPLLSTATUS_LOCK_bit(hw) - || hri_sysctrl_get_DPLLSTATUS_CLKRDY_bit(hw))) - ; -#endif -#if CONF_DPLL_ONDEMAND == 1 - hri_sysctrl_set_DPLLCTRLA_ONDEMAND_bit(hw); -#endif -#endif - -#if CONF_DFLL_CONFIG == 1 - while (hri_gclk_get_STATUS_SYNCBUSY_bit(GCLK)) - ; -#endif - -#if CONF_OSC32K_CONFIG == 0 || CONF_OSC32K_ENABLE == 0 - /* Disable after all possible configurations needs sync written. */ - hri_sysctrl_clear_OSC32K_ENABLE_bit(hw); -#endif - - (void)hw; -} diff --git a/atmel-samd/asf4/samd21/hpl/systick/hpl_systick.c b/atmel-samd/asf4/samd21/hpl/systick/hpl_systick.c deleted file mode 100644 index 783f306e0..000000000 --- a/atmel-samd/asf4/samd21/hpl/systick/hpl_systick.c +++ /dev/null @@ -1,113 +0,0 @@ - -/** - * \file - * - * \brief SysTick related functionality implementation. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Initialize system time module - */ -void _system_time_init(void *const hw) -{ - (void)hw; - SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos); - SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos) - | (1 << SysTick_CTRL_CLKSOURCE_Pos); -} -/** - * \brief Initialize delay functionality - */ -void _delay_init(void *const hw) -{ - _system_time_init(hw); -} - -/** - * \brief De-initialize system time module - */ -void _system_time_deinit(void *const hw) -{ - (void)hw; - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; -} - -/** - * \brief Get system time - */ -system_time_t _system_time_get(const void *const hw) -{ - (void)hw; - return (system_time_t)SysTick->VAL; -} - -/** - * \brief Get maximum possible system time - */ -system_time_t _system_time_get_max_time_value(const void *const hw) -{ - (void)hw; - return 0xFFFFFF; -} -/** - * \brief Delay loop to delay n number of cycles - */ -void _delay_cycles(void *const hw, uint32_t cycles) -{ - (void)hw; - uint8_t n = cycles >> 24; - uint32_t buf = cycles; - - while (n--) { - SysTick->LOAD = 0xFFFFFF; - SysTick->VAL = 0xFFFFFF; - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) - ; - buf -= 0xFFFFFF; - } - - SysTick->LOAD = buf; - SysTick->VAL = buf; - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) - ; -} diff --git a/atmel-samd/asf4/samd21/hpl/tc/hpl_tc.c b/atmel-samd/asf4/samd21/hpl/tc/hpl_tc.c deleted file mode 100644 index 9344729da..000000000 --- a/atmel-samd/asf4/samd21/hpl/tc/hpl_tc.c +++ /dev/null @@ -1,369 +0,0 @@ -/** - * \file - * - * \brief SAM TC - * - * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include -#include -#include - -#ifndef CONF_TC3_ENABLE -#define CONF_TC3_ENABLE 0 -#endif -#ifndef CONF_TC4_ENABLE -#define CONF_TC4_ENABLE 0 -#endif -#ifndef CONF_TC5_ENABLE -#define CONF_TC5_ENABLE 0 -#endif -#ifndef CONF_TC6_ENABLE -#define CONF_TC6_ENABLE 0 -#endif -#ifndef CONF_TC7_ENABLE -#define CONF_TC7_ENABLE 0 -#endif - -/** - * \brief TC IRQ base index - */ -#define TC_IRQ_BASE_INDEX ((uint8_t)TC3_IRQn) - -/** - * \brief TC base address - */ -#define TC_HW_BASE_ADDR ((uint32_t)TC3) - -/** - * \brief TC number offset - */ -#define TC_NUMBER_OFFSET 3 - -/** - * \brief Macro is used to fill usart configuration structure based on its - * number - * - * \param[in] n The number of structures - */ -#define TC_CONFIGURATION(n) \ - { \ - (n), TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_WAVEGEN(TC_CTRLA_WAVEGEN_MPWM_Val) \ - | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) \ - | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC), \ - (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), \ - (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \ - | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \ - | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \ - CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1 \ - } -/** - * \brief TC configuration type - */ -struct tc_configuration { - uint8_t number; - hri_tc_ctrla_reg_t ctrl_a; - hri_tc_dbgctrl_reg_t dbg_ctrl; - hri_tc_evctrl_reg_t event_ctrl; - hri_tc_per_reg_t per; - hri_tc_cc32_reg_t cc0; - hri_tc_cc32_reg_t cc1; -}; - -/** - * \brief Array of TC configurations - */ -static struct tc_configuration _tcs[] = { -#if CONF_TC3_ENABLE == 1 - TC_CONFIGURATION(3), -#endif -#if CONF_TC4_ENABLE == 1 - TC_CONFIGURATION(4), -#endif -#if CONF_TC5_ENABLE == 1 - TC_CONFIGURATION(5), -#endif -#if CONF_TC6_ENABLE == 1 - TC_CONFIGURATION(6), -#endif -#if CONF_TC7_ENABLE == 1 - TC_CONFIGURATION(7), -#endif -}; - -static struct _pwm_device *_tc3_dev = NULL; - -static int8_t get_tc_index(const void *const hw); -static uint8_t tc_get_hardware_index(const void *const hw); -static void _tc_init_irq_param(const void *const hw, void *dev); -static inline uint8_t _get_hardware_offset(const void *const hw); -/** - * \brief Initialize TC for PWM mode - */ -int32_t _pwm_init(struct _pwm_device *const device, void *const hw) -{ - int8_t i = get_tc_index(hw); - device->hw = hw; - - hri_tc_wait_for_sync(hw); - if (hri_tc_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_tc_set_CTRLA_SWRST_bit(hw); - hri_tc_wait_for_sync(hw); - - hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); - hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); - hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); - - if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { - hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); - hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); - } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { - hri_tccount16_write_CC_reg(hw, 0, (hri_tc_count16_reg_t)_tcs[i].cc0); - hri_tccount16_write_CC_reg(hw, 1, (hri_tc_count16_reg_t)_tcs[i].cc1); - } else { - /* 8-bit resolution is not accepted by duty cycle control */ - return ERR_INVALID_DATA; - } - - _tc_init_irq_param(hw, (void *)device); - NVIC_DisableIRQ((IRQn_Type)((uint8_t)TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw))); - NVIC_ClearPendingIRQ((IRQn_Type)((uint8_t)TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw))); - NVIC_EnableIRQ((IRQn_Type)((uint8_t)TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw))); - - return ERR_NONE; -} -/** - * \brief De-initialize TC for PWM mode - */ -void _pwm_deinit(struct _pwm_device *const device) -{ - void *const hw = device->hw; - - NVIC_DisableIRQ((IRQn_Type)(TC_IRQ_BASE_INDEX + tc_get_hardware_index(hw))); - - hri_tc_clear_CTRLA_ENABLE_bit(hw); - hri_tc_set_CTRLA_SWRST_bit(hw); -} -/** - * \brief Start PWM - */ -void _pwm_enable(struct _pwm_device *const device) -{ - hri_tc_set_CTRLA_ENABLE_bit(device->hw); -} -/** - * \brief Stop PWM - */ -void _pwm_disable(struct _pwm_device *const device) -{ - hri_tc_clear_CTRLA_ENABLE_bit(device->hw); -} -/** - * \brief Set PWM parameter - */ -void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle) -{ - int8_t i = get_tc_index(device->hw); - void *const hw = device->hw; - _tcs[i].cc0 = period; - _tcs[i].cc1 = duty_cycle; - if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { - hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); - hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); - } else { - hri_tccount16_write_CC_reg(hw, 0, _tcs[i].cc0); - hri_tccount16_write_CC_reg(hw, 1, _tcs[i].cc1); - } -} -/** - * \brief Get pwm waveform period value - */ -pwm_period_t _pwm_get_period(const struct _pwm_device *const device) -{ - void *const hw = device->hw; - int8_t i = get_tc_index(hw); - - if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { - return (pwm_period_t)(hri_tccount32_read_CC_reg(hw, 0)); - } else { - return (pwm_period_t)(hri_tccount16_read_CC_reg(hw, 0)); - } -} -/** - * \brief Get pwm waveform duty cycle - */ -uint32_t _pwm_get_duty(const struct _pwm_device *const device) -{ - void *const hw = device->hw; - int8_t i = get_tc_index(hw); - uint32_t per; - uint32_t duty_cycle; - - if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { - per = hri_tccount32_read_CC_reg(hw, 0); - duty_cycle = hri_tccount32_read_CC_reg(hw, 1); - } else { - per = hri_tccount16_read_CC_reg(hw, 0); - duty_cycle = hri_tccount16_read_CC_reg(hw, 1); - } - - return ((duty_cycle * 1000) / per); -} -/** - * \brief Check if PWM is running - */ -bool _pwm_is_enabled(const struct _pwm_device *const device) -{ - return hri_tc_get_CTRLA_ENABLE_bit(device->hw); -} -/** - * \brief Enable/disable PWM interrupt - */ -void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable) -{ - ASSERT(device); - - if (PWM_DEVICE_PERIOD_CB == type) { - hri_tc_write_INTEN_OVF_bit(device->hw, disable); - } else if (PWM_DEVICE_ERROR_CB == type) { - hri_tc_write_INTEN_ERR_bit(device->hw, disable); - } -} - -/** - * \brief Retrieve timer helper functions - */ -struct _timer_hpl_interface *_tc_get_timer(void) -{ - return NULL; -} - -/** - * \brief Retrieve pwm helper functions - */ -struct _pwm_hpl_interface *_tc_get_pwm(void) -{ - return NULL; -} -/** - * \internal TC interrupt handler for PWM - * - * \param[in] instance TC instance number - */ -static void tc_pwm_interrupt_handler(struct _pwm_device *device) -{ - void *const hw = device->hw; - - if (hri_tc_get_interrupt_OVF_bit(hw)) { - hri_tc_clear_interrupt_OVF_bit(hw); - if (NULL != device->callback.pwm_period_cb) { - device->callback.pwm_period_cb(device); - } - } - if (hri_tc_get_INTEN_ERR_bit(hw)) { - hri_tc_clear_interrupt_ERR_bit(hw); - if (NULL != device->callback.pwm_error_cb) { - device->callback.pwm_error_cb(device); - } - } -} - -/** -* \brief TC interrupt handler -*/ -void TC3_Handler(void) -{ - tc_pwm_interrupt_handler(_tc3_dev); -} - -/** - * \internal Retrieve TC hardware index - * - * \param[in] hw The pointer to hardware instance - */ -static uint8_t tc_get_hardware_index(const void *const hw) -{ -#ifndef _UNIT_TEST_ - return ((uint32_t)hw - TC_HW_BASE_ADDR) >> 10; -#else - return ((uint32_t)hw - TC_HW_BASE_ADDR) / sizeof(Tc); -#endif -} - -/** - * \internal Retrieve TC index - * - * \param[in] hw The pointer to hardware instance - * - * \return The index of TC configuration - */ -static int8_t get_tc_index(const void *const hw) -{ - uint8_t tc_offset = tc_get_hardware_index(hw) + TC_NUMBER_OFFSET; - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_tcs); i++) { - if (_tcs[i].number == tc_offset) { - return i; - } - } - - ASSERT(false); - return -1; -} - -/** - * \brief Init irq param with the given tc hardware instance - */ -static void _tc_init_irq_param(const void *const hw, void *dev) -{ - if (hw == TC3) { - _tc3_dev = (struct _pwm_device *)dev; - } -} - -static inline uint8_t _get_hardware_offset(const void *const hw) -{ - return (((uint32_t)hw - TC_HW_BASE_ADDR) >> 10) + TC_NUMBER_OFFSET; -} diff --git a/atmel-samd/asf4/samd21/hpl/tc/hpl_tc_base.h b/atmel-samd/asf4/samd21/hpl/tc/hpl_tc_base.h deleted file mode 100644 index 9d7f2c72a..000000000 --- a/atmel-samd/asf4/samd21/hpl/tc/hpl_tc_base.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * \brief SAM Timer/Counter - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distributionn. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifndef _HPL_TC_BASE_H_INCLUDED -#define _HPL_TC_BASE_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup tc_group TC Hardware Proxy Layer - * - * \section tc_hpl_rev Revision History - * - v0.0.0.1 Initial Commit - * - *@{ - */ - -/** - * \name HPL functions - */ -//@{ - -/** - * \brief Retrieve timer helper functions - * - * \return A pointer to set of timer helper functions - */ -struct _timer_hpl_interface *_tc_get_timer(void); - -/** - * \brief Retrieve pwm helper functions - * - * \return A pointer to set of pwm helper functions - */ -struct _pwm_hpl_interface *_tc_get_pwm(void); - -//@} -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_TC_BASE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c b/atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c deleted file mode 100644 index d134967d3..000000000 --- a/atmel-samd/asf4/samd21/hpl/usb/hpl_usb.c +++ /dev/null @@ -1,2051 +0,0 @@ -/** - * \file - * - * \brief SAM USB HPL - * - * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -#include -#include -#include - -/** - * \brief Dummy callback function - * \return Always false. - */ -static bool _dummy_func_no_return(uint32_t unused0, uint32_t unused1) -{ - (void)unused0; - (void)unused1; - return false; -} - -/** - * \brief Load USB calibration value from NVM - */ -static void _usb_load_calib(void) -{ -#define NVM_USB_PAD_TRANSN_POS 45 -#define NVM_USB_PAD_TRANSN_SIZE 5 -#define NVM_USB_PAD_TRANSP_POS 50 -#define NVM_USB_PAD_TRANSP_SIZE 5 -#define NVM_USB_PAD_TRIM_POS 55 -#define NVM_USB_PAD_TRIM_SIZE 3 - Usb * hw = USB; - uint32_t pad_transn - = (*((uint32_t *)(NVMCTRL_OTP4) + (NVM_USB_PAD_TRANSN_POS / 32)) >> (NVM_USB_PAD_TRANSN_POS % 32)) - & ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1); - uint32_t pad_transp - = (*((uint32_t *)(NVMCTRL_OTP4) + (NVM_USB_PAD_TRANSP_POS / 32)) >> (NVM_USB_PAD_TRANSP_POS % 32)) - & ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1); - uint32_t pad_trim = (*((uint32_t *)(NVMCTRL_OTP4) + (NVM_USB_PAD_TRIM_POS / 32)) >> (NVM_USB_PAD_TRIM_POS % 32)) - & ((1 << NVM_USB_PAD_TRIM_SIZE) - 1); - if (pad_transn == 0x1F) { - pad_transn = 5; - } - if (pad_transp == 0x1F) { - pad_transp = 29; - } - if (pad_trim == 0x7) { - pad_trim = 5; - } - - hw->DEVICE.PADCAL.reg = USB_PADCAL_TRANSN(pad_transn) | USB_PADCAL_TRANSP(pad_transp) | USB_PADCAL_TRIM(pad_trim); - - hw->DEVICE.QOSCTRL.bit.CQOS = 3; - hw->DEVICE.QOSCTRL.bit.DQOS = 3; -} - -/** \name USB clock source management */ -/*@{*/ - -/** USB clock is generated by DFLL. */ -#define USB_CLK_SRC_DFLL 0 - -/** USB clock is generated by DPLL. */ -#define USB_CLK_SRC_DPLL 1 - -/** Uses DFLL as USB clock source. */ -#define CONF_USB_D_CLK_SRC USB_CLK_SRC_DFLL - -/** Retry for USB remote wakeup sending. */ -#define CONF_USB_RMT_WKUP_RETRY 5 - -/** - * \brief Wait DPLL clock to be ready - */ -static inline void _usb_d_dev_wait_dpll_rdy(void) -{ -#define DPLL_READY_FLAG (SYSCTRL_DPLLSTATUS_ENABLE | SYSCTRL_DPLLSTATUS_CLKRDY | SYSCTRL_DPLLSTATUS_LOCK) - while (hri_sysctrl_get_DPLLSTATUS_reg(SYSCTRL, DPLL_READY_FLAG) != DPLL_READY_FLAG) - ; -} - -/** - * \brief Wait DFLL clock to be ready - */ -static inline void _usb_d_dev_wait_dfll_rdy(void) -{ -#define DFLL_READY_FLAG (SYSCTRL_PCLKSR_DFLLRDY | SYSCTRL_PCLKSR_DFLLLCKF | SYSCTRL_PCLKSR_DFLLLCKC) - /* In USB recovery mode the status is not checked */ - if (!(SYSCTRL->DFLLCTRL.reg & SYSCTRL_DFLLCTRL_USBCRM)) { - while (hri_sysctrl_get_PCLKSR_reg(SYSCTRL, DFLL_READY_FLAG) != DFLL_READY_FLAG) - ; - } else { - while (hri_sysctrl_get_PCLKSR_reg(SYSCTRL, SYSCTRL_PCLKSR_DFLLRDY) != SYSCTRL_PCLKSR_DFLLRDY) - ; - } -} - -/** - * \brief Wait USB source clock to be ready - * \param[in] clk_src Clock source, could be \ref USB_CLK_SRC_DFLL or - * \ref USB_CLK_SRC_DPLL. - */ -static inline void _usb_d_dev_wait_clk_rdy(const uint8_t clk_src) -{ - if (clk_src == USB_CLK_SRC_DFLL) { - _usb_d_dev_wait_dfll_rdy(); - } else if (clk_src == USB_CLK_SRC_DPLL) { - _usb_d_dev_wait_dpll_rdy(); - } -} - -/*@}*/ - -/** \name USB general settings */ -/*@{*/ - -/** Increase the value to be aligned. */ -#define _usb_align_up(val) (((val)&0x3) ? (((val) + 4 - ((val)&0x3))) : (val)) - -/** Check if the buffer is in RAM (can DMA), or cache needed - * \param[in] a Buffer start address. - * \param[in] s Buffer size, in number of bytes. - * \return \c true If the buffer is in RAM. - */ -#define _IN_RAM(a, s) ((0x20000000 <= (uint32_t)(a)) && (((uint32_t)(a) + (s)) < 0x20008000)) - -/** Check if the address should be placed in RAM. */ -#define _usb_is_addr4dma(addr, size) _IN_RAM((addr), (size)) - -/** Check if the address is 32-bit aligned. */ -#define _usb_is_aligned(val) (((uint32_t)(val)&0x3) == 0) -/*@}*/ - -/* Cache static configurations. - * By default, all OUT endpoint have 64 bytes cache. */ -#ifndef CONF_USB_EP0_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP0_CACHE 64 -#endif - -#ifndef CONF_USB_EP0_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP0_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP1_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP1_CACHE 64 -#endif - -#ifndef CONF_USB_EP1_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP1_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP2_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP2_CACHE 64 -#endif - -#ifndef CONF_USB_EP2_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP2_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP3_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP3_CACHE 64 -#endif - -#ifndef CONF_USB_EP3_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP3_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP4_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP4_CACHE 64 -#endif - -#ifndef CONF_USB_EP4_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP4_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP5_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP5_CACHE 64 -#endif - -#ifndef CONF_USB_EP5_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP5_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP6_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP6_CACHE 64 -#endif - -#ifndef CONF_USB_EP6_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP6_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP7_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP7_CACHE 64 -#endif - -#ifndef CONF_USB_EP7_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP7_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP8_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP8_CACHE 64 -#endif - -#ifndef CONF_USB_EP8_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP8_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP9_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP9_CACHE 64 -#endif - -#ifndef CONF_USB_EP9_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP9_I_CACHE 0 -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP0_CACHE -static uint32_t _usb_ep0_cache[_usb_align_up(CONF_USB_EP0_CACHE) / 4]; -#else -#define _usb_ep0_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#define _usb_ep0_i_cache NULL - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP1_CACHE && CONF_USB_D_MAX_EP_N >= 1 -uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; -#else -#define _usb_ep1_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP1_I_CACHE && CONF_USB_D_MAX_EP_N >= 1 -static uint32_t _usb_ep1_i_cache[_usb_align_up(CONF_USB_EP1_I_CACHE) / 4]; -#else -#define _usb_ep1_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP2_CACHE && CONF_USB_D_MAX_EP_N >= 2 -static uint32_t _usb_ep2_cache[_usb_align_up(CONF_USB_EP2_CACHE) / 4]; -#else -#define _usb_ep2_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP2_I_CACHE && CONF_USB_D_MAX_EP_N >= 2 -static uint32_t _usb_ep2_i_cache[_usb_align_up(CONF_USB_EP2_I_CACHE) / 4]; -#else -#define _usb_ep2_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP3_CACHE && CONF_USB_D_MAX_EP_N >= 3 -static uint32_t _usb_ep3_cache[_usb_align_up(CONF_USB_EP3_CACHE) / 4]; -#else -#define _usb_ep3_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP3_I_CACHE && CONF_USB_D_MAX_EP_N >= 3 -static uint32_t _usb_ep3_i_cache[_usb_align_up(CONF_USB_EP3_I_CACHE) / 4]; -#else -#define _usb_ep3_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP4_CACHE && CONF_USB_D_MAX_EP_N >= 4 -static uint32_t _usb_ep4_cache[_usb_align_up(CONF_USB_EP4_CACHE) / 4]; -#else -#define _usb_ep4_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP4_I_CACHE && CONF_USB_D_MAX_EP_N >= 4 -static uint32_t _usb_ep4_i_cache[_usb_align_up(CONF_USB_EP4_I_CACHE) / 4]; -#else -#define _usb_ep4_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP5_CACHE && CONF_USB_D_MAX_EP_N >= 5 -static uint32_t _usb_ep5_cache[_usb_align_up(CONF_USB_EP5_CACHE) / 4]; -#else -#define _usb_ep5_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP5_I_CACHE && CONF_USB_D_MAX_EP_N >= 5 -static uint32_t _usb_ep5_i_cache[_usb_align_up(CONF_USB_EP5_I_CACHE) / 4]; -#else -#define _usb_ep5_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP6_CACHE && CONF_USB_D_MAX_EP_N >= 6 -static uint32_t _usb_ep6_cache[_usb_align_up(CONF_USB_EP6_CACHE) / 4]; -#else -#define _usb_ep6_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP6_I_CACHE && CONF_USB_D_MAX_EP_N >= 6 -static uint32_t _usb_ep6_i_cache[_usb_align_up(CONF_USB_EP6_I_CACHE) / 4]; -#else -#define _usb_ep6_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP7_CACHE && CONF_USB_D_MAX_EP_N >= 7 -static uint32_t _usb_ep7_cache[_usb_align_up(CONF_USB_EP7_CACHE) / 4]; -#else -#define _usb_ep7_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP7_I_CACHE && CONF_USB_D_MAX_EP_N >= 7 -static uint32_t _usb_ep7_i_cache[_usb_align_up(CONF_USB_EP7_I_CACHE) / 4]; -#else -#define _usb_ep7_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP8_CACHE && CONF_USB_D_MAX_EP_N >= 8 -static uint32_t _usb_ep8_cache[_usb_align_up(CONF_USB_EP8_CACHE) / 4]; -#else -#define _usb_ep8_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP8_I_CACHE && CONF_USB_D_MAX_EP_N >= 8 -static uint32_t _usb_ep8_i_cache[_usb_align_up(CONF_USB_EP8_I_CACHE) / 4]; -#else -#define _usb_ep8_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP9_CACHE && CONF_USB_D_MAX_EP_N >= 9 -static uint32_t _usb_ep9_cache[_usb_align_up(CONF_USB_EP9_CACHE) / 4]; -#else -#define _usb_ep9_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP9_I_CACHE && CONF_USB_D_MAX_EP_N >= 9 -static uint32_t _usb_ep9_i_cache[_usb_align_up(CONF_USB_EP9_I_CACHE) / 4]; -#else -#define _usb_ep9_i_cache NULL -#endif - -/** Access endpoint cache buffer for OUT transactions (none-control) or - * SETUP/IN/OUT transactions (control). */ -#define _USB_EP_CACHE(n) ((void *)_usb_ep##n##_cache) - -/** Access endpoint cache buffer for IN transactions (none-control). */ -#define _USB_EP_I_CACHE(n) ((void *)_usb_ep##n##_i_cache) - -/** The configuration settings for one of the endpoint hardware. */ -struct _usb_ep_cfg_item { - /* Endpoint cache buffer for OUT transactions (none-control) or - * SETUP/IN/OUT transactions (control). */ - void *cache; - /* endpoint cache buffer for IN transactions (none-control). */ - void *i_cache; - /* Cache buffer size for OUT transactions (none-control) or - * SETUP/IN/OUT transactions (control). */ - uint16_t size; - /* Cache buffer size for IN transactions (none-control). */ - uint16_t i_size; -}; - -/** Build the endpoint configuration settings for one endpoint. */ -#define _USB_EP_CFG_ITEM(n) \ - { \ - _USB_EP_CACHE(n), _USB_EP_I_CACHE(n), CONF_USB_EP##n##_CACHE, CONF_USB_EP##n##_I_CACHE, \ - } - -/** The configuration settings for all endpoint. */ -static const struct _usb_ep_cfg_item _usb_ep_cfgs[] = {_USB_EP_CFG_ITEM(0) -#if CONF_USB_D_MAX_EP_N >= 1 - , - _USB_EP_CFG_ITEM(1) -#endif -#if CONF_USB_D_MAX_EP_N >= 2 - , - _USB_EP_CFG_ITEM(2) -#endif -#if CONF_USB_D_MAX_EP_N >= 3 - , - _USB_EP_CFG_ITEM(3) -#endif -#if CONF_USB_D_MAX_EP_N >= 4 - , - _USB_EP_CFG_ITEM(4) -#endif -#if CONF_USB_D_MAX_EP_N >= 5 - , - _USB_EP_CFG_ITEM(5) -#endif -#if CONF_USB_D_MAX_EP_N >= 6 - , - _USB_EP_CFG_ITEM(6) -#endif -#if CONF_USB_D_MAX_EP_N >= 7 - , - _USB_EP_CFG_ITEM(7) -#endif -#if CONF_USB_D_MAX_EP_N >= 8 - , - _USB_EP_CFG_ITEM(8) -#endif -#if CONF_USB_D_MAX_EP_N >= 9 - , - _USB_EP_CFG_ITEM(9) -#endif -}; - -/** \name HW specific settings and implements */ -/*@{*/ - -/** Number of endpoints supported. */ -#define USB_D_N_EP (1 + CONF_USB_D_NUM_EP_SP * 2) - -/** HPL USB device endpoint struct. */ -struct _usb_d_dev_ep { - /** Pointer to transaction buffer. */ - uint8_t *trans_buf; - /** Transaction size. */ - uint32_t trans_size; - /** Transaction transferred count. */ - uint32_t trans_count; - - /** Pointer to cache buffer, must be aligned. */ - uint8_t *cache; - - /** Endpoint size. */ - uint16_t size; - /** Endpoint address. */ - uint8_t ep; - /** Feature flags. */ - union { - /** Interpreted by bit fields. */ - struct { - /** EPCFG.ETYPE. */ - uint8_t eptype : 3; - /** Stall status. */ - uint8_t is_stalled : 1; - /** Transaction auto ZLP. */ - uint8_t need_zlp : 1; - /** Transaction with cache */ - uint8_t use_cache : 1; - /** Endpoint is busy. */ - uint8_t is_busy : 1; - /** Transaction direction. */ - uint8_t dir : 1; - } bits; - uint8_t u8; - } flags; -}; - -/** Check if the endpoint is used. */ -#define _usb_d_dev_ep_is_used(ept) ((ept)->ep != 0xFF) - -/** Check if the endpoint is busy doing transactions. */ -#define _usb_d_dev_ep_is_busy(ept) ((ept)->flags.bits.is_busy) - -/** Check if the endpoint is control endpoint. */ -#define _usb_d_dev_ep_is_ctrl(ept) ((ept)->flags.bits.eptype == USB_D_EPTYPE_CTRL) - -/** Check if the endpoint transactions are IN. */ -#define _usb_d_dev_ep_is_in(ept) ((ept)->flags.bits.dir) - -/** Interrupt flags for SETUP transaction. */ -#define USB_D_SETUP_INT_FLAGS (USB_DEVICE_EPINTFLAG_RXSTP) - -/** Interrupt flags for BANK1 transactions. */ -#define USB_D_BANK1_INT_FLAGS (USB_DEVICE_EPINTFLAG_TRCPT1 | USB_DEVICE_EPINTFLAG_TRFAIL1 | USB_DEVICE_EPINTFLAG_STALL1) - -/** Interrupt flags for BANK0 transactions. */ -#define USB_D_BANK0_INT_FLAGS (USB_DEVICE_EPINTFLAG_TRCPT0 | USB_DEVICE_EPINTFLAG_TRFAIL0 | USB_DEVICE_EPINTFLAG_STALL0) - -/** Interrupt flags for SETUP/IN/OUT transactions. */ -#define USB_D_ALL_INT_FLAGS (0x7F) - -/** Interrupt flags for WAKEUP event. */ -#define USB_D_WAKEUP_INT_FLAGS (USB_DEVICE_INTFLAG_UPRSM | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_WAKEUP) - -/** Interrupt flags for SUSPEND event. */ -#define USB_D_SUSPEND_INT_FLAGS (USB_DEVICE_INTFLAG_LPMSUSP | USB_DEVICE_INTFLAG_SUSPEND) - -/** Max data bytes for a single DMA transfer. */ -#define USB_D_DEV_TRANS_MAX 8192 /* 14-bits, uses 13-bits. */ - -/** Endpoint type setting to disable. */ -#define USB_D_EPTYPE_DISABLE 0 - -/** Endpoint type setting to work as control endpoint. */ -#define USB_D_EPTYPE_CTRL 1 - -/** Endpoint type setting to work as isochronous endpoint. */ -#define USB_D_EPTYPE_ISOCH 2 - -/** Endpoint type setting to work as interrupt endpoint. */ -#define USB_D_EPTYPE_INT 3 - -/** Endpoint type setting to work as bulk endpoint. */ -#define USB_D_EPTYPE_BULK 4 - -/** Endpoint type setting for dual bank endpoint. */ -#define USB_D_EPTYPE_DUAL 5 - -/** EPCFG register value for control endpoints. */ -#define USB_D_EPCFG_CTRL 0x11 - -/** HPL USB device struct. */ -struct _usb_d_dev { - /** Callbacks of USB device. */ - struct _usb_d_dev_callbacks callbacks; - /** Endpoint transaction callbacks. */ - struct _usb_d_dev_ep_callbacks ep_callbacks; - /** Endpoints (ep0 + others). */ - struct _usb_d_dev_ep ep[USB_D_N_EP]; -}; - -/** Private data for SAM0 USB peripheral. - */ -typedef struct _usb_d_dev_prvt { - /** USB device descriptor table for peripheral to work. */ - UsbDeviceDescriptor desc_table[CONF_USB_D_MAX_EP_N + 1]; -} usb_d_dev_prvt_t; - -/*@}*/ - -/** USB device driver instance. */ -static struct _usb_d_dev dev_inst; - -/** USB device driver private data instance. */ -static struct _usb_d_dev_prvt prvt_inst; - -static void _usb_d_dev_reset_epts(void); - -static void _usb_d_dev_trans_done(struct _usb_d_dev_ep *ept, const int32_t status); -static void _usb_d_dev_trans_stop(struct _usb_d_dev_ep *ept, bool dir, const int32_t code); - -static void _usb_d_dev_in_next(struct _usb_d_dev_ep *ept, bool isr); -static void _usb_d_dev_out_next(struct _usb_d_dev_ep *ept, bool isr); - -static inline void _usb_d_dev_trans_setup(struct _usb_d_dev_ep *ept); - -/** \brief ACK the endpoint interrupt - * \param[in] epn Endpoint number. - * \param[in] flags Interrupt flags. - */ -static inline void _usbd_ep_int_ack(uint8_t epn, uint32_t flags) -{ - hri_usbendpoint_clear_EPINTFLAG_reg(USB, epn, flags); -} - -/** \brief Enable the endpoint interrupt - * \param[in] epn Endpoint number. - * \param[in] flags Interrupt flags. - */ -static inline void _usbd_ep_int_en(uint8_t epn, uint32_t flags) -{ - hri_usbendpoint_set_EPINTEN_reg(USB, epn, flags); -} - -/** \brief Disable the endpoint interrupt - * \param[in] epn Endpoint number. - * \param[in] flags Interrupt flags. - */ -static inline void _usbd_ep_int_dis(uint8_t epn, uint32_t flags) -{ - hri_usbendpoint_clear_EPINTEN_reg(USB, epn, flags); -} - -/** \brief Check if endpoint is control endpoint - * \param[in] epn Endpoint number. - */ -static inline bool _usbd_ep_is_ctrl(uint8_t epn) -{ - return (hri_usbendpoint_read_EPCFG_reg(USB, epn) == USB_D_EPCFG_CTRL); -} - -/** \brief Set endpoint stall - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] st Stall status. - */ -static inline void _usbd_ep_set_stall(uint8_t epn, uint8_t bank_n, bool st) -{ - if (st) { - hri_usbendpoint_set_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); - } else { - hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); - } -} - -/** \brief Check if the endpoint is stalled - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \return \c true if it's stalled. - */ -static inline bool _usbd_ep_is_stalled(uint8_t epn, uint8_t bank_n) -{ - Usb *hw = USB; - return (hri_usbendpoint_read_EPSTATUS_reg(hw, epn) & (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); -} - -/** \brief Check if stall has been sent from the endpoint - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \return \c true if it's sent. - */ -static inline bool _usbd_ep_is_stall_sent(uint8_t epn, uint8_t bank_n) -{ - Usb *hw = USB; - return (hri_usbendpoint_read_EPINTFLAG_reg(hw, epn) & (USB_DEVICE_EPINTFLAG_STALL0 << bank_n)); -} - -/** \brief ACK endpoint STALL interrupt - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - */ -static inline void _usbd_ep_ack_stall(uint8_t epn, uint8_t bank_n) -{ - _usbd_ep_int_ack(epn, (USB_DEVICE_EPINTFLAG_STALL0 << bank_n)); -} - -/** \brief Enable/disable endpoint STALL interrupt - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] en \c true to enable, \c false to disable. - */ -static inline void _usbd_ep_int_stall_en(uint8_t epn, uint8_t bank_n, const bool en) -{ - if (en) { - _usbd_ep_int_en(epn, USB_DEVICE_EPINTFLAG_STALL0 << bank_n); - } else { - _usbd_ep_int_dis(epn, USB_DEVICE_EPINTFLAG_STALL0 << bank_n); - } -} - -/** \brief Stop SETUP transactions - * \param[in] epn Endpoint number. - */ -static inline void _usbd_ep_stop_setup(uint8_t epn) -{ - hri_usbendpoint_clear_EPINTEN_RXSTP_bit(USB, epn); -} - -/** \brief Check if SETUP packet is ready in cache - * \param[in] epn Endpoint number. - */ -static inline bool _usbd_ep_is_setup(uint8_t epn) -{ - return hri_usbendpoint_get_EPINTFLAG_reg(USB, epn, USB_DEVICE_EPINTFLAG_RXSTP); -} - -/** \brief ACK endpoint SETUP interrupt - * \param[in] epn Endpoint number. - */ -static inline void _usbd_ep_ack_setup(uint8_t epn) -{ - _usbd_ep_int_ack(epn, USB_DEVICE_EPINTFLAG_RXSTP); -} - -/** \brief Set endpoint toggle value - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] tgl Toggle value. - */ -static inline void _usbd_ep_set_toggle(uint8_t epn, uint8_t bank_n, uint8_t tgl) -{ - if (tgl) { - hri_usbendpoint_set_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_DTGLOUT << bank_n)); - } else { - hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_DTGLOUT << bank_n)); - } -} - -/** \brief ACK IN/OUT complete interrupt - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - */ -static inline void _usbd_ep_ack_io_cpt(uint8_t epn, uint8_t bank_n) -{ - _usbd_ep_int_ack(epn, USB_DEVICE_EPINTFLAG_TRCPT0 << bank_n); -} - -/** \brief Set DMA buffer used for bank data - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] addr DMA buffer address to set. - */ -static inline void _usbd_ep_set_buf(uint8_t epn, uint8_t bank_n, uint32_t addr) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->ADDR.reg = addr; -} - -/** \brief Set bank count for IN transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] count Data count for IN. - */ -static inline void _usbd_ep_set_in_count(uint8_t epn, uint8_t bank_n, uint16_t count) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->PCKSIZE.bit.MULTI_PACKET_SIZE = count; -} - -/** \brief Set bank size for IN transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] size Data size for IN. - */ -static inline void _usbd_ep_set_in_size(uint8_t epn, uint8_t bank_n, uint16_t size) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->PCKSIZE.bit.BYTE_COUNT = size; -} - -/** \brief Set bank count for OUT transaction - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] count Data count for OUT. - */ -static inline void _usbd_ep_set_out_count(uint8_t epn, uint8_t bank_n, uint16_t count) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->PCKSIZE.bit.BYTE_COUNT = count; -} - -/** \brief Set bank size for OUT transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] size Data size for OUT. - */ -static inline void _usbd_ep_set_out_size(uint8_t epn, uint8_t bank_n, uint16_t size) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->PCKSIZE.bit.MULTI_PACKET_SIZE = size; -} - -/** Set bank size and count for IN transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] size Data size. - * \param[in] count Initial data count. - */ -static inline void _usbd_ep_set_in_trans(uint8_t epn, uint8_t bank_n, uint32_t size, uint32_t count) -{ - _usbd_ep_set_in_size(epn, bank_n, size); - _usbd_ep_set_in_count(epn, bank_n, count); -} - -/** \brief Set bank size and count for OUT transaction - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] size Data size. - * \param[in] count Initial data count. - */ -static inline void _usbd_ep_set_out_trans(uint8_t epn, uint8_t bank_n, uint32_t size, uint32_t count) -{ - _usbd_ep_set_out_size(epn, bank_n, size); - _usbd_ep_set_out_count(epn, bank_n, count); -} - -/** \brief Clear bank status - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - */ -static inline void _usbd_ep_clear_bank_status(uint8_t epn, uint8_t bank_n) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->STATUS_BK.reg = 0; -} - -/** Set IN ready for IN transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] rdy Set to \c true to indicate IN packet ready to TX. - */ -static inline void _usbd_ep_set_in_rdy(uint8_t epn, uint8_t bank_n, const bool rdy) -{ - if (rdy) { - hri_usbendpoint_set_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); - } else { - hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); - } -} - -/** \brief Set bank ready for OUT transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] rdy Set to \c true to indicate OUT bank ready to RX. - */ -static inline void _usbd_ep_set_out_rdy(uint8_t epn, uint8_t bank_n, const bool rdy) -{ - if (rdy) { - hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); - } else { - hri_usbendpoint_set_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); - } -} - -/** - * \brief Convert USB endpoint size to HW PCKSIZE.SIZE - * \param[in] n Number of bytes of endpoint size. - */ -static inline uint8_t _usbd_ep_pcksize_size(uint16_t n) -{ - return ( - (n > 512) - ? 7 - : ((n > 256) ? 6 : ((n > 128) ? 5 : ((n > 64) ? 4 : ((n > 32) ? 3 : ((n > 16) ? 2 : ((n > 8) ? 1 : 0))))))); -} - -/** - * \brief Obtain endpoint descriptor pointer - * \param[in] epn Endpoint number. - * \param[in] dir Endpoint direction. - */ -static inline struct _usb_d_dev_ep *_usb_d_dev_ept(uint8_t epn, bool dir) -{ - uint8_t ep_index = (epn == 0) ? 0 : (dir ? (epn + CONF_USB_D_MAX_EP_N) : epn); - return &dev_inst.ep[ep_index]; -} - -/** - * \brief Handles USB SOF interrupt - */ -static inline void _usb_d_dev_sof(void) -{ - /* ACK SOF interrupt. */ - hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_SOF); - dev_inst.callbacks.sof(); -} - -/** - * \brief Handles USB LPM Suspend interrupt - */ -static inline void _usb_d_dev_lpmsusp(void) -{ - uint8_t i; - uint32_t lpm_variable = 0; - - /* ACK LPMSUSP interrupt. */ - hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_SUSPEND_INT_FLAGS); - /* Change interrupt masks */ - hri_usbdevice_clear_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); - hri_usbdevice_set_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); - - /* Find LPM data */ - for (i = 0; i < CONF_USB_D_MAX_EP_N; i++) { - UsbDeviceDescBank *bank = &prvt_inst.desc_table[i].DeviceDescBank[0]; - if (bank->EXTREG.bit.SUBPID == 0x3) { - /* Save LPM variable */ - lpm_variable = bank->EXTREG.bit.VARIABLE; - /* Clear */ - bank->EXTREG.reg = 0; - break; - } - } - dev_inst.callbacks.event(USB_EV_LPM_SUSPEND, lpm_variable); -} - -/** - * \brief Handles USB RAM Error interrupt - */ -static inline void _usb_d_dev_ramerr(void) -{ - hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_RAMACER); - dev_inst.callbacks.event(USB_EV_ERROR, 0); -} - -/** - * \brief Handles USB resume/wakeup interrupts - */ -static inline void _usb_d_dev_wakeup(void) -{ - hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_WAKEUP_INT_FLAGS); - hri_usbdevice_clear_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); - hri_usbdevice_set_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); - - _usb_d_dev_wait_clk_rdy(CONF_USB_D_CLK_SRC); - dev_inst.callbacks.event(USB_EV_WAKEUP, 0); -} - -/** - * \brief Handles USB signal reset interrupt - */ -static inline void _usb_d_dev_reset(void) -{ - /* EP0 will not be reseted by USB RESET, disable manually. */ - hri_usbendpoint_write_EPCFG_reg(USB, 0, 0); - - hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_EORST); - hri_usbdevice_clear_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); - hri_usbdevice_set_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); - - _usb_d_dev_reset_epts(); - dev_inst.callbacks.event(USB_EV_RESET, 0); -} - -static inline void _usb_d_dev_suspend(void) -{ - hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_SUSPEND_INT_FLAGS); - hri_usbdevice_clear_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); - hri_usbdevice_set_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); - - dev_inst.callbacks.event(USB_EV_SUSPEND, 0); -} - -/** - * \brief Handles USB non-endpoint interrupt - */ -static inline bool _usb_d_dev_handle_nep(void) -{ - bool rc = true; - uint16_t flags = hri_usbdevice_read_INTFLAG_reg(USB); - flags &= hri_usbdevice_read_INTEN_reg(USB); - - if (flags & USB_DEVICE_INTFLAG_SOF) { - _usb_d_dev_sof(); - return true; - } - if (flags & USB_DEVICE_INTFLAG_LPMSUSP) { - _usb_d_dev_lpmsusp(); - } else if (flags & USB_DEVICE_INTFLAG_RAMACER) { - _usb_d_dev_ramerr(); - } else if (flags & USB_D_WAKEUP_INT_FLAGS) { - _usb_d_dev_wakeup(); - } else if (flags & USB_DEVICE_INTFLAG_EORST) { - _usb_d_dev_reset(); - } else if (flags & USB_DEVICE_INTFLAG_SUSPEND) { - _usb_d_dev_suspend(); - } else { - rc = false; - } - return rc; -} - -/** - * \brief Prepare next IN transactions - * \param[in] ept Pointer to endpoint information. - * \param[in] isr Invoked from ISR. - */ -static void _usb_d_dev_in_next(struct _usb_d_dev_ep *ept, bool isr) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ept->ep); - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[0]; - uint16_t trans_count = isr ? bank[1].PCKSIZE.bit.BYTE_COUNT : 0; - uint16_t trans_next; - uint16_t last_pkt = trans_count & ((ept->size == 1023) ? ept->size : (ept->size - 1)); - uint8_t inten = 0; - bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); - - if (isr) { - _usbd_ep_ack_io_cpt(epn, 1); - } - - ept->trans_count += trans_count; - /* Send more data. */ - if (ept->trans_count < ept->trans_size) { - trans_next = ept->trans_size - ept->trans_count; - if (ept->flags.bits.use_cache) { - if (trans_next > ept->size) { - trans_next = ept->size; - } - memcpy(ept->cache, &ept->trans_buf[ept->trans_count], trans_next); - _usbd_ep_set_buf(epn, 1, (uint32_t)ept->cache); - } else { - if (trans_next > USB_D_DEV_TRANS_MAX) { - trans_next = USB_D_DEV_TRANS_MAX; - } - _usbd_ep_set_buf(epn, 1, (uint32_t)&ept->trans_buf[ept->trans_count]); - } - _usbd_ep_set_in_trans(epn, 1, trans_next, 0); - goto _in_tx_exec; - } else if (ept->flags.bits.need_zlp) { - ept->flags.bits.need_zlp = 0; - _usbd_ep_set_in_trans(epn, 1, 0, 0); - goto _in_tx_exec; - } - /* Complete. */ - if (is_ctrl) { - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK1_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRCPT0); - } else { - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK1_INT_FLAGS); - } - - /* No ping-pong, so ask more data without background transfer. */ - if (last_pkt == ept->size) { - ept->flags.bits.is_busy = 0; - if (dev_inst.ep_callbacks.more(ept->ep, ept->trans_count)) { - /* More data added. */ - return; - } - ept->flags.bits.is_busy = 1; - } - /* Finish normally. */ - _usb_d_dev_trans_done(ept, USB_TRANS_DONE); - return; - -_in_tx_exec: - if (!isr) { - if (is_ctrl) { - /* Control endpoint: SETUP or OUT will abort IN transaction. - * SETUP: terminate the IN without any notification. Trigger - * SETUP callback. - * OUT NAK: terminate IN. - */ - inten = USB_D_BANK1_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL0; - } else { - /* Initialize normal IN transaction. */ - inten = USB_D_BANK1_INT_FLAGS; - } - hri_usbendpoint_set_EPINTEN_reg(hw, epn, inten); - } - _usbd_ep_set_in_rdy(epn, 1, true); -} - -/** - * \brief Prepare next OUT transactions - * \param[in] ept Pointer to endpoint information. - * \param[in] isr Invoked from ISR. - */ -static void _usb_d_dev_out_next(struct _usb_d_dev_ep *ept, bool isr) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ept->ep); - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[0]; - uint16_t trans_size = isr ? bank->PCKSIZE.bit.MULTI_PACKET_SIZE : 0; - uint16_t last_trans = isr ? bank->PCKSIZE.bit.BYTE_COUNT : 0; - uint16_t size_mask = (ept->size == 1023) ? 1023 : (ept->size - 1); - uint16_t last_pkt = last_trans & size_mask; - uint16_t trans_next; - uint8_t inten; - bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); - - if (isr) { - _usbd_ep_ack_io_cpt(epn, 0); - } - - /* If cache is used, copy data to buffer. */ - if (ept->flags.bits.use_cache && ept->trans_size) { - uint16_t buf_remain = ept->trans_size - ept->trans_count; - memcpy(&ept->trans_buf[ept->trans_count], ept->cache, (buf_remain > last_pkt) ? last_pkt : buf_remain); - } - - /* Force wait ZLP */ - if (ept->trans_size == 0 && ept->flags.bits.need_zlp) { - ept->flags.bits.need_zlp = 0; - ept->flags.bits.use_cache = 1; - _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); - _usbd_ep_set_out_trans(epn, 0, ept->size, 0); - goto _out_rx_exec; - } else if (isr && last_pkt < ept->size) { - /* Short packet. */ - ept->flags.bits.need_zlp = 0; - ept->trans_count += last_trans; - } else { - /* Full packets. */ - ept->trans_count += trans_size; - - /* Wait more data */ - if (ept->trans_count < ept->trans_size) { - /* Continue OUT */ - trans_next = ept->trans_size - ept->trans_count; - if (ept->flags.bits.use_cache) { - /* Expect single packet each time. */ - if (trans_next > ept->size) { - trans_next = ept->size; - } - _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); - } else { - /* Multiple packets each time. */ - if (trans_next > ept->size) { - if (trans_next > USB_D_DEV_TRANS_MAX) { - trans_next = USB_D_DEV_TRANS_MAX; - } else { - /* Must expect multiple of ep size. */ - trans_next -= trans_next & size_mask; - } - } else if (trans_next < ept->size) { - /* Last un-aligned packet should be cached. */ - ept->flags.bits.use_cache = 1; - } - _usbd_ep_set_buf(epn, 0, (uint32_t)&ept->trans_buf[ept->trans_count]); - } - _usbd_ep_set_out_trans(epn, 0, trans_next, 0); - goto _out_rx_exec; - } - } - /* Finish normally. */ - if (is_ctrl) { - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK0_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL1); - } else { - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK0_INT_FLAGS); - } - /* Use ep0 out cache for next setup packets */ - if (0 == epn) { - _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); - } - _usb_d_dev_trans_done(ept, USB_TRANS_DONE); - return; - -_out_rx_exec: - if (!isr) { - if (is_ctrl) { - /* Initialize control OUT transaction. */ - - /* Control transfer: SETUP or IN request will abort the - * OUT transactions. - * SETUP: terminate OUT without any notification. - * Trigger SETUP notification. - * IN NAK: finish OUT normally. Notify data done. - */ - _usbd_ep_clear_bank_status(epn, 1); - /* Detect OUT, SETUP, NAK IN */ - inten = USB_D_BANK0_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL1; - } else { - /* Initialize normal OUT transaction. */ - inten = USB_D_BANK0_INT_FLAGS; - } - hri_usbendpoint_set_EPINTEN_reg(hw, epn, inten); - } - _usbd_ep_set_out_rdy(epn, 0, true); -} - -/** - * \brief Handles setup received interrupt - * \param[in] ept Pointer to endpoint information. - */ -static void _usb_d_dev_handle_setup(struct _usb_d_dev_ep *ept) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); - - if (!is_ctrl) { - /* Should never be here! */ - _usbd_ep_ack_setup(epn); - _usbd_ep_stop_setup(epn); - return; - } - /* Control transfer: - * SETUP transaction will terminate IN/OUT transaction, - * and start new transaction with received SETUP packet. - */ - if (_usb_d_dev_ep_is_busy(ept)) { - ept->flags.bits.is_busy = 0; - - /* Stop transfer on either direction. */ - _usbd_ep_set_in_rdy(epn, 1, false); - _usbd_ep_set_out_rdy(epn, 0, false); - } - ept->flags.bits.is_stalled = 0; - - /* Clear status and notify SETUP */ - _usbd_ep_clear_bank_status(epn, 0); - _usbd_ep_clear_bank_status(epn, 1); - _usbd_ep_int_ack(epn, USB_D_BANK0_INT_FLAGS | USB_D_BANK1_INT_FLAGS); - _usbd_ep_int_dis(epn, USB_D_BANK0_INT_FLAGS | USB_D_BANK1_INT_FLAGS); - /* Invoke callback. */ - dev_inst.ep_callbacks.setup(ept->ep); -} - -/** - * \brief Handles stall sent interrupt - * \param[in] ept Pointer to endpoint information. - * \param[in] bank_n Bank number. - */ -static void _usb_d_dev_handle_stall(struct _usb_d_dev_ep *ept, const uint8_t bank_n) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - /* Clear interrupt enable. Leave status there for status check. */ - _usbd_ep_int_stall_en(epn, bank_n, false); - dev_inst.ep_callbacks.done(ept->ep, USB_TRANS_STALL, ept->trans_count); -} - -/** - * \brief Handles transaction fail interrupt - * \param[in] ept Pointer to endpoint information. - * \param[in] bank_n Bank number. - */ -static void _usb_d_dev_handle_trfail(struct _usb_d_dev_ep *ept, const uint8_t bank_n) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ept->ep); - const uint8_t fail[2] = {USB_DEVICE_EPINTFLAG_TRFAIL0, USB_DEVICE_EPINTFLAG_TRFAIL1}; - UsbDeviceDescBank *bank = prvt_inst.desc_table[epn].DeviceDescBank; - uint8_t eptype - = bank_n ? hri_usbendpoint_read_EPCFG_EPTYPE1_bf(hw, epn) : hri_usbendpoint_read_EPCFG_EPTYPE0_bf(hw, epn); - bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); - USB_DEVICE_STATUS_BK_Type st; - st.reg = bank[bank_n].STATUS_BK.reg; - - if ((eptype == USB_D_EPTYPE_ISOCH) && st.bit.CRCERR) { - bank[bank_n].STATUS_BK.bit.CRCERR = 0; - hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); - _usb_d_dev_trans_stop(ept, bank_n, USB_TRANS_ERROR); - } else if (st.bit.ERRORFLOW) { - bank[bank_n].STATUS_BK.bit.ERRORFLOW = 0; - hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); - /* Abort control transfer. */ - if (is_ctrl && _usb_d_dev_ep_is_busy(ept)) { - if (bank_n != _usb_d_dev_ep_is_in(ept)) { - _usb_d_dev_trans_stop(ept, _usb_d_dev_ep_is_in(ept), USB_TRANS_DONE); - } - } - } else { - _usbd_ep_clear_bank_status(epn, bank_n); - hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); - } -} - -/** - * \brief Analyze flags for setup transaction - * \param[in] ept Pointer to endpoint information. - * \param[in] flags Endpoint interrupt flags. - */ -static inline void _usb_d_dev_trans_setup_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) -{ - /* - * SETPU is automatically ACKed by hardware - * OUT & IN should be set to NAK when checking SETUP - * No need to check OUT & IN status. - */ - if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { - _usb_d_dev_handle_setup(ept); - } else if (flags & USB_DEVICE_EPINTFLAG_STALL1) { - _usb_d_dev_handle_stall(ept, 1); - } else if (flags & USB_DEVICE_EPINTFLAG_STALL0) { - _usb_d_dev_handle_stall(ept, 0); - } -} - -/** - * \brief Analyze flags for IN transactions - * \param[in] ept Pointer to endpoint information. - * \param[in] flags Endpoint interrupt flags. - */ -static inline void _usb_d_dev_trans_in_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) -{ - /* - * Check IN flags - * If control endpoint, SETUP & OUT is checked to see if abort - */ - if (flags & USB_DEVICE_EPINTFLAG_STALL1) { - _usb_d_dev_handle_stall(ept, 1); - } else if (flags & USB_DEVICE_EPINTFLAG_TRFAIL1) { - _usb_d_dev_handle_trfail(ept, 1); - } else if (flags & USB_DEVICE_EPINTFLAG_TRCPT1) { - _usb_d_dev_in_next(ept, true); - } else if (_usb_d_dev_ep_is_ctrl(ept)) { - /* Check OUT NAK - * Check SETUP - */ - if (flags & USB_DEVICE_EPINTFLAG_TRFAIL0) { - _usb_d_dev_handle_trfail(ept, 0); - } else if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { - _usb_d_dev_handle_setup(ept); - } - } -} - -/** - * \brief Analyze flags for OUT transactions - * \param[in] ept Pointer to endpoint information. - * \param[in] flags Endpoint interrupt flags. - */ -static inline void _usb_d_dev_trans_out_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) -{ - /* - * Check OUT flags. - * If control endpoint, SETUP & IN NAK is checked to see if abort - */ - if (flags & USB_DEVICE_EPINTFLAG_STALL0) { - _usb_d_dev_handle_stall(ept, 0); - } else if (flags & USB_DEVICE_EPINTFLAG_TRFAIL0) { - _usb_d_dev_handle_trfail(ept, 0); - } else if (flags & USB_DEVICE_EPINTFLAG_TRCPT0) { - _usb_d_dev_out_next(ept, true); - } else if (_usb_d_dev_ep_is_ctrl(ept)) { - /* Check IN NAK - * Check SETUP - */ - if (flags & USB_DEVICE_EPINTFLAG_TRFAIL1) { - _usb_d_dev_handle_trfail(ept, 1); - } else if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { - _usb_d_dev_handle_setup(ept); - } - } -} - -/** - * \brief Handles the endpoint interrupts. - * \param[in] epint Endpoint interrupt summary (by bits). - * \param[in] ept Pointer to endpoint information. - */ -static inline void _usb_d_dev_handle_eps(uint32_t epint, struct _usb_d_dev_ep *ept) -{ - Usb *hw = USB; - - uint8_t flags, mask; - uint8_t epn = USB_EP_GET_N(ept->ep); - - if (!(epint & (1u << epn))) { - return; - } - flags = hw->DEVICE.DeviceEndpoint[epn].EPINTFLAG.reg; - mask = hw->DEVICE.DeviceEndpoint[epn].EPINTENSET.reg; - flags &= mask; - if (flags) { - if ((ept->flags.bits.eptype == 0x1) && !_usb_d_dev_ep_is_busy(ept)) { - _usb_d_dev_trans_setup_isr(ept, flags); - } else if (_usb_d_dev_ep_is_in(ept)) { - _usb_d_dev_trans_in_isr(ept, flags); - } else { - _usb_d_dev_trans_out_isr(ept, flags); - } - } -} - -/** - * \brief USB device interrupt handler - * \param[in] unused The parameter is not used - */ -static void _usb_d_dev_handler(void) -{ - Usb * hw = USB; - uint8_t i; - - uint16_t epint = hw->DEVICE.EPINTSMRY.reg; - if (0 == epint) { - if (_usb_d_dev_handle_nep()) { - return; - } - } - /* Handle endpoints */ - for (i = 0; i < USB_D_N_EP; i++) { - struct _usb_d_dev_ep *ept = &dev_inst.ep[i]; - if (ept->ep == 0xFF) { - continue; - } - _usb_d_dev_handle_eps(epint, ept); - } -} - -/** - * \brief Reset all endpoint software instances - */ -static void _usb_d_dev_reset_epts(void) -{ - uint8_t i; - for (i = 0; i < USB_D_N_EP; i++) { - _usb_d_dev_trans_done(&dev_inst.ep[i], USB_TRANS_RESET); - dev_inst.ep[i].ep = 0xFF; - dev_inst.ep[i].flags.u8 = 0; - } - memset(prvt_inst.desc_table, 0, sizeof(UsbDeviceDescriptor) * (CONF_USB_D_MAX_EP_N + 1)); -} - -int32_t _usb_d_dev_init(void) -{ - Usb * hw = USB; - uint8_t speed = CONF_USB_D_SPEED; - const uint8_t spdconf[4] = { - USB_DEVICE_CTRLB_SPDCONF(1), /* LS */ - USB_DEVICE_CTRLB_SPDCONF(0), /* FS */ - 0, - 0 /* Reserved */ - }; - - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - if (hri_usbdevice_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_usbdevice_set_CTRLA_SWRST_bit(hw); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - - dev_inst.callbacks.sof = (_usb_d_dev_sof_cb_t)_dummy_func_no_return; - dev_inst.callbacks.event = (_usb_d_dev_event_cb_t)_dummy_func_no_return; - - dev_inst.ep_callbacks.setup = (_usb_d_dev_ep_cb_setup_t)_dummy_func_no_return; - dev_inst.ep_callbacks.more = (_usb_d_dev_ep_cb_more_t)_dummy_func_no_return; - dev_inst.ep_callbacks.done = (_usb_d_dev_ep_cb_done_t)_dummy_func_no_return; - - _usb_d_dev_reset_epts(); - - _usb_load_calib(); - - hri_usbdevice_write_CTRLA_reg(hw, USB_CTRLA_RUNSTDBY); - hri_usbdevice_write_DESCADD_reg(hw, (uint32_t)prvt_inst.desc_table); - hri_usbdevice_write_CTRLB_reg(hw, spdconf[speed] | USB_DEVICE_CTRLB_DETACH); - - return ERR_NONE; -} - -void _usb_d_dev_deinit(void) -{ - Usb *hw = USB; - - while (_usb_d_dev_disable() < 0) - ; - - hri_usbdevice_write_CTRLA_reg(hw, USB_CTRLA_SWRST); - - NVIC_DisableIRQ(USB_IRQn); - NVIC_ClearPendingIRQ(USB_IRQn); -} - -int32_t _usb_d_dev_enable(void) -{ - Usb * hw = USB; - uint8_t ctrla; - - if (hri_usbdevice_get_SYNCBUSY_reg(hw, (USB_SYNCBUSY_ENABLE | USB_SYNCBUSY_SWRST))) { - return -USB_ERR_DENIED; - } - ctrla = hri_usbdevice_read_CTRLA_reg(hw); - if ((ctrla & USB_CTRLA_ENABLE) == 0) { - hri_usbdevice_write_CTRLA_reg(hw, ctrla | USB_CTRLA_ENABLE); - } - - NVIC_EnableIRQ(USB_IRQn); - - hri_usbdevice_set_INTEN_reg(hw, - USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST | USB_DEVICE_INTENSET_RAMACER - | USB_D_SUSPEND_INT_FLAGS); - - return ERR_NONE; -} - -int32_t _usb_d_dev_disable(void) -{ - Usb * hw = USB; - uint8_t ctrla; - - if (hri_usbdevice_get_SYNCBUSY_reg(hw, (USB_SYNCBUSY_ENABLE | USB_SYNCBUSY_SWRST))) { - return -USB_ERR_DENIED; - } - - ctrla = hri_usbdevice_read_CTRLA_reg(hw); - if (ctrla & USB_CTRLA_ENABLE) { - hri_usbdevice_write_CTRLA_reg(hw, ctrla & ~USB_CTRLA_ENABLE); - } - NVIC_DisableIRQ(USB_IRQn); - - hri_usbdevice_clear_INTEN_reg(hw, - USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST | USB_DEVICE_INTENSET_RAMACER - | USB_D_SUSPEND_INT_FLAGS - | USB_D_WAKEUP_INT_FLAGS); - - return ERR_NONE; -} - -void _usb_d_dev_attach(void) -{ - hri_usbdevice_clear_CTRLB_DETACH_bit(USB); -} - -void _usb_d_dev_detach(void) -{ - hri_usbdevice_set_CTRLB_DETACH_bit(USB); -} - -#ifndef USB_FSMSTATUS_FSMSTATE_ON -#define USB_FSMSTATUS_FSMSTATE_ON USB_FSMSTATUS_FSMSTATE(2ul) -#endif -void _usb_d_dev_send_remotewakeup(void) -{ - uint32_t retry = CONF_USB_RMT_WKUP_RETRY; - _usb_d_dev_wait_clk_rdy(CONF_USB_D_CLK_SRC); - while ((USB_FSMSTATUS_FSMSTATE_ON != hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(USB)) && (retry--)) { - USB->DEVICE.CTRLB.bit.UPRSM = 1; - } -} - -enum usb_speed _usb_d_dev_get_speed(void) -{ - uint8_t sp = (enum usb_speed)hri_usbdevice_read_STATUS_SPEED_bf(USB); - const enum usb_speed speed[2] = {USB_SPEED_FS, USB_SPEED_LS}; - - return speed[sp]; -} - -void _usb_d_dev_set_address(uint8_t addr) -{ - hri_usbdevice_write_DADD_reg(USB, USB_DEVICE_DADD_ADDEN | USB_DEVICE_DADD_DADD(addr)); -} - -uint8_t _usb_d_dev_get_address(void) -{ - uint8_t addr = hri_usbdevice_read_DADD_DADD_bf(USB); - return addr; -} - -uint16_t _usb_d_dev_get_frame_n(void) -{ - uint16_t fn = hri_usbdevice_read_FNUM_FNUM_bf(USB); - return fn; -} - -uint8_t _usb_d_dev_get_uframe_n(void) -{ - uint8_t ufn = hri_usbdevice_read_FNUM_MFNUM_bf(USB); - return ufn; -} - -/** - * \brief Start a setup transaction - * \param[in] ept Endpoint information. - */ -static inline void _usb_d_dev_trans_setup(struct _usb_d_dev_ep *ept) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ept->ep); - - _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); - _usbd_ep_set_out_trans(epn, 0, ept->size, 0); - - hri_usbendpoint_clear_EPSTATUS_reg(hw, epn, USB_DEVICE_EPSTATUS_STALLRQ(0x3) | USB_DEVICE_EPSTATUS_BK1RDY); - _usbd_ep_set_out_rdy(epn, 0, false); - - hri_usbendpoint_set_EPINTEN_reg(hw, epn, USB_D_SETUP_INT_FLAGS); -} - -int32_t _usb_d_dev_ep0_init(const uint8_t max_pkt_siz) -{ - return _usb_d_dev_ep_init(0, USB_EP_XTYPE_CTRL, max_pkt_siz); -} - -int32_t _usb_d_dev_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_siz) -{ - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - - uint8_t ep_type = attr & USB_EP_XTYPE_MASK; - const struct _usb_ep_cfg_item *pcfg = &_usb_ep_cfgs[epn]; - - if (epn > CONF_USB_D_MAX_EP_N) { - return -USB_ERR_PARAM; - } - if (ept->ep != 0xFF) { - return -USB_ERR_REDO; - } - if (ep_type == USB_EP_XTYPE_CTRL) { - struct _usb_d_dev_ep *ept_in = _usb_d_dev_ept(epn, !dir); - if (ept_in->ep != 0xFF) { - return -USB_ERR_REDO; - } - if (pcfg->cache == NULL) { - return -USB_ERR_FUNC; - } - } - if ((dir ? pcfg->i_cache : pcfg->cache) && ((dir ? pcfg->i_size : pcfg->size) < max_pkt_siz)) { - return -USB_ERR_FUNC; - } - - /* Initialize EP n settings */ - ept->cache = (uint8_t *)(dir ? pcfg->i_cache : pcfg->cache); - ept->size = max_pkt_siz; - ept->flags.u8 = (ep_type + 1); - ept->ep = ep; - - return USB_OK; -} - -void _usb_d_dev_ep_deinit(uint8_t ep) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - - if (epn > CONF_USB_D_MAX_EP_N || !_usb_d_dev_ep_is_used(ept)) { - return; - } - - /* Finish pending transactions. */ - _usb_d_dev_trans_stop(ept, dir, USB_TRANS_RESET); - - /* Disable the endpoint. */ - if (_usb_d_dev_ep_is_ctrl(ept)) { - hw->DEVICE.DeviceEndpoint[ep].EPCFG.reg = 0; - } else if (USB_EP_GET_DIR(ep)) { - hw->DEVICE.DeviceEndpoint[USB_EP_GET_N(ep)].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - } else { - hw->DEVICE.DeviceEndpoint[ep].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - } - ept->flags.u8 = 0; - ept->ep = 0xFF; -} - -int32_t _usb_d_dev_ep_enable(const uint8_t ep) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - uint8_t epcfg = hri_usbendpoint_read_EPCFG_reg(hw, epn); - UsbDeviceDescBank * bank; - - if (epn > CONF_USB_D_MAX_EP_N || !_usb_d_dev_ep_is_used(ept)) { - return -USB_ERR_PARAM; - } - - bank = prvt_inst.desc_table[epn].DeviceDescBank; - if (ept->flags.bits.eptype == USB_D_EPTYPE_CTRL) { - if (epcfg & (USB_DEVICE_EPCFG_EPTYPE1_Msk | USB_DEVICE_EPCFG_EPTYPE0_Msk)) { - return -USB_ERR_REDO; - } - hri_usbendpoint_write_EPCFG_reg(hw, epn, USB_D_EPCFG_CTRL); - bank[0].PCKSIZE.reg = USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(ept->size) - | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); - bank[1].PCKSIZE.reg - = USB_DEVICE_PCKSIZE_BYTE_COUNT(ept->size) | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); - /* By default, control endpoint accept SETUP and NAK all other token. */ - _usbd_ep_set_out_rdy(epn, 0, false); - _usbd_ep_set_in_rdy(epn, 1, false); - - _usbd_ep_clear_bank_status(epn, 0); - _usbd_ep_clear_bank_status(epn, 1); - - /* Enable SETUP reception for control endpoint. */ - _usb_d_dev_trans_setup(ept); - - } else if (dir) { - if (epcfg & USB_DEVICE_EPCFG_EPTYPE1_Msk) { - return -USB_ERR_REDO; - } - epcfg |= USB_DEVICE_EPCFG_EPTYPE1(ept->flags.bits.eptype); - hri_usbendpoint_write_EPCFG_reg(hw, epn, epcfg); - - bank[1].PCKSIZE.reg - = USB_DEVICE_PCKSIZE_BYTE_COUNT(ept->size) | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); - - /* By default, IN endpoint will NAK all token. */ - _usbd_ep_set_in_rdy(epn, 1, false); - _usbd_ep_clear_bank_status(epn, 1); - - } else { - - if (epcfg & USB_DEVICE_EPCFG_EPTYPE0_Msk) { - return -USB_ERR_REDO; - } - epcfg |= USB_DEVICE_EPCFG_EPTYPE0(ept->flags.bits.eptype); - hri_usbendpoint_write_EPCFG_reg(hw, epn, epcfg); - - bank[0].PCKSIZE.reg = USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(ept->size) - | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); - - /* By default, OUT endpoint will NAK all token. */ - _usbd_ep_set_out_rdy(epn, 0, false); - _usbd_ep_clear_bank_status(epn, 0); - } - - return USB_OK; -} - -void _usb_d_dev_ep_disable(const uint8_t ep) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - - _usb_d_dev_trans_stop(ept, dir, USB_TRANS_RESET); - if (_usb_d_dev_ep_is_ctrl(ept)) { - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_ALL_INT_FLAGS); - } -} - -/** - * \brief Get endpoint stall status - * \param[in] ept Pointer to endpoint information. - * \param[in] dir Endpoint direction. - * \return Stall status. - * \retval \c true Endpoint is stalled. - * \retval \c false Endpoint is not stalled. - */ -static inline int32_t _usb_d_dev_ep_stall_get(struct _usb_d_dev_ep *ept, bool dir) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - return _usbd_ep_is_stalled(epn, dir); -} - -/** - * \brief Set endpoint stall - * \param[in, out] ept Pointer to endpoint information. - * \param[in] dir Endpoint direction. - * \return Always 0, success. - */ -static inline int32_t _usb_d_dev_ep_stall_set(struct _usb_d_dev_ep *ept, bool dir) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - _usbd_ep_set_stall(epn, dir, true); - _usbd_ep_int_en(epn, USB_DEVICE_EPINTFLAG_STALL0 << dir); - ept->flags.bits.is_stalled = 1; - /* In stall interrupt abort the transfer. */ - return ERR_NONE; -} - -/** - * \brief Clear endpoint stall - * \param[in, out] ept Pointer to endpoint information. - * \param[in] dir Endpoint direction. - * \return Always 0, success. - */ -static inline int32_t _usb_d_dev_ep_stall_clr(struct _usb_d_dev_ep *ept, bool dir) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - bool is_stalled = _usbd_ep_is_stalled(epn, dir); - if (!is_stalled) { - return ERR_NONE; - } - _usbd_ep_set_stall(epn, dir, false); - _usbd_ep_int_dis(epn, USB_DEVICE_EPINTFLAG_STALL0 << dir); - if (_usbd_ep_is_stall_sent(epn, dir)) { - _usbd_ep_ack_stall(epn, dir); - _usbd_ep_set_toggle(epn, dir, 0); - } - if (_usb_d_dev_ep_is_ctrl(ept)) { - if ((hri_usbendpoint_read_EPSTATUS_reg(USB, epn) & USB_DEVICE_EPSTATUS_STALLRQ_Msk) == 0) { - ept->flags.bits.is_stalled = 0; - } - } else { - ept->flags.bits.is_stalled = 0; - } - return ERR_NONE; -} - -int32_t _usb_d_dev_ep_stall(const uint8_t ep, const enum usb_ep_stall_ctrl ctrl) -{ - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - int32_t rc; - - if (epn > CONF_USB_D_MAX_EP_N) { - return -USB_ERR_PARAM; - } - - if (USB_EP_STALL_SET == ctrl) { - rc = _usb_d_dev_ep_stall_set(ept, dir); - } else if (USB_EP_STALL_CLR == ctrl) { - rc = _usb_d_dev_ep_stall_clr(ept, dir); - } else { - rc = _usb_d_dev_ep_stall_get(ept, dir); - } - return rc; -} - -/** - * \brief Finish the transaction and invoke callback - * \param[in, out] ept Pointer to endpoint information. - * \param[in] code Information code passed. - */ -static void _usb_d_dev_trans_done(struct _usb_d_dev_ep *ept, const int32_t code) -{ - if (!(_usb_d_dev_ep_is_used(ept) && _usb_d_dev_ep_is_busy(ept))) { - return; - } - ept->flags.bits.is_busy = 0; - dev_inst.ep_callbacks.done(ept->ep, code, ept->trans_count); -} - -/** - * \brief Terminate the transaction with specific status code - * \param[in, out] ept Pointer to endpoint information. - * \param[in] dir Endpoint direction. - * \param[in] code Information code passed. - */ -static void _usb_d_dev_trans_stop(struct _usb_d_dev_ep *ept, bool dir, const int32_t code) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - ; - const uint8_t intflags[2] = {USB_D_BANK0_INT_FLAGS, USB_D_BANK1_INT_FLAGS}; - if (!(_usb_d_dev_ep_is_used(ept) && _usb_d_dev_ep_is_busy(ept))) { - return; - } - /* Stop transfer */ - if (dir) { - /* NAK IN */ - _usbd_ep_set_in_rdy(epn, 1, false); - } else { - /* NAK OUT */ - _usbd_ep_set_out_rdy(epn, 0, false); - } - _usbd_ep_int_ack(epn, intflags[dir]); - _usbd_ep_int_dis(epn, intflags[dir]); - _usb_d_dev_trans_done(ept, code); -} - -int32_t _usb_d_dev_ep_read_req(const uint8_t ep, uint8_t *req_buf) -{ - uint8_t epn = USB_EP_GET_N(ep); - UsbDeviceDescBank *bank = prvt_inst.desc_table[epn].DeviceDescBank; - uint32_t addr = bank[0].ADDR.reg; - uint16_t bytes = bank[0].PCKSIZE.bit.BYTE_COUNT; - - if (epn > CONF_USB_D_MAX_EP_N || !req_buf) { - return -USB_ERR_PARAM; - } - if (!_usbd_ep_is_ctrl(epn)) { - return -USB_ERR_FUNC; - } - if (!_usbd_ep_is_setup(epn)) { - return ERR_NONE; - } - memcpy(req_buf, (void *)addr, 8); - _usbd_ep_ack_setup(epn); - - return bytes; -} - -int32_t _usb_d_dev_ep_trans(const struct usb_d_transfer *trans) -{ - uint8_t epn = USB_EP_GET_N(trans->ep); - bool dir = USB_EP_GET_DIR(trans->ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - - uint16_t size_mask = (ept->size == 1023) ? 1023 : (ept->size - 1); - bool size_n_aligned = (trans->size & size_mask); - - bool use_cache = false; - - volatile hal_atomic_t flags; - - if (epn > CONF_USB_D_MAX_EP_N) { - return -USB_ERR_PARAM; - } - - /* Cases that needs cache: - * 1. Buffer not in RAM (cache all). - * 2. IN/OUT with unaligned buffer (cache all). - * 3. OUT with unaligned packet size (cache last packet). - * 4. OUT size < 8 (sub-case for 3). - */ - if (!_usb_is_addr4dma(trans->buf, trans->size) || (!_usb_is_aligned(trans->buf)) - || (!dir && (trans->size < ept->size))) { - if (!ept->cache) { - return -USB_ERR_FUNC; - } - /* Use cache all the time. */ - use_cache = true; - } - if (!dir && size_n_aligned) { - if (!ept->cache) { - return -USB_ERR_PARAM; - } - /* Set 'use_cache' on last packet. */ - } - - /* Check halt */ - if (ept->flags.bits.is_stalled) { - return USB_HALTED; - } - - /* Try to start transactions. */ - - atomic_enter_critical(&flags); - if (_usb_d_dev_ep_is_busy(ept)) { - atomic_leave_critical(&flags); - return USB_BUSY; - } - ept->flags.bits.is_busy = 1; - atomic_leave_critical(&flags); - - /* Copy transaction information. */ - ept->trans_buf = trans->buf; - ept->trans_size = trans->size; - ept->trans_count = 0; - - ept->flags.bits.dir = dir; - ept->flags.bits.use_cache = use_cache; - ept->flags.bits.need_zlp = (trans->zlp && (!size_n_aligned)); - - if (dir) { - _usb_d_dev_in_next(ept, false); - } else { - _usb_d_dev_out_next(ept, false); - } - - return ERR_NONE; -} - -void _usb_d_dev_ep_abort(const uint8_t ep) -{ - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - if (epn > CONF_USB_D_MAX_EP_N) { - return; - } - _usb_d_dev_trans_stop(ept, dir, USB_TRANS_ABORT); -} - -int32_t _usb_d_dev_ep_get_status(const uint8_t ep, struct usb_d_trans_status *stat) -{ - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - bool busy, stall; - - if (epn > CONF_USB_D_MAX_EP_N) { - return USB_ERR_PARAM; - } - busy = ept->flags.bits.is_busy; - stall = ept->flags.bits.is_stalled; - if (stat) { - stat->stall = stall; - stat->busy = busy; - stat->setup = USB->DEVICE.DeviceEndpoint[epn].EPINTFLAG.bit.RXSTP; - stat->dir = ept->flags.bits.dir; - stat->size = ept->trans_size; - stat->count = ept->trans_count; - stat->ep = ep; - stat->xtype = ept->flags.bits.eptype - 1; - } - if (stall) { - return USB_HALTED; - } - if (busy) { - return USB_BUSY; - } - return USB_OK; -} - -void _usb_d_dev_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func) -{ - FUNC_PTR f = (func == NULL) ? (FUNC_PTR)_dummy_func_no_return : (FUNC_PTR)func; - if (type == USB_D_CB_EVENT) { - dev_inst.callbacks.event = (_usb_d_dev_event_cb_t)f; - } else if (type == USB_D_CB_SOF) { - dev_inst.callbacks.sof = (_usb_d_dev_sof_cb_t)f; - } -} - -void _usb_d_dev_register_ep_callback(const enum usb_d_dev_ep_cb_type type, const FUNC_PTR func) -{ - FUNC_PTR f = (func == NULL) ? (FUNC_PTR)_dummy_func_no_return : (FUNC_PTR)func; - if (type == USB_D_DEV_EP_CB_SETUP) { - dev_inst.ep_callbacks.setup = (_usb_d_dev_ep_cb_setup_t)f; - } else if (type == USB_D_DEV_EP_CB_MORE) { - dev_inst.ep_callbacks.more = (_usb_d_dev_ep_cb_more_t)f; - } else if (type == USB_D_DEV_EP_CB_DONE) { - dev_inst.ep_callbacks.done = (_usb_d_dev_ep_cb_done_t)f; - } -} - -/** -* \brief USB interrupt handler -*/ -void USB_Handler(void) -{ - - _usb_d_dev_handler(); -} diff --git a/atmel-samd/asf4/samd21/hri/hri_ac_d21.h b/atmel-samd/asf4/samd21/hri/hri_ac_d21.h deleted file mode 100644 index 3efd86b22..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_ac_d21.h +++ /dev/null @@ -1,1586 +0,0 @@ -/** - * \file - * - * \brief SAM AC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_AC_COMPONENT_ -#ifndef _HRI_AC_D21_H_INCLUDED_ -#define _HRI_AC_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_AC_CRITICAL_SECTIONS) -#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define AC_CRITICAL_SECTION_ENTER() -#define AC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_ac_evctrl_reg_t; -typedef uint32_t hri_ac_compctrl_reg_t; -typedef uint8_t hri_ac_ctrla_reg_t; -typedef uint8_t hri_ac_ctrlb_reg_t; -typedef uint8_t hri_ac_intenset_reg_t; -typedef uint8_t hri_ac_intflag_reg_t; -typedef uint8_t hri_ac_scaler_reg_t; -typedef uint8_t hri_ac_statusa_reg_t; -typedef uint8_t hri_ac_statusb_reg_t; -typedef uint8_t hri_ac_statusc_reg_t; -typedef uint8_t hri_ac_winctrl_reg_t; - -static inline void hri_ac_wait_for_sync(const void *const hw) -{ - while (((const Ac *)hw)->STATUSB.bit.SYNCBUSY) - ; -} - -static inline bool hri_ac_is_syncing(const void *const hw) -{ - return ((const Ac *)hw)->STATUSB.bit.SYNCBUSY; -} - -static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; -} - -static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; -} - -static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; - } -} - -static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; -} - -static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; -} - -static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; -} - -static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; - } -} - -static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; -} - -static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; -} - -static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; -} - -static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; - } -} - -static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; -} - -static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - ((Ac *)hw)->INTENSET.reg = mask; -} - -static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) -{ - return ((Ac *)hw)->INTENSET.reg; -} - -static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) -{ - ((Ac *)hw)->INTENSET.reg = data; - ((Ac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - ((Ac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; -} - -static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; -} - -static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; -} - -static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; -} - -static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; -} - -static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; -} - -static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; -} - -static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; -} - -static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; -} - -static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; -} - -static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; -} - -static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; -} - -static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) -{ - return ((Ac *)hw)->INTFLAG.reg; -} - -static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) -{ - ((Ac *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLB.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= ~AC_CTRLA_ENABLE; - tmp |= value << AC_CTRLA_ENABLE_Pos; - ((Ac *)hw)->CTRLA.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_RUNSTDBY_Msk; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_RUNSTDBY_Msk) >> AC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= ~AC_CTRLA_RUNSTDBY_Msk; - tmp |= value << AC_CTRLA_RUNSTDBY_Pos; - ((Ac *)hw)->CTRLA.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_RUNSTDBY_Msk; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_RUNSTDBY_Msk; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_CTRLA_LPMUX_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_LPMUX; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_LPMUX_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_LPMUX) >> AC_CTRLA_LPMUX_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_CTRLA_LPMUX_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= ~AC_CTRLA_LPMUX; - tmp |= value << AC_CTRLA_LPMUX_Pos; - ((Ac *)hw)->CTRLA.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_LPMUX_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_LPMUX; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_LPMUX_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_LPMUX; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) -{ - return ((Ac *)hw)->CTRLA.reg; -} - -static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEO0; - tmp |= value << AC_EVCTRL_COMPEO0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEO1; - tmp |= value << AC_EVCTRL_COMPEO1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_WINEO0; - tmp |= value << AC_EVCTRL_WINEO0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEI0; - tmp |= value << AC_EVCTRL_COMPEI0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEI1; - tmp |= value << AC_EVCTRL_COMPEI1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) -{ - return ((Ac *)hw)->EVCTRL.reg; -} - -static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= ~AC_WINCTRL_WEN0; - tmp |= value << AC_WINCTRL_WEN0_Pos; - ((Ac *)hw)->WINCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; - return tmp; -} - -static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= ~AC_WINCTRL_WINTSEL0_Msk; - tmp |= AC_WINCTRL_WINTSEL0(data); - ((Ac *)hw)->WINCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; - return tmp; -} - -static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) -{ - return ((Ac *)hw)->WINCTRL.reg; -} - -static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_ENABLE; - tmp |= value << AC_COMPCTRL_ENABLE_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SINGLE; - tmp |= value << AC_COMPCTRL_SINGLE_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SWAP; - tmp |= value << AC_COMPCTRL_SWAP_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_HYST_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_HYST_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYST) >> AC_COMPCTRL_HYST_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_HYST_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_HYST; - tmp |= value << AC_COMPCTRL_HYST_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_HYST_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_HYST_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SPEED_Msk; - tmp |= AC_COMPCTRL_SPEED(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_INTSEL_Msk; - tmp |= AC_COMPCTRL_INTSEL(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_MUXNEG_Msk; - tmp |= AC_COMPCTRL_MUXNEG(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_MUXPOS_Msk; - tmp |= AC_COMPCTRL_MUXPOS(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_OUT_Msk; - tmp |= AC_COMPCTRL_OUT(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_FLEN_Msk; - tmp |= AC_COMPCTRL_FLEN(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Ac *)hw)->COMPCTRL[index].reg; -} - -static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, - hri_ac_scaler_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; - return tmp; -} - -static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp &= ~AC_SCALER_VALUE_Msk; - tmp |= AC_SCALER_VALUE(data); - ((Ac *)hw)->SCALER[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; - return tmp; -} - -static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) -{ - return ((Ac *)hw)->SCALER[index].reg; -} - -static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; -} - -static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) -{ - return ((Ac *)hw)->STATUSA.reg; -} - -static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; -} - -static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; -} - -static inline bool hri_ac_get_STATUSB_SYNCBUSY_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_SYNCBUSY) >> AC_STATUSB_SYNCBUSY_Pos; -} - -static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) -{ - return ((Ac *)hw)->STATUSB.reg; -} - -static inline bool hri_ac_get_STATUSC_STATE0_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_STATE0) >> AC_STATUSC_STATE0_Pos; -} - -static inline bool hri_ac_get_STATUSC_STATE1_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_STATE1) >> AC_STATUSC_STATE1_Pos; -} - -static inline hri_ac_statusc_reg_t hri_ac_get_STATUSC_WSTATE0_bf(const void *const hw, hri_ac_statusc_reg_t mask) -{ - return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_WSTATE0(mask)) >> AC_STATUSC_WSTATE0_Pos; -} - -static inline hri_ac_statusc_reg_t hri_ac_read_STATUSC_WSTATE0_bf(const void *const hw) -{ - return (((Ac *)hw)->STATUSC.reg & AC_STATUSC_WSTATE0_Msk) >> AC_STATUSC_WSTATE0_Pos; -} - -static inline hri_ac_statusc_reg_t hri_ac_get_STATUSC_reg(const void *const hw, hri_ac_statusc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->STATUSC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_statusc_reg_t hri_ac_read_STATUSC_reg(const void *const hw) -{ - return ((Ac *)hw)->STATUSC.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_AC_D21_H_INCLUDED */ -#endif /* _SAMD21_AC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_adc_d21.h b/atmel-samd/asf4/samd21/hri/hri_adc_d21.h deleted file mode 100644 index f511c59f4..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_adc_d21.h +++ /dev/null @@ -1,2513 +0,0 @@ -/** - * \file - * - * \brief SAM ADC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_ADC_COMPONENT_ -#ifndef _HRI_ADC_D21_H_INCLUDED_ -#define _HRI_ADC_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_ADC_CRITICAL_SECTIONS) -#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define ADC_CRITICAL_SECTION_ENTER() -#define ADC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_adc_calib_reg_t; -typedef uint16_t hri_adc_ctrlb_reg_t; -typedef uint16_t hri_adc_gaincorr_reg_t; -typedef uint16_t hri_adc_offsetcorr_reg_t; -typedef uint16_t hri_adc_result_reg_t; -typedef uint16_t hri_adc_winlt_reg_t; -typedef uint16_t hri_adc_winut_reg_t; -typedef uint32_t hri_adc_inputctrl_reg_t; -typedef uint8_t hri_adc_avgctrl_reg_t; -typedef uint8_t hri_adc_ctrla_reg_t; -typedef uint8_t hri_adc_dbgctrl_reg_t; -typedef uint8_t hri_adc_evctrl_reg_t; -typedef uint8_t hri_adc_intenset_reg_t; -typedef uint8_t hri_adc_intflag_reg_t; -typedef uint8_t hri_adc_refctrl_reg_t; -typedef uint8_t hri_adc_sampctrl_reg_t; -typedef uint8_t hri_adc_status_reg_t; -typedef uint8_t hri_adc_swtrig_reg_t; -typedef uint8_t hri_adc_winctrl_reg_t; - -static inline void hri_adc_wait_for_sync(const void *const hw) -{ - while (((const Adc *)hw)->STATUS.bit.SYNCBUSY) - ; -} - -static inline bool hri_adc_is_syncing(const void *const hw) -{ - return ((const Adc *)hw)->STATUS.bit.SYNCBUSY; -} - -static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; -} - -static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; -} - -static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; - } -} - -static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; -} - -static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; -} - -static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; -} - -static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; - } -} - -static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; -} - -static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; -} - -static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; -} - -static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; - } -} - -static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; -} - -static inline void hri_adc_set_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_SYNCRDY; -} - -static inline bool hri_adc_get_INTEN_SYNCRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_SYNCRDY) >> ADC_INTENSET_SYNCRDY_Pos; -} - -static inline void hri_adc_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_SYNCRDY; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_SYNCRDY; - } -} - -static inline void hri_adc_clear_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_SYNCRDY; -} - -static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - ((Adc *)hw)->INTENSET.reg = mask; -} - -static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) -{ - return ((Adc *)hw)->INTENSET.reg; -} - -static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) -{ - ((Adc *)hw)->INTENSET.reg = data; - ((Adc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - ((Adc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; -} - -static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; -} - -static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; -} - -static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; -} - -static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; -} - -static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; -} - -static inline bool hri_adc_get_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_SYNCRDY) >> ADC_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_adc_clear_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_SYNCRDY; -} - -static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; -} - -static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; -} - -static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; -} - -static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; -} - -static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; -} - -static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; -} - -static inline bool hri_adc_get_interrupt_SYNCRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_SYNCRDY) >> ADC_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_adc_clear_interrupt_SYNCRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_SYNCRDY; -} - -static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) -{ - return ((Adc *)hw)->INTFLAG.reg; -} - -static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) -{ - ((Adc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_ENABLE; - tmp |= value << ADC_CTRLA_ENABLE_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_RUNSTDBY; - tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) -{ - return ((Adc *)hw)->CTRLA.reg; -} - -static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= ~ADC_REFCTRL_REFCOMP; - tmp |= value << ADC_REFCTRL_REFCOMP_Pos; - ((Adc *)hw)->REFCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= ~ADC_REFCTRL_REFSEL_Msk; - tmp |= ADC_REFCTRL_REFSEL(data); - ((Adc *)hw)->REFCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->REFCTRL.reg; -} - -static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; - tmp |= ADC_AVGCTRL_SAMPLENUM(data); - ((Adc *)hw)->AVGCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; - return tmp; -} - -static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= ~ADC_AVGCTRL_ADJRES_Msk; - tmp |= ADC_AVGCTRL_ADJRES(data); - ((Adc *)hw)->AVGCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; - return tmp; -} - -static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->AVGCTRL.reg; -} - -static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; - return tmp; -} - -static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; - tmp |= ADC_SAMPCTRL_SAMPLEN(data); - ((Adc *)hw)->SAMPCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; - return tmp; -} - -static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->SAMPCTRL.reg; -} - -static inline void hri_adc_set_CTRLB_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_DIFFMODE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_DIFFMODE_bit(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_DIFFMODE) >> ADC_CTRLB_DIFFMODE_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_DIFFMODE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_DIFFMODE; - tmp |= value << ADC_CTRLB_DIFFMODE_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_DIFFMODE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_DIFFMODE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_LEFTADJ; - tmp |= value << ADC_CTRLB_LEFTADJ_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_FREERUN; - tmp |= value << ADC_CTRLB_FREERUN_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_CORREN; - tmp |= value << ADC_CTRLB_CORREN_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_RESSEL_Msk; - tmp |= ADC_CTRLB_RESSEL(data); - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_PRESCALER(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_PRESCALER(mask)) >> ADC_CTRLB_PRESCALER_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_PRESCALER_Msk; - tmp |= ADC_CTRLB_PRESCALER(data); - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_PRESCALER(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_PRESCALER_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_PRESCALER(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_PRESCALER_Msk) >> ADC_CTRLB_PRESCALER_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) -{ - return ((Adc *)hw)->CTRLB.reg; -} - -static inline void hri_adc_set_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->WINCTRL.reg |= ADC_WINCTRL_WINMODE(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winctrl_reg_t hri_adc_get_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->WINCTRL.reg; - tmp = (tmp & ADC_WINCTRL_WINMODE(mask)) >> ADC_WINCTRL_WINMODE_Pos; - return tmp; -} - -static inline void hri_adc_write_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->WINCTRL.reg; - tmp &= ~ADC_WINCTRL_WINMODE_Msk; - tmp |= ADC_WINCTRL_WINMODE(data); - ((Adc *)hw)->WINCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->WINCTRL.reg &= ~ADC_WINCTRL_WINMODE(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINCTRL_WINMODE_bf(const void *const hw, hri_adc_winctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->WINCTRL.reg ^= ADC_WINCTRL_WINMODE(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winctrl_reg_t hri_adc_read_WINCTRL_WINMODE_bf(const void *const hw) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->WINCTRL.reg; - tmp = (tmp & ADC_WINCTRL_WINMODE_Msk) >> ADC_WINCTRL_WINMODE_Pos; - return tmp; -} - -static inline void hri_adc_set_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winctrl_reg_t hri_adc_get_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->WINCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINCTRL_reg(const void *const hw, hri_adc_winctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winctrl_reg_t hri_adc_read_WINCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->WINCTRL.reg; -} - -static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= ~ADC_SWTRIG_FLUSH; - tmp |= value << ADC_SWTRIG_FLUSH_Pos; - ((Adc *)hw)->SWTRIG.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) -{ - uint8_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= ~ADC_SWTRIG_START; - tmp |= value << ADC_SWTRIG_START_Pos; - ((Adc *)hw)->SWTRIG.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) -{ - return ((Adc *)hw)->SWTRIG.reg; -} - -static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; - tmp |= ADC_INPUTCTRL_MUXPOS(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; - tmp |= ADC_INPUTCTRL_MUXNEG(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_INPUTSCAN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_INPUTSCAN_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_INPUTSCAN(mask)) >> ADC_INPUTCTRL_INPUTSCAN_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_INPUTSCAN_Msk; - tmp |= ADC_INPUTCTRL_INPUTSCAN(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_INPUTSCAN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_INPUTSCAN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_INPUTSCAN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_INPUTSCAN_bf(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_INPUTSCAN_Msk) >> ADC_INPUTCTRL_INPUTSCAN_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_INPUTOFFSET(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_INPUTOFFSET(mask)) >> ADC_INPUTCTRL_INPUTOFFSET_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_INPUTOFFSET_Msk; - tmp |= ADC_INPUTCTRL_INPUTOFFSET(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_INPUTOFFSET(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_INPUTOFFSET_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_INPUTOFFSET(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_INPUTOFFSET_bf(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_INPUTOFFSET_Msk) >> ADC_INPUTCTRL_INPUTOFFSET_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_GAIN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_GAIN(mask)) >> ADC_INPUTCTRL_GAIN_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_GAIN_Msk; - tmp |= ADC_INPUTCTRL_GAIN(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_GAIN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_GAIN_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_GAIN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_GAIN_bf(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_GAIN_Msk) >> ADC_INPUTCTRL_GAIN_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->INPUTCTRL.reg; -} - -static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_STARTEI; - tmp |= value << ADC_EVCTRL_STARTEI_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_SYNCEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_SYNCEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_SYNCEI_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_SYNCEI) >> ADC_EVCTRL_SYNCEI_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_SYNCEI_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_SYNCEI; - tmp |= value << ADC_EVCTRL_SYNCEI_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_SYNCEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_SYNCEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_SYNCEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_SYNCEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_RESRDYEO; - tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_WINMONEO; - tmp |= value << ADC_EVCTRL_WINMONEO_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->EVCTRL.reg; -} - -static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->WINLT.reg; - tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; - return tmp; -} - -static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->WINLT.reg; - tmp &= ~ADC_WINLT_WINLT_Msk; - tmp |= ADC_WINLT_WINLT(data); - ((Adc *)hw)->WINLT.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->WINLT.reg; - tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; - return tmp; -} - -static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->WINLT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) -{ - return ((Adc *)hw)->WINLT.reg; -} - -static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->WINUT.reg; - tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; - return tmp; -} - -static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->WINUT.reg; - tmp &= ~ADC_WINUT_WINUT_Msk; - tmp |= ADC_WINUT_WINUT(data); - ((Adc *)hw)->WINUT.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw); - ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw); - tmp = ((Adc *)hw)->WINUT.reg; - tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; - return tmp; -} - -static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->WINUT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) -{ - return ((Adc *)hw)->WINUT.reg; -} - -static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; - return tmp; -} - -static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp &= ~ADC_GAINCORR_GAINCORR_Msk; - tmp |= ADC_GAINCORR_GAINCORR(data); - ((Adc *)hw)->GAINCORR.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; - return tmp; -} - -static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) -{ - return ((Adc *)hw)->GAINCORR.reg; -} - -static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, - hri_adc_offsetcorr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; - return tmp; -} - -static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; - tmp |= ADC_OFFSETCORR_OFFSETCORR(data); - ((Adc *)hw)->OFFSETCORR.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; - return tmp; -} - -static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) -{ - return ((Adc *)hw)->OFFSETCORR.reg; -} - -static inline void hri_adc_set_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_LINEARITY_CAL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_LINEARITY_CAL(mask)) >> ADC_CALIB_LINEARITY_CAL_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_LINEARITY_CAL_Msk; - tmp |= ADC_CALIB_LINEARITY_CAL(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_LINEARITY_CAL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_LINEARITY_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_LINEARITY_CAL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_LINEARITY_CAL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_LINEARITY_CAL_Msk) >> ADC_CALIB_LINEARITY_CAL_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIAS_CAL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIAS_CAL(mask)) >> ADC_CALIB_BIAS_CAL_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIAS_CAL_Msk; - tmp |= ADC_CALIB_BIAS_CAL(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIAS_CAL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIAS_CAL_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIAS_CAL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIAS_CAL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIAS_CAL_Msk) >> ADC_CALIB_BIAS_CAL_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) -{ - return ((Adc *)hw)->CALIB.reg; -} - -static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp &= ~ADC_DBGCTRL_DBGRUN; - tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; - ((Adc *)hw)->DBGCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->DBGCTRL.reg; -} - -static inline bool hri_adc_get_STATUS_SYNCBUSY_bit(const void *const hw) -{ - return (((Adc *)hw)->STATUS.reg & ADC_STATUS_SYNCBUSY) >> ADC_STATUS_SYNCBUSY_Pos; -} - -static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw) -{ - return ((Adc *)hw)->STATUS.reg; -} - -static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) -{ - hri_adc_wait_for_sync(hw); - return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; -} - -static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) -{ - hri_adc_wait_for_sync(hw); - return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; -} - -static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->RESULT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) -{ - return ((Adc *)hw)->RESULT.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_ADC_D21_H_INCLUDED */ -#endif /* _SAMD21_ADC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_d21.h b/atmel-samd/asf4/samd21/hri/hri_d21.h deleted file mode 100644 index adaf36067..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_d21.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - * \file - * - * \brief SAM D21 HRI top-level header file - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifndef _HRI_D21_H_INCLUDED_ -#define _HRI_D21_H_INCLUDED_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#endif /* _HRI_D21_H_INCLUDED_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_dac_d21.h b/atmel-samd/asf4/samd21/hri/hri_dac_d21.h deleted file mode 100644 index f4444bf11..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_dac_d21.h +++ /dev/null @@ -1,1033 +0,0 @@ -/** - * \file - * - * \brief SAM DAC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_DAC_COMPONENT_ -#ifndef _HRI_DAC_D21_H_INCLUDED_ -#define _HRI_DAC_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DAC_CRITICAL_SECTIONS) -#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DAC_CRITICAL_SECTION_ENTER() -#define DAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_dac_data_reg_t; -typedef uint16_t hri_dac_databuf_reg_t; -typedef uint8_t hri_dac_ctrla_reg_t; -typedef uint8_t hri_dac_ctrlb_reg_t; -typedef uint8_t hri_dac_evctrl_reg_t; -typedef uint8_t hri_dac_intenset_reg_t; -typedef uint8_t hri_dac_intflag_reg_t; -typedef uint8_t hri_dac_status_reg_t; - -static inline void hri_dac_wait_for_sync(const void *const hw) -{ - while (((const Dac *)hw)->STATUS.bit.SYNCBUSY) - ; -} - -static inline bool hri_dac_is_syncing(const void *const hw) -{ - return ((const Dac *)hw)->STATUS.bit.SYNCBUSY; -} - -static inline void hri_dac_set_INTEN_UNDERRUN_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN; -} - -static inline bool hri_dac_get_INTEN_UNDERRUN_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN) >> DAC_INTENSET_UNDERRUN_Pos; -} - -static inline void hri_dac_write_INTEN_UNDERRUN_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN; - } -} - -static inline void hri_dac_clear_INTEN_UNDERRUN_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN; -} - -static inline void hri_dac_set_INTEN_EMPTY_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY; -} - -static inline bool hri_dac_get_INTEN_EMPTY_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY) >> DAC_INTENSET_EMPTY_Pos; -} - -static inline void hri_dac_write_INTEN_EMPTY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY; - } -} - -static inline void hri_dac_clear_INTEN_EMPTY_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY; -} - -static inline void hri_dac_set_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_SYNCRDY; -} - -static inline bool hri_dac_get_INTEN_SYNCRDY_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_SYNCRDY) >> DAC_INTENSET_SYNCRDY_Pos; -} - -static inline void hri_dac_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_SYNCRDY; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_SYNCRDY; - } -} - -static inline void hri_dac_clear_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_SYNCRDY; -} - -static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - ((Dac *)hw)->INTENSET.reg = mask; -} - -static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) -{ - return ((Dac *)hw)->INTENSET.reg; -} - -static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) -{ - ((Dac *)hw)->INTENSET.reg = data; - ((Dac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - ((Dac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_dac_get_INTFLAG_UNDERRUN_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) >> DAC_INTFLAG_UNDERRUN_Pos; -} - -static inline void hri_dac_clear_INTFLAG_UNDERRUN_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN; -} - -static inline bool hri_dac_get_INTFLAG_EMPTY_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY) >> DAC_INTFLAG_EMPTY_Pos; -} - -static inline void hri_dac_clear_INTFLAG_EMPTY_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY; -} - -static inline bool hri_dac_get_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_SYNCRDY) >> DAC_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_dac_clear_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_SYNCRDY; -} - -static inline bool hri_dac_get_interrupt_UNDERRUN_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN) >> DAC_INTFLAG_UNDERRUN_Pos; -} - -static inline void hri_dac_clear_interrupt_UNDERRUN_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN; -} - -static inline bool hri_dac_get_interrupt_EMPTY_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY) >> DAC_INTFLAG_EMPTY_Pos; -} - -static inline void hri_dac_clear_interrupt_EMPTY_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY; -} - -static inline bool hri_dac_get_interrupt_SYNCRDY_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_SYNCRDY) >> DAC_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_dac_clear_interrupt_SYNCRDY_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_SYNCRDY; -} - -static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) -{ - return ((Dac *)hw)->INTFLAG.reg; -} - -static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) -{ - ((Dac *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_dac_wait_for_sync(hw); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_dac_wait_for_sync(hw); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp &= ~DAC_CTRLA_ENABLE; - tmp |= value << DAC_CTRLA_ENABLE_Pos; - ((Dac *)hw)->CTRLA.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_RUNSTDBY; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - hri_dac_wait_for_sync(hw); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp = (tmp & DAC_CTRLA_RUNSTDBY) >> DAC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp &= ~DAC_CTRLA_RUNSTDBY; - tmp |= value << DAC_CTRLA_RUNSTDBY_Pos; - ((Dac *)hw)->CTRLA.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_RUNSTDBY; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_RUNSTDBY; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) -{ - return ((Dac *)hw)->CTRLA.reg; -} - -static inline void hri_dac_set_CTRLB_EOEN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_EOEN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLB_EOEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_EOEN) >> DAC_CTRLB_EOEN_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLB_EOEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_EOEN; - tmp |= value << DAC_CTRLB_EOEN_Pos; - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_EOEN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_EOEN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_EOEN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_EOEN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLB_IOEN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_IOEN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLB_IOEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_IOEN) >> DAC_CTRLB_IOEN_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLB_IOEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_IOEN; - tmp |= value << DAC_CTRLB_IOEN_Pos; - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_IOEN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_IOEN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_IOEN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_IOEN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLB_LEFTADJ_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_LEFTADJ; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLB_LEFTADJ_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_LEFTADJ) >> DAC_CTRLB_LEFTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_LEFTADJ; - tmp |= value << DAC_CTRLB_LEFTADJ_Pos; - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_LEFTADJ_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_LEFTADJ; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_LEFTADJ_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_LEFTADJ; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLB_VPD_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_VPD; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLB_VPD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_VPD) >> DAC_CTRLB_VPD_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLB_VPD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_VPD; - tmp |= value << DAC_CTRLB_VPD_Pos; - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_VPD_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_VPD; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_VPD_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_VPD; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLB_BDWP_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_BDWP; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLB_BDWP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_BDWP) >> DAC_CTRLB_BDWP_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLB_BDWP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_BDWP; - tmp |= value << DAC_CTRLB_BDWP_Pos; - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_BDWP_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_BDWP; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_BDWP_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_BDWP; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; - return tmp; -} - -static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_REFSEL_Msk; - tmp |= DAC_CTRLB_REFSEL(data); - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; - return tmp; -} - -static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) -{ - return ((Dac *)hw)->CTRLB.reg; -} - -static inline void hri_dac_set_EVCTRL_STARTEI_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_STARTEI_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_STARTEI) >> DAC_EVCTRL_STARTEI_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_STARTEI; - tmp |= value << DAC_EVCTRL_STARTEI_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_STARTEI_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_STARTEI_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_EMPTYEO_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_EMPTYEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_EMPTYEO) >> DAC_EVCTRL_EMPTYEO_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_EMPTYEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_EMPTYEO; - tmp |= value << DAC_EVCTRL_EMPTYEO_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_EMPTYEO_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_EMPTYEO_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) -{ - return ((Dac *)hw)->EVCTRL.reg; -} - -static inline void hri_dac_set_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->DATA.reg |= DAC_DATA_DATA(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_data_reg_t hri_dac_get_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask) -{ - uint16_t tmp; - hri_dac_wait_for_sync(hw); - tmp = ((Dac *)hw)->DATA.reg; - tmp = (tmp & DAC_DATA_DATA(mask)) >> DAC_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dac_write_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t data) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - tmp = ((Dac *)hw)->DATA.reg; - tmp &= ~DAC_DATA_DATA_Msk; - tmp |= DAC_DATA_DATA(data); - ((Dac *)hw)->DATA.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->DATA.reg &= ~DAC_DATA_DATA(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DATA_DATA_bf(const void *const hw, hri_dac_data_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->DATA.reg ^= DAC_DATA_DATA(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_data_reg_t hri_dac_read_DATA_DATA_bf(const void *const hw) -{ - uint16_t tmp; - hri_dac_wait_for_sync(hw); - tmp = ((Dac *)hw)->DATA.reg; - tmp = (tmp & DAC_DATA_DATA_Msk) >> DAC_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dac_set_DATA_reg(const void *const hw, hri_dac_data_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATA.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_data_reg_t hri_dac_get_DATA_reg(const void *const hw, hri_dac_data_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_DATA_reg(const void *const hw, hri_dac_data_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATA.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DATA_reg(const void *const hw, hri_dac_data_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATA.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DATA_reg(const void *const hw, hri_dac_data_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATA.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_data_reg_t hri_dac_read_DATA_reg(const void *const hw) -{ - return ((Dac *)hw)->DATA.reg; -} - -static inline void hri_dac_set_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->DATABUF.reg |= DAC_DATABUF_DATABUF(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_databuf_reg_t hri_dac_get_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask) -{ - uint16_t tmp; - hri_dac_wait_for_sync(hw); - tmp = ((Dac *)hw)->DATABUF.reg; - tmp = (tmp & DAC_DATABUF_DATABUF(mask)) >> DAC_DATABUF_DATABUF_Pos; - return tmp; -} - -static inline void hri_dac_write_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t data) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - tmp = ((Dac *)hw)->DATABUF.reg; - tmp &= ~DAC_DATABUF_DATABUF_Msk; - tmp |= DAC_DATABUF_DATABUF(data); - ((Dac *)hw)->DATABUF.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->DATABUF.reg &= ~DAC_DATABUF_DATABUF(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DATABUF_DATABUF_bf(const void *const hw, hri_dac_databuf_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw); - ((Dac *)hw)->DATABUF.reg ^= DAC_DATABUF_DATABUF(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_databuf_reg_t hri_dac_read_DATABUF_DATABUF_bf(const void *const hw) -{ - uint16_t tmp; - hri_dac_wait_for_sync(hw); - tmp = ((Dac *)hw)->DATABUF.reg; - tmp = (tmp & DAC_DATABUF_DATABUF_Msk) >> DAC_DATABUF_DATABUF_Pos; - return tmp; -} - -static inline void hri_dac_set_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATABUF.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_databuf_reg_t hri_dac_get_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DATABUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATABUF.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATABUF.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DATABUF_reg(const void *const hw, hri_dac_databuf_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATABUF.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_databuf_reg_t hri_dac_read_DATABUF_reg(const void *const hw) -{ - return ((Dac *)hw)->DATABUF.reg; -} - -static inline bool hri_dac_get_STATUS_SYNCBUSY_bit(const void *const hw) -{ - hri_dac_wait_for_sync(hw); - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_SYNCBUSY) >> DAC_STATUS_SYNCBUSY_Pos; -} - -static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) -{ - return ((Dac *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DAC_D21_H_INCLUDED */ -#endif /* _SAMD21_DAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_dmac_d21.h b/atmel-samd/asf4/samd21/hri/hri_dmac_d21.h deleted file mode 100644 index 229091701..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_dmac_d21.h +++ /dev/null @@ -1,4308 +0,0 @@ -/** - * \file - * - * \brief SAM DMAC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_DMAC_COMPONENT_ -#ifndef _HRI_DMAC_D21_H_INCLUDED_ -#define _HRI_DMAC_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) -#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DMAC_CRITICAL_SECTION_ENTER() -#define DMAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_dmac_crcctrl_reg_t; -typedef uint16_t hri_dmac_ctrl_reg_t; -typedef uint16_t hri_dmac_intpend_reg_t; -typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; -typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; -typedef uint32_t hri_dmac_active_reg_t; -typedef uint32_t hri_dmac_baseaddr_reg_t; -typedef uint32_t hri_dmac_busych_reg_t; -typedef uint32_t hri_dmac_chctrlb_reg_t; -typedef uint32_t hri_dmac_crcchksum_reg_t; -typedef uint32_t hri_dmac_crcdatain_reg_t; -typedef uint32_t hri_dmac_intstatus_reg_t; -typedef uint32_t hri_dmac_pendch_reg_t; -typedef uint32_t hri_dmac_prictrl0_reg_t; -typedef uint32_t hri_dmac_swtrigctrl_reg_t; -typedef uint32_t hri_dmac_wrbaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; -typedef uint8_t hri_dmac_chctrla_reg_t; -typedef uint8_t hri_dmac_chid_reg_t; -typedef uint8_t hri_dmac_chintenset_reg_t; -typedef uint8_t hri_dmac_chintflag_reg_t; -typedef uint8_t hri_dmac_chstatus_reg_t; -typedef uint8_t hri_dmac_crcstatus_reg_t; -typedef uint8_t hri_dmac_dbgctrl_reg_t; -typedef uint8_t hri_dmac_qosctrl_reg_t; - -static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; -} - -static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; -} - -static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; - } else { - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; - } -} - -static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; -} - -static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; -} - -static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; - } else { - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; - } -} - -static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; -} - -static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; -} - -static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; - } else { - ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; - } -} - -static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; -} - -static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - ((Dmac *)hw)->CHINTENSET.reg = mask; -} - -static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHINTENSET.reg; -} - -static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) -{ - ((Dmac *)hw)->CHINTENSET.reg = data; - ((Dmac *)hw)->CHINTENCLR.reg = ~data; -} - -static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - ((Dmac *)hw)->CHINTENCLR.reg = mask; -} - -static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw) -{ - ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHINTFLAG.reg; -} - -static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) -{ - ((Dmac *)hw)->CHINTFLAG.reg = mask; -} - -static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_DMAENABLE; - tmp |= value << DMAC_CTRL_DMAENABLE_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_CRCENABLE; - tmp |= value << DMAC_CTRL_CRCENABLE_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN0; - tmp |= value << DMAC_CTRL_LVLEN0_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN1; - tmp |= value << DMAC_CTRL_LVLEN1_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN2; - tmp |= value << DMAC_CTRL_LVLEN2_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN3; - tmp |= value << DMAC_CTRL_LVLEN3_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->CTRL.reg; -} - -static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, - hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; - tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; - tmp |= DMAC_CRCCTRL_CRCPOLY(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; - tmp |= DMAC_CRCCTRL_CRCSRC(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCCTRL.reg; -} - -static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, - hri_dmac_crcdatain_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; - tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); - ((Dmac *)hw)->CRCDATAIN.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCDATAIN.reg; -} - -static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, - hri_dmac_crcchksum_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; - tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); - ((Dmac *)hw)->CRCCHKSUM.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCCHKSUM.reg; -} - -static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp &= ~DMAC_DBGCTRL_DBGRUN; - tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; - ((Dmac *)hw)->DBGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->DBGCTRL.reg; -} - -static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos; - return tmp; -} - -static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk; - tmp |= DMAC_QOSCTRL_WRBQOS(data); - ((Dmac *)hw)->QOSCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos; - return tmp; -} - -static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos; - return tmp; -} - -static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp &= ~DMAC_QOSCTRL_FQOS_Msk; - tmp |= DMAC_QOSCTRL_FQOS(data); - ((Dmac *)hw)->QOSCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos; - return tmp; -} - -static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp &= ~DMAC_QOSCTRL_DQOS_Msk; - tmp |= DMAC_QOSCTRL_DQOS(data); - ((Dmac *)hw)->QOSCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->QOSCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->QOSCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->QOSCTRL.reg; -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, - hri_dmac_swtrigctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->SWTRIGCTRL.reg; -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN0; - tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN1; - tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN2; - tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN3; - tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI0(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI1(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI2(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI3(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) -{ - return ((Dmac *)hw)->PRICTRL0.reg; -} - -static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_TERR; - tmp |= value << DMAC_INTPEND_TERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_TCMPL; - tmp |= value << DMAC_INTPEND_TCMPL_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_SUSP; - tmp |= value << DMAC_INTPEND_SUSP_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_FERR; - tmp |= value << DMAC_INTPEND_FERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_BUSY; - tmp |= value << DMAC_INTPEND_BUSY_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_PEND; - tmp |= value << DMAC_INTPEND_PEND_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_ID_Msk; - tmp |= DMAC_INTPEND_ID(data); - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) -{ - return ((Dmac *)hw)->INTPEND.reg; -} - -static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, - hri_dmac_baseaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; - return tmp; -} - -static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; - tmp |= DMAC_BASEADDR_BASEADDR(data); - ((Dmac *)hw)->BASEADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; - return tmp; -} - -static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) -{ - return ((Dmac *)hw)->BASEADDR.reg; -} - -static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; - return tmp; -} - -static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; - tmp |= DMAC_WRBADDR_WRBADDR(data); - ((Dmac *)hw)->WRBADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; - return tmp; -} - -static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) -{ - return ((Dmac *)hw)->WRBADDR.reg; -} - -static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHID.reg; - tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHID.reg; - tmp &= ~DMAC_CHID_ID_Msk; - tmp |= DMAC_CHID_ID(data); - ((Dmac *)hw)->CHID.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHID.reg; - tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHID.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHID.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHID.reg; -} - -static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_ENABLE; - tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; - ((Dmac *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLA.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHCTRLA.reg; -} - -static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_EVIE; - tmp |= value << DMAC_CHCTRLB_EVIE_Pos; - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_EVOE; - tmp |= value << DMAC_CHCTRLB_EVOE_Pos; - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_EVACT_Msk; - tmp |= DMAC_CHCTRLB_EVACT(data); - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_LVL_Msk; - tmp |= DMAC_CHCTRLB_LVL(data); - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk; - tmp |= DMAC_CHCTRLB_TRIGSRC(data); - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk; - tmp |= DMAC_CHCTRLB_TRIGACT(data); - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_CMD_Msk; - tmp |= DMAC_CHCTRLB_CMD(data); - ((Dmac *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CHCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CHCTRLB.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHCTRLB.reg; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; -} - -static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->INTSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->INTSTATUS.reg; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; -} - -static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BUSYCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) -{ - return ((Dmac *)hw)->BUSYCH.reg; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; -} - -static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PENDCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) -{ - return ((Dmac *)hw)->PENDCH.reg; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->ACTIVE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) -{ - return ((Dmac *)hw)->ACTIVE.reg; -} - -static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; -} - -static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; -} - -static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw) -{ - return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; -} - -static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->CHSTATUS.reg; -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CRCSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCSTATUS.reg; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_VALID; - tmp |= value << DMAC_BTCTRL_VALID_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_SRCINC; - tmp |= value << DMAC_BTCTRL_SRCINC_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_DSTINC; - tmp |= value << DMAC_BTCTRL_DSTINC_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_STEPSEL; - tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; - tmp |= DMAC_BTCTRL_EVOSEL(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; - tmp |= DMAC_BTCTRL_BLOCKACT(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; - tmp |= DMAC_BTCTRL_BEATSIZE(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; - tmp |= DMAC_BTCTRL_STEPSIZE(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->BTCTRL.reg; -} - -static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, - hri_dmacdescriptor_btcnt_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp &= ~DMAC_BTCNT_BTCNT_Msk; - tmp |= DMAC_BTCNT_BTCNT(data); - ((DmacDescriptor *)hw)->BTCNT.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, - hri_dmacdescriptor_btcnt_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->BTCNT.reg; -} - -static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t -hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; - tmp |= DMAC_SRCADDR_SRCADDR(data); - ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->SRCADDR.reg; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t -hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; - tmp |= DMAC_DSTADDR_DSTADDR(data); - ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->DSTADDR.reg; -} - -static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t -hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; - tmp |= DMAC_DESCADDR_DESCADDR(data); - ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t -hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->DESCADDR.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DMAC_D21_H_INCLUDED */ -#endif /* _SAMD21_DMAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_dsu_d21.h b/atmel-samd/asf4/samd21/hri/hri_dsu_d21.h deleted file mode 100644 index cd001e0a7..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_dsu_d21.h +++ /dev/null @@ -1,979 +0,0 @@ -/** - * \file - * - * \brief SAM DSU - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_DSU_COMPONENT_ -#ifndef _HRI_DSU_D21_H_INCLUDED_ -#define _HRI_DSU_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DSU_CRITICAL_SECTIONS) -#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DSU_CRITICAL_SECTION_ENTER() -#define DSU_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_dsu_addr_reg_t; -typedef uint32_t hri_dsu_cid0_reg_t; -typedef uint32_t hri_dsu_cid1_reg_t; -typedef uint32_t hri_dsu_cid2_reg_t; -typedef uint32_t hri_dsu_cid3_reg_t; -typedef uint32_t hri_dsu_data_reg_t; -typedef uint32_t hri_dsu_dcc_reg_t; -typedef uint32_t hri_dsu_did_reg_t; -typedef uint32_t hri_dsu_end_reg_t; -typedef uint32_t hri_dsu_entry_reg_t; -typedef uint32_t hri_dsu_length_reg_t; -typedef uint32_t hri_dsu_memtype_reg_t; -typedef uint32_t hri_dsu_pid0_reg_t; -typedef uint32_t hri_dsu_pid1_reg_t; -typedef uint32_t hri_dsu_pid2_reg_t; -typedef uint32_t hri_dsu_pid3_reg_t; -typedef uint32_t hri_dsu_pid4_reg_t; -typedef uint8_t hri_dsu_ctrl_reg_t; -typedef uint8_t hri_dsu_statusa_reg_t; -typedef uint8_t hri_dsu_statusb_reg_t; - -static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CTRL.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= ~DSU_ADDR_ADDR_Msk; - tmp |= DSU_ADDR_ADDR(data); - ((Dsu *)hw)->ADDR.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) -{ - return ((Dsu *)hw)->ADDR.reg; -} - -static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; - return tmp; -} - -static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp &= ~DSU_LENGTH_LENGTH_Msk; - tmp |= DSU_LENGTH_LENGTH(data); - ((Dsu *)hw)->LENGTH.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; - return tmp; -} - -static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) -{ - return ((Dsu *)hw)->LENGTH.reg; -} - -static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DATA.reg; - tmp &= ~DSU_DATA_DATA_Msk; - tmp |= DSU_DATA_DATA(data); - ((Dsu *)hw)->DATA.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) -{ - return ((Dsu *)hw)->DATA.reg; -} - -static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp &= ~DSU_DCC_DATA_Msk; - tmp |= DSU_DCC_DATA(data); - ((Dsu *)hw)->DCC[index].reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) -{ - return ((Dsu *)hw)->DCC[index].reg; -} - -static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; -} - -static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; -} - -static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dsu *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) -{ - return ((Dsu *)hw)->STATUSB.reg; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DID.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) -{ - return ((Dsu *)hw)->DID.reg; -} - -static inline bool hri_dsu_get_ENTRY_EPRES_bit(const void *const hw, uint8_t index) -{ - return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_EPRES) >> DSU_ENTRY_EPRES_Pos; -} - -static inline bool hri_dsu_get_ENTRY_FMT_bit(const void *const hw, uint8_t index) -{ - return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_FMT) >> DSU_ENTRY_FMT_Pos; -} - -static inline hri_dsu_entry_reg_t hri_dsu_get_ENTRY_ADDOFF_bf(const void *const hw, uint8_t index, - hri_dsu_entry_reg_t mask) -{ - return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_ADDOFF(mask)) >> DSU_ENTRY_ADDOFF_Pos; -} - -static inline hri_dsu_entry_reg_t hri_dsu_read_ENTRY_ADDOFF_bf(const void *const hw, uint8_t index) -{ - return (((Dsu *)hw)->ENTRY[index].reg & DSU_ENTRY_ADDOFF_Msk) >> DSU_ENTRY_ADDOFF_Pos; -} - -static inline hri_dsu_entry_reg_t hri_dsu_get_ENTRY_reg(const void *const hw, uint8_t index, hri_dsu_entry_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ENTRY[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_entry_reg_t hri_dsu_read_ENTRY_reg(const void *const hw, uint8_t index) -{ - return ((Dsu *)hw)->ENTRY[index].reg; -} - -static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) -{ - return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; -} - -static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) -{ - return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; -} - -static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->END.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) -{ - return ((Dsu *)hw)->END.reg; -} - -static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) -{ - return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; -} - -static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MEMTYPE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) -{ - return ((Dsu *)hw)->MEMTYPE.reg; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID4.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID4.reg; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) -{ - return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID0.reg; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID1.reg; -} - -static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID2.reg; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID3.reg; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) -{ - return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID0.reg; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID1.reg; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) -{ - return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID2.reg; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) -{ - return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID3.reg; -} - -static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; -} - -static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; -} - -static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; -} - -static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; -} - -static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; -} - -static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dsu *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) -{ - return ((Dsu *)hw)->STATUSA.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DSU_D21_H_INCLUDED */ -#endif /* _SAMD21_DSU_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_eic_d21.h b/atmel-samd/asf4/samd21/hri/hri_eic_d21.h deleted file mode 100644 index 89919db6e..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_eic_d21.h +++ /dev/null @@ -1,3233 +0,0 @@ -/** - * \file - * - * \brief SAM EIC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_EIC_COMPONENT_ -#ifndef _HRI_EIC_D21_H_INCLUDED_ -#define _HRI_EIC_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_EIC_CRITICAL_SECTIONS) -#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define EIC_CRITICAL_SECTION_ENTER() -#define EIC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_eic_config_reg_t; -typedef uint32_t hri_eic_evctrl_reg_t; -typedef uint32_t hri_eic_intenset_reg_t; -typedef uint32_t hri_eic_intflag_reg_t; -typedef uint32_t hri_eic_wakeup_reg_t; -typedef uint8_t hri_eic_ctrl_reg_t; -typedef uint8_t hri_eic_nmictrl_reg_t; -typedef uint8_t hri_eic_nmiflag_reg_t; -typedef uint8_t hri_eic_status_reg_t; - -static inline void hri_eic_wait_for_sync(const void *const hw) -{ - while (((const Eic *)hw)->STATUS.bit.SYNCBUSY) - ; -} - -static inline bool hri_eic_is_syncing(const void *const hw) -{ - return ((const Eic *)hw)->STATUS.bit.SYNCBUSY; -} - -static inline void hri_eic_set_INTEN_EXTINT0_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT0; -} - -static inline bool hri_eic_get_INTEN_EXTINT0_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT0) >> EIC_INTENSET_EXTINT0_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT0; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT0; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT0_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT0; -} - -static inline void hri_eic_set_INTEN_EXTINT1_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT1; -} - -static inline bool hri_eic_get_INTEN_EXTINT1_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT1) >> EIC_INTENSET_EXTINT1_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT1; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT1; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT1_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT1; -} - -static inline void hri_eic_set_INTEN_EXTINT2_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT2; -} - -static inline bool hri_eic_get_INTEN_EXTINT2_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT2) >> EIC_INTENSET_EXTINT2_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT2; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT2; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT2_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT2; -} - -static inline void hri_eic_set_INTEN_EXTINT3_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT3; -} - -static inline bool hri_eic_get_INTEN_EXTINT3_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT3) >> EIC_INTENSET_EXTINT3_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT3; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT3; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT3_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT3; -} - -static inline void hri_eic_set_INTEN_EXTINT4_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT4; -} - -static inline bool hri_eic_get_INTEN_EXTINT4_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT4) >> EIC_INTENSET_EXTINT4_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT4; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT4; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT4_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT4; -} - -static inline void hri_eic_set_INTEN_EXTINT5_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT5; -} - -static inline bool hri_eic_get_INTEN_EXTINT5_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT5) >> EIC_INTENSET_EXTINT5_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT5; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT5; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT5_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT5; -} - -static inline void hri_eic_set_INTEN_EXTINT6_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT6; -} - -static inline bool hri_eic_get_INTEN_EXTINT6_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT6) >> EIC_INTENSET_EXTINT6_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT6; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT6; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT6_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT6; -} - -static inline void hri_eic_set_INTEN_EXTINT7_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT7; -} - -static inline bool hri_eic_get_INTEN_EXTINT7_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT7) >> EIC_INTENSET_EXTINT7_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT7; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT7; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT7_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT7; -} - -static inline void hri_eic_set_INTEN_EXTINT8_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT8; -} - -static inline bool hri_eic_get_INTEN_EXTINT8_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT8) >> EIC_INTENSET_EXTINT8_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT8_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT8; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT8; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT8_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT8; -} - -static inline void hri_eic_set_INTEN_EXTINT9_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT9; -} - -static inline bool hri_eic_get_INTEN_EXTINT9_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT9) >> EIC_INTENSET_EXTINT9_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT9_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT9; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT9; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT9_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT9; -} - -static inline void hri_eic_set_INTEN_EXTINT10_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT10; -} - -static inline bool hri_eic_get_INTEN_EXTINT10_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT10) >> EIC_INTENSET_EXTINT10_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT10_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT10; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT10; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT10_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT10; -} - -static inline void hri_eic_set_INTEN_EXTINT11_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT11; -} - -static inline bool hri_eic_get_INTEN_EXTINT11_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT11) >> EIC_INTENSET_EXTINT11_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT11_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT11; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT11; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT11_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT11; -} - -static inline void hri_eic_set_INTEN_EXTINT12_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT12; -} - -static inline bool hri_eic_get_INTEN_EXTINT12_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT12) >> EIC_INTENSET_EXTINT12_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT12_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT12; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT12; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT12_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT12; -} - -static inline void hri_eic_set_INTEN_EXTINT13_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT13; -} - -static inline bool hri_eic_get_INTEN_EXTINT13_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT13) >> EIC_INTENSET_EXTINT13_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT13_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT13; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT13; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT13_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT13; -} - -static inline void hri_eic_set_INTEN_EXTINT14_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT14; -} - -static inline bool hri_eic_get_INTEN_EXTINT14_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT14) >> EIC_INTENSET_EXTINT14_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT14_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT14; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT14; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT14_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT14; -} - -static inline void hri_eic_set_INTEN_EXTINT15_bit(const void *const hw) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT15; -} - -static inline bool hri_eic_get_INTEN_EXTINT15_bit(const void *const hw) -{ - return (((Eic *)hw)->INTENSET.reg & EIC_INTENSET_EXTINT15) >> EIC_INTENSET_EXTINT15_Pos; -} - -static inline void hri_eic_write_INTEN_EXTINT15_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT15; - } else { - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT15; - } -} - -static inline void hri_eic_clear_INTEN_EXTINT15_bit(const void *const hw) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT15; -} - -static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENSET.reg = mask; -} - -static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) -{ - return ((Eic *)hw)->INTENSET.reg; -} - -static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) -{ - ((Eic *)hw)->INTENSET.reg = data; - ((Eic *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) -{ - return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; -} - -static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) -{ - ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; -} - -static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMIFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) -{ - return ((Eic *)hw)->NMIFLAG.reg; -} - -static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) -{ - ((Eic *)hw)->NMIFLAG.reg = mask; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT0_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT0) >> EIC_INTFLAG_EXTINT0_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT0_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT0; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT1_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT1) >> EIC_INTFLAG_EXTINT1_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT1_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT1; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT2_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT2) >> EIC_INTFLAG_EXTINT2_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT2_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT2; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT3_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT3) >> EIC_INTFLAG_EXTINT3_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT3_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT3; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT4_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT4) >> EIC_INTFLAG_EXTINT4_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT4_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT4; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT5_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT5) >> EIC_INTFLAG_EXTINT5_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT5_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT5; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT6_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT6) >> EIC_INTFLAG_EXTINT6_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT6_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT6; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT7_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT7) >> EIC_INTFLAG_EXTINT7_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT7_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT7; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT8_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT8) >> EIC_INTFLAG_EXTINT8_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT8_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT8; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT9_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT9) >> EIC_INTFLAG_EXTINT9_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT9_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT9; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT10_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT10) >> EIC_INTFLAG_EXTINT10_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT10_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT10; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT11_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT11) >> EIC_INTFLAG_EXTINT11_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT11_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT11; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT12_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT12) >> EIC_INTFLAG_EXTINT12_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT12_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT12; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT13_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT13) >> EIC_INTFLAG_EXTINT13_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT13_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT13; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT14_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT14) >> EIC_INTFLAG_EXTINT14_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT14_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT14; -} - -static inline bool hri_eic_get_INTFLAG_EXTINT15_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT15) >> EIC_INTFLAG_EXTINT15_Pos; -} - -static inline void hri_eic_clear_INTFLAG_EXTINT15_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT15; -} - -static inline bool hri_eic_get_interrupt_EXTINT0_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT0) >> EIC_INTFLAG_EXTINT0_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT0_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT0; -} - -static inline bool hri_eic_get_interrupt_EXTINT1_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT1) >> EIC_INTFLAG_EXTINT1_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT1_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT1; -} - -static inline bool hri_eic_get_interrupt_EXTINT2_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT2) >> EIC_INTFLAG_EXTINT2_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT2_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT2; -} - -static inline bool hri_eic_get_interrupt_EXTINT3_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT3) >> EIC_INTFLAG_EXTINT3_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT3_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT3; -} - -static inline bool hri_eic_get_interrupt_EXTINT4_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT4) >> EIC_INTFLAG_EXTINT4_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT4_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT4; -} - -static inline bool hri_eic_get_interrupt_EXTINT5_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT5) >> EIC_INTFLAG_EXTINT5_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT5_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT5; -} - -static inline bool hri_eic_get_interrupt_EXTINT6_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT6) >> EIC_INTFLAG_EXTINT6_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT6_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT6; -} - -static inline bool hri_eic_get_interrupt_EXTINT7_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT7) >> EIC_INTFLAG_EXTINT7_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT7_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT7; -} - -static inline bool hri_eic_get_interrupt_EXTINT8_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT8) >> EIC_INTFLAG_EXTINT8_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT8_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT8; -} - -static inline bool hri_eic_get_interrupt_EXTINT9_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT9) >> EIC_INTFLAG_EXTINT9_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT9_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT9; -} - -static inline bool hri_eic_get_interrupt_EXTINT10_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT10) >> EIC_INTFLAG_EXTINT10_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT10_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT10; -} - -static inline bool hri_eic_get_interrupt_EXTINT11_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT11) >> EIC_INTFLAG_EXTINT11_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT11_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT11; -} - -static inline bool hri_eic_get_interrupt_EXTINT12_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT12) >> EIC_INTFLAG_EXTINT12_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT12_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT12; -} - -static inline bool hri_eic_get_interrupt_EXTINT13_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT13) >> EIC_INTFLAG_EXTINT13_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT13_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT13; -} - -static inline bool hri_eic_get_interrupt_EXTINT14_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT14) >> EIC_INTFLAG_EXTINT14_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT14_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT14; -} - -static inline bool hri_eic_get_interrupt_EXTINT15_bit(const void *const hw) -{ - return (((Eic *)hw)->INTFLAG.reg & EIC_INTFLAG_EXTINT15) >> EIC_INTFLAG_EXTINT15_Pos; -} - -static inline void hri_eic_clear_interrupt_EXTINT15_bit(const void *const hw) -{ - ((Eic *)hw)->INTFLAG.reg = EIC_INTFLAG_EXTINT15; -} - -static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) -{ - return ((Eic *)hw)->INTFLAG.reg; -} - -static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) -{ - ((Eic *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_eic_set_CTRL_SWRST_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw); - ((Eic *)hw)->CTRL.reg |= EIC_CTRL_SWRST; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRL_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw); - tmp = ((Eic *)hw)->CTRL.reg; - tmp = (tmp & EIC_CTRL_SWRST) >> EIC_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_eic_set_CTRL_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw); - ((Eic *)hw)->CTRL.reg |= EIC_CTRL_ENABLE; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRL_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw); - tmp = ((Eic *)hw)->CTRL.reg; - tmp = (tmp & EIC_CTRL_ENABLE) >> EIC_CTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw); - tmp = ((Eic *)hw)->CTRL.reg; - tmp &= ~EIC_CTRL_ENABLE; - tmp |= value << EIC_CTRL_ENABLE_Pos; - ((Eic *)hw)->CTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRL_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw); - ((Eic *)hw)->CTRL.reg &= ~EIC_CTRL_ENABLE; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRL_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw); - ((Eic *)hw)->CTRL.reg ^= EIC_CTRL_ENABLE; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRL.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_ctrl_reg_t hri_eic_get_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRL.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRL.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRL_reg(const void *const hw, hri_eic_ctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRL.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_ctrl_reg_t hri_eic_read_CTRL_reg(const void *const hw) -{ - return ((Eic *)hw)->CTRL.reg; -} - -static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMIFILTEN; - tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; - return tmp; -} - -static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMISENSE_Msk; - tmp |= EIC_NMICTRL_NMISENSE(data); - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; - return tmp; -} - -static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) -{ - return ((Eic *)hw)->NMICTRL.reg; -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO0) >> EIC_EVCTRL_EXTINTEO0_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO0; - tmp |= value << EIC_EVCTRL_EXTINTEO0_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO1) >> EIC_EVCTRL_EXTINTEO1_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO1; - tmp |= value << EIC_EVCTRL_EXTINTEO1_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO2_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO2) >> EIC_EVCTRL_EXTINTEO2_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO2; - tmp |= value << EIC_EVCTRL_EXTINTEO2_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO2_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO2_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO3_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO3) >> EIC_EVCTRL_EXTINTEO3_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO3; - tmp |= value << EIC_EVCTRL_EXTINTEO3_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO3_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO3_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO4_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO4) >> EIC_EVCTRL_EXTINTEO4_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO4; - tmp |= value << EIC_EVCTRL_EXTINTEO4_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO4_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO4_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO5_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO5) >> EIC_EVCTRL_EXTINTEO5_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO5; - tmp |= value << EIC_EVCTRL_EXTINTEO5_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO5_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO5_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO6_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO6) >> EIC_EVCTRL_EXTINTEO6_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO6; - tmp |= value << EIC_EVCTRL_EXTINTEO6_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO6_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO6_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO7_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO7) >> EIC_EVCTRL_EXTINTEO7_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO7; - tmp |= value << EIC_EVCTRL_EXTINTEO7_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO7_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO7_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO8_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO8; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO8) >> EIC_EVCTRL_EXTINTEO8_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO8; - tmp |= value << EIC_EVCTRL_EXTINTEO8_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO8_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO8; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO8_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO8; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO9_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO9; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO9) >> EIC_EVCTRL_EXTINTEO9_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO9; - tmp |= value << EIC_EVCTRL_EXTINTEO9_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO9_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO9; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO9_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO9; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO10_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO10; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO10) >> EIC_EVCTRL_EXTINTEO10_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO10; - tmp |= value << EIC_EVCTRL_EXTINTEO10_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO10_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO10; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO10_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO10; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO11_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO11; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO11) >> EIC_EVCTRL_EXTINTEO11_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO11; - tmp |= value << EIC_EVCTRL_EXTINTEO11_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO11_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO11; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO11_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO11; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO12_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO12; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO12) >> EIC_EVCTRL_EXTINTEO12_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO12; - tmp |= value << EIC_EVCTRL_EXTINTEO12_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO12_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO12; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO12_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO12; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO13_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO13; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO13) >> EIC_EVCTRL_EXTINTEO13_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO13; - tmp |= value << EIC_EVCTRL_EXTINTEO13_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO13_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO13; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO13_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO13; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO14_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO14; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO14) >> EIC_EVCTRL_EXTINTEO14_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO14; - tmp |= value << EIC_EVCTRL_EXTINTEO14_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO14_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO14; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO14_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO14; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO15_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO15; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_EVCTRL_EXTINTEO15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO15) >> EIC_EVCTRL_EXTINTEO15_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO15; - tmp |= value << EIC_EVCTRL_EXTINTEO15_Pos; - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO15_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO15; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO15_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO15; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) -{ - return ((Eic *)hw)->EVCTRL.reg; -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN0) >> EIC_WAKEUP_WAKEUPEN0_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN0; - tmp |= value << EIC_WAKEUP_WAKEUPEN0_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN1) >> EIC_WAKEUP_WAKEUPEN1_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN1; - tmp |= value << EIC_WAKEUP_WAKEUPEN1_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN2_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN2) >> EIC_WAKEUP_WAKEUPEN2_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN2; - tmp |= value << EIC_WAKEUP_WAKEUPEN2_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN2_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN2_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN3_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN3) >> EIC_WAKEUP_WAKEUPEN3_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN3; - tmp |= value << EIC_WAKEUP_WAKEUPEN3_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN3_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN3_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN4_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN4) >> EIC_WAKEUP_WAKEUPEN4_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN4; - tmp |= value << EIC_WAKEUP_WAKEUPEN4_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN4_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN4_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN5_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN5) >> EIC_WAKEUP_WAKEUPEN5_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN5; - tmp |= value << EIC_WAKEUP_WAKEUPEN5_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN5_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN5_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN6_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN6) >> EIC_WAKEUP_WAKEUPEN6_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN6; - tmp |= value << EIC_WAKEUP_WAKEUPEN6_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN6_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN6_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN7_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN7) >> EIC_WAKEUP_WAKEUPEN7_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN7; - tmp |= value << EIC_WAKEUP_WAKEUPEN7_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN7_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN7_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN8_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN8; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN8) >> EIC_WAKEUP_WAKEUPEN8_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN8; - tmp |= value << EIC_WAKEUP_WAKEUPEN8_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN8_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN8; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN8_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN8; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN9_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN9; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN9) >> EIC_WAKEUP_WAKEUPEN9_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN9; - tmp |= value << EIC_WAKEUP_WAKEUPEN9_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN9_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN9; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN9_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN9; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN10_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN10; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN10) >> EIC_WAKEUP_WAKEUPEN10_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN10; - tmp |= value << EIC_WAKEUP_WAKEUPEN10_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN10_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN10; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN10_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN10; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN11_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN11; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN11) >> EIC_WAKEUP_WAKEUPEN11_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN11; - tmp |= value << EIC_WAKEUP_WAKEUPEN11_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN11_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN11; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN11_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN11; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN12_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN12; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN12) >> EIC_WAKEUP_WAKEUPEN12_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN12; - tmp |= value << EIC_WAKEUP_WAKEUPEN12_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN12_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN12; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN12_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN12; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN13_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN13; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN13) >> EIC_WAKEUP_WAKEUPEN13_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN13; - tmp |= value << EIC_WAKEUP_WAKEUPEN13_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN13_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN13; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN13_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN13; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN14_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN14; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN14) >> EIC_WAKEUP_WAKEUPEN14_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN14; - tmp |= value << EIC_WAKEUP_WAKEUPEN14_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN14_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN14; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN14_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN14; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_WAKEUPEN15_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= EIC_WAKEUP_WAKEUPEN15; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_WAKEUP_WAKEUPEN15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp = (tmp & EIC_WAKEUP_WAKEUPEN15) >> EIC_WAKEUP_WAKEUPEN15_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_WAKEUP_WAKEUPEN15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= ~EIC_WAKEUP_WAKEUPEN15; - tmp |= value << EIC_WAKEUP_WAKEUPEN15_Pos; - ((Eic *)hw)->WAKEUP.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_WAKEUPEN15_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~EIC_WAKEUP_WAKEUPEN15; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_WAKEUPEN15_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= EIC_WAKEUP_WAKEUPEN15; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_wakeup_reg_t hri_eic_get_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->WAKEUP.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_WAKEUP_reg(const void *const hw, hri_eic_wakeup_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->WAKEUP.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_wakeup_reg_t hri_eic_read_WAKEUP_reg(const void *const hw) -{ - return ((Eic *)hw)->WAKEUP.reg; -} - -static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN0; - tmp |= value << EIC_CONFIG_FILTEN0_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN1; - tmp |= value << EIC_CONFIG_FILTEN1_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN2; - tmp |= value << EIC_CONFIG_FILTEN2_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN3; - tmp |= value << EIC_CONFIG_FILTEN3_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN4; - tmp |= value << EIC_CONFIG_FILTEN4_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN5; - tmp |= value << EIC_CONFIG_FILTEN5_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN6; - tmp |= value << EIC_CONFIG_FILTEN6_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN7; - tmp |= value << EIC_CONFIG_FILTEN7_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE0_Msk; - tmp |= EIC_CONFIG_SENSE0(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE1_Msk; - tmp |= EIC_CONFIG_SENSE1(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE2_Msk; - tmp |= EIC_CONFIG_SENSE2(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE3_Msk; - tmp |= EIC_CONFIG_SENSE3(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE4_Msk; - tmp |= EIC_CONFIG_SENSE4(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE5_Msk; - tmp |= EIC_CONFIG_SENSE5(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE6_Msk; - tmp |= EIC_CONFIG_SENSE6(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE7_Msk; - tmp |= EIC_CONFIG_SENSE7(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) -{ - return ((Eic *)hw)->CONFIG[index].reg; -} - -static inline bool hri_eic_get_STATUS_SYNCBUSY_bit(const void *const hw) -{ - return (((Eic *)hw)->STATUS.reg & EIC_STATUS_SYNCBUSY) >> EIC_STATUS_SYNCBUSY_Pos; -} - -static inline hri_eic_status_reg_t hri_eic_get_STATUS_reg(const void *const hw, hri_eic_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_status_reg_t hri_eic_read_STATUS_reg(const void *const hw) -{ - return ((Eic *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_EIC_D21_H_INCLUDED */ -#endif /* _SAMD21_EIC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_evsys_d21.h b/atmel-samd/asf4/samd21/hri/hri_evsys_d21.h deleted file mode 100644 index a624728b7..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_evsys_d21.h +++ /dev/null @@ -1,1729 +0,0 @@ -/** - * \file - * - * \brief SAM EVSYS - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_EVSYS_COMPONENT_ -#ifndef _HRI_EVSYS_D21_H_INCLUDED_ -#define _HRI_EVSYS_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) -#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define EVSYS_CRITICAL_SECTION_ENTER() -#define EVSYS_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_evsys_user_reg_t; -typedef uint32_t hri_evsys_channel_reg_t; -typedef uint32_t hri_evsys_chstatus_reg_t; -typedef uint32_t hri_evsys_intenset_reg_t; -typedef uint32_t hri_evsys_intflag_reg_t; -typedef uint8_t hri_evsys_ctrl_reg_t; - -static inline void hri_evsys_set_INTEN_OVR0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; -} - -static inline bool hri_evsys_get_INTEN_OVR0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; - } -} - -static inline void hri_evsys_clear_INTEN_OVR0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; -} - -static inline void hri_evsys_set_INTEN_OVR1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; -} - -static inline bool hri_evsys_get_INTEN_OVR1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; - } -} - -static inline void hri_evsys_clear_INTEN_OVR1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; -} - -static inline void hri_evsys_set_INTEN_OVR2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; -} - -static inline bool hri_evsys_get_INTEN_OVR2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR2) >> EVSYS_INTENSET_OVR2_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR2; - } -} - -static inline void hri_evsys_clear_INTEN_OVR2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR2; -} - -static inline void hri_evsys_set_INTEN_OVR3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; -} - -static inline bool hri_evsys_get_INTEN_OVR3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR3) >> EVSYS_INTENSET_OVR3_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR3; - } -} - -static inline void hri_evsys_clear_INTEN_OVR3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR3; -} - -static inline void hri_evsys_set_INTEN_OVR4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; -} - -static inline bool hri_evsys_get_INTEN_OVR4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR4) >> EVSYS_INTENSET_OVR4_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR4; - } -} - -static inline void hri_evsys_clear_INTEN_OVR4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR4; -} - -static inline void hri_evsys_set_INTEN_OVR5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; -} - -static inline bool hri_evsys_get_INTEN_OVR5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR5) >> EVSYS_INTENSET_OVR5_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR5; - } -} - -static inline void hri_evsys_clear_INTEN_OVR5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR5; -} - -static inline void hri_evsys_set_INTEN_OVR6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; -} - -static inline bool hri_evsys_get_INTEN_OVR6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR6) >> EVSYS_INTENSET_OVR6_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR6; - } -} - -static inline void hri_evsys_clear_INTEN_OVR6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR6; -} - -static inline void hri_evsys_set_INTEN_OVR7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; -} - -static inline bool hri_evsys_get_INTEN_OVR7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR7) >> EVSYS_INTENSET_OVR7_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR7; - } -} - -static inline void hri_evsys_clear_INTEN_OVR7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR7; -} - -static inline void hri_evsys_set_INTEN_EVD0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; -} - -static inline bool hri_evsys_get_INTEN_EVD0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD0) >> EVSYS_INTENSET_EVD0_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD0; - } -} - -static inline void hri_evsys_clear_INTEN_EVD0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD0; -} - -static inline void hri_evsys_set_INTEN_EVD1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; -} - -static inline bool hri_evsys_get_INTEN_EVD1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD1) >> EVSYS_INTENSET_EVD1_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD1; - } -} - -static inline void hri_evsys_clear_INTEN_EVD1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD1; -} - -static inline void hri_evsys_set_INTEN_EVD2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; -} - -static inline bool hri_evsys_get_INTEN_EVD2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD2) >> EVSYS_INTENSET_EVD2_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD2; - } -} - -static inline void hri_evsys_clear_INTEN_EVD2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD2; -} - -static inline void hri_evsys_set_INTEN_EVD3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; -} - -static inline bool hri_evsys_get_INTEN_EVD3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD3) >> EVSYS_INTENSET_EVD3_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD3; - } -} - -static inline void hri_evsys_clear_INTEN_EVD3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD3; -} - -static inline void hri_evsys_set_INTEN_EVD4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; -} - -static inline bool hri_evsys_get_INTEN_EVD4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD4) >> EVSYS_INTENSET_EVD4_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD4; - } -} - -static inline void hri_evsys_clear_INTEN_EVD4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD4; -} - -static inline void hri_evsys_set_INTEN_EVD5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; -} - -static inline bool hri_evsys_get_INTEN_EVD5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD5) >> EVSYS_INTENSET_EVD5_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD5; - } -} - -static inline void hri_evsys_clear_INTEN_EVD5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD5; -} - -static inline void hri_evsys_set_INTEN_EVD6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; -} - -static inline bool hri_evsys_get_INTEN_EVD6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD6) >> EVSYS_INTENSET_EVD6_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD6; - } -} - -static inline void hri_evsys_clear_INTEN_EVD6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD6; -} - -static inline void hri_evsys_set_INTEN_EVD7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; -} - -static inline bool hri_evsys_get_INTEN_EVD7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD7) >> EVSYS_INTENSET_EVD7_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD7; - } -} - -static inline void hri_evsys_clear_INTEN_EVD7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD7; -} - -static inline void hri_evsys_set_INTEN_OVR8_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; -} - -static inline bool hri_evsys_get_INTEN_OVR8_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR8) >> EVSYS_INTENSET_OVR8_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR8_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR8; - } -} - -static inline void hri_evsys_clear_INTEN_OVR8_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR8; -} - -static inline void hri_evsys_set_INTEN_OVR9_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; -} - -static inline bool hri_evsys_get_INTEN_OVR9_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR9) >> EVSYS_INTENSET_OVR9_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR9_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR9; - } -} - -static inline void hri_evsys_clear_INTEN_OVR9_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR9; -} - -static inline void hri_evsys_set_INTEN_OVR10_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; -} - -static inline bool hri_evsys_get_INTEN_OVR10_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR10) >> EVSYS_INTENSET_OVR10_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR10_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR10; - } -} - -static inline void hri_evsys_clear_INTEN_OVR10_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR10; -} - -static inline void hri_evsys_set_INTEN_OVR11_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; -} - -static inline bool hri_evsys_get_INTEN_OVR11_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR11) >> EVSYS_INTENSET_OVR11_Pos; -} - -static inline void hri_evsys_write_INTEN_OVR11_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR11; - } -} - -static inline void hri_evsys_clear_INTEN_OVR11_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR11; -} - -static inline void hri_evsys_set_INTEN_EVD8_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; -} - -static inline bool hri_evsys_get_INTEN_EVD8_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD8) >> EVSYS_INTENSET_EVD8_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD8_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD8; - } -} - -static inline void hri_evsys_clear_INTEN_EVD8_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD8; -} - -static inline void hri_evsys_set_INTEN_EVD9_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; -} - -static inline bool hri_evsys_get_INTEN_EVD9_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD9) >> EVSYS_INTENSET_EVD9_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD9_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD9; - } -} - -static inline void hri_evsys_clear_INTEN_EVD9_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD9; -} - -static inline void hri_evsys_set_INTEN_EVD10_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; -} - -static inline bool hri_evsys_get_INTEN_EVD10_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD10) >> EVSYS_INTENSET_EVD10_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD10_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD10; - } -} - -static inline void hri_evsys_clear_INTEN_EVD10_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD10; -} - -static inline void hri_evsys_set_INTEN_EVD11_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; -} - -static inline bool hri_evsys_get_INTEN_EVD11_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_EVD11) >> EVSYS_INTENSET_EVD11_Pos; -} - -static inline void hri_evsys_write_INTEN_EVD11_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; - } else { - ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_EVD11; - } -} - -static inline void hri_evsys_clear_INTEN_EVD11_bit(const void *const hw) -{ - ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_EVD11; -} - -static inline void hri_evsys_set_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) -{ - ((Evsys *)hw)->INTENSET.reg = mask; -} - -static inline hri_evsys_intenset_reg_t hri_evsys_get_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_intenset_reg_t hri_evsys_read_INTEN_reg(const void *const hw) -{ - return ((Evsys *)hw)->INTENSET.reg; -} - -static inline void hri_evsys_write_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t data) -{ - ((Evsys *)hw)->INTENSET.reg = data; - ((Evsys *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_evsys_clear_INTEN_reg(const void *const hw, hri_evsys_intenset_reg_t mask) -{ - ((Evsys *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_evsys_get_INTFLAG_OVR0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; -} - -static inline bool hri_evsys_get_INTFLAG_OVR1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; -} - -static inline bool hri_evsys_get_INTFLAG_OVR2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; -} - -static inline bool hri_evsys_get_INTFLAG_OVR3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; -} - -static inline bool hri_evsys_get_INTFLAG_OVR4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; -} - -static inline bool hri_evsys_get_INTFLAG_OVR5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; -} - -static inline bool hri_evsys_get_INTFLAG_OVR6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; -} - -static inline bool hri_evsys_get_INTFLAG_OVR7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; -} - -static inline bool hri_evsys_get_INTFLAG_EVD0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; -} - -static inline bool hri_evsys_get_INTFLAG_EVD1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; -} - -static inline bool hri_evsys_get_INTFLAG_EVD2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; -} - -static inline bool hri_evsys_get_INTFLAG_EVD3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; -} - -static inline bool hri_evsys_get_INTFLAG_EVD4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; -} - -static inline bool hri_evsys_get_INTFLAG_EVD5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; -} - -static inline bool hri_evsys_get_INTFLAG_EVD6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; -} - -static inline bool hri_evsys_get_INTFLAG_EVD7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; -} - -static inline bool hri_evsys_get_INTFLAG_OVR8_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR8_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; -} - -static inline bool hri_evsys_get_INTFLAG_OVR9_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR9_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; -} - -static inline bool hri_evsys_get_INTFLAG_OVR10_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR10_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; -} - -static inline bool hri_evsys_get_INTFLAG_OVR11_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_OVR11_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; -} - -static inline bool hri_evsys_get_INTFLAG_EVD8_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD8_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; -} - -static inline bool hri_evsys_get_INTFLAG_EVD9_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD9_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; -} - -static inline bool hri_evsys_get_INTFLAG_EVD10_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD10_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; -} - -static inline bool hri_evsys_get_INTFLAG_EVD11_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; -} - -static inline void hri_evsys_clear_INTFLAG_EVD11_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; -} - -static inline bool hri_evsys_get_interrupt_OVR0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR0) >> EVSYS_INTFLAG_OVR0_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR0; -} - -static inline bool hri_evsys_get_interrupt_OVR1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR1) >> EVSYS_INTFLAG_OVR1_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR1; -} - -static inline bool hri_evsys_get_interrupt_OVR2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR2) >> EVSYS_INTFLAG_OVR2_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR2; -} - -static inline bool hri_evsys_get_interrupt_OVR3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR3) >> EVSYS_INTFLAG_OVR3_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR3; -} - -static inline bool hri_evsys_get_interrupt_OVR4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR4) >> EVSYS_INTFLAG_OVR4_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR4; -} - -static inline bool hri_evsys_get_interrupt_OVR5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR5) >> EVSYS_INTFLAG_OVR5_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR5; -} - -static inline bool hri_evsys_get_interrupt_OVR6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR6) >> EVSYS_INTFLAG_OVR6_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR6; -} - -static inline bool hri_evsys_get_interrupt_OVR7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR7) >> EVSYS_INTFLAG_OVR7_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR7; -} - -static inline bool hri_evsys_get_interrupt_EVD0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD0) >> EVSYS_INTFLAG_EVD0_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD0_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD0; -} - -static inline bool hri_evsys_get_interrupt_EVD1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD1) >> EVSYS_INTFLAG_EVD1_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD1_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD1; -} - -static inline bool hri_evsys_get_interrupt_EVD2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD2) >> EVSYS_INTFLAG_EVD2_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD2_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD2; -} - -static inline bool hri_evsys_get_interrupt_EVD3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD3) >> EVSYS_INTFLAG_EVD3_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD3_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD3; -} - -static inline bool hri_evsys_get_interrupt_EVD4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD4) >> EVSYS_INTFLAG_EVD4_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD4_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD4; -} - -static inline bool hri_evsys_get_interrupt_EVD5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD5) >> EVSYS_INTFLAG_EVD5_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD5_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD5; -} - -static inline bool hri_evsys_get_interrupt_EVD6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD6) >> EVSYS_INTFLAG_EVD6_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD6_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD6; -} - -static inline bool hri_evsys_get_interrupt_EVD7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD7) >> EVSYS_INTFLAG_EVD7_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD7_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD7; -} - -static inline bool hri_evsys_get_interrupt_OVR8_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR8) >> EVSYS_INTFLAG_OVR8_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR8_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR8; -} - -static inline bool hri_evsys_get_interrupt_OVR9_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR9) >> EVSYS_INTFLAG_OVR9_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR9_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR9; -} - -static inline bool hri_evsys_get_interrupt_OVR10_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR10) >> EVSYS_INTFLAG_OVR10_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR10_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR10; -} - -static inline bool hri_evsys_get_interrupt_OVR11_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_OVR11) >> EVSYS_INTFLAG_OVR11_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR11_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_OVR11; -} - -static inline bool hri_evsys_get_interrupt_EVD8_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD8) >> EVSYS_INTFLAG_EVD8_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD8_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD8; -} - -static inline bool hri_evsys_get_interrupt_EVD9_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD9) >> EVSYS_INTFLAG_EVD9_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD9_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD9; -} - -static inline bool hri_evsys_get_interrupt_EVD10_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD10) >> EVSYS_INTFLAG_EVD10_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD10_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD10; -} - -static inline bool hri_evsys_get_interrupt_EVD11_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTFLAG.reg & EVSYS_INTFLAG_EVD11) >> EVSYS_INTFLAG_EVD11_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD11_bit(const void *const hw) -{ - ((Evsys *)hw)->INTFLAG.reg = EVSYS_INTFLAG_EVD11; -} - -static inline hri_evsys_intflag_reg_t hri_evsys_get_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_intflag_reg_t hri_evsys_read_INTFLAG_reg(const void *const hw) -{ - return ((Evsys *)hw)->INTFLAG.reg; -} - -static inline void hri_evsys_clear_INTFLAG_reg(const void *const hw, hri_evsys_intflag_reg_t mask) -{ - ((Evsys *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_evsys_write_CTRL_reg(const void *const hw, hri_evsys_ctrl_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRL.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_CHANNEL_SWEVT_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_SWEVT; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CHANNEL_SWEVT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_SWEVT) >> EVSYS_CHANNEL_SWEVT_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_CHANNEL_SWEVT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_SWEVT; - tmp |= value << EVSYS_CHANNEL_SWEVT_Pos; - ((Evsys *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_SWEVT_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_SWEVT; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_SWEVT_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_SWEVT; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_CHANNEL_bf(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_CHANNEL(mask)) >> EVSYS_CHANNEL_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_CHANNEL_Msk; - tmp |= EVSYS_CHANNEL_CHANNEL(data); - ((Evsys *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_CHANNEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_CHANNEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_CHANNEL_Msk) >> EVSYS_CHANNEL_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; - tmp |= EVSYS_CHANNEL_EVGEN(data); - ((Evsys *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_PATH_Msk; - tmp |= EVSYS_CHANNEL_PATH(data); - ((Evsys *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; - tmp |= EVSYS_CHANNEL_EDGSEL(data); - ((Evsys *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHANNEL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CHANNEL.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw) -{ - return ((Evsys *)hw)->CHANNEL.reg; -} - -static inline void hri_evsys_set_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER.reg |= EVSYS_USER_USER(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_get_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->USER.reg; - tmp = (tmp & EVSYS_USER_USER(mask)) >> EVSYS_USER_USER_Pos; - return tmp; -} - -static inline void hri_evsys_write_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t data) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->USER.reg; - tmp &= ~EVSYS_USER_USER_Msk; - tmp |= EVSYS_USER_USER(data); - ((Evsys *)hw)->USER.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER.reg &= ~EVSYS_USER_USER(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_USER_USER_bf(const void *const hw, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER.reg ^= EVSYS_USER_USER(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_read_USER_USER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->USER.reg; - tmp = (tmp & EVSYS_USER_USER_Msk) >> EVSYS_USER_USER_Pos; - return tmp; -} - -static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER.reg |= EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->USER.reg; - tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t data) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->USER.reg; - tmp &= ~EVSYS_USER_CHANNEL_Msk; - tmp |= EVSYS_USER_CHANNEL(data); - ((Evsys *)hw)->USER.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER.reg &= ~EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER.reg ^= EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->USER.reg; - tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_set_USER_reg(const void *const hw, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, hri_evsys_user_reg_t mask) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->USER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_USER_reg(const void *const hw, hri_evsys_user_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_USER_reg(const void *const hw, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_USER_reg(const void *const hw, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw) -{ - return ((Evsys *)hw)->USER.reg; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY0_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY0) >> EVSYS_CHSTATUS_USRRDY0_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY1_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY1) >> EVSYS_CHSTATUS_USRRDY1_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY2_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY2) >> EVSYS_CHSTATUS_USRRDY2_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY3_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY3) >> EVSYS_CHSTATUS_USRRDY3_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY4_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY4) >> EVSYS_CHSTATUS_USRRDY4_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY5_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY5) >> EVSYS_CHSTATUS_USRRDY5_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY6_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY6) >> EVSYS_CHSTATUS_USRRDY6_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY7_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY7) >> EVSYS_CHSTATUS_USRRDY7_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY0_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY0) >> EVSYS_CHSTATUS_CHBUSY0_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY1_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY1) >> EVSYS_CHSTATUS_CHBUSY1_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY2_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY2) >> EVSYS_CHSTATUS_CHBUSY2_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY3_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY3) >> EVSYS_CHSTATUS_CHBUSY3_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY4_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY4) >> EVSYS_CHSTATUS_CHBUSY4_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY5_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY5) >> EVSYS_CHSTATUS_CHBUSY5_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY6_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY6) >> EVSYS_CHSTATUS_CHBUSY6_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY7_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY7) >> EVSYS_CHSTATUS_CHBUSY7_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY8_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY8) >> EVSYS_CHSTATUS_USRRDY8_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY9_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY9) >> EVSYS_CHSTATUS_USRRDY9_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY10_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY10) >> EVSYS_CHSTATUS_USRRDY10_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_USRRDY11_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_USRRDY11) >> EVSYS_CHSTATUS_USRRDY11_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY8_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY8) >> EVSYS_CHSTATUS_CHBUSY8_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY9_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY9) >> EVSYS_CHSTATUS_CHBUSY9_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY10_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY10) >> EVSYS_CHSTATUS_CHBUSY10_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_CHBUSY11_bit(const void *const hw) -{ - return (((Evsys *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_CHBUSY11) >> EVSYS_CHSTATUS_CHBUSY11_Pos; -} - -static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, hri_evsys_chstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw) -{ - return ((Evsys *)hw)->CHSTATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_EVSYS_D21_H_INCLUDED */ -#endif /* _SAMD21_EVSYS_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_gclk_d21.h b/atmel-samd/asf4/samd21/hri/hri_gclk_d21.h deleted file mode 100644 index 39aa44eab..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_gclk_d21.h +++ /dev/null @@ -1,933 +0,0 @@ -/** - * \file - * - * \brief SAM GCLK - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_GCLK_COMPONENT_ -#ifndef _HRI_GCLK_D21_H_INCLUDED_ -#define _HRI_GCLK_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) -#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define GCLK_CRITICAL_SECTION_ENTER() -#define GCLK_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_gclk_clkctrl_reg_t; -typedef uint32_t hri_gclk_genctrl_reg_t; -typedef uint32_t hri_gclk_gendiv_reg_t; -typedef uint8_t hri_gclk_ctrl_reg_t; -typedef uint8_t hri_gclk_status_reg_t; - -static inline void hri_gclk_wait_for_sync(const void *const hw) -{ - while (((const Gclk *)hw)->STATUS.bit.SYNCBUSY) - ; -} - -static inline bool hri_gclk_is_syncing(const void *const hw) -{ - return ((const Gclk *)hw)->STATUS.bit.SYNCBUSY; -} - -static inline void hri_gclk_set_CTRL_SWRST_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->CTRL.reg |= GCLK_CTRL_SWRST; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_CTRL_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->CTRL.reg; - tmp = (tmp & GCLK_CTRL_SWRST) >> GCLK_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_set_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRL.reg |= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_ctrl_reg_t hri_gclk_get_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Gclk *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRL.reg = data; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRL.reg &= ~mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_CTRL_reg(const void *const hw, hri_gclk_ctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRL.reg ^= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_ctrl_reg_t hri_gclk_read_CTRL_reg(const void *const hw) -{ - return ((Gclk *)hw)->CTRL.reg; -} - -static inline void hri_gclk_set_CLKCTRL_CLKEN_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_CLKEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_CLKCTRL_CLKEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Gclk *)hw)->CLKCTRL.reg; - tmp = (tmp & GCLK_CLKCTRL_CLKEN) >> GCLK_CLKCTRL_CLKEN_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_CLKCTRL_CLKEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->CLKCTRL.reg; - tmp &= ~GCLK_CLKCTRL_CLKEN; - tmp |= value << GCLK_CLKCTRL_CLKEN_Pos; - ((Gclk *)hw)->CLKCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_CLKCTRL_CLKEN_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_CLKEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_CLKCTRL_CLKEN_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_CLKEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_CLKCTRL_WRTLOCK_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_CLKCTRL_WRTLOCK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Gclk *)hw)->CLKCTRL.reg; - tmp = (tmp & GCLK_CLKCTRL_WRTLOCK) >> GCLK_CLKCTRL_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_CLKCTRL_WRTLOCK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->CLKCTRL.reg; - tmp &= ~GCLK_CLKCTRL_WRTLOCK; - tmp |= value << GCLK_CLKCTRL_WRTLOCK_Pos; - ((Gclk *)hw)->CLKCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_CLKCTRL_WRTLOCK_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_CLKCTRL_WRTLOCK_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_ID(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_clkctrl_reg_t hri_gclk_get_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Gclk *)hw)->CLKCTRL.reg; - tmp = (tmp & GCLK_CLKCTRL_ID(mask)) >> GCLK_CLKCTRL_ID_Pos; - return tmp; -} - -static inline void hri_gclk_write_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t data) -{ - uint16_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->CLKCTRL.reg; - tmp &= ~GCLK_CLKCTRL_ID_Msk; - tmp |= GCLK_CLKCTRL_ID(data); - ((Gclk *)hw)->CLKCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_ID(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_CLKCTRL_ID_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_ID(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_clkctrl_reg_t hri_gclk_read_CLKCTRL_ID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Gclk *)hw)->CLKCTRL.reg; - tmp = (tmp & GCLK_CLKCTRL_ID_Msk) >> GCLK_CLKCTRL_ID_Pos; - return tmp; -} - -static inline void hri_gclk_set_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg |= GCLK_CLKCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_clkctrl_reg_t hri_gclk_get_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Gclk *)hw)->CLKCTRL.reg; - tmp = (tmp & GCLK_CLKCTRL_GEN(mask)) >> GCLK_CLKCTRL_GEN_Pos; - return tmp; -} - -static inline void hri_gclk_write_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t data) -{ - uint16_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->CLKCTRL.reg; - tmp &= ~GCLK_CLKCTRL_GEN_Msk; - tmp |= GCLK_CLKCTRL_GEN(data); - ((Gclk *)hw)->CLKCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg &= ~GCLK_CLKCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_CLKCTRL_GEN_bf(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg ^= GCLK_CLKCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_clkctrl_reg_t hri_gclk_read_CLKCTRL_GEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Gclk *)hw)->CLKCTRL.reg; - tmp = (tmp & GCLK_CLKCTRL_GEN_Msk) >> GCLK_CLKCTRL_GEN_Pos; - return tmp; -} - -static inline void hri_gclk_set_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg |= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_clkctrl_reg_t hri_gclk_get_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Gclk *)hw)->CLKCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg = data; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg &= ~mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_CLKCTRL_reg(const void *const hw, hri_gclk_clkctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CLKCTRL.reg ^= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_clkctrl_reg_t hri_gclk_read_CLKCTRL_reg(const void *const hw) -{ - return ((Gclk *)hw)->CLKCTRL.reg; -} - -static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_GENEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp &= ~GCLK_GENCTRL_GENEN; - tmp |= value << GCLK_GENCTRL_GENEN_Pos; - ((Gclk *)hw)->GENCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_GENEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_GENEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_IDC; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp &= ~GCLK_GENCTRL_IDC; - tmp |= value << GCLK_GENCTRL_IDC_Pos; - ((Gclk *)hw)->GENCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_IDC; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_IDC; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_OOV; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp &= ~GCLK_GENCTRL_OOV; - tmp |= value << GCLK_GENCTRL_OOV_Pos; - ((Gclk *)hw)->GENCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_OOV; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_OOV; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_OE; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp &= ~GCLK_GENCTRL_OE; - tmp |= value << GCLK_GENCTRL_OE_Pos; - ((Gclk *)hw)->GENCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_OE; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_OE; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_DIVSEL; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp &= ~GCLK_GENCTRL_DIVSEL; - tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; - ((Gclk *)hw)->GENCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_DIVSEL; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_DIVSEL; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_RUNSTDBY; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp &= ~GCLK_GENCTRL_RUNSTDBY; - tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; - ((Gclk *)hw)->GENCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_RUNSTDBY; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_RUNSTDBY; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_ID(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp = (tmp & GCLK_GENCTRL_ID(mask)) >> GCLK_GENCTRL_ID_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp &= ~GCLK_GENCTRL_ID_Msk; - tmp |= GCLK_GENCTRL_ID(data); - ((Gclk *)hw)->GENCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_ID(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_ID_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_ID(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_ID_bf(const void *const hw) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp = (tmp & GCLK_GENCTRL_ID_Msk) >> GCLK_GENCTRL_ID_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg |= GCLK_GENCTRL_SRC(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp &= ~GCLK_GENCTRL_SRC_Msk; - tmp |= GCLK_GENCTRL_SRC(data); - ((Gclk *)hw)->GENCTRL.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg &= ~GCLK_GENCTRL_SRC(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw); - ((Gclk *)hw)->GENCTRL.reg ^= GCLK_GENCTRL_SRC(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw) -{ - uint32_t tmp; - hri_gclk_wait_for_sync(hw); - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL.reg |= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL.reg = data; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL.reg &= ~mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL.reg ^= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw) -{ - return ((Gclk *)hw)->GENCTRL.reg; -} - -static inline void hri_gclk_set_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENDIV.reg |= GCLK_GENDIV_ID(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_gendiv_reg_t hri_gclk_get_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENDIV.reg; - tmp = (tmp & GCLK_GENDIV_ID(mask)) >> GCLK_GENDIV_ID_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENDIV.reg; - tmp &= ~GCLK_GENDIV_ID_Msk; - tmp |= GCLK_GENDIV_ID(data); - ((Gclk *)hw)->GENDIV.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENDIV.reg &= ~GCLK_GENDIV_ID(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENDIV_ID_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENDIV.reg ^= GCLK_GENDIV_ID(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_gendiv_reg_t hri_gclk_read_GENDIV_ID_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENDIV.reg; - tmp = (tmp & GCLK_GENDIV_ID_Msk) >> GCLK_GENDIV_ID_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENDIV.reg |= GCLK_GENDIV_DIV(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_gendiv_reg_t hri_gclk_get_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENDIV.reg; - tmp = (tmp & GCLK_GENDIV_DIV(mask)) >> GCLK_GENDIV_DIV_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENDIV.reg; - tmp &= ~GCLK_GENDIV_DIV_Msk; - tmp |= GCLK_GENDIV_DIV(data); - ((Gclk *)hw)->GENDIV.reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENDIV.reg &= ~GCLK_GENDIV_DIV(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENDIV_DIV_bf(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENDIV.reg ^= GCLK_GENDIV_DIV(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_gendiv_reg_t hri_gclk_read_GENDIV_DIV_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENDIV.reg; - tmp = (tmp & GCLK_GENDIV_DIV_Msk) >> GCLK_GENDIV_DIV_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENDIV.reg |= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_gendiv_reg_t hri_gclk_get_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENDIV.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENDIV.reg = data; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENDIV.reg &= ~mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENDIV_reg(const void *const hw, hri_gclk_gendiv_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENDIV.reg ^= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_gendiv_reg_t hri_gclk_read_GENDIV_reg(const void *const hw) -{ - return ((Gclk *)hw)->GENDIV.reg; -} - -static inline bool hri_gclk_get_STATUS_SYNCBUSY_bit(const void *const hw) -{ - return (((Gclk *)hw)->STATUS.reg & GCLK_STATUS_SYNCBUSY) >> GCLK_STATUS_SYNCBUSY_Pos; -} - -static inline hri_gclk_status_reg_t hri_gclk_get_STATUS_reg(const void *const hw, hri_gclk_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Gclk *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gclk_status_reg_t hri_gclk_read_STATUS_reg(const void *const hw) -{ - return ((Gclk *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_GCLK_D21_H_INCLUDED */ -#endif /* _SAMD21_GCLK_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_hmatrixb_d21.h b/atmel-samd/asf4/samd21/hri/hri_hmatrixb_d21.h deleted file mode 100644 index d9c598687..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_hmatrixb_d21.h +++ /dev/null @@ -1,289 +0,0 @@ -/** - * \file - * - * \brief SAM HMATRIXB - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_HMATRIXB_COMPONENT_ -#ifndef _HRI_HMATRIXB_D21_H_INCLUDED_ -#define _HRI_HMATRIXB_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) -#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define HMATRIXB_CRITICAL_SECTION_ENTER() -#define HMATRIXB_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_hmatrixb_pras_reg_t; -typedef uint32_t hri_hmatrixb_prbs_reg_t; -typedef uint32_t hri_hmatrixb_sfr_reg_t; -typedef uint32_t hri_hmatrixbprs_pras_reg_t; -typedef uint32_t hri_hmatrixbprs_prbs_reg_t; - -static inline void hri_hmatrixb_set_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->SFR[index].reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_sfr_reg_t hri_hmatrixb_get_SFR_reg(const void *const hw, uint8_t index, - hri_hmatrixb_sfr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Hmatrixb *)hw)->SFR[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixb_write_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->SFR[index].reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_clear_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->SFR[index].reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_toggle_SFR_reg(const void *const hw, uint8_t index, hri_hmatrixb_sfr_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->SFR[index].reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_sfr_reg_t hri_hmatrixb_read_SFR_reg(const void *const hw, uint8_t index) -{ - return ((Hmatrixb *)hw)->SFR[index].reg; -} - -static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - uint32_t tmp; - tmp = ((HmatrixbPrs *)hw)->PRAS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) -{ - return ((HmatrixbPrs *)hw)->PRAS.reg; -} - -static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - uint32_t tmp; - tmp = ((HmatrixbPrs *)hw)->PRBS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) -{ - return ((HmatrixbPrs *)hw)->PRBS.reg; -} - -static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - uint32_t tmp; - tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; -} - -static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - uint32_t tmp; - tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_HMATRIXB_D21_H_INCLUDED */ -#endif /* _SAMD21_HMATRIXB_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_i2s_d21.h b/atmel-samd/asf4/samd21/hri/hri_i2s_d21.h deleted file mode 100644 index 5ab2f76c0..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_i2s_d21.h +++ /dev/null @@ -1,2516 +0,0 @@ -/** - * \file - * - * \brief SAM I2S - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_I2S_COMPONENT_ -#ifndef _HRI_I2S_D21_H_INCLUDED_ -#define _HRI_I2S_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_I2S_CRITICAL_SECTIONS) -#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define I2S_CRITICAL_SECTION_ENTER() -#define I2S_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_i2s_intenset_reg_t; -typedef uint16_t hri_i2s_intflag_reg_t; -typedef uint16_t hri_i2s_syncbusy_reg_t; -typedef uint32_t hri_i2s_clkctrl_reg_t; -typedef uint32_t hri_i2s_data_reg_t; -typedef uint32_t hri_i2s_serctrl_reg_t; -typedef uint8_t hri_i2s_ctrla_reg_t; - -static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg) -{ - while (((I2s *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg) -{ - return ((I2s *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; -} - -static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos; -} - -static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; - } -} - -static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; -} - -static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; -} - -static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos; -} - -static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; - } -} - -static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; -} - -static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; -} - -static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos; -} - -static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; - } -} - -static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; -} - -static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; -} - -static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos; -} - -static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; - } -} - -static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; -} - -static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; -} - -static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos; -} - -static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; - } -} - -static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; -} - -static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; -} - -static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos; -} - -static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; - } -} - -static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; -} - -static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; -} - -static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos; -} - -static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; - } -} - -static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; -} - -static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; -} - -static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos; -} - -static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; - } -} - -static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; -} - -static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - ((I2s *)hw)->INTENSET.reg = mask; -} - -static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw) -{ - return ((I2s *)hw)->INTENSET.reg; -} - -static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data) -{ - ((I2s *)hw)->INTENSET.reg = data; - ((I2s *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - ((I2s *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; -} - -static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; -} - -static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; -} - -static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; -} - -static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; -} - -static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; -} - -static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; -} - -static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; -} - -static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; -} - -static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; -} - -static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; -} - -static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; -} - -static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; -} - -static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; -} - -static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; -} - -static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; -} - -static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw) -{ - return ((I2s *)hw)->INTFLAG.reg; -} - -static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) -{ - ((I2s *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_ENABLE; - tmp |= value << I2S_CTRLA_ENABLE_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_CKEN0; - tmp |= value << I2S_CTRLA_CKEN0_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_CKEN1; - tmp |= value << I2S_CTRLA_CKEN1_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_SEREN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SEREN0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_SEREN0_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_SEREN0) >> I2S_CTRLA_SEREN0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_SEREN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_SEREN0; - tmp |= value << I2S_CTRLA_SEREN0_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_SEREN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_SEREN0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_SEREN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_SEREN0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_SEREN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SEREN1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_SEREN1_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_SEREN1) >> I2S_CTRLA_SEREN1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_SEREN1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_SEREN1; - tmp |= value << I2S_CTRLA_SEREN1_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_SEREN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_SEREN1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_SEREN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_SEREN0 - | I2S_SYNCBUSY_SEREN1); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_SEREN1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw) -{ - return ((I2s *)hw)->CTRLA.reg; -} - -static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_BITDELAY; - tmp |= value << I2S_CLKCTRL_BITDELAY_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSSEL; - tmp |= value << I2S_CLKCTRL_FSSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSINV; - tmp |= value << I2S_CLKCTRL_FSINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SCKSEL; - tmp |= value << I2S_CLKCTRL_SCKSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKSEL; - tmp |= value << I2S_CLKCTRL_MCKSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKEN; - tmp |= value << I2S_CLKCTRL_MCKEN_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSOUTINV; - tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SCKOUTINV; - tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKOUTINV; - tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk; - tmp |= I2S_CLKCTRL_SLOTSIZE(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk; - tmp |= I2S_CLKCTRL_NBSLOTS(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk; - tmp |= I2S_CLKCTRL_FSWIDTH(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKDIV_Msk; - tmp |= I2S_CLKCTRL_MCKDIV(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk; - tmp |= I2S_CLKCTRL_MCKOUTDIV(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index) -{ - return ((I2s *)hw)->CLKCTRL[index].reg; -} - -static inline void hri_i2s_set_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_TXSAME) >> I2S_SERCTRL_TXSAME_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_TXSAME; - tmp |= value << I2S_SERCTRL_TXSAME_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_TXSAME_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_CLKSEL) >> I2S_SERCTRL_CLKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_CLKSEL; - tmp |= value << I2S_SERCTRL_CLKSEL_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_CLKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_SLOTADJ) >> I2S_SERCTRL_SLOTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_SLOTADJ; - tmp |= value << I2S_SERCTRL_SLOTADJ_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_SLOTADJ_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_WORDADJ) >> I2S_SERCTRL_WORDADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_WORDADJ; - tmp |= value << I2S_SERCTRL_WORDADJ_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_WORDADJ_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_BITREV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_BITREV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_BITREV) >> I2S_SERCTRL_BITREV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_BITREV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_BITREV; - tmp |= value << I2S_SERCTRL_BITREV_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_BITREV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_BITREV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_SLOTDIS0) >> I2S_SERCTRL_SLOTDIS0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_SLOTDIS0; - tmp |= value << I2S_SERCTRL_SLOTDIS0_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_SLOTDIS0_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_SLOTDIS1) >> I2S_SERCTRL_SLOTDIS1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_SLOTDIS1; - tmp |= value << I2S_SERCTRL_SLOTDIS1_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_SLOTDIS1_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_SLOTDIS2) >> I2S_SERCTRL_SLOTDIS2_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_SLOTDIS2; - tmp |= value << I2S_SERCTRL_SLOTDIS2_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_SLOTDIS2_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_SLOTDIS3) >> I2S_SERCTRL_SLOTDIS3_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_SLOTDIS3; - tmp |= value << I2S_SERCTRL_SLOTDIS3_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_SLOTDIS3_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_SLOTDIS4) >> I2S_SERCTRL_SLOTDIS4_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_SLOTDIS4; - tmp |= value << I2S_SERCTRL_SLOTDIS4_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_SLOTDIS4_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_SLOTDIS5) >> I2S_SERCTRL_SLOTDIS5_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_SLOTDIS5; - tmp |= value << I2S_SERCTRL_SLOTDIS5_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_SLOTDIS5_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_SLOTDIS6) >> I2S_SERCTRL_SLOTDIS6_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_SLOTDIS6; - tmp |= value << I2S_SERCTRL_SLOTDIS6_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_SLOTDIS6_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_SLOTDIS7) >> I2S_SERCTRL_SLOTDIS7_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_SLOTDIS7; - tmp |= value << I2S_SERCTRL_SLOTDIS7_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_SLOTDIS7_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_MONO_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_MONO_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_MONO) >> I2S_SERCTRL_MONO_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_MONO_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_MONO; - tmp |= value << I2S_SERCTRL_MONO_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_MONO_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_MONO_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_DMA_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_DMA_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_DMA) >> I2S_SERCTRL_DMA_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_DMA_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_DMA; - tmp |= value << I2S_SERCTRL_DMA_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_DMA_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_DMA_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_RXLOOP) >> I2S_SERCTRL_RXLOOP_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_RXLOOP; - tmp |= value << I2S_SERCTRL_RXLOOP_Pos; - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_RXLOOP_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, - hri_i2s_serctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_SERMODE(mask)) >> I2S_SERCTRL_SERMODE_Pos; - return tmp; -} - -static inline void hri_i2s_write_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_SERMODE_Msk; - tmp |= I2S_SERCTRL_SERMODE(data); - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_SERMODE_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_SERMODE_Msk) >> I2S_SERCTRL_SERMODE_Pos; - return tmp; -} - -static inline void hri_i2s_set_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, - hri_i2s_serctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_TXDEFAULT(mask)) >> I2S_SERCTRL_TXDEFAULT_Pos; - return tmp; -} - -static inline void hri_i2s_write_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_TXDEFAULT_Msk; - tmp |= I2S_SERCTRL_TXDEFAULT(data); - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_TXDEFAULT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_TXDEFAULT_Msk) >> I2S_SERCTRL_TXDEFAULT_Pos; - return tmp; -} - -static inline void hri_i2s_set_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, - hri_i2s_serctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_DATASIZE(mask)) >> I2S_SERCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_write_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_DATASIZE_Msk; - tmp |= I2S_SERCTRL_DATASIZE(data); - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_DATASIZE_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_DATASIZE_Msk) >> I2S_SERCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_set_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= I2S_SERCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, - hri_i2s_serctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_EXTEND(mask)) >> I2S_SERCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_write_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= ~I2S_SERCTRL_EXTEND_Msk; - tmp |= I2S_SERCTRL_EXTEND(data); - ((I2s *)hw)->SERCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~I2S_SERCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= I2S_SERCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_EXTEND_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp = (tmp & I2S_SERCTRL_EXTEND_Msk) >> I2S_SERCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_set_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_serctrl_reg_t hri_i2s_get_SERCTRL_reg(const void *const hw, uint8_t index, - hri_i2s_serctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->SERCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_SERCTRL_reg(const void *const hw, uint8_t index, hri_i2s_serctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->SERCTRL[index].reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_serctrl_reg_t hri_i2s_read_SERCTRL_reg(const void *const hw, uint8_t index) -{ - return ((I2s *)hw)->SERCTRL[index].reg; -} - -static inline void hri_i2s_set_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - ((I2s *)hw)->DATA[index].reg |= I2S_DATA_DATA(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_data_reg_t hri_i2s_get_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) -{ - uint32_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - tmp = ((I2s *)hw)->DATA[index].reg; - tmp = (tmp & I2S_DATA_DATA(mask)) >> I2S_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_i2s_write_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - tmp = ((I2s *)hw)->DATA[index].reg; - tmp &= ~I2S_DATA_DATA_Msk; - tmp |= I2S_DATA_DATA(data); - ((I2s *)hw)->DATA[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - ((I2s *)hw)->DATA[index].reg &= ~I2S_DATA_DATA(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_DATA_DATA_bf(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - ((I2s *)hw)->DATA[index].reg ^= I2S_DATA_DATA(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_data_reg_t hri_i2s_read_DATA_DATA_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - tmp = ((I2s *)hw)->DATA[index].reg; - tmp = (tmp & I2S_DATA_DATA_Msk) >> I2S_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_i2s_set_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->DATA[index].reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_data_reg_t hri_i2s_get_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->DATA[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->DATA[index].reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->DATA[index].reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_DATA_reg(const void *const hw, uint8_t index, hri_i2s_data_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->DATA[index].reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_data_reg_t hri_i2s_read_DATA_reg(const void *const hw, uint8_t index) -{ - return ((I2s *)hw)->DATA[index].reg; -} - -static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_SEREN0_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SEREN0) >> I2S_SYNCBUSY_SEREN0_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_SEREN1_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SEREN1) >> I2S_SYNCBUSY_SEREN1_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_DATA0_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_DATA0) >> I2S_SYNCBUSY_DATA0_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_DATA1_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_DATA1) >> I2S_SYNCBUSY_DATA1_Pos; -} - -static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw) -{ - return ((I2s *)hw)->SYNCBUSY.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_I2S_D21_H_INCLUDED */ -#endif /* _SAMD21_I2S_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_mtb_d21.h b/atmel-samd/asf4/samd21/hri/hri_mtb_d21.h deleted file mode 100644 index 09f5f66d6..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_mtb_d21.h +++ /dev/null @@ -1,560 +0,0 @@ -/** - * \file - * - * \brief SAM MTB - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_MTB_COMPONENT_ -#ifndef _HRI_MTB_D21_H_INCLUDED_ -#define _HRI_MTB_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_MTB_CRITICAL_SECTIONS) -#define MTB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define MTB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define MTB_CRITICAL_SECTION_ENTER() -#define MTB_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_mtb_authstatus_reg_t; -typedef uint32_t hri_mtb_base_reg_t; -typedef uint32_t hri_mtb_cid0_reg_t; -typedef uint32_t hri_mtb_cid1_reg_t; -typedef uint32_t hri_mtb_cid2_reg_t; -typedef uint32_t hri_mtb_cid3_reg_t; -typedef uint32_t hri_mtb_claimset_reg_t; -typedef uint32_t hri_mtb_devarch_reg_t; -typedef uint32_t hri_mtb_devid_reg_t; -typedef uint32_t hri_mtb_devtype_reg_t; -typedef uint32_t hri_mtb_flow_reg_t; -typedef uint32_t hri_mtb_itctrl_reg_t; -typedef uint32_t hri_mtb_lockaccess_reg_t; -typedef uint32_t hri_mtb_lockstatus_reg_t; -typedef uint32_t hri_mtb_master_reg_t; -typedef uint32_t hri_mtb_pid0_reg_t; -typedef uint32_t hri_mtb_pid1_reg_t; -typedef uint32_t hri_mtb_pid2_reg_t; -typedef uint32_t hri_mtb_pid3_reg_t; -typedef uint32_t hri_mtb_pid4_reg_t; -typedef uint32_t hri_mtb_pid5_reg_t; -typedef uint32_t hri_mtb_pid6_reg_t; -typedef uint32_t hri_mtb_pid7_reg_t; -typedef uint32_t hri_mtb_position_reg_t; - -static inline void hri_mtb_set_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) -{ - ((Mtb *)hw)->CLAIMSET.reg = mask; -} - -static inline hri_mtb_claimset_reg_t hri_mtb_get_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->CLAIMSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_claimset_reg_t hri_mtb_read_CLAIM_reg(const void *const hw) -{ - return ((Mtb *)hw)->CLAIMSET.reg; -} - -static inline void hri_mtb_write_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t data) -{ - ((Mtb *)hw)->CLAIMSET.reg = data; - ((Mtb *)hw)->CLAIMCLR.reg = ~data; -} - -static inline void hri_mtb_clear_CLAIM_reg(const void *const hw, hri_mtb_claimset_reg_t mask) -{ - ((Mtb *)hw)->CLAIMCLR.reg = mask; -} - -static inline void hri_mtb_set_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->POSITION.reg |= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_position_reg_t hri_mtb_get_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->POSITION.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mtb_write_POSITION_reg(const void *const hw, hri_mtb_position_reg_t data) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->POSITION.reg = data; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_clear_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->POSITION.reg &= ~mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_toggle_POSITION_reg(const void *const hw, hri_mtb_position_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->POSITION.reg ^= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_position_reg_t hri_mtb_read_POSITION_reg(const void *const hw) -{ - return ((Mtb *)hw)->POSITION.reg; -} - -static inline void hri_mtb_set_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->MASTER.reg |= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_master_reg_t hri_mtb_get_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->MASTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mtb_write_MASTER_reg(const void *const hw, hri_mtb_master_reg_t data) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->MASTER.reg = data; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_clear_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->MASTER.reg &= ~mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_toggle_MASTER_reg(const void *const hw, hri_mtb_master_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->MASTER.reg ^= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_master_reg_t hri_mtb_read_MASTER_reg(const void *const hw) -{ - return ((Mtb *)hw)->MASTER.reg; -} - -static inline void hri_mtb_set_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->FLOW.reg |= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_flow_reg_t hri_mtb_get_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->FLOW.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mtb_write_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t data) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->FLOW.reg = data; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_clear_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->FLOW.reg &= ~mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_toggle_FLOW_reg(const void *const hw, hri_mtb_flow_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->FLOW.reg ^= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_flow_reg_t hri_mtb_read_FLOW_reg(const void *const hw) -{ - return ((Mtb *)hw)->FLOW.reg; -} - -static inline void hri_mtb_set_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->ITCTRL.reg |= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_itctrl_reg_t hri_mtb_get_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->ITCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mtb_write_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t data) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->ITCTRL.reg = data; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_clear_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->ITCTRL.reg &= ~mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_toggle_ITCTRL_reg(const void *const hw, hri_mtb_itctrl_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->ITCTRL.reg ^= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_itctrl_reg_t hri_mtb_read_ITCTRL_reg(const void *const hw) -{ - return ((Mtb *)hw)->ITCTRL.reg; -} - -static inline void hri_mtb_set_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->LOCKACCESS.reg |= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_lockaccess_reg_t hri_mtb_get_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->LOCKACCESS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mtb_write_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t data) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->LOCKACCESS.reg = data; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_clear_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->LOCKACCESS.reg &= ~mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mtb_toggle_LOCKACCESS_reg(const void *const hw, hri_mtb_lockaccess_reg_t mask) -{ - MTB_CRITICAL_SECTION_ENTER(); - ((Mtb *)hw)->LOCKACCESS.reg ^= mask; - MTB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mtb_lockaccess_reg_t hri_mtb_read_LOCKACCESS_reg(const void *const hw) -{ - return ((Mtb *)hw)->LOCKACCESS.reg; -} - -static inline hri_mtb_base_reg_t hri_mtb_get_BASE_reg(const void *const hw, hri_mtb_base_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->BASE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_base_reg_t hri_mtb_read_BASE_reg(const void *const hw) -{ - return ((Mtb *)hw)->BASE.reg; -} - -static inline hri_mtb_lockstatus_reg_t hri_mtb_get_LOCKSTATUS_reg(const void *const hw, hri_mtb_lockstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->LOCKSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_lockstatus_reg_t hri_mtb_read_LOCKSTATUS_reg(const void *const hw) -{ - return ((Mtb *)hw)->LOCKSTATUS.reg; -} - -static inline hri_mtb_authstatus_reg_t hri_mtb_get_AUTHSTATUS_reg(const void *const hw, hri_mtb_authstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->AUTHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_authstatus_reg_t hri_mtb_read_AUTHSTATUS_reg(const void *const hw) -{ - return ((Mtb *)hw)->AUTHSTATUS.reg; -} - -static inline hri_mtb_devarch_reg_t hri_mtb_get_DEVARCH_reg(const void *const hw, hri_mtb_devarch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->DEVARCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_devarch_reg_t hri_mtb_read_DEVARCH_reg(const void *const hw) -{ - return ((Mtb *)hw)->DEVARCH.reg; -} - -static inline hri_mtb_devid_reg_t hri_mtb_get_DEVID_reg(const void *const hw, hri_mtb_devid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->DEVID.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_devid_reg_t hri_mtb_read_DEVID_reg(const void *const hw) -{ - return ((Mtb *)hw)->DEVID.reg; -} - -static inline hri_mtb_devtype_reg_t hri_mtb_get_DEVTYPE_reg(const void *const hw, hri_mtb_devtype_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->DEVTYPE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_devtype_reg_t hri_mtb_read_DEVTYPE_reg(const void *const hw) -{ - return ((Mtb *)hw)->DEVTYPE.reg; -} - -static inline hri_mtb_pid4_reg_t hri_mtb_get_PID4_reg(const void *const hw, hri_mtb_pid4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID4.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid4_reg_t hri_mtb_read_PID4_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID4.reg; -} - -static inline hri_mtb_pid5_reg_t hri_mtb_get_PID5_reg(const void *const hw, hri_mtb_pid5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID5.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid5_reg_t hri_mtb_read_PID5_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID5.reg; -} - -static inline hri_mtb_pid6_reg_t hri_mtb_get_PID6_reg(const void *const hw, hri_mtb_pid6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID6.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid6_reg_t hri_mtb_read_PID6_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID6.reg; -} - -static inline hri_mtb_pid7_reg_t hri_mtb_get_PID7_reg(const void *const hw, hri_mtb_pid7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID7.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid7_reg_t hri_mtb_read_PID7_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID7.reg; -} - -static inline hri_mtb_pid0_reg_t hri_mtb_get_PID0_reg(const void *const hw, hri_mtb_pid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid0_reg_t hri_mtb_read_PID0_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID0.reg; -} - -static inline hri_mtb_pid1_reg_t hri_mtb_get_PID1_reg(const void *const hw, hri_mtb_pid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid1_reg_t hri_mtb_read_PID1_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID1.reg; -} - -static inline hri_mtb_pid2_reg_t hri_mtb_get_PID2_reg(const void *const hw, hri_mtb_pid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid2_reg_t hri_mtb_read_PID2_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID2.reg; -} - -static inline hri_mtb_pid3_reg_t hri_mtb_get_PID3_reg(const void *const hw, hri_mtb_pid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->PID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_pid3_reg_t hri_mtb_read_PID3_reg(const void *const hw) -{ - return ((Mtb *)hw)->PID3.reg; -} - -static inline hri_mtb_cid0_reg_t hri_mtb_get_CID0_reg(const void *const hw, hri_mtb_cid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->CID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_cid0_reg_t hri_mtb_read_CID0_reg(const void *const hw) -{ - return ((Mtb *)hw)->CID0.reg; -} - -static inline hri_mtb_cid1_reg_t hri_mtb_get_CID1_reg(const void *const hw, hri_mtb_cid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->CID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_cid1_reg_t hri_mtb_read_CID1_reg(const void *const hw) -{ - return ((Mtb *)hw)->CID1.reg; -} - -static inline hri_mtb_cid2_reg_t hri_mtb_get_CID2_reg(const void *const hw, hri_mtb_cid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->CID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_cid2_reg_t hri_mtb_read_CID2_reg(const void *const hw) -{ - return ((Mtb *)hw)->CID2.reg; -} - -static inline hri_mtb_cid3_reg_t hri_mtb_get_CID3_reg(const void *const hw, hri_mtb_cid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mtb *)hw)->CID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mtb_cid3_reg_t hri_mtb_read_CID3_reg(const void *const hw) -{ - return ((Mtb *)hw)->CID3.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_MTB_D21_H_INCLUDED */ -#endif /* _SAMD21_MTB_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_nvic_d21.h b/atmel-samd/asf4/samd21/hri/hri_nvic_d21.h deleted file mode 100644 index 366387209..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_nvic_d21.h +++ /dev/null @@ -1,2304 +0,0 @@ -/** - * \file - * - * \brief SAM NVIC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_NVIC_COMPONENT_ -#ifndef _HRI_NVIC_D21_H_INCLUDED_ -#define _HRI_NVIC_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_NVIC_CRITICAL_SECTIONS) -#define NVIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define NVIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define NVIC_CRITICAL_SECTION_ENTER() -#define NVIC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_nvic_nvicicer_reg_t; -typedef uint32_t hri_nvic_nvicicpr_reg_t; -typedef uint32_t hri_nvic_nvicipr0_reg_t; -typedef uint32_t hri_nvic_nvicipr1_reg_t; -typedef uint32_t hri_nvic_nvicipr2_reg_t; -typedef uint32_t hri_nvic_nvicipr3_reg_t; -typedef uint32_t hri_nvic_nvicipr4_reg_t; -typedef uint32_t hri_nvic_nvicipr5_reg_t; -typedef uint32_t hri_nvic_nvicipr6_reg_t; -typedef uint32_t hri_nvic_nvicipr7_reg_t; -typedef uint32_t hri_nvic_nviciser_reg_t; -typedef uint32_t hri_nvic_nvicispr_reg_t; - -static inline void hri_nvic_set_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISER.reg |= NVIC_NVICISER_SETENA(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nviciser_reg_t hri_nvic_get_NVICISER_SETENA_bf(const void *const hw, - hri_nvic_nviciser_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICISER.reg; - tmp = (tmp & NVIC_NVICISER_SETENA(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICISER.reg; - tmp &= ~NVIC_NVICISER_SETENA_Msk; - tmp |= NVIC_NVICISER_SETENA(data); - ((Nvic *)hw)->NVICISER.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISER.reg &= ~NVIC_NVICISER_SETENA(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICISER_SETENA_bf(const void *const hw, hri_nvic_nviciser_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISER.reg ^= NVIC_NVICISER_SETENA(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nviciser_reg_t hri_nvic_read_NVICISER_SETENA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICISER.reg; - tmp = (tmp & NVIC_NVICISER_SETENA_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISER.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nviciser_reg_t hri_nvic_get_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICISER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISER.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISER.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICISER_reg(const void *const hw, hri_nvic_nviciser_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISER.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nviciser_reg_t hri_nvic_read_NVICISER_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICISER.reg; -} - -static inline void hri_nvic_set_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICER.reg |= NVIC_NVICICER_CLRENA(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicicer_reg_t hri_nvic_get_NVICICER_CLRENA_bf(const void *const hw, - hri_nvic_nvicicer_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICICER.reg; - tmp = (tmp & NVIC_NVICICER_CLRENA(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICICER.reg; - tmp &= ~NVIC_NVICICER_CLRENA_Msk; - tmp |= NVIC_NVICICER_CLRENA(data); - ((Nvic *)hw)->NVICICER.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICER.reg &= ~NVIC_NVICICER_CLRENA(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICICER_CLRENA_bf(const void *const hw, hri_nvic_nvicicer_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICER.reg ^= NVIC_NVICICER_CLRENA(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicicer_reg_t hri_nvic_read_NVICICER_CLRENA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICICER.reg; - tmp = (tmp & NVIC_NVICICER_CLRENA_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICER.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicicer_reg_t hri_nvic_get_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICICER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICER.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICER.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICICER_reg(const void *const hw, hri_nvic_nvicicer_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICER.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicicer_reg_t hri_nvic_read_NVICICER_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICICER.reg; -} - -static inline void hri_nvic_set_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISPR.reg |= NVIC_NVICISPR_SETPEND(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicispr_reg_t hri_nvic_get_NVICISPR_SETPEND_bf(const void *const hw, - hri_nvic_nvicispr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICISPR.reg; - tmp = (tmp & NVIC_NVICISPR_SETPEND(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICISPR.reg; - tmp &= ~NVIC_NVICISPR_SETPEND_Msk; - tmp |= NVIC_NVICISPR_SETPEND(data); - ((Nvic *)hw)->NVICISPR.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISPR.reg &= ~NVIC_NVICISPR_SETPEND(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICISPR_SETPEND_bf(const void *const hw, hri_nvic_nvicispr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISPR.reg ^= NVIC_NVICISPR_SETPEND(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicispr_reg_t hri_nvic_read_NVICISPR_SETPEND_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICISPR.reg; - tmp = (tmp & NVIC_NVICISPR_SETPEND_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISPR.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicispr_reg_t hri_nvic_get_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICISPR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISPR.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISPR.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICISPR_reg(const void *const hw, hri_nvic_nvicispr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICISPR.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicispr_reg_t hri_nvic_read_NVICISPR_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICISPR.reg; -} - -static inline void hri_nvic_set_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICPR.reg |= NVIC_NVICICPR_CLRPEND(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicicpr_reg_t hri_nvic_get_NVICICPR_CLRPEND_bf(const void *const hw, - hri_nvic_nvicicpr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICICPR.reg; - tmp = (tmp & NVIC_NVICICPR_CLRPEND(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICICPR.reg; - tmp &= ~NVIC_NVICICPR_CLRPEND_Msk; - tmp |= NVIC_NVICICPR_CLRPEND(data); - ((Nvic *)hw)->NVICICPR.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICPR.reg &= ~NVIC_NVICICPR_CLRPEND(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICICPR_CLRPEND_bf(const void *const hw, hri_nvic_nvicicpr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICPR.reg ^= NVIC_NVICICPR_CLRPEND(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicicpr_reg_t hri_nvic_read_NVICICPR_CLRPEND_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICICPR.reg; - tmp = (tmp & NVIC_NVICICPR_CLRPEND_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICPR.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicicpr_reg_t hri_nvic_get_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICICPR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICPR.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICPR.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICICPR_reg(const void *const hw, hri_nvic_nvicicpr_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICICPR.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicicpr_reg_t hri_nvic_read_NVICICPR_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICICPR.reg; -} - -static inline void hri_nvic_set_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI0(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp = (tmp & NVIC_NVICIPR0_PRI0(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp &= ~NVIC_NVICIPR0_PRI0_Msk; - tmp |= NVIC_NVICIPR0_PRI0(data); - ((Nvic *)hw)->NVICIPR0.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI0(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR0_PRI0_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI0(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp = (tmp & NVIC_NVICIPR0_PRI0_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI1(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp = (tmp & NVIC_NVICIPR0_PRI1(mask)) >> 8; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp &= ~NVIC_NVICIPR0_PRI1_Msk; - tmp |= NVIC_NVICIPR0_PRI1(data); - ((Nvic *)hw)->NVICIPR0.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI1(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR0_PRI1_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI1(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp = (tmp & NVIC_NVICIPR0_PRI1_Msk) >> 8; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI2(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp = (tmp & NVIC_NVICIPR0_PRI2(mask)) >> 16; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp &= ~NVIC_NVICIPR0_PRI2_Msk; - tmp |= NVIC_NVICIPR0_PRI2(data); - ((Nvic *)hw)->NVICIPR0.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI2(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR0_PRI2_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI2(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp = (tmp & NVIC_NVICIPR0_PRI2_Msk) >> 16; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg |= NVIC_NVICIPR0_PRI3(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp = (tmp & NVIC_NVICIPR0_PRI3(mask)) >> 24; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp &= ~NVIC_NVICIPR0_PRI3_Msk; - tmp |= NVIC_NVICIPR0_PRI3(data); - ((Nvic *)hw)->NVICIPR0.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg &= ~NVIC_NVICIPR0_PRI3(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR0_PRI3_bf(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg ^= NVIC_NVICIPR0_PRI3(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_PRI3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp = (tmp & NVIC_NVICIPR0_PRI3_Msk) >> 24; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr0_reg_t hri_nvic_get_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR0_reg(const void *const hw, hri_nvic_nvicipr0_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR0.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr0_reg_t hri_nvic_read_NVICIPR0_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICIPR0.reg; -} - -static inline void hri_nvic_set_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI4(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp = (tmp & NVIC_NVICIPR1_PRI4(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp &= ~NVIC_NVICIPR1_PRI4_Msk; - tmp |= NVIC_NVICIPR1_PRI4(data); - ((Nvic *)hw)->NVICIPR1.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI4(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR1_PRI4_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI4(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI4_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp = (tmp & NVIC_NVICIPR1_PRI4_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI5(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp = (tmp & NVIC_NVICIPR1_PRI5(mask)) >> 8; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp &= ~NVIC_NVICIPR1_PRI5_Msk; - tmp |= NVIC_NVICIPR1_PRI5(data); - ((Nvic *)hw)->NVICIPR1.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI5(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR1_PRI5_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI5(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI5_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp = (tmp & NVIC_NVICIPR1_PRI5_Msk) >> 8; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI6(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp = (tmp & NVIC_NVICIPR1_PRI6(mask)) >> 16; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp &= ~NVIC_NVICIPR1_PRI6_Msk; - tmp |= NVIC_NVICIPR1_PRI6(data); - ((Nvic *)hw)->NVICIPR1.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI6(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR1_PRI6_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI6(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI6_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp = (tmp & NVIC_NVICIPR1_PRI6_Msk) >> 16; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg |= NVIC_NVICIPR1_PRI7(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp = (tmp & NVIC_NVICIPR1_PRI7(mask)) >> 24; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp &= ~NVIC_NVICIPR1_PRI7_Msk; - tmp |= NVIC_NVICIPR1_PRI7(data); - ((Nvic *)hw)->NVICIPR1.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg &= ~NVIC_NVICIPR1_PRI7(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR1_PRI7_bf(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg ^= NVIC_NVICIPR1_PRI7(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_PRI7_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp = (tmp & NVIC_NVICIPR1_PRI7_Msk) >> 24; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr1_reg_t hri_nvic_get_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR1_reg(const void *const hw, hri_nvic_nvicipr1_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR1.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr1_reg_t hri_nvic_read_NVICIPR1_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICIPR1.reg; -} - -static inline void hri_nvic_set_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI8(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp = (tmp & NVIC_NVICIPR2_PRI8(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp &= ~NVIC_NVICIPR2_PRI8_Msk; - tmp |= NVIC_NVICIPR2_PRI8(data); - ((Nvic *)hw)->NVICIPR2.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI8(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR2_PRI8_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI8(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI8_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp = (tmp & NVIC_NVICIPR2_PRI8_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI9(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp = (tmp & NVIC_NVICIPR2_PRI9(mask)) >> 8; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp &= ~NVIC_NVICIPR2_PRI9_Msk; - tmp |= NVIC_NVICIPR2_PRI9(data); - ((Nvic *)hw)->NVICIPR2.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI9(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR2_PRI9_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI9(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI9_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp = (tmp & NVIC_NVICIPR2_PRI9_Msk) >> 8; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI10(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp = (tmp & NVIC_NVICIPR2_PRI10(mask)) >> 16; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp &= ~NVIC_NVICIPR2_PRI10_Msk; - tmp |= NVIC_NVICIPR2_PRI10(data); - ((Nvic *)hw)->NVICIPR2.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI10(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR2_PRI10_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI10(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI10_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp = (tmp & NVIC_NVICIPR2_PRI10_Msk) >> 16; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg |= NVIC_NVICIPR2_PRI11(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp = (tmp & NVIC_NVICIPR2_PRI11(mask)) >> 24; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp &= ~NVIC_NVICIPR2_PRI11_Msk; - tmp |= NVIC_NVICIPR2_PRI11(data); - ((Nvic *)hw)->NVICIPR2.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg &= ~NVIC_NVICIPR2_PRI11(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR2_PRI11_bf(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg ^= NVIC_NVICIPR2_PRI11(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_PRI11_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp = (tmp & NVIC_NVICIPR2_PRI11_Msk) >> 24; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr2_reg_t hri_nvic_get_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR2.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR2_reg(const void *const hw, hri_nvic_nvicipr2_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR2.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr2_reg_t hri_nvic_read_NVICIPR2_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICIPR2.reg; -} - -static inline void hri_nvic_set_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI12(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp = (tmp & NVIC_NVICIPR3_PRI12(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp &= ~NVIC_NVICIPR3_PRI12_Msk; - tmp |= NVIC_NVICIPR3_PRI12(data); - ((Nvic *)hw)->NVICIPR3.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI12(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR3_PRI12_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI12(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI12_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp = (tmp & NVIC_NVICIPR3_PRI12_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI13(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp = (tmp & NVIC_NVICIPR3_PRI13(mask)) >> 8; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp &= ~NVIC_NVICIPR3_PRI13_Msk; - tmp |= NVIC_NVICIPR3_PRI13(data); - ((Nvic *)hw)->NVICIPR3.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI13(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR3_PRI13_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI13(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI13_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp = (tmp & NVIC_NVICIPR3_PRI13_Msk) >> 8; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI14(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp = (tmp & NVIC_NVICIPR3_PRI14(mask)) >> 16; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp &= ~NVIC_NVICIPR3_PRI14_Msk; - tmp |= NVIC_NVICIPR3_PRI14(data); - ((Nvic *)hw)->NVICIPR3.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI14(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR3_PRI14_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI14(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI14_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp = (tmp & NVIC_NVICIPR3_PRI14_Msk) >> 16; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg |= NVIC_NVICIPR3_PRI15(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp = (tmp & NVIC_NVICIPR3_PRI15(mask)) >> 24; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp &= ~NVIC_NVICIPR3_PRI15_Msk; - tmp |= NVIC_NVICIPR3_PRI15(data); - ((Nvic *)hw)->NVICIPR3.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg &= ~NVIC_NVICIPR3_PRI15(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR3_PRI15_bf(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg ^= NVIC_NVICIPR3_PRI15(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_PRI15_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp = (tmp & NVIC_NVICIPR3_PRI15_Msk) >> 24; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr3_reg_t hri_nvic_get_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR3.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR3_reg(const void *const hw, hri_nvic_nvicipr3_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR3.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr3_reg_t hri_nvic_read_NVICIPR3_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICIPR3.reg; -} - -static inline void hri_nvic_set_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI16(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp = (tmp & NVIC_NVICIPR4_PRI16(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp &= ~NVIC_NVICIPR4_PRI16_Msk; - tmp |= NVIC_NVICIPR4_PRI16(data); - ((Nvic *)hw)->NVICIPR4.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI16(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR4_PRI16_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI16(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI16_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp = (tmp & NVIC_NVICIPR4_PRI16_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI17(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp = (tmp & NVIC_NVICIPR4_PRI17(mask)) >> 8; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp &= ~NVIC_NVICIPR4_PRI17_Msk; - tmp |= NVIC_NVICIPR4_PRI17(data); - ((Nvic *)hw)->NVICIPR4.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI17(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR4_PRI17_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI17(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI17_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp = (tmp & NVIC_NVICIPR4_PRI17_Msk) >> 8; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI18(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp = (tmp & NVIC_NVICIPR4_PRI18(mask)) >> 16; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp &= ~NVIC_NVICIPR4_PRI18_Msk; - tmp |= NVIC_NVICIPR4_PRI18(data); - ((Nvic *)hw)->NVICIPR4.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI18(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR4_PRI18_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI18(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI18_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp = (tmp & NVIC_NVICIPR4_PRI18_Msk) >> 16; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg |= NVIC_NVICIPR4_PRI19(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp = (tmp & NVIC_NVICIPR4_PRI19(mask)) >> 24; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp &= ~NVIC_NVICIPR4_PRI19_Msk; - tmp |= NVIC_NVICIPR4_PRI19(data); - ((Nvic *)hw)->NVICIPR4.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg &= ~NVIC_NVICIPR4_PRI19(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR4_PRI19_bf(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg ^= NVIC_NVICIPR4_PRI19(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_PRI19_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp = (tmp & NVIC_NVICIPR4_PRI19_Msk) >> 24; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr4_reg_t hri_nvic_get_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR4.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR4_reg(const void *const hw, hri_nvic_nvicipr4_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR4.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr4_reg_t hri_nvic_read_NVICIPR4_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICIPR4.reg; -} - -static inline void hri_nvic_set_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI20(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp = (tmp & NVIC_NVICIPR5_PRI20(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp &= ~NVIC_NVICIPR5_PRI20_Msk; - tmp |= NVIC_NVICIPR5_PRI20(data); - ((Nvic *)hw)->NVICIPR5.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI20(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR5_PRI20_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI20(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI20_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp = (tmp & NVIC_NVICIPR5_PRI20_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI21(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp = (tmp & NVIC_NVICIPR5_PRI21(mask)) >> 8; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp &= ~NVIC_NVICIPR5_PRI21_Msk; - tmp |= NVIC_NVICIPR5_PRI21(data); - ((Nvic *)hw)->NVICIPR5.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI21(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR5_PRI21_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI21(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI21_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp = (tmp & NVIC_NVICIPR5_PRI21_Msk) >> 8; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI22(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp = (tmp & NVIC_NVICIPR5_PRI22(mask)) >> 16; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp &= ~NVIC_NVICIPR5_PRI22_Msk; - tmp |= NVIC_NVICIPR5_PRI22(data); - ((Nvic *)hw)->NVICIPR5.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI22(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR5_PRI22_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI22(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI22_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp = (tmp & NVIC_NVICIPR5_PRI22_Msk) >> 16; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg |= NVIC_NVICIPR5_PRI23(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp = (tmp & NVIC_NVICIPR5_PRI23(mask)) >> 24; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp &= ~NVIC_NVICIPR5_PRI23_Msk; - tmp |= NVIC_NVICIPR5_PRI23(data); - ((Nvic *)hw)->NVICIPR5.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg &= ~NVIC_NVICIPR5_PRI23(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR5_PRI23_bf(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg ^= NVIC_NVICIPR5_PRI23(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_PRI23_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp = (tmp & NVIC_NVICIPR5_PRI23_Msk) >> 24; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr5_reg_t hri_nvic_get_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR5.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR5_reg(const void *const hw, hri_nvic_nvicipr5_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR5.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr5_reg_t hri_nvic_read_NVICIPR5_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICIPR5.reg; -} - -static inline void hri_nvic_set_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI24(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp = (tmp & NVIC_NVICIPR6_PRI24(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp &= ~NVIC_NVICIPR6_PRI24_Msk; - tmp |= NVIC_NVICIPR6_PRI24(data); - ((Nvic *)hw)->NVICIPR6.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI24(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR6_PRI24_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI24(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI24_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp = (tmp & NVIC_NVICIPR6_PRI24_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI25(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp = (tmp & NVIC_NVICIPR6_PRI25(mask)) >> 8; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp &= ~NVIC_NVICIPR6_PRI25_Msk; - tmp |= NVIC_NVICIPR6_PRI25(data); - ((Nvic *)hw)->NVICIPR6.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI25(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR6_PRI25_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI25(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI25_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp = (tmp & NVIC_NVICIPR6_PRI25_Msk) >> 8; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI26(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp = (tmp & NVIC_NVICIPR6_PRI26(mask)) >> 16; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp &= ~NVIC_NVICIPR6_PRI26_Msk; - tmp |= NVIC_NVICIPR6_PRI26(data); - ((Nvic *)hw)->NVICIPR6.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI26(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR6_PRI26_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI26(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI26_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp = (tmp & NVIC_NVICIPR6_PRI26_Msk) >> 16; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg |= NVIC_NVICIPR6_PRI27(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp = (tmp & NVIC_NVICIPR6_PRI27(mask)) >> 24; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp &= ~NVIC_NVICIPR6_PRI27_Msk; - tmp |= NVIC_NVICIPR6_PRI27(data); - ((Nvic *)hw)->NVICIPR6.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg &= ~NVIC_NVICIPR6_PRI27(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR6_PRI27_bf(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg ^= NVIC_NVICIPR6_PRI27(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_PRI27_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp = (tmp & NVIC_NVICIPR6_PRI27_Msk) >> 24; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr6_reg_t hri_nvic_get_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR6.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR6_reg(const void *const hw, hri_nvic_nvicipr6_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR6.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr6_reg_t hri_nvic_read_NVICIPR6_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICIPR6.reg; -} - -static inline void hri_nvic_set_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI28(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp = (tmp & NVIC_NVICIPR7_PRI28(mask)) >> 0; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp &= ~NVIC_NVICIPR7_PRI28_Msk; - tmp |= NVIC_NVICIPR7_PRI28(data); - ((Nvic *)hw)->NVICIPR7.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI28(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR7_PRI28_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI28(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI28_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp = (tmp & NVIC_NVICIPR7_PRI28_Msk) >> 0; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI29(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp = (tmp & NVIC_NVICIPR7_PRI29(mask)) >> 8; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp &= ~NVIC_NVICIPR7_PRI29_Msk; - tmp |= NVIC_NVICIPR7_PRI29(data); - ((Nvic *)hw)->NVICIPR7.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI29(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR7_PRI29_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI29(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI29_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp = (tmp & NVIC_NVICIPR7_PRI29_Msk) >> 8; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI30(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp = (tmp & NVIC_NVICIPR7_PRI30(mask)) >> 16; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp &= ~NVIC_NVICIPR7_PRI30_Msk; - tmp |= NVIC_NVICIPR7_PRI30(data); - ((Nvic *)hw)->NVICIPR7.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI30(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR7_PRI30_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI30(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI30_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp = (tmp & NVIC_NVICIPR7_PRI30_Msk) >> 16; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg |= NVIC_NVICIPR7_PRI31(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp = (tmp & NVIC_NVICIPR7_PRI31(mask)) >> 24; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t data) -{ - uint32_t tmp; - NVIC_CRITICAL_SECTION_ENTER(); - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp &= ~NVIC_NVICIPR7_PRI31_Msk; - tmp |= NVIC_NVICIPR7_PRI31(data); - ((Nvic *)hw)->NVICIPR7.reg = tmp; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg &= ~NVIC_NVICIPR7_PRI31(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR7_PRI31_bf(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg ^= NVIC_NVICIPR7_PRI31(mask); - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_PRI31_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp = (tmp & NVIC_NVICIPR7_PRI31_Msk) >> 24; - return tmp; -} - -static inline void hri_nvic_set_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg |= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr7_reg_t hri_nvic_get_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvic *)hw)->NVICIPR7.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvic_write_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t data) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg = data; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_clear_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg &= ~mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvic_toggle_NVICIPR7_reg(const void *const hw, hri_nvic_nvicipr7_reg_t mask) -{ - NVIC_CRITICAL_SECTION_ENTER(); - ((Nvic *)hw)->NVICIPR7.reg ^= mask; - NVIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvic_nvicipr7_reg_t hri_nvic_read_NVICIPR7_reg(const void *const hw) -{ - return ((Nvic *)hw)->NVICIPR7.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_NVIC_D21_H_INCLUDED */ -#endif /* _SAMD21_NVIC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_nvmctrl_d21.h b/atmel-samd/asf4/samd21/hri/hri_nvmctrl_d21.h deleted file mode 100644 index dcf781f98..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_nvmctrl_d21.h +++ /dev/null @@ -1,1024 +0,0 @@ -/** - * \file - * - * \brief SAM NVMCTRL - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_NVMCTRL_COMPONENT_ -#ifndef _HRI_NVMCTRL_D21_H_INCLUDED_ -#define _HRI_NVMCTRL_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) -#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define NVMCTRL_CRITICAL_SECTION_ENTER() -#define NVMCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_nvmctrl_ctrla_reg_t; -typedef uint16_t hri_nvmctrl_lock_reg_t; -typedef uint16_t hri_nvmctrl_status_reg_t; -typedef uint32_t hri_nvmctrl_addr_reg_t; -typedef uint32_t hri_nvmctrl_ctrlb_reg_t; -typedef uint32_t hri_nvmctrl_param_reg_t; -typedef uint8_t hri_nvmctrl_intenset_reg_t; -typedef uint8_t hri_nvmctrl_intflag_reg_t; - -static inline void hri_nvmctrl_set_INTEN_READY_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; -} - -static inline bool hri_nvmctrl_get_INTEN_READY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_READY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; - } -} - -static inline void hri_nvmctrl_clear_INTEN_READY_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; -} - -static inline void hri_nvmctrl_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; -} - -static inline bool hri_nvmctrl_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; - } -} - -static inline void hri_nvmctrl_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; -} - -static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) -{ - ((Nvmctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, - hri_nvmctrl_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->INTENSET.reg; -} - -static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) -{ - ((Nvmctrl *)hw)->INTENSET.reg = data; - ((Nvmctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_nvmctrl_get_INTFLAG_READY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_READY_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; -} - -static inline bool hri_nvmctrl_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; -} - -static inline bool hri_nvmctrl_get_interrupt_READY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_READY) >> NVMCTRL_INTFLAG_READY_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_READY_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_READY; -} - -static inline bool hri_nvmctrl_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ERROR) >> NVMCTRL_INTFLAG_ERROR_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ERROR; -} - -static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, - hri_nvmctrl_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_nvmctrl_set_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMD(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CMD(mask)) >> NVMCTRL_CTRLA_CMD_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_CMD_Msk; - tmp |= NVMCTRL_CTRLA_CMD(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMD(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_CMD_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMD(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CMD_Msk) >> NVMCTRL_CTRLA_CMD_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CMDEX(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CMDEX(mask)) >> NVMCTRL_CTRLA_CMDEX_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_CMDEX_Msk; - tmp |= NVMCTRL_CTRLA_CMDEX(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CMDEX(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_CMDEX_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CMDEX(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_CMDEX_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CMDEX_Msk) >> NVMCTRL_CTRLA_CMDEX_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->CTRLA.reg; -} - -static inline void hri_nvmctrl_set_CTRLB_MANW_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_MANW; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLB_MANW_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_MANW) >> NVMCTRL_CTRLB_MANW_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_MANW_bit(const void *const hw, bool value) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= ~NVMCTRL_CTRLB_MANW; - tmp |= value << NVMCTRL_CTRLB_MANW_Pos; - ((Nvmctrl *)hw)->CTRLB.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_MANW_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_MANW; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_MANW_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_MANW; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLB_CACHEDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_CACHEDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLB_CACHEDIS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_CACHEDIS) >> NVMCTRL_CTRLB_CACHEDIS_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_CACHEDIS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= ~NVMCTRL_CTRLB_CACHEDIS; - tmp |= value << NVMCTRL_CTRLB_CACHEDIS_Pos; - ((Nvmctrl *)hw)->CTRLB.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_CACHEDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_CACHEDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_CACHEDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_CACHEDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_RWS(mask)) >> NVMCTRL_CTRLB_RWS_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= ~NVMCTRL_CTRLB_RWS_Msk; - tmp |= NVMCTRL_CTRLB_RWS(data); - ((Nvmctrl *)hw)->CTRLB.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_RWS_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_RWS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_RWS_Msk) >> NVMCTRL_CTRLB_RWS_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_SLEEPPRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_SLEEPPRM_bf(const void *const hw, - hri_nvmctrl_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM(mask)) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= ~NVMCTRL_CTRLB_SLEEPPRM_Msk; - tmp |= NVMCTRL_CTRLB_SLEEPPRM(data); - ((Nvmctrl *)hw)->CTRLB.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_SLEEPPRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_SLEEPPRM_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_SLEEPPRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_SLEEPPRM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_SLEEPPRM_Msk) >> NVMCTRL_CTRLB_SLEEPPRM_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= NVMCTRL_CTRLB_READMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_READMODE_bf(const void *const hw, - hri_nvmctrl_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_READMODE(mask)) >> NVMCTRL_CTRLB_READMODE_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= ~NVMCTRL_CTRLB_READMODE_Msk; - tmp |= NVMCTRL_CTRLB_READMODE(data); - ((Nvmctrl *)hw)->CTRLB.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~NVMCTRL_CTRLB_READMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_READMODE_bf(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= NVMCTRL_CTRLB_READMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_READMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp = (tmp & NVMCTRL_CTRLB_READMODE_Msk) >> NVMCTRL_CTRLB_READMODE_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_get_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrlb_reg_t hri_nvmctrl_read_CTRLB_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->CTRLB.reg; -} - -static inline void hri_nvmctrl_set_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_NVMP(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp = (tmp & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp &= ~NVMCTRL_PARAM_NVMP_Msk; - tmp |= NVMCTRL_PARAM_NVMP(data); - ((Nvmctrl *)hw)->PARAM.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_NVMP(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_NVMP(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp = (tmp & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg |= NVMCTRL_PARAM_PSZ(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp = (tmp & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp &= ~NVMCTRL_PARAM_PSZ_Msk; - tmp |= NVMCTRL_PARAM_PSZ(data); - ((Nvmctrl *)hw)->PARAM.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg &= ~NVMCTRL_PARAM_PSZ(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg ^= NVMCTRL_PARAM_PSZ(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp = (tmp & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->PARAM.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->PARAM.reg; -} - -static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp &= ~NVMCTRL_ADDR_ADDR_Msk; - tmp |= NVMCTRL_ADDR_ADDR(data); - ((Nvmctrl *)hw)->ADDR.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->ADDR.reg; -} - -static inline void hri_nvmctrl_set_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg |= NVMCTRL_LOCK_LOCK(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->LOCK.reg; - tmp = (tmp & NVMCTRL_LOCK_LOCK(mask)) >> NVMCTRL_LOCK_LOCK_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->LOCK.reg; - tmp &= ~NVMCTRL_LOCK_LOCK_Msk; - tmp |= NVMCTRL_LOCK_LOCK(data); - ((Nvmctrl *)hw)->LOCK.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg &= ~NVMCTRL_LOCK_LOCK(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_LOCK_LOCK_bf(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg ^= NVMCTRL_LOCK_LOCK(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_LOCK_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->LOCK.reg; - tmp = (tmp & NVMCTRL_LOCK_LOCK_Msk) >> NVMCTRL_LOCK_LOCK_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_get_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->LOCK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_LOCK_reg(const void *const hw, hri_nvmctrl_lock_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->LOCK.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_lock_reg_t hri_nvmctrl_read_LOCK_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->LOCK.reg; -} - -static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_PRM_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PRM; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_LOAD_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOAD; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_STATUS_PROGE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PROGE) >> NVMCTRL_STATUS_PROGE_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_PROGE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_PROGE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_STATUS_LOCKE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOCKE) >> NVMCTRL_STATUS_LOCKE_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_LOCKE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_LOCKE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_STATUS_NVME_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_NVME) >> NVMCTRL_STATUS_NVME_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_NVME_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_NVME; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_STATUS_SB_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SB) >> NVMCTRL_STATUS_SB_Pos; -} - -static inline void hri_nvmctrl_clear_STATUS_SB_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = NVMCTRL_STATUS_SB; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_clear_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->STATUS.reg = mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_NVMCTRL_D21_H_INCLUDED */ -#endif /* _SAMD21_NVMCTRL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_pac_d21.h b/atmel-samd/asf4/samd21/hri/hri_pac_d21.h deleted file mode 100644 index fbd75c46c..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_pac_d21.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * \file - * - * \brief SAM PAC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_PAC_COMPONENT_ -#ifndef _HRI_PAC_D21_H_INCLUDED_ -#define _HRI_PAC_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PAC_CRITICAL_SECTIONS) -#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PAC_CRITICAL_SECTION_ENTER() -#define PAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_pac_wpset_reg_t; - -static inline void hri_pac_set_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t mask) -{ - ((Pac *)hw)->WPSET.reg = PAC_WPSET_WP(mask); -} - -static inline hri_pac_wpset_reg_t hri_pac_get_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WPSET.reg; - tmp = (tmp & PAC_WPSET_WP(mask)) >> PAC_WPSET_WP_Pos; - return tmp; -} - -static inline hri_pac_wpset_reg_t hri_pac_read_WP_WP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WPSET.reg; - tmp = (tmp & PAC_WPSET_WP_Msk) >> PAC_WPSET_WP_Pos; - return tmp; -} - -static inline void hri_pac_write_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t data) -{ - ((Pac *)hw)->WPSET.reg = PAC_WPSET_WP(data); - ((Pac *)hw)->WPCLR.reg = ~PAC_WPSET_WP(data); -} - -static inline void hri_pac_clear_WP_WP_bf(const void *const hw, hri_pac_wpset_reg_t mask) -{ - ((Pac *)hw)->WPCLR.reg = PAC_WPSET_WP(mask); -} - -static inline void hri_pac_set_WP_reg(const void *const hw, hri_pac_wpset_reg_t mask) -{ - ((Pac *)hw)->WPSET.reg = mask; -} - -static inline hri_pac_wpset_reg_t hri_pac_get_WP_reg(const void *const hw, hri_pac_wpset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WPSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_wpset_reg_t hri_pac_read_WP_reg(const void *const hw) -{ - return ((Pac *)hw)->WPSET.reg; -} - -static inline void hri_pac_write_WP_reg(const void *const hw, hri_pac_wpset_reg_t data) -{ - ((Pac *)hw)->WPSET.reg = data; - ((Pac *)hw)->WPCLR.reg = ~data; -} - -static inline void hri_pac_clear_WP_reg(const void *const hw, hri_pac_wpset_reg_t mask) -{ - ((Pac *)hw)->WPCLR.reg = mask; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PAC_D21_H_INCLUDED */ -#endif /* _SAMD21_PAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_pm_d21.h b/atmel-samd/asf4/samd21/hri/hri_pm_d21.h deleted file mode 100644 index 41f84b5ea..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_pm_d21.h +++ /dev/null @@ -1,2545 +0,0 @@ -/** - * \file - * - * \brief SAM PM - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_PM_COMPONENT_ -#ifndef _HRI_PM_D21_H_INCLUDED_ -#define _HRI_PM_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PM_CRITICAL_SECTIONS) -#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PM_CRITICAL_SECTION_ENTER() -#define PM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_pm_ahbmask_reg_t; -typedef uint32_t hri_pm_apbamask_reg_t; -typedef uint32_t hri_pm_apbbmask_reg_t; -typedef uint32_t hri_pm_apbcmask_reg_t; -typedef uint8_t hri_pm_apbasel_reg_t; -typedef uint8_t hri_pm_apbbsel_reg_t; -typedef uint8_t hri_pm_apbcsel_reg_t; -typedef uint8_t hri_pm_cpusel_reg_t; -typedef uint8_t hri_pm_ctrl_reg_t; -typedef uint8_t hri_pm_intenset_reg_t; -typedef uint8_t hri_pm_intflag_reg_t; -typedef uint8_t hri_pm_rcause_reg_t; -typedef uint8_t hri_pm_sleep_reg_t; - -static inline void hri_pm_set_INTEN_CKRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTENSET.reg = PM_INTENSET_CKRDY; -} - -static inline bool hri_pm_get_INTEN_CKRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_CKRDY) >> PM_INTENSET_CKRDY_Pos; -} - -static inline void hri_pm_write_INTEN_CKRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_CKRDY; - } else { - ((Pm *)hw)->INTENSET.reg = PM_INTENSET_CKRDY; - } -} - -static inline void hri_pm_clear_INTEN_CKRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_CKRDY; -} - -static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - ((Pm *)hw)->INTENSET.reg = mask; -} - -static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) -{ - return ((Pm *)hw)->INTENSET.reg; -} - -static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) -{ - ((Pm *)hw)->INTENSET.reg = data; - ((Pm *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - ((Pm *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_pm_get_INTFLAG_CKRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_CKRDY) >> PM_INTFLAG_CKRDY_Pos; -} - -static inline void hri_pm_clear_INTFLAG_CKRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_CKRDY; -} - -static inline bool hri_pm_get_interrupt_CKRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_CKRDY) >> PM_INTFLAG_CKRDY_Pos; -} - -static inline void hri_pm_clear_interrupt_CKRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_CKRDY; -} - -static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) -{ - return ((Pm *)hw)->INTFLAG.reg; -} - -static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) -{ - ((Pm *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_pm_set_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRL.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ctrl_reg_t hri_pm_get_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRL.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRL.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_CTRL_reg(const void *const hw, hri_pm_ctrl_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRL.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ctrl_reg_t hri_pm_read_CTRL_reg(const void *const hw) -{ - return ((Pm *)hw)->CTRL.reg; -} - -static inline void hri_pm_set_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEP.reg |= PM_SLEEP_IDLE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleep_reg_t hri_pm_get_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEP.reg; - tmp = (tmp & PM_SLEEP_IDLE(mask)) >> PM_SLEEP_IDLE_Pos; - return tmp; -} - -static inline void hri_pm_write_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->SLEEP.reg; - tmp &= ~PM_SLEEP_IDLE_Msk; - tmp |= PM_SLEEP_IDLE(data); - ((Pm *)hw)->SLEEP.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEP.reg &= ~PM_SLEEP_IDLE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_SLEEP_IDLE_bf(const void *const hw, hri_pm_sleep_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEP.reg ^= PM_SLEEP_IDLE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleep_reg_t hri_pm_read_SLEEP_IDLE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEP.reg; - tmp = (tmp & PM_SLEEP_IDLE_Msk) >> PM_SLEEP_IDLE_Pos; - return tmp; -} - -static inline void hri_pm_set_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEP.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleep_reg_t hri_pm_get_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEP.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEP.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEP.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_SLEEP_reg(const void *const hw, hri_pm_sleep_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEP.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleep_reg_t hri_pm_read_SLEEP_reg(const void *const hw) -{ - return ((Pm *)hw)->SLEEP.reg; -} - -static inline void hri_pm_set_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CPUSEL.reg |= PM_CPUSEL_CPUDIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_cpusel_reg_t hri_pm_get_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CPUSEL.reg; - tmp = (tmp & PM_CPUSEL_CPUDIV(mask)) >> PM_CPUSEL_CPUDIV_Pos; - return tmp; -} - -static inline void hri_pm_write_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->CPUSEL.reg; - tmp &= ~PM_CPUSEL_CPUDIV_Msk; - tmp |= PM_CPUSEL_CPUDIV(data); - ((Pm *)hw)->CPUSEL.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CPUSEL.reg &= ~PM_CPUSEL_CPUDIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_CPUSEL_CPUDIV_bf(const void *const hw, hri_pm_cpusel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CPUSEL.reg ^= PM_CPUSEL_CPUDIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_cpusel_reg_t hri_pm_read_CPUSEL_CPUDIV_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CPUSEL.reg; - tmp = (tmp & PM_CPUSEL_CPUDIV_Msk) >> PM_CPUSEL_CPUDIV_Pos; - return tmp; -} - -static inline void hri_pm_set_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CPUSEL.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_cpusel_reg_t hri_pm_get_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CPUSEL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CPUSEL.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CPUSEL.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_CPUSEL_reg(const void *const hw, hri_pm_cpusel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CPUSEL.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_cpusel_reg_t hri_pm_read_CPUSEL_reg(const void *const hw) -{ - return ((Pm *)hw)->CPUSEL.reg; -} - -static inline void hri_pm_set_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBASEL.reg |= PM_APBASEL_APBADIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbasel_reg_t hri_pm_get_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->APBASEL.reg; - tmp = (tmp & PM_APBASEL_APBADIV(mask)) >> PM_APBASEL_APBADIV_Pos; - return tmp; -} - -static inline void hri_pm_write_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBASEL.reg; - tmp &= ~PM_APBASEL_APBADIV_Msk; - tmp |= PM_APBASEL_APBADIV(data); - ((Pm *)hw)->APBASEL.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBASEL.reg &= ~PM_APBASEL_APBADIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBASEL_APBADIV_bf(const void *const hw, hri_pm_apbasel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBASEL.reg ^= PM_APBASEL_APBADIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbasel_reg_t hri_pm_read_APBASEL_APBADIV_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->APBASEL.reg; - tmp = (tmp & PM_APBASEL_APBADIV_Msk) >> PM_APBASEL_APBADIV_Pos; - return tmp; -} - -static inline void hri_pm_set_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBASEL.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbasel_reg_t hri_pm_get_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->APBASEL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBASEL.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBASEL.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBASEL_reg(const void *const hw, hri_pm_apbasel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBASEL.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbasel_reg_t hri_pm_read_APBASEL_reg(const void *const hw) -{ - return ((Pm *)hw)->APBASEL.reg; -} - -static inline void hri_pm_set_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBSEL.reg |= PM_APBBSEL_APBBDIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbbsel_reg_t hri_pm_get_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->APBBSEL.reg; - tmp = (tmp & PM_APBBSEL_APBBDIV(mask)) >> PM_APBBSEL_APBBDIV_Pos; - return tmp; -} - -static inline void hri_pm_write_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBBSEL.reg; - tmp &= ~PM_APBBSEL_APBBDIV_Msk; - tmp |= PM_APBBSEL_APBBDIV(data); - ((Pm *)hw)->APBBSEL.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBSEL.reg &= ~PM_APBBSEL_APBBDIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBBSEL_APBBDIV_bf(const void *const hw, hri_pm_apbbsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBSEL.reg ^= PM_APBBSEL_APBBDIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbbsel_reg_t hri_pm_read_APBBSEL_APBBDIV_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->APBBSEL.reg; - tmp = (tmp & PM_APBBSEL_APBBDIV_Msk) >> PM_APBBSEL_APBBDIV_Pos; - return tmp; -} - -static inline void hri_pm_set_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBSEL.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbbsel_reg_t hri_pm_get_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->APBBSEL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBSEL.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBSEL.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBBSEL_reg(const void *const hw, hri_pm_apbbsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBSEL.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbbsel_reg_t hri_pm_read_APBBSEL_reg(const void *const hw) -{ - return ((Pm *)hw)->APBBSEL.reg; -} - -static inline void hri_pm_set_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCSEL.reg |= PM_APBCSEL_APBCDIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbcsel_reg_t hri_pm_get_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->APBCSEL.reg; - tmp = (tmp & PM_APBCSEL_APBCDIV(mask)) >> PM_APBCSEL_APBCDIV_Pos; - return tmp; -} - -static inline void hri_pm_write_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCSEL.reg; - tmp &= ~PM_APBCSEL_APBCDIV_Msk; - tmp |= PM_APBCSEL_APBCDIV(data); - ((Pm *)hw)->APBCSEL.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCSEL.reg &= ~PM_APBCSEL_APBCDIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCSEL_APBCDIV_bf(const void *const hw, hri_pm_apbcsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCSEL.reg ^= PM_APBCSEL_APBCDIV(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbcsel_reg_t hri_pm_read_APBCSEL_APBCDIV_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->APBCSEL.reg; - tmp = (tmp & PM_APBCSEL_APBCDIV_Msk) >> PM_APBCSEL_APBCDIV_Pos; - return tmp; -} - -static inline void hri_pm_set_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCSEL.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbcsel_reg_t hri_pm_get_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->APBCSEL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCSEL.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCSEL.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCSEL_reg(const void *const hw, hri_pm_apbcsel_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCSEL.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbcsel_reg_t hri_pm_read_APBCSEL_reg(const void *const hw) -{ - return ((Pm *)hw)->APBCSEL.reg; -} - -static inline void hri_pm_set_AHBMASK_HPB0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_HPB0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_AHBMASK_HPB0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp = (tmp & PM_AHBMASK_HPB0) >> PM_AHBMASK_HPB0_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_AHBMASK_HPB0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp &= ~PM_AHBMASK_HPB0; - tmp |= value << PM_AHBMASK_HPB0_Pos; - ((Pm *)hw)->AHBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_AHBMASK_HPB0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_HPB0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_AHBMASK_HPB0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_HPB0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_AHBMASK_HPB1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_HPB1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_AHBMASK_HPB1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp = (tmp & PM_AHBMASK_HPB1) >> PM_AHBMASK_HPB1_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_AHBMASK_HPB1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp &= ~PM_AHBMASK_HPB1; - tmp |= value << PM_AHBMASK_HPB1_Pos; - ((Pm *)hw)->AHBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_AHBMASK_HPB1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_HPB1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_AHBMASK_HPB1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_HPB1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_AHBMASK_HPB2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_HPB2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_AHBMASK_HPB2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp = (tmp & PM_AHBMASK_HPB2) >> PM_AHBMASK_HPB2_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_AHBMASK_HPB2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp &= ~PM_AHBMASK_HPB2; - tmp |= value << PM_AHBMASK_HPB2_Pos; - ((Pm *)hw)->AHBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_AHBMASK_HPB2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_HPB2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_AHBMASK_HPB2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_HPB2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_AHBMASK_DSU_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_DSU; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_AHBMASK_DSU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp = (tmp & PM_AHBMASK_DSU) >> PM_AHBMASK_DSU_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_AHBMASK_DSU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp &= ~PM_AHBMASK_DSU; - tmp |= value << PM_AHBMASK_DSU_Pos; - ((Pm *)hw)->AHBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_AHBMASK_DSU_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_DSU; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_AHBMASK_DSU_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_DSU; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_NVMCTRL; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp = (tmp & PM_AHBMASK_NVMCTRL) >> PM_AHBMASK_NVMCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp &= ~PM_AHBMASK_NVMCTRL; - tmp |= value << PM_AHBMASK_NVMCTRL_Pos; - ((Pm *)hw)->AHBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_NVMCTRL; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_NVMCTRL; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_AHBMASK_DMAC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_DMAC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_AHBMASK_DMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp = (tmp & PM_AHBMASK_DMAC) >> PM_AHBMASK_DMAC_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_AHBMASK_DMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp &= ~PM_AHBMASK_DMAC; - tmp |= value << PM_AHBMASK_DMAC_Pos; - ((Pm *)hw)->AHBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_AHBMASK_DMAC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_DMAC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_AHBMASK_DMAC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_DMAC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_AHBMASK_USB_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg |= PM_AHBMASK_USB; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_AHBMASK_USB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp = (tmp & PM_AHBMASK_USB) >> PM_AHBMASK_USB_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_AHBMASK_USB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp &= ~PM_AHBMASK_USB; - tmp |= value << PM_AHBMASK_USB_Pos; - ((Pm *)hw)->AHBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_AHBMASK_USB_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg &= ~PM_AHBMASK_USB; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_AHBMASK_USB_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg ^= PM_AHBMASK_USB; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ahbmask_reg_t hri_pm_get_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->AHBMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_AHBMASK_reg(const void *const hw, hri_pm_ahbmask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->AHBMASK.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ahbmask_reg_t hri_pm_read_AHBMASK_reg(const void *const hw) -{ - return ((Pm *)hw)->AHBMASK.reg; -} - -static inline void hri_pm_set_APBAMASK_PAC0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_PAC0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBAMASK_PAC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp = (tmp & PM_APBAMASK_PAC0) >> PM_APBAMASK_PAC0_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBAMASK_PAC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp &= ~PM_APBAMASK_PAC0; - tmp |= value << PM_APBAMASK_PAC0_Pos; - ((Pm *)hw)->APBAMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBAMASK_PAC0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_PAC0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBAMASK_PAC0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_PAC0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBAMASK_PM_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_PM; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBAMASK_PM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp = (tmp & PM_APBAMASK_PM) >> PM_APBAMASK_PM_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBAMASK_PM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp &= ~PM_APBAMASK_PM; - tmp |= value << PM_APBAMASK_PM_Pos; - ((Pm *)hw)->APBAMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBAMASK_PM_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_PM; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBAMASK_PM_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_PM; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBAMASK_SYSCTRL_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_SYSCTRL; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBAMASK_SYSCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp = (tmp & PM_APBAMASK_SYSCTRL) >> PM_APBAMASK_SYSCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBAMASK_SYSCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp &= ~PM_APBAMASK_SYSCTRL; - tmp |= value << PM_APBAMASK_SYSCTRL_Pos; - ((Pm *)hw)->APBAMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBAMASK_SYSCTRL_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_SYSCTRL; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBAMASK_SYSCTRL_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_SYSCTRL; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBAMASK_GCLK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_GCLK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBAMASK_GCLK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp = (tmp & PM_APBAMASK_GCLK) >> PM_APBAMASK_GCLK_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBAMASK_GCLK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp &= ~PM_APBAMASK_GCLK; - tmp |= value << PM_APBAMASK_GCLK_Pos; - ((Pm *)hw)->APBAMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBAMASK_GCLK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_GCLK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBAMASK_GCLK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_GCLK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBAMASK_WDT_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_WDT; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBAMASK_WDT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp = (tmp & PM_APBAMASK_WDT) >> PM_APBAMASK_WDT_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBAMASK_WDT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp &= ~PM_APBAMASK_WDT; - tmp |= value << PM_APBAMASK_WDT_Pos; - ((Pm *)hw)->APBAMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBAMASK_WDT_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_WDT; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBAMASK_WDT_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_WDT; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBAMASK_RTC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_RTC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBAMASK_RTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp = (tmp & PM_APBAMASK_RTC) >> PM_APBAMASK_RTC_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBAMASK_RTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp &= ~PM_APBAMASK_RTC; - tmp |= value << PM_APBAMASK_RTC_Pos; - ((Pm *)hw)->APBAMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBAMASK_RTC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_RTC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBAMASK_RTC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_RTC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBAMASK_EIC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg |= PM_APBAMASK_EIC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBAMASK_EIC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp = (tmp & PM_APBAMASK_EIC) >> PM_APBAMASK_EIC_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBAMASK_EIC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp &= ~PM_APBAMASK_EIC; - tmp |= value << PM_APBAMASK_EIC_Pos; - ((Pm *)hw)->APBAMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBAMASK_EIC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg &= ~PM_APBAMASK_EIC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBAMASK_EIC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg ^= PM_APBAMASK_EIC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbamask_reg_t hri_pm_get_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBAMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBAMASK_reg(const void *const hw, hri_pm_apbamask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBAMASK.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbamask_reg_t hri_pm_read_APBAMASK_reg(const void *const hw) -{ - return ((Pm *)hw)->APBAMASK.reg; -} - -static inline void hri_pm_set_APBBMASK_PAC1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_PAC1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBBMASK_PAC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp = (tmp & PM_APBBMASK_PAC1) >> PM_APBBMASK_PAC1_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBBMASK_PAC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp &= ~PM_APBBMASK_PAC1; - tmp |= value << PM_APBBMASK_PAC1_Pos; - ((Pm *)hw)->APBBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBBMASK_PAC1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_PAC1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBBMASK_PAC1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_PAC1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBBMASK_DSU_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_DSU; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBBMASK_DSU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp = (tmp & PM_APBBMASK_DSU) >> PM_APBBMASK_DSU_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBBMASK_DSU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp &= ~PM_APBBMASK_DSU; - tmp |= value << PM_APBBMASK_DSU_Pos; - ((Pm *)hw)->APBBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBBMASK_DSU_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_DSU; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBBMASK_DSU_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_DSU; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_NVMCTRL; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp = (tmp & PM_APBBMASK_NVMCTRL) >> PM_APBBMASK_NVMCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp &= ~PM_APBBMASK_NVMCTRL; - tmp |= value << PM_APBBMASK_NVMCTRL_Pos; - ((Pm *)hw)->APBBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_NVMCTRL; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_NVMCTRL; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBBMASK_PORT_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_PORT; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBBMASK_PORT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp = (tmp & PM_APBBMASK_PORT) >> PM_APBBMASK_PORT_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBBMASK_PORT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp &= ~PM_APBBMASK_PORT; - tmp |= value << PM_APBBMASK_PORT_Pos; - ((Pm *)hw)->APBBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBBMASK_PORT_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_PORT; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBBMASK_PORT_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_PORT; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBBMASK_DMAC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_DMAC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBBMASK_DMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp = (tmp & PM_APBBMASK_DMAC) >> PM_APBBMASK_DMAC_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBBMASK_DMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp &= ~PM_APBBMASK_DMAC; - tmp |= value << PM_APBBMASK_DMAC_Pos; - ((Pm *)hw)->APBBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBBMASK_DMAC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_DMAC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBBMASK_DMAC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_DMAC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBBMASK_USB_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_USB; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBBMASK_USB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp = (tmp & PM_APBBMASK_USB) >> PM_APBBMASK_USB_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBBMASK_USB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp &= ~PM_APBBMASK_USB; - tmp |= value << PM_APBBMASK_USB_Pos; - ((Pm *)hw)->APBBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBBMASK_USB_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_USB; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBBMASK_USB_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_USB; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBBMASK_HMATRIX_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg |= PM_APBBMASK_HMATRIX; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBBMASK_HMATRIX_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp = (tmp & PM_APBBMASK_HMATRIX) >> PM_APBBMASK_HMATRIX_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp &= ~PM_APBBMASK_HMATRIX; - tmp |= value << PM_APBBMASK_HMATRIX_Pos; - ((Pm *)hw)->APBBMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBBMASK_HMATRIX_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg &= ~PM_APBBMASK_HMATRIX; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBBMASK_HMATRIX_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg ^= PM_APBBMASK_HMATRIX; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbbmask_reg_t hri_pm_get_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBBMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBBMASK_reg(const void *const hw, hri_pm_apbbmask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBBMASK.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbbmask_reg_t hri_pm_read_APBBMASK_reg(const void *const hw) -{ - return ((Pm *)hw)->APBBMASK.reg; -} - -static inline void hri_pm_set_APBCMASK_PAC2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_PAC2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_PAC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_PAC2) >> PM_APBCMASK_PAC2_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_PAC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_PAC2; - tmp |= value << PM_APBCMASK_PAC2_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_PAC2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_PAC2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_PAC2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_PAC2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_EVSYS_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_EVSYS; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_EVSYS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_EVSYS) >> PM_APBCMASK_EVSYS_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_EVSYS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_EVSYS; - tmp |= value << PM_APBCMASK_EVSYS_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_EVSYS_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_EVSYS; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_EVSYS_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_EVSYS; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_SERCOM0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_SERCOM0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_SERCOM0) >> PM_APBCMASK_SERCOM0_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_SERCOM0; - tmp |= value << PM_APBCMASK_SERCOM0_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_SERCOM0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_SERCOM0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_SERCOM1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_SERCOM1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_SERCOM1) >> PM_APBCMASK_SERCOM1_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_SERCOM1; - tmp |= value << PM_APBCMASK_SERCOM1_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_SERCOM1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_SERCOM1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_SERCOM2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_SERCOM2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_SERCOM2) >> PM_APBCMASK_SERCOM2_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_SERCOM2; - tmp |= value << PM_APBCMASK_SERCOM2_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_SERCOM2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_SERCOM2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_SERCOM3_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM3; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_SERCOM3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_SERCOM3) >> PM_APBCMASK_SERCOM3_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_SERCOM3; - tmp |= value << PM_APBCMASK_SERCOM3_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_SERCOM3_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM3; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_SERCOM3_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM3; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_SERCOM4_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM4; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_SERCOM4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_SERCOM4) >> PM_APBCMASK_SERCOM4_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_SERCOM4; - tmp |= value << PM_APBCMASK_SERCOM4_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_SERCOM4_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM4; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_SERCOM4_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM4; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_SERCOM5_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_SERCOM5; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_SERCOM5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_SERCOM5) >> PM_APBCMASK_SERCOM5_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_SERCOM5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_SERCOM5; - tmp |= value << PM_APBCMASK_SERCOM5_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_SERCOM5_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_SERCOM5; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_SERCOM5_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_SERCOM5; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_TCC0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TCC0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_TCC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_TCC0) >> PM_APBCMASK_TCC0_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_TCC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_TCC0; - tmp |= value << PM_APBCMASK_TCC0_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_TCC0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TCC0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_TCC0_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TCC0; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_TCC1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TCC1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_TCC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_TCC1) >> PM_APBCMASK_TCC1_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_TCC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_TCC1; - tmp |= value << PM_APBCMASK_TCC1_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_TCC1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TCC1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_TCC1_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TCC1; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_TCC2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TCC2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_TCC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_TCC2) >> PM_APBCMASK_TCC2_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_TCC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_TCC2; - tmp |= value << PM_APBCMASK_TCC2_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_TCC2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TCC2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_TCC2_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TCC2; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_TC3_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC3; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_TC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_TC3) >> PM_APBCMASK_TC3_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_TC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_TC3; - tmp |= value << PM_APBCMASK_TC3_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_TC3_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC3; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_TC3_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC3; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_TC4_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC4; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_TC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_TC4) >> PM_APBCMASK_TC4_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_TC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_TC4; - tmp |= value << PM_APBCMASK_TC4_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_TC4_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC4; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_TC4_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC4; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_TC5_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC5; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_TC5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_TC5) >> PM_APBCMASK_TC5_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_TC5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_TC5; - tmp |= value << PM_APBCMASK_TC5_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_TC5_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC5; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_TC5_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC5; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_TC6_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC6; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_TC6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_TC6) >> PM_APBCMASK_TC6_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_TC6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_TC6; - tmp |= value << PM_APBCMASK_TC6_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_TC6_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC6; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_TC6_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC6; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_TC7_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_TC7; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_TC7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_TC7) >> PM_APBCMASK_TC7_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_TC7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_TC7; - tmp |= value << PM_APBCMASK_TC7_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_TC7_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_TC7; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_TC7_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_TC7; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_ADC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_ADC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_ADC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_ADC) >> PM_APBCMASK_ADC_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_ADC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_ADC; - tmp |= value << PM_APBCMASK_ADC_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_ADC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_ADC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_ADC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_ADC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_AC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_AC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_AC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_AC) >> PM_APBCMASK_AC_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_AC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_AC; - tmp |= value << PM_APBCMASK_AC_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_AC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_AC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_AC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_AC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_DAC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_DAC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_DAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_DAC) >> PM_APBCMASK_DAC_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_DAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_DAC; - tmp |= value << PM_APBCMASK_DAC_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_DAC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_DAC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_DAC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_DAC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_PTC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_PTC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_PTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_PTC) >> PM_APBCMASK_PTC_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_PTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_PTC; - tmp |= value << PM_APBCMASK_PTC_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_PTC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_PTC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_PTC_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_PTC; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_I2S_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= PM_APBCMASK_I2S; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_APBCMASK_I2S_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp = (tmp & PM_APBCMASK_I2S) >> PM_APBCMASK_I2S_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_APBCMASK_I2S_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= ~PM_APBCMASK_I2S; - tmp |= value << PM_APBCMASK_I2S_Pos; - ((Pm *)hw)->APBCMASK.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_I2S_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~PM_APBCMASK_I2S; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_I2S_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= PM_APBCMASK_I2S; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbcmask_reg_t hri_pm_get_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pm *)hw)->APBCMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_APBCMASK_reg(const void *const hw, hri_pm_apbcmask_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->APBCMASK.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_apbcmask_reg_t hri_pm_read_APBCMASK_reg(const void *const hw) -{ - return ((Pm *)hw)->APBCMASK.reg; -} - -static inline bool hri_pm_get_RCAUSE_POR_bit(const void *const hw) -{ - return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_POR) >> PM_RCAUSE_POR_Pos; -} - -static inline bool hri_pm_get_RCAUSE_BOD12_bit(const void *const hw) -{ - return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_BOD12) >> PM_RCAUSE_BOD12_Pos; -} - -static inline bool hri_pm_get_RCAUSE_BOD33_bit(const void *const hw) -{ - return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_BOD33) >> PM_RCAUSE_BOD33_Pos; -} - -static inline bool hri_pm_get_RCAUSE_EXT_bit(const void *const hw) -{ - return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_EXT) >> PM_RCAUSE_EXT_Pos; -} - -static inline bool hri_pm_get_RCAUSE_WDT_bit(const void *const hw) -{ - return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_WDT) >> PM_RCAUSE_WDT_Pos; -} - -static inline bool hri_pm_get_RCAUSE_SYST_bit(const void *const hw) -{ - return (((Pm *)hw)->RCAUSE.reg & PM_RCAUSE_SYST) >> PM_RCAUSE_SYST_Pos; -} - -static inline hri_pm_rcause_reg_t hri_pm_get_RCAUSE_reg(const void *const hw, hri_pm_rcause_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->RCAUSE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pm_rcause_reg_t hri_pm_read_RCAUSE_reg(const void *const hw) -{ - return ((Pm *)hw)->RCAUSE.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PM_D21_H_INCLUDED */ -#endif /* _SAMD21_PM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_port_d21.h b/atmel-samd/asf4/samd21/hri/hri_port_d21.h deleted file mode 100644 index cf37b2a40..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_port_d21.h +++ /dev/null @@ -1,1324 +0,0 @@ -/** - * \file - * - * \brief SAM PORT - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_PORT_COMPONENT_ -#ifndef _HRI_PORT_D21_H_INCLUDED_ -#define _HRI_PORT_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PORT_CRITICAL_SECTIONS) -#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PORT_CRITICAL_SECTION_ENTER() -#define PORT_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_port_ctrl_reg_t; -typedef uint32_t hri_port_dir_reg_t; -typedef uint32_t hri_port_in_reg_t; -typedef uint32_t hri_port_out_reg_t; -typedef uint32_t hri_port_wrconfig_reg_t; -typedef uint32_t hri_portgroup_ctrl_reg_t; -typedef uint32_t hri_portgroup_dir_reg_t; -typedef uint32_t hri_portgroup_in_reg_t; -typedef uint32_t hri_portgroup_out_reg_t; -typedef uint32_t hri_portgroup_wrconfig_reg_t; -typedef uint8_t hri_port_pincfg_reg_t; -typedef uint8_t hri_port_pmux_reg_t; -typedef uint8_t hri_portgroup_pincfg_reg_t; -typedef uint8_t hri_portgroup_pmux_reg_t; - -static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); -} - -static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) -{ - ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); - ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); -} - -static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRSET.reg = mask; -} - -static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) -{ - return ((PortGroup *)hw)->DIR.reg; -} - -static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) -{ - ((PortGroup *)hw)->DIRSET.reg = data; - ((PortGroup *)hw)->DIRCLR.reg = ~data; -} - -static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRCLR.reg = mask; -} - -static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRTGL.reg = mask; -} - -static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); -} - -static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) -{ - ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); - ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); -} - -static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTSET.reg = mask; -} - -static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) -{ - return ((PortGroup *)hw)->OUT.reg; -} - -static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) -{ - ((PortGroup *)hw)->OUTSET.reg = data; - ((PortGroup *)hw)->OUTCLR.reg = ~data; -} - -static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTCLR.reg = mask; -} - -static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTTGL.reg = mask; -} - -static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->WRCONFIG.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp &= ~PORT_CTRL_SAMPLING_Msk; - tmp |= PORT_CTRL_SAMPLING(data); - ((PortGroup *)hw)->CTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) -{ - return ((PortGroup *)hw)->CTRL.reg; -} - -static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXE_Msk; - tmp |= PORT_PMUX_PMUXE(data); - ((PortGroup *)hw)->PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXO_Msk; - tmp |= PORT_PMUX_PMUXO(data); - ((PortGroup *)hw)->PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) -{ - return ((PortGroup *)hw)->PMUX[index].reg; -} - -static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PMUXEN; - tmp |= value << PORT_PINCFG_PMUXEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_INEN; - tmp |= value << PORT_PINCFG_INEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PULLEN; - tmp |= value << PORT_PINCFG_PULLEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_DRVSTR; - tmp |= value << PORT_PINCFG_DRVSTR_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) -{ - return ((PortGroup *)hw)->PINCFG[index].reg; -} - -static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) -{ - return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) -{ - return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->IN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) -{ - return ((PortGroup *)hw)->IN.reg; -} - -static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); -} - -static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, - hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); -} - -static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; -} - -static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, - hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].DIR.reg; -} - -static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; -} - -static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; -} - -static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; -} - -static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); -} - -static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, - hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); -} - -static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; -} - -static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, - hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].OUT.reg; -} - -static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; -} - -static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; -} - -static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; -} - -static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, - hri_port_wrconfig_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp &= ~PORT_CTRL_SAMPLING_Msk; - tmp |= PORT_CTRL_SAMPLING(data); - ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].CTRL.reg; -} - -static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXE_Msk; - tmp |= PORT_PMUX_PMUXE(data); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXO_Msk; - tmp |= PORT_PMUX_PMUXO(data); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; -} - -static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PMUXEN; - tmp |= value << PORT_PINCFG_PMUXEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_INEN; - tmp |= value << PORT_PINCFG_INEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PULLEN; - tmp |= value << PORT_PINCFG_PULLEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_DRVSTR; - tmp |= value << PORT_PINCFG_DRVSTR_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pincfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; -} - -static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, - hri_port_in_reg_t mask) -{ - return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) -{ - return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, - hri_port_in_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].IN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].IN.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PORT_D21_H_INCLUDED */ -#endif /* _SAMD21_PORT_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_rtc_d21.h b/atmel-samd/asf4/samd21/hri/hri_rtc_d21.h deleted file mode 100644 index 49808d60a..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_rtc_d21.h +++ /dev/null @@ -1,5921 +0,0 @@ -/** - * \file - * - * \brief SAM RTC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_RTC_COMPONENT_ -#ifndef _HRI_RTC_D21_H_INCLUDED_ -#define _HRI_RTC_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RTC_CRITICAL_SECTIONS) -#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RTC_CRITICAL_SECTION_ENTER() -#define RTC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_rtcmode0_ctrl_reg_t; -typedef uint16_t hri_rtcmode0_evctrl_reg_t; -typedef uint16_t hri_rtcmode0_readreq_reg_t; -typedef uint16_t hri_rtcmode1_comp_reg_t; -typedef uint16_t hri_rtcmode1_count_reg_t; -typedef uint16_t hri_rtcmode1_ctrl_reg_t; -typedef uint16_t hri_rtcmode1_evctrl_reg_t; -typedef uint16_t hri_rtcmode1_per_reg_t; -typedef uint16_t hri_rtcmode1_readreq_reg_t; -typedef uint16_t hri_rtcmode2_ctrl_reg_t; -typedef uint16_t hri_rtcmode2_evctrl_reg_t; -typedef uint16_t hri_rtcmode2_readreq_reg_t; -typedef uint32_t hri_rtcalarm_alarm_reg_t; -typedef uint32_t hri_rtcmode0_comp_reg_t; -typedef uint32_t hri_rtcmode0_count_reg_t; -typedef uint32_t hri_rtcmode2_alarm_reg_t; -typedef uint32_t hri_rtcmode2_clock_reg_t; -typedef uint8_t hri_rtcalarm_mask_reg_t; -typedef uint8_t hri_rtcmode0_dbgctrl_reg_t; -typedef uint8_t hri_rtcmode0_freqcorr_reg_t; -typedef uint8_t hri_rtcmode0_intenset_reg_t; -typedef uint8_t hri_rtcmode0_intflag_reg_t; -typedef uint8_t hri_rtcmode0_status_reg_t; -typedef uint8_t hri_rtcmode1_dbgctrl_reg_t; -typedef uint8_t hri_rtcmode1_freqcorr_reg_t; -typedef uint8_t hri_rtcmode1_intenset_reg_t; -typedef uint8_t hri_rtcmode1_intflag_reg_t; -typedef uint8_t hri_rtcmode1_status_reg_t; -typedef uint8_t hri_rtcmode2_dbgctrl_reg_t; -typedef uint8_t hri_rtcmode2_freqcorr_reg_t; -typedef uint8_t hri_rtcmode2_intenset_reg_t; -typedef uint8_t hri_rtcmode2_intflag_reg_t; -typedef uint8_t hri_rtcmode2_mask_reg_t; -typedef uint8_t hri_rtcmode2_status_reg_t; - -static inline void hri_rtcmode0_wait_for_sync(const void *const hw) -{ - while (((const Rtc *)hw)->MODE0.STATUS.bit.SYNCBUSY) - ; -} - -static inline bool hri_rtcmode0_is_syncing(const void *const hw) -{ - return ((const Rtc *)hw)->MODE0.STATUS.bit.SYNCBUSY; -} - -static inline void hri_rtcmode1_wait_for_sync(const void *const hw) -{ - while (((const Rtc *)hw)->MODE1.STATUS.bit.SYNCBUSY) - ; -} - -static inline bool hri_rtcmode1_is_syncing(const void *const hw) -{ - return ((const Rtc *)hw)->MODE1.STATUS.bit.SYNCBUSY; -} - -static inline void hri_rtcmode2_wait_for_sync(const void *const hw) -{ - while (((const Rtc *)hw)->MODE2.STATUS.bit.SYNCBUSY) - ; -} - -static inline bool hri_rtcmode2_is_syncing(const void *const hw) -{ - return ((const Rtc *)hw)->MODE2.STATUS.bit.SYNCBUSY; -} - -static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; - tmp |= RTC_MODE2_ALARM_SECOND(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; - tmp |= RTC_MODE2_ALARM_MINUTE(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; - tmp |= RTC_MODE2_ALARM_HOUR(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_DAY_Msk; - tmp |= RTC_MODE2_ALARM_DAY(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; - tmp |= RTC_MODE2_ALARM_MONTH(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; - tmp |= RTC_MODE2_ALARM_YEAR(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) -{ - return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; -} - -static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp &= ~RTC_MODE2_MASK_SEL_Msk; - tmp |= RTC_MODE2_MASK_SEL(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; -} - -static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; - tmp |= RTC_MODE2_ALARM_SECOND(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; - tmp |= RTC_MODE2_ALARM_MINUTE(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; - tmp |= RTC_MODE2_ALARM_HOUR(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_DAY_Msk; - tmp |= RTC_MODE2_ALARM_DAY(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; - tmp |= RTC_MODE2_ALARM_MONTH(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; - tmp |= RTC_MODE2_ALARM_YEAR(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; -} - -static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp &= ~RTC_MODE2_MASK_SEL_Msk; - tmp |= RTC_MODE2_MASK_SEL(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; -} - -static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; -} - -static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; - } -} - -static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; -} - -static inline void hri_rtcmode2_set_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_SYNCRDY; -} - -static inline bool hri_rtcmode2_get_INTEN_SYNCRDY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_SYNCRDY) >> RTC_MODE2_INTENSET_SYNCRDY_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_SYNCRDY; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_SYNCRDY; - } -} - -static inline void hri_rtcmode2_clear_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_SYNCRDY; -} - -static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; -} - -static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; - } -} - -static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; -} - -static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = mask; -} - -static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, - hri_rtcmode2_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.INTENSET.reg; -} - -static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = data; - ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; -} - -static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; -} - -static inline bool hri_rtcmode2_get_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_SYNCRDY) >> RTC_MODE2_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_SYNCRDY; -} - -static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; -} - -static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; -} - -static inline bool hri_rtcmode2_get_interrupt_SYNCRDY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_SYNCRDY) >> RTC_MODE2_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_SYNCRDY; -} - -static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; -} - -static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, - hri_rtcmode2_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.INTFLAG.reg; -} - -static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; -} - -static inline void hri_rtcmode2_set_CTRL_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_SWRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRL_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp = (tmp & RTC_MODE2_CTRL_SWRST) >> RTC_MODE2_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_set_CTRL_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRL_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp = (tmp & RTC_MODE2_CTRL_ENABLE) >> RTC_MODE2_CTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp &= ~RTC_MODE2_CTRL_ENABLE; - tmp |= value << RTC_MODE2_CTRL_ENABLE_Pos; - ((Rtc *)hw)->MODE2.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRL_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRL_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRL_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_CLKREP; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRL_CLKREP_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp = (tmp & RTC_MODE2_CTRL_CLKREP) >> RTC_MODE2_CTRL_CLKREP_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRL_CLKREP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp &= ~RTC_MODE2_CTRL_CLKREP; - tmp |= value << RTC_MODE2_CTRL_CLKREP_Pos; - ((Rtc *)hw)->MODE2.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRL_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_CLKREP; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRL_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_CLKREP; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRL_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRL_MATCHCLR_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp = (tmp & RTC_MODE2_CTRL_MATCHCLR) >> RTC_MODE2_CTRL_MATCHCLR_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRL_MATCHCLR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp &= ~RTC_MODE2_CTRL_MATCHCLR; - tmp |= value << RTC_MODE2_CTRL_MATCHCLR_Pos; - ((Rtc *)hw)->MODE2.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRL_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRL_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_get_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp = (tmp & RTC_MODE2_CTRL_MODE(mask)) >> RTC_MODE2_CTRL_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp &= ~RTC_MODE2_CTRL_MODE_Msk; - tmp |= RTC_MODE2_CTRL_MODE(data); - ((Rtc *)hw)->MODE2.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRL_MODE_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_read_CTRL_MODE_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp = (tmp & RTC_MODE2_CTRL_MODE_Msk) >> RTC_MODE2_CTRL_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg |= RTC_MODE2_CTRL_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_get_CTRL_PRESCALER_bf(const void *const hw, - hri_rtcmode2_ctrl_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp = (tmp & RTC_MODE2_CTRL_PRESCALER(mask)) >> RTC_MODE2_CTRL_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp &= ~RTC_MODE2_CTRL_PRESCALER_Msk; - tmp |= RTC_MODE2_CTRL_PRESCALER(data); - ((Rtc *)hw)->MODE2.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg &= ~RTC_MODE2_CTRL_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CTRL.reg ^= RTC_MODE2_CTRL_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_read_CTRL_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp = (tmp & RTC_MODE2_CTRL_PRESCALER_Msk) >> RTC_MODE2_CTRL_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_get_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRL_reg(const void *const hw, hri_rtcmode2_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrl_reg_t hri_rtcmode2_read_CTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.CTRL.reg; -} - -static inline void hri_rtcmode2_set_READREQ_RCONT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg |= RTC_READREQ_RCONT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_READREQ_RCONT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.READREQ.reg; - tmp = (tmp & RTC_READREQ_RCONT) >> RTC_READREQ_RCONT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_READREQ_RCONT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.READREQ.reg; - tmp &= ~RTC_READREQ_RCONT; - tmp |= value << RTC_READREQ_RCONT_Pos; - ((Rtc *)hw)->MODE2.READREQ.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_READREQ_RCONT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg &= ~RTC_READREQ_RCONT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_READREQ_RCONT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg ^= RTC_READREQ_RCONT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_READREQ_RREQ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg |= RTC_READREQ_RREQ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_READREQ_RREQ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.READREQ.reg; - tmp = (tmp & RTC_READREQ_RREQ) >> RTC_READREQ_RREQ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_READREQ_RREQ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.READREQ.reg; - tmp &= ~RTC_READREQ_RREQ; - tmp |= value << RTC_READREQ_RREQ_Pos; - ((Rtc *)hw)->MODE2.READREQ.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_READREQ_RREQ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg &= ~RTC_READREQ_RREQ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_READREQ_RREQ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg ^= RTC_READREQ_RREQ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg |= RTC_READREQ_ADDR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_get_READREQ_ADDR_bf(const void *const hw, - hri_rtcmode2_readreq_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.READREQ.reg; - tmp = (tmp & RTC_READREQ_ADDR(mask)) >> RTC_READREQ_ADDR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.READREQ.reg; - tmp &= ~RTC_READREQ_ADDR_Msk; - tmp |= RTC_READREQ_ADDR(data); - ((Rtc *)hw)->MODE2.READREQ.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg &= ~RTC_READREQ_ADDR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_READREQ_ADDR_bf(const void *const hw, hri_rtcmode2_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg ^= RTC_READREQ_ADDR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_read_READREQ_ADDR_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.READREQ.reg; - tmp = (tmp & RTC_READREQ_ADDR_Msk) >> RTC_READREQ_ADDR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_get_READREQ_reg(const void *const hw, - hri_rtcmode2_readreq_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.READREQ.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_READREQ_reg(const void *const hw, hri_rtcmode2_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.READREQ.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_readreq_reg_t hri_rtcmode2_read_READREQ_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.READREQ.reg; -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO0; - tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO1; - tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO2; - tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO3; - tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO4; - tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO5; - tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO6; - tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO7; - tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; - tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_OVFEO; - tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, - hri_rtcmode2_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.EVCTRL.reg; -} - -static inline void hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; - tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; - tmp &= ~RTC_DBGCTRL_DBGRUN; - tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; - ((Rtc *)hw)->MODE2.DBGCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_get_DBGCTRL_reg(const void *const hw, - hri_rtcmode2_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_read_DBGCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.DBGCTRL.reg; -} - -static inline void hri_rtcmode2_set_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_FREQCORR_SIGN_bit(const void *const hw) -{ - uint8_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_FREQCORR_SIGN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_SIGN; - tmp |= value << RTC_FREQCORR_SIGN_Pos; - ((Rtc *)hw)->MODE2.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_VALUE_bf(const void *const hw, - hri_rtcmode2_freqcorr_reg_t mask) -{ - uint8_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_VALUE_Msk; - tmp |= RTC_FREQCORR_VALUE(data); - ((Rtc *)hw)->MODE2.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_VALUE_bf(const void *const hw) -{ - uint8_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.FREQCORR.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_reg(const void *const hw, - hri_rtcmode2_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.FREQCORR.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.FREQCORR.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.FREQCORR.reg; -} - -static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; - tmp |= RTC_MODE2_CLOCK_SECOND(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; - tmp |= RTC_MODE2_CLOCK_MINUTE(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; - tmp |= RTC_MODE2_CLOCK_HOUR(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; - tmp |= RTC_MODE2_CLOCK_DAY(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; - tmp |= RTC_MODE2_CLOCK_MONTH(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; - tmp |= RTC_MODE2_CLOCK_YEAR(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.CLOCK.reg; -} - -static inline bool hri_rtcmode2_get_STATUS_SYNCBUSY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.STATUS.reg & RTC_STATUS_SYNCBUSY) >> RTC_STATUS_SYNCBUSY_Pos; -} - -static inline void hri_rtcmode2_clear_STATUS_SYNCBUSY_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.STATUS.reg = RTC_STATUS_SYNCBUSY; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_status_reg_t hri_rtcmode2_get_STATUS_reg(const void *const hw, - hri_rtcmode2_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_clear_STATUS_reg(const void *const hw, hri_rtcmode2_status_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.STATUS.reg = mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_status_reg_t hri_rtcmode2_read_STATUS_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.STATUS.reg; -} - -static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; -} - -static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; - } -} - -static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; -} - -static inline void hri_rtcmode0_set_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_SYNCRDY; -} - -static inline bool hri_rtcmode0_get_INTEN_SYNCRDY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_SYNCRDY) >> RTC_MODE0_INTENSET_SYNCRDY_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_SYNCRDY; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_SYNCRDY; - } -} - -static inline void hri_rtcmode0_clear_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_SYNCRDY; -} - -static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; -} - -static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; - } -} - -static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; -} - -static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = mask; -} - -static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, - hri_rtcmode0_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.INTENSET.reg; -} - -static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = data; - ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; -} - -static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode0_get_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_SYNCRDY) >> RTC_MODE0_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_SYNCRDY; -} - -static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; -} - -static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode0_get_interrupt_SYNCRDY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_SYNCRDY) >> RTC_MODE0_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_SYNCRDY; -} - -static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; -} - -static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, - hri_rtcmode0_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.INTFLAG.reg; -} - -static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; -} - -static inline void hri_rtcmode0_set_CTRL_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_SWRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRL_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp = (tmp & RTC_MODE0_CTRL_SWRST) >> RTC_MODE0_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_set_CTRL_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRL_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp = (tmp & RTC_MODE0_CTRL_ENABLE) >> RTC_MODE0_CTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp &= ~RTC_MODE0_CTRL_ENABLE; - tmp |= value << RTC_MODE0_CTRL_ENABLE_Pos; - ((Rtc *)hw)->MODE0.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRL_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRL_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRL_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRL_MATCHCLR_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp = (tmp & RTC_MODE0_CTRL_MATCHCLR) >> RTC_MODE0_CTRL_MATCHCLR_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRL_MATCHCLR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp &= ~RTC_MODE0_CTRL_MATCHCLR; - tmp |= value << RTC_MODE0_CTRL_MATCHCLR_Pos; - ((Rtc *)hw)->MODE0.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRL_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRL_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_get_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp = (tmp & RTC_MODE0_CTRL_MODE(mask)) >> RTC_MODE0_CTRL_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp &= ~RTC_MODE0_CTRL_MODE_Msk; - tmp |= RTC_MODE0_CTRL_MODE(data); - ((Rtc *)hw)->MODE0.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRL_MODE_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_read_CTRL_MODE_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp = (tmp & RTC_MODE0_CTRL_MODE_Msk) >> RTC_MODE0_CTRL_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg |= RTC_MODE0_CTRL_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_get_CTRL_PRESCALER_bf(const void *const hw, - hri_rtcmode0_ctrl_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp = (tmp & RTC_MODE0_CTRL_PRESCALER(mask)) >> RTC_MODE0_CTRL_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp &= ~RTC_MODE0_CTRL_PRESCALER_Msk; - tmp |= RTC_MODE0_CTRL_PRESCALER(data); - ((Rtc *)hw)->MODE0.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg &= ~RTC_MODE0_CTRL_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.CTRL.reg ^= RTC_MODE0_CTRL_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_read_CTRL_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp = (tmp & RTC_MODE0_CTRL_PRESCALER_Msk) >> RTC_MODE0_CTRL_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_get_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRL_reg(const void *const hw, hri_rtcmode0_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrl_reg_t hri_rtcmode0_read_CTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.CTRL.reg; -} - -static inline void hri_rtcmode0_set_READREQ_RCONT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg |= RTC_READREQ_RCONT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_READREQ_RCONT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.READREQ.reg; - tmp = (tmp & RTC_READREQ_RCONT) >> RTC_READREQ_RCONT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_READREQ_RCONT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.READREQ.reg; - tmp &= ~RTC_READREQ_RCONT; - tmp |= value << RTC_READREQ_RCONT_Pos; - ((Rtc *)hw)->MODE0.READREQ.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_READREQ_RCONT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg &= ~RTC_READREQ_RCONT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_READREQ_RCONT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg ^= RTC_READREQ_RCONT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_READREQ_RREQ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg |= RTC_READREQ_RREQ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_READREQ_RREQ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.READREQ.reg; - tmp = (tmp & RTC_READREQ_RREQ) >> RTC_READREQ_RREQ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_READREQ_RREQ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.READREQ.reg; - tmp &= ~RTC_READREQ_RREQ; - tmp |= value << RTC_READREQ_RREQ_Pos; - ((Rtc *)hw)->MODE0.READREQ.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_READREQ_RREQ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg &= ~RTC_READREQ_RREQ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_READREQ_RREQ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg ^= RTC_READREQ_RREQ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg |= RTC_READREQ_ADDR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_get_READREQ_ADDR_bf(const void *const hw, - hri_rtcmode0_readreq_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.READREQ.reg; - tmp = (tmp & RTC_READREQ_ADDR(mask)) >> RTC_READREQ_ADDR_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.READREQ.reg; - tmp &= ~RTC_READREQ_ADDR_Msk; - tmp |= RTC_READREQ_ADDR(data); - ((Rtc *)hw)->MODE0.READREQ.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg &= ~RTC_READREQ_ADDR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_READREQ_ADDR_bf(const void *const hw, hri_rtcmode0_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg ^= RTC_READREQ_ADDR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_read_READREQ_ADDR_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.READREQ.reg; - tmp = (tmp & RTC_READREQ_ADDR_Msk) >> RTC_READREQ_ADDR_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_get_READREQ_reg(const void *const hw, - hri_rtcmode0_readreq_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.READREQ.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_READREQ_reg(const void *const hw, hri_rtcmode0_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.READREQ.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_readreq_reg_t hri_rtcmode0_read_READREQ_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.READREQ.reg; -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO0; - tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO1; - tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO2; - tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO3; - tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO4; - tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO5; - tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO6; - tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO7; - tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; - tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_OVFEO; - tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, - hri_rtcmode0_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.EVCTRL.reg; -} - -static inline void hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp &= ~RTC_DBGCTRL_DBGRUN; - tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; - ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_get_DBGCTRL_reg(const void *const hw, - hri_rtcmode0_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_read_DBGCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.DBGCTRL.reg; -} - -static inline void hri_rtcmode0_set_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_FREQCORR_SIGN_bit(const void *const hw) -{ - uint8_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_FREQCORR_SIGN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_SIGN; - tmp |= value << RTC_FREQCORR_SIGN_Pos; - ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_VALUE_bf(const void *const hw, - hri_rtcmode0_freqcorr_reg_t mask) -{ - uint8_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_VALUE_Msk; - tmp |= RTC_FREQCORR_VALUE(data); - ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_VALUE_bf(const void *const hw) -{ - uint8_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_reg(const void *const hw, - hri_rtcmode0_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.FREQCORR.reg; -} - -static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, - hri_rtcmode0_count_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; - tmp |= RTC_MODE0_COUNT_COUNT(data); - ((Rtc *)hw)->MODE0.COUNT.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.COUNT.reg; -} - -static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, - hri_rtcmode0_comp_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp &= ~RTC_MODE0_COMP_COMP_Msk; - tmp |= RTC_MODE0_COMP_COMP(data); - ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw); - ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, - hri_rtcmode0_comp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE0.COMP[index].reg; -} - -static inline bool hri_rtcmode0_get_STATUS_SYNCBUSY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) >> RTC_STATUS_SYNCBUSY_Pos; -} - -static inline void hri_rtcmode0_clear_STATUS_SYNCBUSY_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.STATUS.reg = RTC_STATUS_SYNCBUSY; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_status_reg_t hri_rtcmode0_get_STATUS_reg(const void *const hw, - hri_rtcmode0_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_clear_STATUS_reg(const void *const hw, hri_rtcmode0_status_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.STATUS.reg = mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_status_reg_t hri_rtcmode0_read_STATUS_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.STATUS.reg; -} - -static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; -} - -static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; -} - -static inline void hri_rtcmode1_set_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_SYNCRDY; -} - -static inline bool hri_rtcmode1_get_INTEN_SYNCRDY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_SYNCRDY) >> RTC_MODE1_INTENSET_SYNCRDY_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_SYNCRDY; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_SYNCRDY; - } -} - -static inline void hri_rtcmode1_clear_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_SYNCRDY; -} - -static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; -} - -static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; - } -} - -static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; -} - -static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = mask; -} - -static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, - hri_rtcmode1_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.INTENSET.reg; -} - -static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = data; - ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode1_get_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_SYNCRDY) >> RTC_MODE1_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_SYNCRDY; -} - -static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode1_get_interrupt_SYNCRDY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_SYNCRDY) >> RTC_MODE1_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_SYNCRDY_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_SYNCRDY; -} - -static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; -} - -static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, - hri_rtcmode1_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.INTFLAG.reg; -} - -static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; -} - -static inline void hri_rtcmode1_set_CTRL_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_SWRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRL_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.CTRL.reg; - tmp = (tmp & RTC_MODE1_CTRL_SWRST) >> RTC_MODE1_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_set_CTRL_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRL_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.CTRL.reg; - tmp = (tmp & RTC_MODE1_CTRL_ENABLE) >> RTC_MODE1_CTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.CTRL.reg; - tmp &= ~RTC_MODE1_CTRL_ENABLE; - tmp |= value << RTC_MODE1_CTRL_ENABLE_Pos; - ((Rtc *)hw)->MODE1.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRL_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.CTRL.reg &= ~RTC_MODE1_CTRL_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRL_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.CTRL.reg ^= RTC_MODE1_CTRL_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_get_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.CTRL.reg; - tmp = (tmp & RTC_MODE1_CTRL_MODE(mask)) >> RTC_MODE1_CTRL_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.CTRL.reg; - tmp &= ~RTC_MODE1_CTRL_MODE_Msk; - tmp |= RTC_MODE1_CTRL_MODE(data); - ((Rtc *)hw)->MODE1.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.CTRL.reg &= ~RTC_MODE1_CTRL_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRL_MODE_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.CTRL.reg ^= RTC_MODE1_CTRL_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_read_CTRL_MODE_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.CTRL.reg; - tmp = (tmp & RTC_MODE1_CTRL_MODE_Msk) >> RTC_MODE1_CTRL_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.CTRL.reg |= RTC_MODE1_CTRL_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_get_CTRL_PRESCALER_bf(const void *const hw, - hri_rtcmode1_ctrl_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.CTRL.reg; - tmp = (tmp & RTC_MODE1_CTRL_PRESCALER(mask)) >> RTC_MODE1_CTRL_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.CTRL.reg; - tmp &= ~RTC_MODE1_CTRL_PRESCALER_Msk; - tmp |= RTC_MODE1_CTRL_PRESCALER(data); - ((Rtc *)hw)->MODE1.CTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.CTRL.reg &= ~RTC_MODE1_CTRL_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRL_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.CTRL.reg ^= RTC_MODE1_CTRL_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_read_CTRL_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.CTRL.reg; - tmp = (tmp & RTC_MODE1_CTRL_PRESCALER_Msk) >> RTC_MODE1_CTRL_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_get_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRL_reg(const void *const hw, hri_rtcmode1_ctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrl_reg_t hri_rtcmode1_read_CTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.CTRL.reg; -} - -static inline void hri_rtcmode1_set_READREQ_RCONT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg |= RTC_READREQ_RCONT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_READREQ_RCONT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.READREQ.reg; - tmp = (tmp & RTC_READREQ_RCONT) >> RTC_READREQ_RCONT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_READREQ_RCONT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.READREQ.reg; - tmp &= ~RTC_READREQ_RCONT; - tmp |= value << RTC_READREQ_RCONT_Pos; - ((Rtc *)hw)->MODE1.READREQ.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_READREQ_RCONT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg &= ~RTC_READREQ_RCONT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_READREQ_RCONT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg ^= RTC_READREQ_RCONT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_READREQ_RREQ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg |= RTC_READREQ_RREQ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_READREQ_RREQ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.READREQ.reg; - tmp = (tmp & RTC_READREQ_RREQ) >> RTC_READREQ_RREQ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_READREQ_RREQ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.READREQ.reg; - tmp &= ~RTC_READREQ_RREQ; - tmp |= value << RTC_READREQ_RREQ_Pos; - ((Rtc *)hw)->MODE1.READREQ.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_READREQ_RREQ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg &= ~RTC_READREQ_RREQ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_READREQ_RREQ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg ^= RTC_READREQ_RREQ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg |= RTC_READREQ_ADDR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_get_READREQ_ADDR_bf(const void *const hw, - hri_rtcmode1_readreq_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.READREQ.reg; - tmp = (tmp & RTC_READREQ_ADDR(mask)) >> RTC_READREQ_ADDR_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.READREQ.reg; - tmp &= ~RTC_READREQ_ADDR_Msk; - tmp |= RTC_READREQ_ADDR(data); - ((Rtc *)hw)->MODE1.READREQ.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg &= ~RTC_READREQ_ADDR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_READREQ_ADDR_bf(const void *const hw, hri_rtcmode1_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg ^= RTC_READREQ_ADDR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_read_READREQ_ADDR_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.READREQ.reg; - tmp = (tmp & RTC_READREQ_ADDR_Msk) >> RTC_READREQ_ADDR_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_get_READREQ_reg(const void *const hw, - hri_rtcmode1_readreq_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.READREQ.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_READREQ_reg(const void *const hw, hri_rtcmode1_readreq_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.READREQ.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_readreq_reg_t hri_rtcmode1_read_READREQ_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.READREQ.reg; -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO0; - tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO1; - tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO2; - tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO3; - tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO4; - tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO5; - tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO6; - tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO7; - tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_OVFEO; - tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, - hri_rtcmode1_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.EVCTRL.reg; -} - -static inline void hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; - tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; - tmp &= ~RTC_DBGCTRL_DBGRUN; - tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; - ((Rtc *)hw)->MODE1.DBGCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_get_DBGCTRL_reg(const void *const hw, - hri_rtcmode1_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_read_DBGCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.DBGCTRL.reg; -} - -static inline void hri_rtcmode1_set_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_FREQCORR_SIGN_bit(const void *const hw) -{ - uint8_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_FREQCORR_SIGN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_SIGN; - tmp |= value << RTC_FREQCORR_SIGN_Pos; - ((Rtc *)hw)->MODE1.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_VALUE_bf(const void *const hw, - hri_rtcmode1_freqcorr_reg_t mask) -{ - uint8_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_VALUE_Msk; - tmp |= RTC_FREQCORR_VALUE(data); - ((Rtc *)hw)->MODE1.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_VALUE_bf(const void *const hw) -{ - uint8_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.FREQCORR.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_reg(const void *const hw, - hri_rtcmode1_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.FREQCORR.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.FREQCORR.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.FREQCORR.reg; -} - -static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, - hri_rtcmode1_count_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; - tmp |= RTC_MODE1_COUNT_COUNT(data); - ((Rtc *)hw)->MODE1.COUNT.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.COUNT.reg; -} - -static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp &= ~RTC_MODE1_PER_PER_Msk; - tmp |= RTC_MODE1_PER_PER(data); - ((Rtc *)hw)->MODE1.PER.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.PER.reg; -} - -static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, - hri_rtcmode1_comp_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp &= ~RTC_MODE1_COMP_COMP_Msk; - tmp |= RTC_MODE1_COMP_COMP(data); - ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw); - ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw); - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, - hri_rtcmode1_comp_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE1.COMP[index].reg; -} - -static inline bool hri_rtcmode1_get_STATUS_SYNCBUSY_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.STATUS.reg & RTC_STATUS_SYNCBUSY) >> RTC_STATUS_SYNCBUSY_Pos; -} - -static inline void hri_rtcmode1_clear_STATUS_SYNCBUSY_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.STATUS.reg = RTC_STATUS_SYNCBUSY; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_status_reg_t hri_rtcmode1_get_STATUS_reg(const void *const hw, - hri_rtcmode1_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_clear_STATUS_reg(const void *const hw, hri_rtcmode1_status_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.STATUS.reg = mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_status_reg_t hri_rtcmode1_read_STATUS_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RTC_D21_H_INCLUDED */ -#endif /* _SAMD21_RTC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_sercom_d21.h b/atmel-samd/asf4/samd21/hri/hri_sercom_d21.h deleted file mode 100644 index 52b72b7ba..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_sercom_d21.h +++ /dev/null @@ -1,7188 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_SERCOM_COMPONENT_ -#ifndef _HRI_SERCOM_D21_H_INCLUDED_ -#define _HRI_SERCOM_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) -#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SERCOM_CRITICAL_SECTION_ENTER() -#define SERCOM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_sercomi2cm_status_reg_t; -typedef uint16_t hri_sercomi2cs_status_reg_t; -typedef uint16_t hri_sercomspi_status_reg_t; -typedef uint16_t hri_sercomusart_baud_reg_t; -typedef uint16_t hri_sercomusart_data_reg_t; -typedef uint16_t hri_sercomusart_status_reg_t; -typedef uint32_t hri_sercomi2cm_addr_reg_t; -typedef uint32_t hri_sercomi2cm_baud_reg_t; -typedef uint32_t hri_sercomi2cm_ctrla_reg_t; -typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; -typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; -typedef uint32_t hri_sercomi2cs_addr_reg_t; -typedef uint32_t hri_sercomi2cs_ctrla_reg_t; -typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; -typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; -typedef uint32_t hri_sercomspi_addr_reg_t; -typedef uint32_t hri_sercomspi_ctrla_reg_t; -typedef uint32_t hri_sercomspi_ctrlb_reg_t; -typedef uint32_t hri_sercomspi_data_reg_t; -typedef uint32_t hri_sercomspi_syncbusy_reg_t; -typedef uint32_t hri_sercomusart_ctrla_reg_t; -typedef uint32_t hri_sercomusart_ctrlb_reg_t; -typedef uint32_t hri_sercomusart_syncbusy_reg_t; -typedef uint8_t hri_sercomi2cm_data_reg_t; -typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; -typedef uint8_t hri_sercomi2cm_intenset_reg_t; -typedef uint8_t hri_sercomi2cm_intflag_reg_t; -typedef uint8_t hri_sercomi2cs_data_reg_t; -typedef uint8_t hri_sercomi2cs_intenset_reg_t; -typedef uint8_t hri_sercomi2cs_intflag_reg_t; -typedef uint8_t hri_sercomspi_baud_reg_t; -typedef uint8_t hri_sercomspi_dbgctrl_reg_t; -typedef uint8_t hri_sercomspi_intenset_reg_t; -typedef uint8_t hri_sercomspi_intflag_reg_t; -typedef uint8_t hri_sercomusart_dbgctrl_reg_t; -typedef uint8_t hri_sercomusart_intenset_reg_t; -typedef uint8_t hri_sercomusart_intflag_reg_t; -typedef uint8_t hri_sercomusart_rxpl_reg_t; - -static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; -} - -static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; -} - -static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; - } -} - -static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; -} - -static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; -} - -static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; -} - -static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; - } -} - -static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; -} - -static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; -} - -static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; -} - -static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; - } -} - -static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; -} - -static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; -} - -static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; -} - -static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; - } -} - -static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; -} - -static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; -} - -static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; - } -} - -static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; -} - -static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = mask; -} - -static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, - hri_sercomspi_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.INTENSET.reg; -} - -static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = data; - ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; -} - -static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = mask; -} - -static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; -} - -static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; -} - -static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; -} - -static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; -} - -static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; -} - -static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; -} - -static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; -} - -static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; -} - -static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; -} - -static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; -} - -static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, - hri_sercomspi_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.INTFLAG.reg; -} - -static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = mask; -} - -static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_ENABLE; - tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_IBON; - tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_CPHA; - tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_CPOL; - tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DORD; - tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; - tmp |= SERCOM_SPI_CTRLA_MODE(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; - tmp |= SERCOM_SPI_CTRLA_DOPO(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; - tmp |= SERCOM_SPI_CTRLA_DIPO(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; - tmp |= SERCOM_SPI_CTRLA_FORM(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.CTRLA.reg; -} - -static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; - tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_SSDE; - tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_MSSEN; - tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_RXEN; - tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; - tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; - tmp |= SERCOM_SPI_CTRLB_AMODE(data); - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.CTRLB.reg; -} - -static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomspi_baud_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; - tmp |= SERCOM_SPI_BAUD_BAUD(data); - ((Sercom *)hw)->SPI.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.BAUD.reg; -} - -static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; - tmp |= SERCOM_SPI_ADDR_ADDR(data); - ((Sercom *)hw)->SPI.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, - hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; - tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); - ((Sercom *)hw)->SPI.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.ADDR.reg; -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.DATA.reg; -} - -static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, - hri_sercomspi_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.DBGCTRL.reg; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; -} - -static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, - hri_sercomspi_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.SYNCBUSY.reg; -} - -static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; -} - -static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, - hri_sercomspi_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.STATUS.reg; -} - -static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; -} - -static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; -} - -static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; -} - -static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; -} - -static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; -} - -static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; -} - -static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = mask; -} - -static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, - hri_sercomi2cm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.INTENSET.reg; -} - -static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = data; - ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; -} - -static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; -} - -static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; -} - -static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; -} - -static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; -} - -static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, - hri_sercomi2cm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.INTFLAG.reg; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; -} - -static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_BUSERR; - tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; - tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_RXNACK; - tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; - tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; - tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; - tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; - tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_LENERR; - tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, - hri_sercomi2cm_status_reg_t mask) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; -} - -static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; - tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, - hri_sercomi2cm_status_reg_t mask) -{ - uint16_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg |= mask; -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.STATUS.reg; -} - -static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg = data; -} - -static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; -} - -static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; - tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; - tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; - tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; - tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; - tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; - tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; - tmp |= SERCOM_I2CM_CTRLA_MODE(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; - tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; - tmp |= SERCOM_I2CM_CTRLA_SPEED(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; - tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.CTRLA.reg; -} - -static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_SMEN; - tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_QCEN; - tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; - tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, - hri_sercomi2cm_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; - tmp |= SERCOM_I2CM_CTRLB_CMD(data); - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, - hri_sercomi2cm_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.CTRLB.reg; -} - -static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; - tmp |= SERCOM_I2CM_BAUD_BAUD(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; - tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; - tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; - tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.BAUD.reg; -} - -static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_LENEN; - tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_HS; - tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; - tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; - tmp |= SERCOM_I2CM_ADDR_ADDR(data); - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; - tmp |= SERCOM_I2CM_ADDR_LEN(data); - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.ADDR.reg; -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.DATA.reg; -} - -static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, - hri_sercomi2cm_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.DBGCTRL.reg; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; -} - -static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, - hri_sercomi2cm_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; -} - -static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD(mask)) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRAC_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_FRAC_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD_Msk) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; - tmp |= SERCOM_USART_BAUD_FRAC_FP(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD(mask)) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRACFP_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_FRACFP_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD_Msk) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; - tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_USARTFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD(mask)) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_USARTFP_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_USARTFP_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_USARTFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_USARTFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD_Msk) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.BAUD.reg; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_reg(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.BAUD.reg; -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_reg(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.BAUD.reg; -} - -static inline void hri_sercomusart_set_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_reg(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.BAUD.reg; -} - -static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; -} - -static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; -} - -static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; - } -} - -static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; -} - -static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; -} - -static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; - } -} - -static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; -} - -static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; -} - -static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; -} - -static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; -} - -static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; -} - -static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; -} - -static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; - } -} - -static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; -} - -static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; -} - -static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; -} - -static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; -} - -static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; - } -} - -static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; -} - -static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) -{ - ((Sercom *)hw)->USART.INTENSET.reg = mask; -} - -static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, - hri_sercomusart_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.INTENSET.reg; -} - -static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) -{ - ((Sercom *)hw)->USART.INTENSET.reg = data; - ((Sercom *)hw)->USART.INTENCLR.reg = ~data; -} - -static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = mask; -} - -static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; -} - -static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; -} - -static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; -} - -static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; -} - -static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; -} - -static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; -} - -static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; -} - -static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; -} - -static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; -} - -static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; -} - -static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; -} - -static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, - hri_sercomusart_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.INTFLAG.reg; -} - -static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = mask; -} - -static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_ENABLE; - tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_IBON; - tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_CMODE; - tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_CPOL; - tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_DORD; - tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; - tmp |= SERCOM_USART_CTRLA_MODE(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; - tmp |= SERCOM_USART_CTRLA_SAMPR(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; - tmp |= SERCOM_USART_CTRLA_TXPO(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; - tmp |= SERCOM_USART_CTRLA_RXPO(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; - tmp |= SERCOM_USART_CTRLA_SAMPA(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; - tmp |= SERCOM_USART_CTRLA_FORM(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.CTRLA.reg; -} - -static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_SBMODE; - tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_COLDEN; - tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_SFDE; - tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_ENC; - tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_PMODE; - tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_TXEN; - tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_RXEN; - tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; - tmp |= SERCOM_USART_CTRLB_CHSIZE(data); - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.CTRLB.reg; -} - -static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, - hri_sercomusart_rxpl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; - tmp |= SERCOM_USART_RXPL_RXPL(data); - ((Sercom *)hw)->USART.RXPL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, - hri_sercomusart_rxpl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.RXPL.reg; -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.DATA.reg; -} - -static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, - hri_sercomusart_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.DBGCTRL.reg; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; -} - -static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, - hri_sercomusart_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.SYNCBUSY.reg; -} - -static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, - hri_sercomusart_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.STATUS.reg; -} - -static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; -} - -static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; -} - -static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; -} - -static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; -} - -static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; -} - -static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; -} - -static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; -} - -static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; -} - -static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = mask; -} - -static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, - hri_sercomi2cs_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.INTENSET.reg; -} - -static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = data; - ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; -} - -static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; -} - -static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; -} - -static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -} - -static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; -} - -static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; -} - -static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, - hri_sercomi2cs_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.INTFLAG.reg; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; -} - -static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; - tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; - tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; - tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; - tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; - tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; - tmp |= SERCOM_I2CS_CTRLA_MODE(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; - tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; - tmp |= SERCOM_I2CS_CTRLA_SPEED(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.CTRLA.reg; -} - -static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_SMEN; - tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_GCMD; - tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; - tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; - tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; - tmp |= SERCOM_I2CS_CTRLB_AMODE(data); - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; - tmp |= SERCOM_I2CS_CTRLB_CMD(data); - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.CTRLB.reg; -} - -static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_GENCEN; - tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; - tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; - tmp |= SERCOM_I2CS_ADDR_ADDR(data); - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; - tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.ADDR.reg; -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.DATA.reg; -} - -static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, - hri_sercomi2cs_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; -} - -static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, - hri_sercomi2cs_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SERCOM_D21_H_INCLUDED */ -#endif /* _SAMD21_SERCOM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_sysctrl_d21.h b/atmel-samd/asf4/samd21/hri/hri_sysctrl_d21.h deleted file mode 100644 index 879a2f939..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_sysctrl_d21.h +++ /dev/null @@ -1,4760 +0,0 @@ -/** - * \file - * - * \brief SAM SYSCTRL - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_SYSCTRL_COMPONENT_ -#ifndef _HRI_SYSCTRL_D21_H_INCLUDED_ -#define _HRI_SYSCTRL_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SYSCTRL_CRITICAL_SECTIONS) -#define SYSCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SYSCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SYSCTRL_CRITICAL_SECTION_ENTER() -#define SYSCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_sysctrl_dfllctrl_reg_t; -typedef uint16_t hri_sysctrl_vreg_reg_t; -typedef uint16_t hri_sysctrl_xosc32k_reg_t; -typedef uint16_t hri_sysctrl_xosc_reg_t; -typedef uint32_t hri_sysctrl_bod33_reg_t; -typedef uint32_t hri_sysctrl_dfllmul_reg_t; -typedef uint32_t hri_sysctrl_dfllval_reg_t; -typedef uint32_t hri_sysctrl_dpllctrlb_reg_t; -typedef uint32_t hri_sysctrl_dpllratio_reg_t; -typedef uint32_t hri_sysctrl_intenset_reg_t; -typedef uint32_t hri_sysctrl_intflag_reg_t; -typedef uint32_t hri_sysctrl_osc32k_reg_t; -typedef uint32_t hri_sysctrl_osc8m_reg_t; -typedef uint32_t hri_sysctrl_pclksr_reg_t; -typedef uint32_t hri_sysctrl_vref_reg_t; -typedef uint8_t hri_sysctrl_dfllsync_reg_t; -typedef uint8_t hri_sysctrl_dpllctrla_reg_t; -typedef uint8_t hri_sysctrl_dpllstatus_reg_t; -typedef uint8_t hri_sysctrl_osculp32k_reg_t; - -static inline void hri_sysctrl_set_INTEN_XOSCRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSCRDY; -} - -static inline bool hri_sysctrl_get_INTEN_XOSCRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_XOSCRDY) >> SYSCTRL_INTENSET_XOSCRDY_Pos; -} - -static inline void hri_sysctrl_write_INTEN_XOSCRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSCRDY; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSCRDY; - } -} - -static inline void hri_sysctrl_clear_INTEN_XOSCRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSCRDY; -} - -static inline void hri_sysctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSC32KRDY; -} - -static inline bool hri_sysctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_XOSC32KRDY) >> SYSCTRL_INTENSET_XOSC32KRDY_Pos; -} - -static inline void hri_sysctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSC32KRDY; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_XOSC32KRDY; - } -} - -static inline void hri_sysctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_XOSC32KRDY; -} - -static inline void hri_sysctrl_set_INTEN_OSC32KRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC32KRDY; -} - -static inline bool hri_sysctrl_get_INTEN_OSC32KRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_OSC32KRDY) >> SYSCTRL_INTENSET_OSC32KRDY_Pos; -} - -static inline void hri_sysctrl_write_INTEN_OSC32KRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC32KRDY; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC32KRDY; - } -} - -static inline void hri_sysctrl_clear_INTEN_OSC32KRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC32KRDY; -} - -static inline void hri_sysctrl_set_INTEN_OSC8MRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC8MRDY; -} - -static inline bool hri_sysctrl_get_INTEN_OSC8MRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_OSC8MRDY) >> SYSCTRL_INTENSET_OSC8MRDY_Pos; -} - -static inline void hri_sysctrl_write_INTEN_OSC8MRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC8MRDY; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_OSC8MRDY; - } -} - -static inline void hri_sysctrl_clear_INTEN_OSC8MRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_OSC8MRDY; -} - -static inline void hri_sysctrl_set_INTEN_DFLLRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRDY; -} - -static inline bool hri_sysctrl_get_INTEN_DFLLRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLRDY) >> SYSCTRL_INTENSET_DFLLRDY_Pos; -} - -static inline void hri_sysctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRDY; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRDY; - } -} - -static inline void hri_sysctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRDY; -} - -static inline void hri_sysctrl_set_INTEN_DFLLOOB_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLOOB; -} - -static inline bool hri_sysctrl_get_INTEN_DFLLOOB_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLOOB) >> SYSCTRL_INTENSET_DFLLOOB_Pos; -} - -static inline void hri_sysctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLOOB; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLOOB; - } -} - -static inline void hri_sysctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLOOB; -} - -static inline void hri_sysctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKF; -} - -static inline bool hri_sysctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLLCKF) >> SYSCTRL_INTENSET_DFLLLCKF_Pos; -} - -static inline void hri_sysctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKF; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKF; - } -} - -static inline void hri_sysctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKF; -} - -static inline void hri_sysctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKC; -} - -static inline bool hri_sysctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLLCKC) >> SYSCTRL_INTENSET_DFLLLCKC_Pos; -} - -static inline void hri_sysctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKC; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLLCKC; - } -} - -static inline void hri_sysctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLLCKC; -} - -static inline void hri_sysctrl_set_INTEN_DFLLRCS_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRCS; -} - -static inline bool hri_sysctrl_get_INTEN_DFLLRCS_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DFLLRCS) >> SYSCTRL_INTENSET_DFLLRCS_Pos; -} - -static inline void hri_sysctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRCS; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DFLLRCS; - } -} - -static inline void hri_sysctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DFLLRCS; -} - -static inline void hri_sysctrl_set_INTEN_BOD33RDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33RDY; -} - -static inline bool hri_sysctrl_get_INTEN_BOD33RDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_BOD33RDY) >> SYSCTRL_INTENSET_BOD33RDY_Pos; -} - -static inline void hri_sysctrl_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33RDY; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33RDY; - } -} - -static inline void hri_sysctrl_clear_INTEN_BOD33RDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33RDY; -} - -static inline void hri_sysctrl_set_INTEN_BOD33DET_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33DET; -} - -static inline bool hri_sysctrl_get_INTEN_BOD33DET_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_BOD33DET) >> SYSCTRL_INTENSET_BOD33DET_Pos; -} - -static inline void hri_sysctrl_write_INTEN_BOD33DET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33DET; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_BOD33DET; - } -} - -static inline void hri_sysctrl_clear_INTEN_BOD33DET_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_BOD33DET; -} - -static inline void hri_sysctrl_set_INTEN_B33SRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_B33SRDY; -} - -static inline bool hri_sysctrl_get_INTEN_B33SRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_B33SRDY) >> SYSCTRL_INTENSET_B33SRDY_Pos; -} - -static inline void hri_sysctrl_write_INTEN_B33SRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_B33SRDY; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_B33SRDY; - } -} - -static inline void hri_sysctrl_clear_INTEN_B33SRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_B33SRDY; -} - -static inline void hri_sysctrl_set_INTEN_DPLLLCKR_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKR; -} - -static inline bool hri_sysctrl_get_INTEN_DPLLLCKR_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DPLLLCKR) >> SYSCTRL_INTENSET_DPLLLCKR_Pos; -} - -static inline void hri_sysctrl_write_INTEN_DPLLLCKR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKR; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKR; - } -} - -static inline void hri_sysctrl_clear_INTEN_DPLLLCKR_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKR; -} - -static inline void hri_sysctrl_set_INTEN_DPLLLCKF_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKF; -} - -static inline bool hri_sysctrl_get_INTEN_DPLLLCKF_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DPLLLCKF) >> SYSCTRL_INTENSET_DPLLLCKF_Pos; -} - -static inline void hri_sysctrl_write_INTEN_DPLLLCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKF; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLCKF; - } -} - -static inline void hri_sysctrl_clear_INTEN_DPLLLCKF_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLCKF; -} - -static inline void hri_sysctrl_set_INTEN_DPLLLTO_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLTO; -} - -static inline bool hri_sysctrl_get_INTEN_DPLLLTO_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTENSET.reg & SYSCTRL_INTENSET_DPLLLTO) >> SYSCTRL_INTENSET_DPLLLTO_Pos; -} - -static inline void hri_sysctrl_write_INTEN_DPLLLTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLTO; - } else { - ((Sysctrl *)hw)->INTENSET.reg = SYSCTRL_INTENSET_DPLLLTO; - } -} - -static inline void hri_sysctrl_clear_INTEN_DPLLLTO_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTENCLR.reg = SYSCTRL_INTENSET_DPLLLTO; -} - -static inline void hri_sysctrl_set_INTEN_reg(const void *const hw, hri_sysctrl_intenset_reg_t mask) -{ - ((Sysctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_sysctrl_intenset_reg_t hri_sysctrl_get_INTEN_reg(const void *const hw, - hri_sysctrl_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sysctrl_intenset_reg_t hri_sysctrl_read_INTEN_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->INTENSET.reg; -} - -static inline void hri_sysctrl_write_INTEN_reg(const void *const hw, hri_sysctrl_intenset_reg_t data) -{ - ((Sysctrl *)hw)->INTENSET.reg = data; - ((Sysctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_sysctrl_clear_INTEN_reg(const void *const hw, hri_sysctrl_intenset_reg_t mask) -{ - ((Sysctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_sysctrl_get_INTFLAG_XOSCRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSCRDY) >> SYSCTRL_INTFLAG_XOSCRDY_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_XOSCRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSCRDY; -} - -static inline bool hri_sysctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSC32KRDY) >> SYSCTRL_INTFLAG_XOSC32KRDY_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSC32KRDY; -} - -static inline bool hri_sysctrl_get_INTFLAG_OSC32KRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC32KRDY) >> SYSCTRL_INTFLAG_OSC32KRDY_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_OSC32KRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC32KRDY; -} - -static inline bool hri_sysctrl_get_INTFLAG_OSC8MRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC8MRDY) >> SYSCTRL_INTFLAG_OSC8MRDY_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_OSC8MRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC8MRDY; -} - -static inline bool hri_sysctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRDY) >> SYSCTRL_INTFLAG_DFLLRDY_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRDY; -} - -static inline bool hri_sysctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLOOB) >> SYSCTRL_INTFLAG_DFLLOOB_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLOOB; -} - -static inline bool hri_sysctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKF) >> SYSCTRL_INTFLAG_DFLLLCKF_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKF; -} - -static inline bool hri_sysctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKC) >> SYSCTRL_INTFLAG_DFLLLCKC_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKC; -} - -static inline bool hri_sysctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRCS) >> SYSCTRL_INTFLAG_DFLLRCS_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRCS; -} - -static inline bool hri_sysctrl_get_INTFLAG_BOD33RDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33RDY) >> SYSCTRL_INTFLAG_BOD33RDY_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_BOD33RDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY; -} - -static inline bool hri_sysctrl_get_INTFLAG_BOD33DET_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33DET) >> SYSCTRL_INTFLAG_BOD33DET_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_BOD33DET_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33DET; -} - -static inline bool hri_sysctrl_get_INTFLAG_B33SRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_B33SRDY) >> SYSCTRL_INTFLAG_B33SRDY_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_B33SRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_B33SRDY; -} - -static inline bool hri_sysctrl_get_INTFLAG_DPLLLCKR_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKR) >> SYSCTRL_INTFLAG_DPLLLCKR_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_DPLLLCKR_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKR; -} - -static inline bool hri_sysctrl_get_INTFLAG_DPLLLCKF_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKF) >> SYSCTRL_INTFLAG_DPLLLCKF_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_DPLLLCKF_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKF; -} - -static inline bool hri_sysctrl_get_INTFLAG_DPLLLTO_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLTO) >> SYSCTRL_INTFLAG_DPLLLTO_Pos; -} - -static inline void hri_sysctrl_clear_INTFLAG_DPLLLTO_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLTO; -} - -static inline bool hri_sysctrl_get_interrupt_XOSCRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSCRDY) >> SYSCTRL_INTFLAG_XOSCRDY_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_XOSCRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSCRDY; -} - -static inline bool hri_sysctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_XOSC32KRDY) >> SYSCTRL_INTFLAG_XOSC32KRDY_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_XOSC32KRDY; -} - -static inline bool hri_sysctrl_get_interrupt_OSC32KRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC32KRDY) >> SYSCTRL_INTFLAG_OSC32KRDY_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_OSC32KRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC32KRDY; -} - -static inline bool hri_sysctrl_get_interrupt_OSC8MRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_OSC8MRDY) >> SYSCTRL_INTFLAG_OSC8MRDY_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_OSC8MRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_OSC8MRDY; -} - -static inline bool hri_sysctrl_get_interrupt_DFLLRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRDY) >> SYSCTRL_INTFLAG_DFLLRDY_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRDY; -} - -static inline bool hri_sysctrl_get_interrupt_DFLLOOB_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLOOB) >> SYSCTRL_INTFLAG_DFLLOOB_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLOOB; -} - -static inline bool hri_sysctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKF) >> SYSCTRL_INTFLAG_DFLLLCKF_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKF; -} - -static inline bool hri_sysctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLLCKC) >> SYSCTRL_INTFLAG_DFLLLCKC_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLLCKC; -} - -static inline bool hri_sysctrl_get_interrupt_DFLLRCS_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DFLLRCS) >> SYSCTRL_INTFLAG_DFLLRCS_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DFLLRCS; -} - -static inline bool hri_sysctrl_get_interrupt_BOD33RDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33RDY) >> SYSCTRL_INTFLAG_BOD33RDY_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_BOD33RDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33RDY; -} - -static inline bool hri_sysctrl_get_interrupt_BOD33DET_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_BOD33DET) >> SYSCTRL_INTFLAG_BOD33DET_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_BOD33DET_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_BOD33DET; -} - -static inline bool hri_sysctrl_get_interrupt_B33SRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_B33SRDY) >> SYSCTRL_INTFLAG_B33SRDY_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_B33SRDY_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_B33SRDY; -} - -static inline bool hri_sysctrl_get_interrupt_DPLLLCKR_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKR) >> SYSCTRL_INTFLAG_DPLLLCKR_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_DPLLLCKR_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKR; -} - -static inline bool hri_sysctrl_get_interrupt_DPLLLCKF_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLCKF) >> SYSCTRL_INTFLAG_DPLLLCKF_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_DPLLLCKF_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLCKF; -} - -static inline bool hri_sysctrl_get_interrupt_DPLLLTO_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->INTFLAG.reg & SYSCTRL_INTFLAG_DPLLLTO) >> SYSCTRL_INTFLAG_DPLLLTO_Pos; -} - -static inline void hri_sysctrl_clear_interrupt_DPLLLTO_bit(const void *const hw) -{ - ((Sysctrl *)hw)->INTFLAG.reg = SYSCTRL_INTFLAG_DPLLLTO; -} - -static inline hri_sysctrl_intflag_reg_t hri_sysctrl_get_INTFLAG_reg(const void *const hw, - hri_sysctrl_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sysctrl_intflag_reg_t hri_sysctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_sysctrl_clear_INTFLAG_reg(const void *const hw, hri_sysctrl_intflag_reg_t mask) -{ - ((Sysctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_sysctrl_set_XOSC_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp = (tmp & SYSCTRL_XOSC_ENABLE) >> SYSCTRL_XOSC_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp &= ~SYSCTRL_XOSC_ENABLE; - tmp |= value << SYSCTRL_XOSC_ENABLE_Pos; - ((Sysctrl *)hw)->XOSC.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC_XTALEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_XTALEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC_XTALEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp = (tmp & SYSCTRL_XOSC_XTALEN) >> SYSCTRL_XOSC_XTALEN_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC_XTALEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp &= ~SYSCTRL_XOSC_XTALEN; - tmp |= value << SYSCTRL_XOSC_XTALEN_Pos; - ((Sysctrl *)hw)->XOSC.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC_XTALEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_XTALEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC_XTALEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_XTALEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp = (tmp & SYSCTRL_XOSC_RUNSTDBY) >> SYSCTRL_XOSC_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp &= ~SYSCTRL_XOSC_RUNSTDBY; - tmp |= value << SYSCTRL_XOSC_RUNSTDBY_Pos; - ((Sysctrl *)hw)->XOSC.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp = (tmp & SYSCTRL_XOSC_ONDEMAND) >> SYSCTRL_XOSC_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp &= ~SYSCTRL_XOSC_ONDEMAND; - tmp |= value << SYSCTRL_XOSC_ONDEMAND_Pos; - ((Sysctrl *)hw)->XOSC.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC_AMPGC_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_AMPGC; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC_AMPGC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp = (tmp & SYSCTRL_XOSC_AMPGC) >> SYSCTRL_XOSC_AMPGC_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC_AMPGC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp &= ~SYSCTRL_XOSC_AMPGC; - tmp |= value << SYSCTRL_XOSC_AMPGC_Pos; - ((Sysctrl *)hw)->XOSC.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC_AMPGC_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_AMPGC; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC_AMPGC_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_AMPGC; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_GAIN(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_xosc_reg_t hri_sysctrl_get_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp = (tmp & SYSCTRL_XOSC_GAIN(mask)) >> SYSCTRL_XOSC_GAIN_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t data) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp &= ~SYSCTRL_XOSC_GAIN_Msk; - tmp |= SYSCTRL_XOSC_GAIN(data); - ((Sysctrl *)hw)->XOSC.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_GAIN(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC_GAIN_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_GAIN(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_xosc_reg_t hri_sysctrl_read_XOSC_GAIN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp = (tmp & SYSCTRL_XOSC_GAIN_Msk) >> SYSCTRL_XOSC_GAIN_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg |= SYSCTRL_XOSC_STARTUP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_xosc_reg_t hri_sysctrl_get_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp = (tmp & SYSCTRL_XOSC_STARTUP(mask)) >> SYSCTRL_XOSC_STARTUP_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t data) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp &= ~SYSCTRL_XOSC_STARTUP_Msk; - tmp |= SYSCTRL_XOSC_STARTUP(data); - ((Sysctrl *)hw)->XOSC.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg &= ~SYSCTRL_XOSC_STARTUP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC_STARTUP_bf(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg ^= SYSCTRL_XOSC_STARTUP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_xosc_reg_t hri_sysctrl_read_XOSC_STARTUP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp = (tmp & SYSCTRL_XOSC_STARTUP_Msk) >> SYSCTRL_XOSC_STARTUP_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_xosc_reg_t hri_sysctrl_get_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC_reg(const void *const hw, hri_sysctrl_xosc_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_xosc_reg_t hri_sysctrl_read_XOSC_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->XOSC.reg; -} - -static inline void hri_sysctrl_set_XOSC32K_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC32K_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp = (tmp & SYSCTRL_XOSC32K_ENABLE) >> SYSCTRL_XOSC32K_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp &= ~SYSCTRL_XOSC32K_ENABLE; - tmp |= value << SYSCTRL_XOSC32K_ENABLE_Pos; - ((Sysctrl *)hw)->XOSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC32K_XTALEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_XTALEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC32K_XTALEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp = (tmp & SYSCTRL_XOSC32K_XTALEN) >> SYSCTRL_XOSC32K_XTALEN_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp &= ~SYSCTRL_XOSC32K_XTALEN; - tmp |= value << SYSCTRL_XOSC32K_XTALEN_Pos; - ((Sysctrl *)hw)->XOSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_XTALEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_XTALEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC32K_EN32K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_EN32K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC32K_EN32K_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp = (tmp & SYSCTRL_XOSC32K_EN32K) >> SYSCTRL_XOSC32K_EN32K_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp &= ~SYSCTRL_XOSC32K_EN32K; - tmp |= value << SYSCTRL_XOSC32K_EN32K_Pos; - ((Sysctrl *)hw)->XOSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC32K_EN32K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_EN32K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_EN32K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC32K_EN1K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_EN1K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC32K_EN1K_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp = (tmp & SYSCTRL_XOSC32K_EN1K) >> SYSCTRL_XOSC32K_EN1K_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp &= ~SYSCTRL_XOSC32K_EN1K; - tmp |= value << SYSCTRL_XOSC32K_EN1K_Pos; - ((Sysctrl *)hw)->XOSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC32K_EN1K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_EN1K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_EN1K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC32K_AAMPEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_AAMPEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC32K_AAMPEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp = (tmp & SYSCTRL_XOSC32K_AAMPEN) >> SYSCTRL_XOSC32K_AAMPEN_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC32K_AAMPEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp &= ~SYSCTRL_XOSC32K_AAMPEN; - tmp |= value << SYSCTRL_XOSC32K_AAMPEN_Pos; - ((Sysctrl *)hw)->XOSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC32K_AAMPEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_AAMPEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC32K_AAMPEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_AAMPEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp = (tmp & SYSCTRL_XOSC32K_RUNSTDBY) >> SYSCTRL_XOSC32K_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp &= ~SYSCTRL_XOSC32K_RUNSTDBY; - tmp |= value << SYSCTRL_XOSC32K_RUNSTDBY_Pos; - ((Sysctrl *)hw)->XOSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp = (tmp & SYSCTRL_XOSC32K_ONDEMAND) >> SYSCTRL_XOSC32K_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp &= ~SYSCTRL_XOSC32K_ONDEMAND; - tmp |= value << SYSCTRL_XOSC32K_ONDEMAND_Pos; - ((Sysctrl *)hw)->XOSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_WRTLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp = (tmp & SYSCTRL_XOSC32K_WRTLOCK) >> SYSCTRL_XOSC32K_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp &= ~SYSCTRL_XOSC32K_WRTLOCK; - tmp |= value << SYSCTRL_XOSC32K_WRTLOCK_Pos; - ((Sysctrl *)hw)->XOSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_WRTLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_WRTLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg |= SYSCTRL_XOSC32K_STARTUP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_get_XOSC32K_STARTUP_bf(const void *const hw, - hri_sysctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp = (tmp & SYSCTRL_XOSC32K_STARTUP(mask)) >> SYSCTRL_XOSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t data) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp &= ~SYSCTRL_XOSC32K_STARTUP_Msk; - tmp |= SYSCTRL_XOSC32K_STARTUP(data); - ((Sysctrl *)hw)->XOSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg &= ~SYSCTRL_XOSC32K_STARTUP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg ^= SYSCTRL_XOSC32K_STARTUP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_read_XOSC32K_STARTUP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp = (tmp & SYSCTRL_XOSC32K_STARTUP_Msk) >> SYSCTRL_XOSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_get_XOSC32K_reg(const void *const hw, - hri_sysctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->XOSC32K.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_XOSC32K_reg(const void *const hw, hri_sysctrl_xosc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->XOSC32K.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_xosc32k_reg_t hri_sysctrl_read_XOSC32K_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->XOSC32K.reg; -} - -static inline void hri_sysctrl_set_OSC32K_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_OSC32K_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp = (tmp & SYSCTRL_OSC32K_ENABLE) >> SYSCTRL_OSC32K_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_OSC32K_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp &= ~SYSCTRL_OSC32K_ENABLE; - tmp |= value << SYSCTRL_OSC32K_ENABLE_Pos; - ((Sysctrl *)hw)->OSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC32K_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC32K_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_OSC32K_EN32K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_EN32K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_OSC32K_EN32K_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp = (tmp & SYSCTRL_OSC32K_EN32K) >> SYSCTRL_OSC32K_EN32K_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_OSC32K_EN32K_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp &= ~SYSCTRL_OSC32K_EN32K; - tmp |= value << SYSCTRL_OSC32K_EN32K_Pos; - ((Sysctrl *)hw)->OSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC32K_EN32K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_EN32K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC32K_EN32K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_EN32K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_OSC32K_EN1K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_EN1K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_OSC32K_EN1K_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp = (tmp & SYSCTRL_OSC32K_EN1K) >> SYSCTRL_OSC32K_EN1K_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_OSC32K_EN1K_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp &= ~SYSCTRL_OSC32K_EN1K; - tmp |= value << SYSCTRL_OSC32K_EN1K_Pos; - ((Sysctrl *)hw)->OSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC32K_EN1K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_EN1K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC32K_EN1K_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_EN1K; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_OSC32K_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_OSC32K_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp = (tmp & SYSCTRL_OSC32K_RUNSTDBY) >> SYSCTRL_OSC32K_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_OSC32K_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp &= ~SYSCTRL_OSC32K_RUNSTDBY; - tmp |= value << SYSCTRL_OSC32K_RUNSTDBY_Pos; - ((Sysctrl *)hw)->OSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC32K_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC32K_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_OSC32K_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_OSC32K_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp = (tmp & SYSCTRL_OSC32K_ONDEMAND) >> SYSCTRL_OSC32K_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_OSC32K_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp &= ~SYSCTRL_OSC32K_ONDEMAND; - tmp |= value << SYSCTRL_OSC32K_ONDEMAND_Pos; - ((Sysctrl *)hw)->OSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC32K_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC32K_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_OSC32K_WRTLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_WRTLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_OSC32K_WRTLOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp = (tmp & SYSCTRL_OSC32K_WRTLOCK) >> SYSCTRL_OSC32K_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_OSC32K_WRTLOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp &= ~SYSCTRL_OSC32K_WRTLOCK; - tmp |= value << SYSCTRL_OSC32K_WRTLOCK_Pos; - ((Sysctrl *)hw)->OSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC32K_WRTLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_WRTLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC32K_WRTLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_WRTLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_STARTUP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_get_OSC32K_STARTUP_bf(const void *const hw, - hri_sysctrl_osc32k_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp = (tmp & SYSCTRL_OSC32K_STARTUP(mask)) >> SYSCTRL_OSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp &= ~SYSCTRL_OSC32K_STARTUP_Msk; - tmp |= SYSCTRL_OSC32K_STARTUP(data); - ((Sysctrl *)hw)->OSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_STARTUP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC32K_STARTUP_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_STARTUP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_read_OSC32K_STARTUP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp = (tmp & SYSCTRL_OSC32K_STARTUP_Msk) >> SYSCTRL_OSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg |= SYSCTRL_OSC32K_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_get_OSC32K_CALIB_bf(const void *const hw, - hri_sysctrl_osc32k_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp = (tmp & SYSCTRL_OSC32K_CALIB(mask)) >> SYSCTRL_OSC32K_CALIB_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp &= ~SYSCTRL_OSC32K_CALIB_Msk; - tmp |= SYSCTRL_OSC32K_CALIB(data); - ((Sysctrl *)hw)->OSC32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg &= ~SYSCTRL_OSC32K_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC32K_CALIB_bf(const void *const hw, hri_sysctrl_osc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg ^= SYSCTRL_OSC32K_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_read_OSC32K_CALIB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp = (tmp & SYSCTRL_OSC32K_CALIB_Msk) >> SYSCTRL_OSC32K_CALIB_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_get_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC32K.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC32K_reg(const void *const hw, hri_sysctrl_osc32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC32K.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc32k_reg_t hri_sysctrl_read_OSC32K_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->OSC32K.reg; -} - -static inline void hri_sysctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSCULP32K.reg |= SYSCTRL_OSCULP32K_WRTLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sysctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & SYSCTRL_OSCULP32K_WRTLOCK) >> SYSCTRL_OSCULP32K_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSCULP32K.reg; - tmp &= ~SYSCTRL_OSCULP32K_WRTLOCK; - tmp |= value << SYSCTRL_OSCULP32K_WRTLOCK_Pos; - ((Sysctrl *)hw)->OSCULP32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSCULP32K.reg &= ~SYSCTRL_OSCULP32K_WRTLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSCULP32K.reg ^= SYSCTRL_OSCULP32K_WRTLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSCULP32K.reg |= SYSCTRL_OSCULP32K_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_get_OSCULP32K_CALIB_bf(const void *const hw, - hri_sysctrl_osculp32k_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sysctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & SYSCTRL_OSCULP32K_CALIB(mask)) >> SYSCTRL_OSCULP32K_CALIB_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t data) -{ - uint8_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSCULP32K.reg; - tmp &= ~SYSCTRL_OSCULP32K_CALIB_Msk; - tmp |= SYSCTRL_OSCULP32K_CALIB(data); - ((Sysctrl *)hw)->OSCULP32K.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSCULP32K.reg &= ~SYSCTRL_OSCULP32K_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSCULP32K.reg ^= SYSCTRL_OSCULP32K_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_read_OSCULP32K_CALIB_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sysctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & SYSCTRL_OSCULP32K_CALIB_Msk) >> SYSCTRL_OSCULP32K_CALIB_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSCULP32K.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_get_OSCULP32K_reg(const void *const hw, - hri_sysctrl_osculp32k_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sysctrl *)hw)->OSCULP32K.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSCULP32K.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSCULP32K.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSCULP32K_reg(const void *const hw, hri_sysctrl_osculp32k_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSCULP32K.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osculp32k_reg_t hri_sysctrl_read_OSCULP32K_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->OSCULP32K.reg; -} - -static inline void hri_sysctrl_set_OSC8M_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_OSC8M_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp = (tmp & SYSCTRL_OSC8M_ENABLE) >> SYSCTRL_OSC8M_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_OSC8M_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp &= ~SYSCTRL_OSC8M_ENABLE; - tmp |= value << SYSCTRL_OSC8M_ENABLE_Pos; - ((Sysctrl *)hw)->OSC8M.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC8M_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC8M_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_OSC8M_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_OSC8M_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp = (tmp & SYSCTRL_OSC8M_RUNSTDBY) >> SYSCTRL_OSC8M_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_OSC8M_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp &= ~SYSCTRL_OSC8M_RUNSTDBY; - tmp |= value << SYSCTRL_OSC8M_RUNSTDBY_Pos; - ((Sysctrl *)hw)->OSC8M.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC8M_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC8M_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_OSC8M_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_OSC8M_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp = (tmp & SYSCTRL_OSC8M_ONDEMAND) >> SYSCTRL_OSC8M_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_OSC8M_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp &= ~SYSCTRL_OSC8M_ONDEMAND; - tmp |= value << SYSCTRL_OSC8M_ONDEMAND_Pos; - ((Sysctrl *)hw)->OSC8M.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC8M_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC8M_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_PRESC(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp = (tmp & SYSCTRL_OSC8M_PRESC(mask)) >> SYSCTRL_OSC8M_PRESC_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp &= ~SYSCTRL_OSC8M_PRESC_Msk; - tmp |= SYSCTRL_OSC8M_PRESC(data); - ((Sysctrl *)hw)->OSC8M.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_PRESC(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC8M_PRESC_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_PRESC(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_PRESC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp = (tmp & SYSCTRL_OSC8M_PRESC_Msk) >> SYSCTRL_OSC8M_PRESC_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp = (tmp & SYSCTRL_OSC8M_CALIB(mask)) >> SYSCTRL_OSC8M_CALIB_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp &= ~SYSCTRL_OSC8M_CALIB_Msk; - tmp |= SYSCTRL_OSC8M_CALIB(data); - ((Sysctrl *)hw)->OSC8M.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC8M_CALIB_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_CALIB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp = (tmp & SYSCTRL_OSC8M_CALIB_Msk) >> SYSCTRL_OSC8M_CALIB_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg |= SYSCTRL_OSC8M_FRANGE(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_FRANGE_bf(const void *const hw, - hri_sysctrl_osc8m_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp = (tmp & SYSCTRL_OSC8M_FRANGE(mask)) >> SYSCTRL_OSC8M_FRANGE_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp &= ~SYSCTRL_OSC8M_FRANGE_Msk; - tmp |= SYSCTRL_OSC8M_FRANGE(data); - ((Sysctrl *)hw)->OSC8M.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg &= ~SYSCTRL_OSC8M_FRANGE(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC8M_FRANGE_bf(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg ^= SYSCTRL_OSC8M_FRANGE(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_FRANGE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp = (tmp & SYSCTRL_OSC8M_FRANGE_Msk) >> SYSCTRL_OSC8M_FRANGE_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_get_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->OSC8M.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_OSC8M_reg(const void *const hw, hri_sysctrl_osc8m_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->OSC8M.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_osc8m_reg_t hri_sysctrl_read_OSC8M_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->OSC8M.reg; -} - -static inline void hri_sysctrl_set_DFLLCTRL_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLCTRL_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & SYSCTRL_DFLLCTRL_ENABLE) >> SYSCTRL_DFLLCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= ~SYSCTRL_DFLLCTRL_ENABLE; - tmp |= value << SYSCTRL_DFLLCTRL_ENABLE_Pos; - ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLCTRL_MODE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_MODE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLCTRL_MODE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & SYSCTRL_DFLLCTRL_MODE) >> SYSCTRL_DFLLCTRL_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_MODE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= ~SYSCTRL_DFLLCTRL_MODE; - tmp |= value << SYSCTRL_DFLLCTRL_MODE_Pos; - ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_MODE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_MODE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_MODE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_MODE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLCTRL_STABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_STABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLCTRL_STABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & SYSCTRL_DFLLCTRL_STABLE) >> SYSCTRL_DFLLCTRL_STABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_STABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= ~SYSCTRL_DFLLCTRL_STABLE; - tmp |= value << SYSCTRL_DFLLCTRL_STABLE_Pos; - ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_STABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_STABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_STABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_STABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLCTRL_LLAW_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_LLAW; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLCTRL_LLAW_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & SYSCTRL_DFLLCTRL_LLAW) >> SYSCTRL_DFLLCTRL_LLAW_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_LLAW_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= ~SYSCTRL_DFLLCTRL_LLAW; - tmp |= value << SYSCTRL_DFLLCTRL_LLAW_Pos; - ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_LLAW_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_LLAW; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_LLAW_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_LLAW; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLCTRL_USBCRM_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_USBCRM; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLCTRL_USBCRM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & SYSCTRL_DFLLCTRL_USBCRM) >> SYSCTRL_DFLLCTRL_USBCRM_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_USBCRM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= ~SYSCTRL_DFLLCTRL_USBCRM; - tmp |= value << SYSCTRL_DFLLCTRL_USBCRM_Pos; - ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_USBCRM_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_USBCRM; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_USBCRM_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_USBCRM; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLCTRL_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLCTRL_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & SYSCTRL_DFLLCTRL_RUNSTDBY) >> SYSCTRL_DFLLCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= ~SYSCTRL_DFLLCTRL_RUNSTDBY; - tmp |= value << SYSCTRL_DFLLCTRL_RUNSTDBY_Pos; - ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLCTRL_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLCTRL_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & SYSCTRL_DFLLCTRL_ONDEMAND) >> SYSCTRL_DFLLCTRL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= ~SYSCTRL_DFLLCTRL_ONDEMAND; - tmp |= value << SYSCTRL_DFLLCTRL_ONDEMAND_Pos; - ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLCTRL_CCDIS_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_CCDIS; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLCTRL_CCDIS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & SYSCTRL_DFLLCTRL_CCDIS) >> SYSCTRL_DFLLCTRL_CCDIS_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_CCDIS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= ~SYSCTRL_DFLLCTRL_CCDIS; - tmp |= value << SYSCTRL_DFLLCTRL_CCDIS_Pos; - ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_CCDIS_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_CCDIS; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_CCDIS_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_CCDIS; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLCTRL_QLDIS_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_QLDIS; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLCTRL_QLDIS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & SYSCTRL_DFLLCTRL_QLDIS) >> SYSCTRL_DFLLCTRL_QLDIS_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_QLDIS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= ~SYSCTRL_DFLLCTRL_QLDIS; - tmp |= value << SYSCTRL_DFLLCTRL_QLDIS_Pos; - ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_QLDIS_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_QLDIS; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_QLDIS_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_QLDIS; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLCTRL_BPLCKC_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_BPLCKC; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLCTRL_BPLCKC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & SYSCTRL_DFLLCTRL_BPLCKC) >> SYSCTRL_DFLLCTRL_BPLCKC_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_BPLCKC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= ~SYSCTRL_DFLLCTRL_BPLCKC; - tmp |= value << SYSCTRL_DFLLCTRL_BPLCKC_Pos; - ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_BPLCKC_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_BPLCKC; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_BPLCKC_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_BPLCKC; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLCTRL_WAITLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= SYSCTRL_DFLLCTRL_WAITLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLCTRL_WAITLOCK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp = (tmp & SYSCTRL_DFLLCTRL_WAITLOCK) >> SYSCTRL_DFLLCTRL_WAITLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_WAITLOCK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= ~SYSCTRL_DFLLCTRL_WAITLOCK; - tmp |= value << SYSCTRL_DFLLCTRL_WAITLOCK_Pos; - ((Sysctrl *)hw)->DFLLCTRL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_WAITLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~SYSCTRL_DFLLCTRL_WAITLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_WAITLOCK_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= SYSCTRL_DFLLCTRL_WAITLOCK; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllctrl_reg_t hri_sysctrl_get_DFLLCTRL_reg(const void *const hw, - hri_sysctrl_dfllctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->DFLLCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLCTRL_reg(const void *const hw, hri_sysctrl_dfllctrl_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLCTRL.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllctrl_reg_t hri_sysctrl_read_DFLLCTRL_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->DFLLCTRL.reg; -} - -static inline void hri_sysctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg |= SYSCTRL_DFLLVAL_FINE(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_FINE_bf(const void *const hw, - hri_sysctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & SYSCTRL_DFLLVAL_FINE(mask)) >> SYSCTRL_DFLLVAL_FINE_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLVAL.reg; - tmp &= ~SYSCTRL_DFLLVAL_FINE_Msk; - tmp |= SYSCTRL_DFLLVAL_FINE(data); - ((Sysctrl *)hw)->DFLLVAL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg &= ~SYSCTRL_DFLLVAL_FINE(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg ^= SYSCTRL_DFLLVAL_FINE(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_FINE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & SYSCTRL_DFLLVAL_FINE_Msk) >> SYSCTRL_DFLLVAL_FINE_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg |= SYSCTRL_DFLLVAL_COARSE(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_COARSE_bf(const void *const hw, - hri_sysctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & SYSCTRL_DFLLVAL_COARSE(mask)) >> SYSCTRL_DFLLVAL_COARSE_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLVAL.reg; - tmp &= ~SYSCTRL_DFLLVAL_COARSE_Msk; - tmp |= SYSCTRL_DFLLVAL_COARSE(data); - ((Sysctrl *)hw)->DFLLVAL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg &= ~SYSCTRL_DFLLVAL_COARSE(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg ^= SYSCTRL_DFLLVAL_COARSE(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_COARSE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & SYSCTRL_DFLLVAL_COARSE_Msk) >> SYSCTRL_DFLLVAL_COARSE_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg |= SYSCTRL_DFLLVAL_DIFF(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_DIFF_bf(const void *const hw, - hri_sysctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & SYSCTRL_DFLLVAL_DIFF(mask)) >> SYSCTRL_DFLLVAL_DIFF_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLVAL.reg; - tmp &= ~SYSCTRL_DFLLVAL_DIFF_Msk; - tmp |= SYSCTRL_DFLLVAL_DIFF(data); - ((Sysctrl *)hw)->DFLLVAL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg &= ~SYSCTRL_DFLLVAL_DIFF(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg ^= SYSCTRL_DFLLVAL_DIFF(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_DIFF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & SYSCTRL_DFLLVAL_DIFF_Msk) >> SYSCTRL_DFLLVAL_DIFF_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_get_DFLLVAL_reg(const void *const hw, - hri_sysctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLVAL_reg(const void *const hw, hri_sysctrl_dfllval_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLVAL.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllval_reg_t hri_sysctrl_read_DFLLVAL_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->DFLLVAL.reg; -} - -static inline void hri_sysctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg |= SYSCTRL_DFLLMUL_MUL(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_MUL_bf(const void *const hw, - hri_sysctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & SYSCTRL_DFLLMUL_MUL(mask)) >> SYSCTRL_DFLLMUL_MUL_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLMUL.reg; - tmp &= ~SYSCTRL_DFLLMUL_MUL_Msk; - tmp |= SYSCTRL_DFLLMUL_MUL(data); - ((Sysctrl *)hw)->DFLLMUL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg &= ~SYSCTRL_DFLLMUL_MUL(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg ^= SYSCTRL_DFLLMUL_MUL(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_MUL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & SYSCTRL_DFLLMUL_MUL_Msk) >> SYSCTRL_DFLLMUL_MUL_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg |= SYSCTRL_DFLLMUL_FSTEP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, - hri_sysctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & SYSCTRL_DFLLMUL_FSTEP(mask)) >> SYSCTRL_DFLLMUL_FSTEP_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLMUL.reg; - tmp &= ~SYSCTRL_DFLLMUL_FSTEP_Msk; - tmp |= SYSCTRL_DFLLMUL_FSTEP(data); - ((Sysctrl *)hw)->DFLLMUL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg &= ~SYSCTRL_DFLLMUL_FSTEP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg ^= SYSCTRL_DFLLMUL_FSTEP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & SYSCTRL_DFLLMUL_FSTEP_Msk) >> SYSCTRL_DFLLMUL_FSTEP_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg |= SYSCTRL_DFLLMUL_CSTEP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, - hri_sysctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & SYSCTRL_DFLLMUL_CSTEP(mask)) >> SYSCTRL_DFLLMUL_CSTEP_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLMUL.reg; - tmp &= ~SYSCTRL_DFLLMUL_CSTEP_Msk; - tmp |= SYSCTRL_DFLLMUL_CSTEP(data); - ((Sysctrl *)hw)->DFLLMUL.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg &= ~SYSCTRL_DFLLMUL_CSTEP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg ^= SYSCTRL_DFLLMUL_CSTEP(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & SYSCTRL_DFLLMUL_CSTEP_Msk) >> SYSCTRL_DFLLMUL_CSTEP_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_get_DFLLMUL_reg(const void *const hw, - hri_sysctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DFLLMUL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLMUL_reg(const void *const hw, hri_sysctrl_dfllmul_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLMUL.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllmul_reg_t hri_sysctrl_read_DFLLMUL_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->DFLLMUL.reg; -} - -static inline void hri_sysctrl_set_DFLLSYNC_READREQ_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLSYNC.reg |= SYSCTRL_DFLLSYNC_READREQ; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DFLLSYNC_READREQ_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sysctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & SYSCTRL_DFLLSYNC_READREQ) >> SYSCTRL_DFLLSYNC_READREQ_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DFLLSYNC_READREQ_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DFLLSYNC.reg; - tmp &= ~SYSCTRL_DFLLSYNC_READREQ; - tmp |= value << SYSCTRL_DFLLSYNC_READREQ_Pos; - ((Sysctrl *)hw)->DFLLSYNC.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLSYNC_READREQ_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLSYNC.reg &= ~SYSCTRL_DFLLSYNC_READREQ; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLSYNC_READREQ_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLSYNC.reg ^= SYSCTRL_DFLLSYNC_READREQ; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLSYNC.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllsync_reg_t hri_sysctrl_get_DFLLSYNC_reg(const void *const hw, - hri_sysctrl_dfllsync_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sysctrl *)hw)->DFLLSYNC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLSYNC.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLSYNC.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_sysctrl_dfllsync_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DFLLSYNC.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dfllsync_reg_t hri_sysctrl_read_DFLLSYNC_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->DFLLSYNC.reg; -} - -static inline void hri_sysctrl_set_BOD33_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_BOD33_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp = (tmp & SYSCTRL_BOD33_ENABLE) >> SYSCTRL_BOD33_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_BOD33_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp &= ~SYSCTRL_BOD33_ENABLE; - tmp |= value << SYSCTRL_BOD33_ENABLE_Pos; - ((Sysctrl *)hw)->BOD33.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_BOD33_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_BOD33_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_BOD33_HYST_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_HYST; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_BOD33_HYST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp = (tmp & SYSCTRL_BOD33_HYST) >> SYSCTRL_BOD33_HYST_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_BOD33_HYST_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp &= ~SYSCTRL_BOD33_HYST; - tmp |= value << SYSCTRL_BOD33_HYST_Pos; - ((Sysctrl *)hw)->BOD33.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_BOD33_HYST_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_HYST; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_BOD33_HYST_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_HYST; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_BOD33_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp = (tmp & SYSCTRL_BOD33_RUNSTDBY) >> SYSCTRL_BOD33_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp &= ~SYSCTRL_BOD33_RUNSTDBY; - tmp |= value << SYSCTRL_BOD33_RUNSTDBY_Pos; - ((Sysctrl *)hw)->BOD33.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_BOD33_MODE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_MODE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_BOD33_MODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp = (tmp & SYSCTRL_BOD33_MODE) >> SYSCTRL_BOD33_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_BOD33_MODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp &= ~SYSCTRL_BOD33_MODE; - tmp |= value << SYSCTRL_BOD33_MODE_Pos; - ((Sysctrl *)hw)->BOD33.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_BOD33_MODE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_MODE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_BOD33_MODE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_MODE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_BOD33_CEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_CEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_BOD33_CEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp = (tmp & SYSCTRL_BOD33_CEN) >> SYSCTRL_BOD33_CEN_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_BOD33_CEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp &= ~SYSCTRL_BOD33_CEN; - tmp |= value << SYSCTRL_BOD33_CEN_Pos; - ((Sysctrl *)hw)->BOD33.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_BOD33_CEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_CEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_BOD33_CEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_CEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_ACTION(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_ACTION_bf(const void *const hw, - hri_sysctrl_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp = (tmp & SYSCTRL_BOD33_ACTION(mask)) >> SYSCTRL_BOD33_ACTION_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp &= ~SYSCTRL_BOD33_ACTION_Msk; - tmp |= SYSCTRL_BOD33_ACTION(data); - ((Sysctrl *)hw)->BOD33.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_ACTION(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_BOD33_ACTION_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_ACTION(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_ACTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp = (tmp & SYSCTRL_BOD33_ACTION_Msk) >> SYSCTRL_BOD33_ACTION_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_PSEL(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp = (tmp & SYSCTRL_BOD33_PSEL(mask)) >> SYSCTRL_BOD33_PSEL_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp &= ~SYSCTRL_BOD33_PSEL_Msk; - tmp |= SYSCTRL_BOD33_PSEL(data); - ((Sysctrl *)hw)->BOD33.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_PSEL(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_BOD33_PSEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_PSEL(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_PSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp = (tmp & SYSCTRL_BOD33_PSEL_Msk) >> SYSCTRL_BOD33_PSEL_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg |= SYSCTRL_BOD33_LEVEL(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp = (tmp & SYSCTRL_BOD33_LEVEL(mask)) >> SYSCTRL_BOD33_LEVEL_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp &= ~SYSCTRL_BOD33_LEVEL_Msk; - tmp |= SYSCTRL_BOD33_LEVEL(data); - ((Sysctrl *)hw)->BOD33.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg &= ~SYSCTRL_BOD33_LEVEL(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_BOD33_LEVEL_bf(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg ^= SYSCTRL_BOD33_LEVEL(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_LEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp = (tmp & SYSCTRL_BOD33_LEVEL_Msk) >> SYSCTRL_BOD33_LEVEL_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_bod33_reg_t hri_sysctrl_get_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->BOD33.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_BOD33_reg(const void *const hw, hri_sysctrl_bod33_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->BOD33.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_bod33_reg_t hri_sysctrl_read_BOD33_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->BOD33.reg; -} - -static inline void hri_sysctrl_set_VREG_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREG.reg |= SYSCTRL_VREG_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_VREG_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->VREG.reg; - tmp = (tmp & SYSCTRL_VREG_RUNSTDBY) >> SYSCTRL_VREG_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_VREG_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->VREG.reg; - tmp &= ~SYSCTRL_VREG_RUNSTDBY; - tmp |= value << SYSCTRL_VREG_RUNSTDBY_Pos; - ((Sysctrl *)hw)->VREG.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_VREG_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREG.reg &= ~SYSCTRL_VREG_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_VREG_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREG.reg ^= SYSCTRL_VREG_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_VREG_FORCELDO_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREG.reg |= SYSCTRL_VREG_FORCELDO; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_VREG_FORCELDO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->VREG.reg; - tmp = (tmp & SYSCTRL_VREG_FORCELDO) >> SYSCTRL_VREG_FORCELDO_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_VREG_FORCELDO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->VREG.reg; - tmp &= ~SYSCTRL_VREG_FORCELDO; - tmp |= value << SYSCTRL_VREG_FORCELDO_Pos; - ((Sysctrl *)hw)->VREG.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_VREG_FORCELDO_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREG.reg &= ~SYSCTRL_VREG_FORCELDO; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_VREG_FORCELDO_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREG.reg ^= SYSCTRL_VREG_FORCELDO; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREG.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_vreg_reg_t hri_sysctrl_get_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sysctrl *)hw)->VREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREG.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREG.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_VREG_reg(const void *const hw, hri_sysctrl_vreg_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREG.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_vreg_reg_t hri_sysctrl_read_VREG_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->VREG.reg; -} - -static inline void hri_sysctrl_set_VREF_TSEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg |= SYSCTRL_VREF_TSEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_VREF_TSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->VREF.reg; - tmp = (tmp & SYSCTRL_VREF_TSEN) >> SYSCTRL_VREF_TSEN_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_VREF_TSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->VREF.reg; - tmp &= ~SYSCTRL_VREF_TSEN; - tmp |= value << SYSCTRL_VREF_TSEN_Pos; - ((Sysctrl *)hw)->VREF.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_VREF_TSEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg &= ~SYSCTRL_VREF_TSEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_VREF_TSEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg ^= SYSCTRL_VREF_TSEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_VREF_BGOUTEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg |= SYSCTRL_VREF_BGOUTEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_VREF_BGOUTEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->VREF.reg; - tmp = (tmp & SYSCTRL_VREF_BGOUTEN) >> SYSCTRL_VREF_BGOUTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_VREF_BGOUTEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->VREF.reg; - tmp &= ~SYSCTRL_VREF_BGOUTEN; - tmp |= value << SYSCTRL_VREF_BGOUTEN_Pos; - ((Sysctrl *)hw)->VREF.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_VREF_BGOUTEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg &= ~SYSCTRL_VREF_BGOUTEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_VREF_BGOUTEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg ^= SYSCTRL_VREF_BGOUTEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg |= SYSCTRL_VREF_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_vref_reg_t hri_sysctrl_get_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->VREF.reg; - tmp = (tmp & SYSCTRL_VREF_CALIB(mask)) >> SYSCTRL_VREF_CALIB_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->VREF.reg; - tmp &= ~SYSCTRL_VREF_CALIB_Msk; - tmp |= SYSCTRL_VREF_CALIB(data); - ((Sysctrl *)hw)->VREF.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg &= ~SYSCTRL_VREF_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_VREF_CALIB_bf(const void *const hw, hri_sysctrl_vref_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg ^= SYSCTRL_VREF_CALIB(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_vref_reg_t hri_sysctrl_read_VREF_CALIB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->VREF.reg; - tmp = (tmp & SYSCTRL_VREF_CALIB_Msk) >> SYSCTRL_VREF_CALIB_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_vref_reg_t hri_sysctrl_get_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->VREF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_VREF_reg(const void *const hw, hri_sysctrl_vref_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->VREF.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_vref_reg_t hri_sysctrl_read_VREF_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->VREF.reg; -} - -static inline void hri_sysctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLA_ENABLE) >> SYSCTRL_DPLLCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; - tmp &= ~SYSCTRL_DPLLCTRLA_ENABLE; - tmp |= value << SYSCTRL_DPLLCTRLA_ENABLE_Pos; - ((Sysctrl *)hw)->DPLLCTRLA.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg ^= SYSCTRL_DPLLCTRLA_ENABLE; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLA_RUNSTDBY) >> SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; - tmp &= ~SYSCTRL_DPLLCTRLA_RUNSTDBY; - tmp |= value << SYSCTRL_DPLLCTRLA_RUNSTDBY_Pos; - ((Sysctrl *)hw)->DPLLCTRLA.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg ^= SYSCTRL_DPLLCTRLA_RUNSTDBY; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg |= SYSCTRL_DPLLCTRLA_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLA_ONDEMAND) >> SYSCTRL_DPLLCTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; - tmp &= ~SYSCTRL_DPLLCTRLA_ONDEMAND; - tmp |= value << SYSCTRL_DPLLCTRLA_ONDEMAND_Pos; - ((Sysctrl *)hw)->DPLLCTRLA.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg &= ~SYSCTRL_DPLLCTRLA_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg ^= SYSCTRL_DPLLCTRLA_ONDEMAND; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrla_reg_t hri_sysctrl_get_DPLLCTRLA_reg(const void *const hw, - hri_sysctrl_dpllctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLA_reg(const void *const hw, hri_sysctrl_dpllctrla_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLA.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrla_reg_t hri_sysctrl_read_DPLLCTRLA_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->DPLLCTRLA.reg; -} - -static inline void hri_sysctrl_set_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLRATIO.reg |= SYSCTRL_DPLLRATIO_LDR(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_get_DPLLRATIO_LDR_bf(const void *const hw, - hri_sysctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; - tmp = (tmp & SYSCTRL_DPLLRATIO_LDR(mask)) >> SYSCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; - tmp &= ~SYSCTRL_DPLLRATIO_LDR_Msk; - tmp |= SYSCTRL_DPLLRATIO_LDR(data); - ((Sysctrl *)hw)->DPLLRATIO.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLRATIO.reg &= ~SYSCTRL_DPLLRATIO_LDR(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLRATIO.reg ^= SYSCTRL_DPLLRATIO_LDR(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_read_DPLLRATIO_LDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; - tmp = (tmp & SYSCTRL_DPLLRATIO_LDR_Msk) >> SYSCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLRATIO.reg |= SYSCTRL_DPLLRATIO_LDRFRAC(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, - hri_sysctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; - tmp = (tmp & SYSCTRL_DPLLRATIO_LDRFRAC(mask)) >> SYSCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; - tmp &= ~SYSCTRL_DPLLRATIO_LDRFRAC_Msk; - tmp |= SYSCTRL_DPLLRATIO_LDRFRAC(data); - ((Sysctrl *)hw)->DPLLRATIO.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLRATIO.reg &= ~SYSCTRL_DPLLRATIO_LDRFRAC(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLRATIO.reg ^= SYSCTRL_DPLLRATIO_LDRFRAC(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; - tmp = (tmp & SYSCTRL_DPLLRATIO_LDRFRAC_Msk) >> SYSCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLRATIO.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_get_DPLLRATIO_reg(const void *const hw, - hri_sysctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLRATIO.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLRATIO.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLRATIO.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLRATIO_reg(const void *const hw, hri_sysctrl_dpllratio_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLRATIO.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllratio_reg_t hri_sysctrl_read_DPLLRATIO_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->DPLLRATIO.reg; -} - -static inline void hri_sysctrl_set_DPLLCTRLB_LPEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_LPEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DPLLCTRLB_LPEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLB_LPEN) >> SYSCTRL_DPLLCTRLB_LPEN_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLB_LPEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~SYSCTRL_DPLLCTRLB_LPEN; - tmp |= value << SYSCTRL_DPLLCTRLB_LPEN_Pos; - ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLB_LPEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_LPEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLB_LPEN_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_LPEN; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DPLLCTRLB_WUF_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_WUF; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DPLLCTRLB_WUF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLB_WUF) >> SYSCTRL_DPLLCTRLB_WUF_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~SYSCTRL_DPLLCTRLB_WUF; - tmp |= value << SYSCTRL_DPLLCTRLB_WUF_Pos; - ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_WUF; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_WUF; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_LBYPASS; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sysctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLB_LBYPASS) >> SYSCTRL_DPLLCTRLB_LBYPASS_Pos; - return (bool)tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~SYSCTRL_DPLLCTRLB_LBYPASS; - tmp |= value << SYSCTRL_DPLLCTRLB_LBYPASS_Pos; - ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_LBYPASS; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_LBYPASS; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_FILTER(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, - hri_sysctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLB_FILTER(mask)) >> SYSCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~SYSCTRL_DPLLCTRLB_FILTER_Msk; - tmp |= SYSCTRL_DPLLCTRLB_FILTER(data); - ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_FILTER(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_FILTER(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLB_FILTER_Msk) >> SYSCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_REFCLK(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, - hri_sysctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLB_REFCLK(mask)) >> SYSCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~SYSCTRL_DPLLCTRLB_REFCLK_Msk; - tmp |= SYSCTRL_DPLLCTRLB_REFCLK(data); - ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_REFCLK(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_REFCLK(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLB_REFCLK_Msk) >> SYSCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_LTIME(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, - hri_sysctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLB_LTIME(mask)) >> SYSCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~SYSCTRL_DPLLCTRLB_LTIME_Msk; - tmp |= SYSCTRL_DPLLCTRLB_LTIME(data); - ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_LTIME(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_LTIME(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLB_LTIME_Msk) >> SYSCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg |= SYSCTRL_DPLLCTRLB_DIV(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, - hri_sysctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLB_DIV(mask)) >> SYSCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - SYSCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp &= ~SYSCTRL_DPLLCTRLB_DIV_Msk; - tmp |= SYSCTRL_DPLLCTRLB_DIV(data); - ((Sysctrl *)hw)->DPLLCTRLB.reg = tmp; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~SYSCTRL_DPLLCTRLB_DIV(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg ^= SYSCTRL_DPLLCTRLB_DIV(mask); - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_DIV_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp = (tmp & SYSCTRL_DPLLCTRLB_DIV_Msk) >> SYSCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_sysctrl_set_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg |= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_get_DPLLCTRLB_reg(const void *const hw, - hri_sysctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->DPLLCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sysctrl_write_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t data) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg = data; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_clear_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg &= ~mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sysctrl_toggle_DPLLCTRLB_reg(const void *const hw, hri_sysctrl_dpllctrlb_reg_t mask) -{ - SYSCTRL_CRITICAL_SECTION_ENTER(); - ((Sysctrl *)hw)->DPLLCTRLB.reg ^= mask; - SYSCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sysctrl_dpllctrlb_reg_t hri_sysctrl_read_DPLLCTRLB_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->DPLLCTRLB.reg; -} - -static inline bool hri_sysctrl_get_PCLKSR_XOSCRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_XOSCRDY) >> SYSCTRL_PCLKSR_XOSCRDY_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_XOSC32KRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_XOSC32KRDY) >> SYSCTRL_PCLKSR_XOSC32KRDY_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_OSC32KRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_OSC32KRDY) >> SYSCTRL_PCLKSR_OSC32KRDY_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_OSC8MRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_OSC8MRDY) >> SYSCTRL_PCLKSR_OSC8MRDY_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_DFLLRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRDY) >> SYSCTRL_PCLKSR_DFLLRDY_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_DFLLOOB_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLOOB) >> SYSCTRL_PCLKSR_DFLLOOB_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_DFLLLCKF_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKF) >> SYSCTRL_PCLKSR_DFLLLCKF_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_DFLLLCKC_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLLCKC) >> SYSCTRL_PCLKSR_DFLLLCKC_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_DFLLRCS_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DFLLRCS) >> SYSCTRL_PCLKSR_DFLLRCS_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_BOD33RDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_BOD33RDY) >> SYSCTRL_PCLKSR_BOD33RDY_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_BOD33DET_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_BOD33DET) >> SYSCTRL_PCLKSR_BOD33DET_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_B33SRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_B33SRDY) >> SYSCTRL_PCLKSR_B33SRDY_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_DPLLLCKR_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DPLLLCKR) >> SYSCTRL_PCLKSR_DPLLLCKR_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_DPLLLCKF_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DPLLLCKF) >> SYSCTRL_PCLKSR_DPLLLCKF_Pos; -} - -static inline bool hri_sysctrl_get_PCLKSR_DPLLLTO_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->PCLKSR.reg & SYSCTRL_PCLKSR_DPLLLTO) >> SYSCTRL_PCLKSR_DPLLLTO_Pos; -} - -static inline hri_sysctrl_pclksr_reg_t hri_sysctrl_get_PCLKSR_reg(const void *const hw, hri_sysctrl_pclksr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sysctrl *)hw)->PCLKSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sysctrl_pclksr_reg_t hri_sysctrl_read_PCLKSR_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->PCLKSR.reg; -} - -static inline bool hri_sysctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_LOCK) >> SYSCTRL_DPLLSTATUS_LOCK_Pos; -} - -static inline bool hri_sysctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_CLKRDY) >> SYSCTRL_DPLLSTATUS_CLKRDY_Pos; -} - -static inline bool hri_sysctrl_get_DPLLSTATUS_ENABLE_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_ENABLE) >> SYSCTRL_DPLLSTATUS_ENABLE_Pos; -} - -static inline bool hri_sysctrl_get_DPLLSTATUS_DIV_bit(const void *const hw) -{ - return (((Sysctrl *)hw)->DPLLSTATUS.reg & SYSCTRL_DPLLSTATUS_DIV) >> SYSCTRL_DPLLSTATUS_DIV_Pos; -} - -static inline hri_sysctrl_dpllstatus_reg_t hri_sysctrl_get_DPLLSTATUS_reg(const void *const hw, - hri_sysctrl_dpllstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sysctrl *)hw)->DPLLSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sysctrl_dpllstatus_reg_t hri_sysctrl_read_DPLLSTATUS_reg(const void *const hw) -{ - return ((Sysctrl *)hw)->DPLLSTATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SYSCTRL_D21_H_INCLUDED */ -#endif /* _SAMD21_SYSCTRL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_systemcontrol_d21.h b/atmel-samd/asf4/samd21/hri/hri_systemcontrol_d21.h deleted file mode 100644 index 5969d32bf..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_systemcontrol_d21.h +++ /dev/null @@ -1,1477 +0,0 @@ -/** - * \file - * - * \brief SAM SystemControl - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_SystemControl_COMPONENT_ -#ifndef _HRI_SystemControl_D21_H_INCLUDED_ -#define _HRI_SystemControl_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SystemControl_CRITICAL_SECTIONS) -#define SystemControl_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SystemControl_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SystemControl_CRITICAL_SECTION_ENTER() -#define SystemControl_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_systemcontrol_aircr_reg_t; -typedef uint32_t hri_systemcontrol_ccr_reg_t; -typedef uint32_t hri_systemcontrol_cpuid_reg_t; -typedef uint32_t hri_systemcontrol_icsr_reg_t; -typedef uint32_t hri_systemcontrol_scr_reg_t; -typedef uint32_t hri_systemcontrol_shpr2_reg_t; -typedef uint32_t hri_systemcontrol_shpr3_reg_t; -typedef uint32_t hri_systemcontrol_vtor_reg_t; - -static inline void hri_systemcontrol_set_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_REVISION(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_REVISION_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp = (tmp & SystemControl_CPUID_REVISION(mask)) >> 0; - return tmp; -} - -static inline void hri_systemcontrol_write_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp &= ~SystemControl_CPUID_REVISION_Msk; - tmp |= SystemControl_CPUID_REVISION(data); - ((Systemcontrol *)hw)->CPUID.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_REVISION(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_CPUID_REVISION_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_REVISION(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_REVISION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp = (tmp & SystemControl_CPUID_REVISION_Msk) >> 0; - return tmp; -} - -static inline void hri_systemcontrol_set_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_PARTNO(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_PARTNO_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp = (tmp & SystemControl_CPUID_PARTNO(mask)) >> 4; - return tmp; -} - -static inline void hri_systemcontrol_write_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp &= ~SystemControl_CPUID_PARTNO_Msk; - tmp |= SystemControl_CPUID_PARTNO(data); - ((Systemcontrol *)hw)->CPUID.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_PARTNO(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_CPUID_PARTNO_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_PARTNO(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_PARTNO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp = (tmp & SystemControl_CPUID_PARTNO_Msk) >> 4; - return tmp; -} - -static inline void hri_systemcontrol_set_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_ARCHITECTURE(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t -hri_systemcontrol_get_CPUID_ARCHITECTURE_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp = (tmp & SystemControl_CPUID_ARCHITECTURE(mask)) >> 16; - return tmp; -} - -static inline void hri_systemcontrol_write_CPUID_ARCHITECTURE_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t data) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp &= ~SystemControl_CPUID_ARCHITECTURE_Msk; - tmp |= SystemControl_CPUID_ARCHITECTURE(data); - ((Systemcontrol *)hw)->CPUID.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_CPUID_ARCHITECTURE_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_ARCHITECTURE(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_CPUID_ARCHITECTURE_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_ARCHITECTURE(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_ARCHITECTURE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp = (tmp & SystemControl_CPUID_ARCHITECTURE_Msk) >> 16; - return tmp; -} - -static inline void hri_systemcontrol_set_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_VARIANT(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_VARIANT_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp = (tmp & SystemControl_CPUID_VARIANT(mask)) >> 20; - return tmp; -} - -static inline void hri_systemcontrol_write_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t data) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp &= ~SystemControl_CPUID_VARIANT_Msk; - tmp |= SystemControl_CPUID_VARIANT(data); - ((Systemcontrol *)hw)->CPUID.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_VARIANT(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_CPUID_VARIANT_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_VARIANT(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_VARIANT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp = (tmp & SystemControl_CPUID_VARIANT_Msk) >> 20; - return tmp; -} - -static inline void hri_systemcontrol_set_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_IMPLEMENTER(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t -hri_systemcontrol_get_CPUID_IMPLEMENTER_bf(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp = (tmp & SystemControl_CPUID_IMPLEMENTER(mask)) >> 24; - return tmp; -} - -static inline void hri_systemcontrol_write_CPUID_IMPLEMENTER_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t data) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp &= ~SystemControl_CPUID_IMPLEMENTER_Msk; - tmp |= SystemControl_CPUID_IMPLEMENTER(data); - ((Systemcontrol *)hw)->CPUID.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_CPUID_IMPLEMENTER_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_IMPLEMENTER(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_CPUID_IMPLEMENTER_bf(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_IMPLEMENTER(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_IMPLEMENTER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp = (tmp & SystemControl_CPUID_IMPLEMENTER_Msk) >> 24; - return tmp; -} - -static inline void hri_systemcontrol_set_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_get_CPUID_reg(const void *const hw, - hri_systemcontrol_cpuid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CPUID.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_CPUID_reg(const void *const hw, hri_systemcontrol_cpuid_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CPUID.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_cpuid_reg_t hri_systemcontrol_read_CPUID_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->CPUID.reg; -} - -static inline void hri_systemcontrol_set_ICSR_PENDSTCLR_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSTCLR; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_ICSR_PENDSTCLR_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp = (tmp & SystemControl_ICSR_PENDSTCLR) >> 25; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_ICSR_PENDSTCLR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp &= ~SystemControl_ICSR_PENDSTCLR; - tmp |= value << 25; - ((Systemcontrol *)hw)->ICSR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_ICSR_PENDSTCLR_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSTCLR; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_ICSR_PENDSTCLR_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSTCLR; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_ICSR_PENDSTSET_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSTSET; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_ICSR_PENDSTSET_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp = (tmp & SystemControl_ICSR_PENDSTSET) >> 26; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_ICSR_PENDSTSET_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp &= ~SystemControl_ICSR_PENDSTSET; - tmp |= value << 26; - ((Systemcontrol *)hw)->ICSR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_ICSR_PENDSTSET_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSTSET; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_ICSR_PENDSTSET_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSTSET; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_ICSR_PENDSVCLR_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSVCLR; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_ICSR_PENDSVCLR_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp = (tmp & SystemControl_ICSR_PENDSVCLR) >> 27; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_ICSR_PENDSVCLR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp &= ~SystemControl_ICSR_PENDSVCLR; - tmp |= value << 27; - ((Systemcontrol *)hw)->ICSR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_ICSR_PENDSVCLR_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSVCLR; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_ICSR_PENDSVCLR_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSVCLR; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_ICSR_PENDSVSET_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_PENDSVSET; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_ICSR_PENDSVSET_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp = (tmp & SystemControl_ICSR_PENDSVSET) >> 28; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_ICSR_PENDSVSET_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp &= ~SystemControl_ICSR_PENDSVSET; - tmp |= value << 28; - ((Systemcontrol *)hw)->ICSR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_ICSR_PENDSVSET_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_PENDSVSET; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_ICSR_PENDSVSET_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_PENDSVSET; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_ICSR_NMIPENDSET_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_NMIPENDSET; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_ICSR_NMIPENDSET_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp = (tmp & SystemControl_ICSR_NMIPENDSET) >> 31; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_ICSR_NMIPENDSET_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp &= ~SystemControl_ICSR_NMIPENDSET; - tmp |= value << 31; - ((Systemcontrol *)hw)->ICSR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_ICSR_NMIPENDSET_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_NMIPENDSET; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_ICSR_NMIPENDSET_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_NMIPENDSET; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg |= SystemControl_ICSR_VECTPENDING(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_VECTPENDING_bf(const void *const hw, - hri_systemcontrol_icsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp = (tmp & SystemControl_ICSR_VECTPENDING(mask)) >> 12; - return tmp; -} - -static inline void hri_systemcontrol_write_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t data) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp &= ~SystemControl_ICSR_VECTPENDING_Msk; - tmp |= SystemControl_ICSR_VECTPENDING(data); - ((Systemcontrol *)hw)->ICSR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg &= ~SystemControl_ICSR_VECTPENDING(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_ICSR_VECTPENDING_bf(const void *const hw, hri_systemcontrol_icsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg ^= SystemControl_ICSR_VECTPENDING(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_VECTPENDING_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp = (tmp & SystemControl_ICSR_VECTPENDING_Msk) >> 12; - return tmp; -} - -static inline void hri_systemcontrol_set_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_get_ICSR_reg(const void *const hw, - hri_systemcontrol_icsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->ICSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_ICSR_reg(const void *const hw, hri_systemcontrol_icsr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->ICSR.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_icsr_reg_t hri_systemcontrol_read_ICSR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->ICSR.reg; -} - -static inline void hri_systemcontrol_set_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->VTOR.reg |= SystemControl_VTOR_TBLOFF(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_TBLOFF_bf(const void *const hw, - hri_systemcontrol_vtor_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->VTOR.reg; - tmp = (tmp & SystemControl_VTOR_TBLOFF(mask)) >> 7; - return tmp; -} - -static inline void hri_systemcontrol_write_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t data) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->VTOR.reg; - tmp &= ~SystemControl_VTOR_TBLOFF_Msk; - tmp |= SystemControl_VTOR_TBLOFF(data); - ((Systemcontrol *)hw)->VTOR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->VTOR.reg &= ~SystemControl_VTOR_TBLOFF(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_VTOR_TBLOFF_bf(const void *const hw, hri_systemcontrol_vtor_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->VTOR.reg ^= SystemControl_VTOR_TBLOFF(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_TBLOFF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->VTOR.reg; - tmp = (tmp & SystemControl_VTOR_TBLOFF_Msk) >> 7; - return tmp; -} - -static inline void hri_systemcontrol_set_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->VTOR.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_get_VTOR_reg(const void *const hw, - hri_systemcontrol_vtor_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->VTOR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->VTOR.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->VTOR.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_VTOR_reg(const void *const hw, hri_systemcontrol_vtor_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->VTOR.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_vtor_reg_t hri_systemcontrol_read_VTOR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->VTOR.reg; -} - -static inline void hri_systemcontrol_set_AIRCR_VECTCLRACTIVE_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_VECTCLRACTIVE; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_AIRCR_VECTCLRACTIVE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->AIRCR.reg; - tmp = (tmp & SystemControl_AIRCR_VECTCLRACTIVE) >> 1; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_AIRCR_VECTCLRACTIVE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->AIRCR.reg; - tmp &= ~SystemControl_AIRCR_VECTCLRACTIVE; - tmp |= value << 1; - ((Systemcontrol *)hw)->AIRCR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_AIRCR_VECTCLRACTIVE_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_VECTCLRACTIVE; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_AIRCR_VECTCLRACTIVE_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_VECTCLRACTIVE; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_AIRCR_SYSRESETREQ_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_SYSRESETREQ; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_AIRCR_SYSRESETREQ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->AIRCR.reg; - tmp = (tmp & SystemControl_AIRCR_SYSRESETREQ) >> 2; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_AIRCR_SYSRESETREQ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->AIRCR.reg; - tmp &= ~SystemControl_AIRCR_SYSRESETREQ; - tmp |= value << 2; - ((Systemcontrol *)hw)->AIRCR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_AIRCR_SYSRESETREQ_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_SYSRESETREQ; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_AIRCR_SYSRESETREQ_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_SYSRESETREQ; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_AIRCR_ENDIANNESS_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_ENDIANNESS; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_AIRCR_ENDIANNESS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->AIRCR.reg; - tmp = (tmp & SystemControl_AIRCR_ENDIANNESS) >> 15; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_AIRCR_ENDIANNESS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->AIRCR.reg; - tmp &= ~SystemControl_AIRCR_ENDIANNESS; - tmp |= value << 15; - ((Systemcontrol *)hw)->AIRCR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_AIRCR_ENDIANNESS_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_ENDIANNESS; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_AIRCR_ENDIANNESS_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_ENDIANNESS; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg |= SystemControl_AIRCR_VECTKEY(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_VECTKEY_bf(const void *const hw, - hri_systemcontrol_aircr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->AIRCR.reg; - tmp = (tmp & SystemControl_AIRCR_VECTKEY(mask)) >> 16; - return tmp; -} - -static inline void hri_systemcontrol_write_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t data) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->AIRCR.reg; - tmp &= ~SystemControl_AIRCR_VECTKEY_Msk; - tmp |= SystemControl_AIRCR_VECTKEY(data); - ((Systemcontrol *)hw)->AIRCR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg &= ~SystemControl_AIRCR_VECTKEY(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_AIRCR_VECTKEY_bf(const void *const hw, hri_systemcontrol_aircr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg ^= SystemControl_AIRCR_VECTKEY(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_VECTKEY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->AIRCR.reg; - tmp = (tmp & SystemControl_AIRCR_VECTKEY_Msk) >> 16; - return tmp; -} - -static inline void hri_systemcontrol_set_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_get_AIRCR_reg(const void *const hw, - hri_systemcontrol_aircr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->AIRCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_AIRCR_reg(const void *const hw, hri_systemcontrol_aircr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->AIRCR.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_aircr_reg_t hri_systemcontrol_read_AIRCR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->AIRCR.reg; -} - -static inline void hri_systemcontrol_set_SCR_SLEEPONEXIT_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPONEXIT; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_SCR_SLEEPONEXIT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SCR.reg; - tmp = (tmp & SystemControl_SCR_SLEEPONEXIT) >> 1; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_SCR_SLEEPONEXIT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->SCR.reg; - tmp &= ~SystemControl_SCR_SLEEPONEXIT; - tmp |= value << 1; - ((Systemcontrol *)hw)->SCR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SCR_SLEEPONEXIT_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SLEEPONEXIT; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SCR_SLEEPONEXIT_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SLEEPONEXIT; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_SCR_SLEEPDEEP_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SLEEPDEEP; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_SCR_SLEEPDEEP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SCR.reg; - tmp = (tmp & SystemControl_SCR_SLEEPDEEP) >> 2; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_SCR_SLEEPDEEP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->SCR.reg; - tmp &= ~SystemControl_SCR_SLEEPDEEP; - tmp |= value << 2; - ((Systemcontrol *)hw)->SCR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SCR_SLEEPDEEP_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SLEEPDEEP; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SCR_SLEEPDEEP_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SLEEPDEEP; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_SCR_SEVONPEND_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg |= SystemControl_SCR_SEVONPEND; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_SCR_SEVONPEND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SCR.reg; - tmp = (tmp & SystemControl_SCR_SEVONPEND) >> 4; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_SCR_SEVONPEND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->SCR.reg; - tmp &= ~SystemControl_SCR_SEVONPEND; - tmp |= value << 4; - ((Systemcontrol *)hw)->SCR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SCR_SEVONPEND_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg &= ~SystemControl_SCR_SEVONPEND; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SCR_SEVONPEND_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg ^= SystemControl_SCR_SEVONPEND; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_get_SCR_reg(const void *const hw, - hri_systemcontrol_scr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SCR_reg(const void *const hw, hri_systemcontrol_scr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SCR.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_scr_reg_t hri_systemcontrol_read_SCR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->SCR.reg; -} - -static inline void hri_systemcontrol_set_CCR_UNALIGN_TRP_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CCR.reg |= SystemControl_CCR_UNALIGN_TRP; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_CCR_UNALIGN_TRP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CCR.reg; - tmp = (tmp & SystemControl_CCR_UNALIGN_TRP) >> 3; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_CCR_UNALIGN_TRP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->CCR.reg; - tmp &= ~SystemControl_CCR_UNALIGN_TRP; - tmp |= value << 3; - ((Systemcontrol *)hw)->CCR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_CCR_UNALIGN_TRP_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CCR.reg &= ~SystemControl_CCR_UNALIGN_TRP; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_CCR_UNALIGN_TRP_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CCR.reg ^= SystemControl_CCR_UNALIGN_TRP; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_CCR_STKALIGN_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CCR.reg |= SystemControl_CCR_STKALIGN; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systemcontrol_get_CCR_STKALIGN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CCR.reg; - tmp = (tmp & SystemControl_CCR_STKALIGN) >> 9; - return (bool)tmp; -} - -static inline void hri_systemcontrol_write_CCR_STKALIGN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->CCR.reg; - tmp &= ~SystemControl_CCR_STKALIGN; - tmp |= value << 9; - ((Systemcontrol *)hw)->CCR.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_CCR_STKALIGN_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CCR.reg &= ~SystemControl_CCR_STKALIGN; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_CCR_STKALIGN_bit(const void *const hw) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CCR.reg ^= SystemControl_CCR_STKALIGN; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_set_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CCR.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_get_CCR_reg(const void *const hw, - hri_systemcontrol_ccr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->CCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CCR.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CCR.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_CCR_reg(const void *const hw, hri_systemcontrol_ccr_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->CCR.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_ccr_reg_t hri_systemcontrol_read_CCR_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->CCR.reg; -} - -static inline void hri_systemcontrol_set_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR2.reg |= SystemControl_SHPR2_PRI_11(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_PRI_11_bf(const void *const hw, - hri_systemcontrol_shpr2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SHPR2.reg; - tmp = (tmp & SystemControl_SHPR2_PRI_11(mask)) >> 24; - return tmp; -} - -static inline void hri_systemcontrol_write_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t data) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->SHPR2.reg; - tmp &= ~SystemControl_SHPR2_PRI_11_Msk; - tmp |= SystemControl_SHPR2_PRI_11(data); - ((Systemcontrol *)hw)->SHPR2.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR2.reg &= ~SystemControl_SHPR2_PRI_11(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SHPR2_PRI_11_bf(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR2.reg ^= SystemControl_SHPR2_PRI_11(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_PRI_11_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SHPR2.reg; - tmp = (tmp & SystemControl_SHPR2_PRI_11_Msk) >> 24; - return tmp; -} - -static inline void hri_systemcontrol_set_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR2.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_get_SHPR2_reg(const void *const hw, - hri_systemcontrol_shpr2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SHPR2.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR2.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR2.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SHPR2_reg(const void *const hw, hri_systemcontrol_shpr2_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR2.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr2_reg_t hri_systemcontrol_read_SHPR2_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->SHPR2.reg; -} - -static inline void hri_systemcontrol_set_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg |= SystemControl_SHPR3_PRI_14(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_PRI_14_bf(const void *const hw, - hri_systemcontrol_shpr3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SHPR3.reg; - tmp = (tmp & SystemControl_SHPR3_PRI_14(mask)) >> 16; - return tmp; -} - -static inline void hri_systemcontrol_write_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t data) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->SHPR3.reg; - tmp &= ~SystemControl_SHPR3_PRI_14_Msk; - tmp |= SystemControl_SHPR3_PRI_14(data); - ((Systemcontrol *)hw)->SHPR3.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg &= ~SystemControl_SHPR3_PRI_14(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SHPR3_PRI_14_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg ^= SystemControl_SHPR3_PRI_14(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_PRI_14_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SHPR3.reg; - tmp = (tmp & SystemControl_SHPR3_PRI_14_Msk) >> 16; - return tmp; -} - -static inline void hri_systemcontrol_set_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg |= SystemControl_SHPR3_PRI_15(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_PRI_15_bf(const void *const hw, - hri_systemcontrol_shpr3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SHPR3.reg; - tmp = (tmp & SystemControl_SHPR3_PRI_15(mask)) >> 24; - return tmp; -} - -static inline void hri_systemcontrol_write_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t data) -{ - uint32_t tmp; - SystemControl_CRITICAL_SECTION_ENTER(); - tmp = ((Systemcontrol *)hw)->SHPR3.reg; - tmp &= ~SystemControl_SHPR3_PRI_15_Msk; - tmp |= SystemControl_SHPR3_PRI_15(data); - ((Systemcontrol *)hw)->SHPR3.reg = tmp; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg &= ~SystemControl_SHPR3_PRI_15(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SHPR3_PRI_15_bf(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg ^= SystemControl_SHPR3_PRI_15(mask); - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_PRI_15_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SHPR3.reg; - tmp = (tmp & SystemControl_SHPR3_PRI_15_Msk) >> 24; - return tmp; -} - -static inline void hri_systemcontrol_set_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg |= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_get_SHPR3_reg(const void *const hw, - hri_systemcontrol_shpr3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systemcontrol *)hw)->SHPR3.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systemcontrol_write_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t data) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg = data; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_clear_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg &= ~mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systemcontrol_toggle_SHPR3_reg(const void *const hw, hri_systemcontrol_shpr3_reg_t mask) -{ - SystemControl_CRITICAL_SECTION_ENTER(); - ((Systemcontrol *)hw)->SHPR3.reg ^= mask; - SystemControl_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systemcontrol_shpr3_reg_t hri_systemcontrol_read_SHPR3_reg(const void *const hw) -{ - return ((Systemcontrol *)hw)->SHPR3.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SystemControl_D21_H_INCLUDED */ -#endif /* _SAMD21_SystemControl_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_systick_d21.h b/atmel-samd/asf4/samd21/hri/hri_systick_d21.h deleted file mode 100644 index 34d4558c0..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_systick_d21.h +++ /dev/null @@ -1,620 +0,0 @@ -/** - * \file - * - * \brief SAM SysTick - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_SysTick_COMPONENT_ -#ifndef _HRI_SysTick_D21_H_INCLUDED_ -#define _HRI_SysTick_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SysTick_CRITICAL_SECTIONS) -#define SysTick_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SysTick_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SysTick_CRITICAL_SECTION_ENTER() -#define SysTick_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_systick_calib_reg_t; -typedef uint32_t hri_systick_csr_reg_t; -typedef uint32_t hri_systick_cvr_reg_t; -typedef uint32_t hri_systick_rvr_reg_t; - -static inline void hri_systick_set_CSR_ENABLE_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg |= SysTick_CSR_ENABLE; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systick_get_CSR_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CSR.reg; - tmp = (tmp & SysTick_CSR_ENABLE) >> 0; - return (bool)tmp; -} - -static inline void hri_systick_write_CSR_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SysTick_CRITICAL_SECTION_ENTER(); - tmp = ((Systick *)hw)->CSR.reg; - tmp &= ~SysTick_CSR_ENABLE; - tmp |= value << 0; - ((Systick *)hw)->CSR.reg = tmp; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CSR_ENABLE_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg &= ~SysTick_CSR_ENABLE; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CSR_ENABLE_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg ^= SysTick_CSR_ENABLE; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_set_CSR_TICKINT_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg |= SysTick_CSR_TICKINT; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systick_get_CSR_TICKINT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CSR.reg; - tmp = (tmp & SysTick_CSR_TICKINT) >> 1; - return (bool)tmp; -} - -static inline void hri_systick_write_CSR_TICKINT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SysTick_CRITICAL_SECTION_ENTER(); - tmp = ((Systick *)hw)->CSR.reg; - tmp &= ~SysTick_CSR_TICKINT; - tmp |= value << 1; - ((Systick *)hw)->CSR.reg = tmp; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CSR_TICKINT_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg &= ~SysTick_CSR_TICKINT; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CSR_TICKINT_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg ^= SysTick_CSR_TICKINT; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_set_CSR_CLKSOURCE_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg |= SysTick_CSR_CLKSOURCE; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systick_get_CSR_CLKSOURCE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CSR.reg; - tmp = (tmp & SysTick_CSR_CLKSOURCE) >> 2; - return (bool)tmp; -} - -static inline void hri_systick_write_CSR_CLKSOURCE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SysTick_CRITICAL_SECTION_ENTER(); - tmp = ((Systick *)hw)->CSR.reg; - tmp &= ~SysTick_CSR_CLKSOURCE; - tmp |= value << 2; - ((Systick *)hw)->CSR.reg = tmp; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CSR_CLKSOURCE_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg &= ~SysTick_CSR_CLKSOURCE; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CSR_CLKSOURCE_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg ^= SysTick_CSR_CLKSOURCE; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_set_CSR_COUNTFLAG_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg |= SysTick_CSR_COUNTFLAG; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systick_get_CSR_COUNTFLAG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CSR.reg; - tmp = (tmp & SysTick_CSR_COUNTFLAG) >> 16; - return (bool)tmp; -} - -static inline void hri_systick_write_CSR_COUNTFLAG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SysTick_CRITICAL_SECTION_ENTER(); - tmp = ((Systick *)hw)->CSR.reg; - tmp &= ~SysTick_CSR_COUNTFLAG; - tmp |= value << 16; - ((Systick *)hw)->CSR.reg = tmp; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CSR_COUNTFLAG_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg &= ~SysTick_CSR_COUNTFLAG; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CSR_COUNTFLAG_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg ^= SysTick_CSR_COUNTFLAG; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_set_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg |= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_csr_reg_t hri_systick_get_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systick_write_CSR_reg(const void *const hw, hri_systick_csr_reg_t data) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg = data; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg &= ~mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CSR_reg(const void *const hw, hri_systick_csr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CSR.reg ^= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_csr_reg_t hri_systick_read_CSR_reg(const void *const hw) -{ - return ((Systick *)hw)->CSR.reg; -} - -static inline void hri_systick_set_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->RVR.reg |= SysTick_RVR_RELOAD(mask); - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_rvr_reg_t hri_systick_get_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->RVR.reg; - tmp = (tmp & SysTick_RVR_RELOAD(mask)) >> 0; - return tmp; -} - -static inline void hri_systick_write_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t data) -{ - uint32_t tmp; - SysTick_CRITICAL_SECTION_ENTER(); - tmp = ((Systick *)hw)->RVR.reg; - tmp &= ~SysTick_RVR_RELOAD_Msk; - tmp |= SysTick_RVR_RELOAD(data); - ((Systick *)hw)->RVR.reg = tmp; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->RVR.reg &= ~SysTick_RVR_RELOAD(mask); - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_RVR_RELOAD_bf(const void *const hw, hri_systick_rvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->RVR.reg ^= SysTick_RVR_RELOAD(mask); - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_rvr_reg_t hri_systick_read_RVR_RELOAD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->RVR.reg; - tmp = (tmp & SysTick_RVR_RELOAD_Msk) >> 0; - return tmp; -} - -static inline void hri_systick_set_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->RVR.reg |= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_rvr_reg_t hri_systick_get_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->RVR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systick_write_RVR_reg(const void *const hw, hri_systick_rvr_reg_t data) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->RVR.reg = data; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->RVR.reg &= ~mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_RVR_reg(const void *const hw, hri_systick_rvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->RVR.reg ^= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_rvr_reg_t hri_systick_read_RVR_reg(const void *const hw) -{ - return ((Systick *)hw)->RVR.reg; -} - -static inline void hri_systick_set_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CVR.reg |= SysTick_CVR_CURRENT(mask); - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_cvr_reg_t hri_systick_get_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CVR.reg; - tmp = (tmp & SysTick_CVR_CURRENT(mask)) >> 0; - return tmp; -} - -static inline void hri_systick_write_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t data) -{ - uint32_t tmp; - SysTick_CRITICAL_SECTION_ENTER(); - tmp = ((Systick *)hw)->CVR.reg; - tmp &= ~SysTick_CVR_CURRENT_Msk; - tmp |= SysTick_CVR_CURRENT(data); - ((Systick *)hw)->CVR.reg = tmp; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CVR.reg &= ~SysTick_CVR_CURRENT(mask); - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CVR_CURRENT_bf(const void *const hw, hri_systick_cvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CVR.reg ^= SysTick_CVR_CURRENT(mask); - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_cvr_reg_t hri_systick_read_CVR_CURRENT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CVR.reg; - tmp = (tmp & SysTick_CVR_CURRENT_Msk) >> 0; - return tmp; -} - -static inline void hri_systick_set_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CVR.reg |= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_cvr_reg_t hri_systick_get_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CVR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systick_write_CVR_reg(const void *const hw, hri_systick_cvr_reg_t data) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CVR.reg = data; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CVR.reg &= ~mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CVR_reg(const void *const hw, hri_systick_cvr_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CVR.reg ^= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_cvr_reg_t hri_systick_read_CVR_reg(const void *const hw) -{ - return ((Systick *)hw)->CVR.reg; -} - -static inline void hri_systick_set_CALIB_SKEW_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg |= SysTick_CALIB_SKEW; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systick_get_CALIB_SKEW_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CALIB.reg; - tmp = (tmp & SysTick_CALIB_SKEW) >> 30; - return (bool)tmp; -} - -static inline void hri_systick_write_CALIB_SKEW_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SysTick_CRITICAL_SECTION_ENTER(); - tmp = ((Systick *)hw)->CALIB.reg; - tmp &= ~SysTick_CALIB_SKEW; - tmp |= value << 30; - ((Systick *)hw)->CALIB.reg = tmp; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CALIB_SKEW_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg &= ~SysTick_CALIB_SKEW; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CALIB_SKEW_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg ^= SysTick_CALIB_SKEW; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_set_CALIB_NOREF_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg |= SysTick_CALIB_NOREF; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_systick_get_CALIB_NOREF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CALIB.reg; - tmp = (tmp & SysTick_CALIB_NOREF) >> 31; - return (bool)tmp; -} - -static inline void hri_systick_write_CALIB_NOREF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SysTick_CRITICAL_SECTION_ENTER(); - tmp = ((Systick *)hw)->CALIB.reg; - tmp &= ~SysTick_CALIB_NOREF; - tmp |= value << 31; - ((Systick *)hw)->CALIB.reg = tmp; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CALIB_NOREF_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg &= ~SysTick_CALIB_NOREF; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CALIB_NOREF_bit(const void *const hw) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg ^= SysTick_CALIB_NOREF; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_set_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg |= SysTick_CALIB_TENMS(mask); - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_calib_reg_t hri_systick_get_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CALIB.reg; - tmp = (tmp & SysTick_CALIB_TENMS(mask)) >> 0; - return tmp; -} - -static inline void hri_systick_write_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t data) -{ - uint32_t tmp; - SysTick_CRITICAL_SECTION_ENTER(); - tmp = ((Systick *)hw)->CALIB.reg; - tmp &= ~SysTick_CALIB_TENMS_Msk; - tmp |= SysTick_CALIB_TENMS(data); - ((Systick *)hw)->CALIB.reg = tmp; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg &= ~SysTick_CALIB_TENMS(mask); - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CALIB_TENMS_bf(const void *const hw, hri_systick_calib_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg ^= SysTick_CALIB_TENMS(mask); - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_calib_reg_t hri_systick_read_CALIB_TENMS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CALIB.reg; - tmp = (tmp & SysTick_CALIB_TENMS_Msk) >> 0; - return tmp; -} - -static inline void hri_systick_set_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg |= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_calib_reg_t hri_systick_get_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) -{ - uint32_t tmp; - tmp = ((Systick *)hw)->CALIB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_systick_write_CALIB_reg(const void *const hw, hri_systick_calib_reg_t data) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg = data; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_clear_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg &= ~mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_systick_toggle_CALIB_reg(const void *const hw, hri_systick_calib_reg_t mask) -{ - SysTick_CRITICAL_SECTION_ENTER(); - ((Systick *)hw)->CALIB.reg ^= mask; - SysTick_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_systick_calib_reg_t hri_systick_read_CALIB_reg(const void *const hw) -{ - return ((Systick *)hw)->CALIB.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SysTick_D21_H_INCLUDED */ -#endif /* _SAMD21_SysTick_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_tc_d21.h b/atmel-samd/asf4/samd21/hri/hri_tc_d21.h deleted file mode 100644 index 08058f4f7..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_tc_d21.h +++ /dev/null @@ -1,2190 +0,0 @@ -/** - * \file - * - * \brief SAM TC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_TC_COMPONENT_ -#ifndef _HRI_TC_D21_H_INCLUDED_ -#define _HRI_TC_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TC_CRITICAL_SECTIONS) -#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TC_CRITICAL_SECTION_ENTER() -#define TC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_tc_cc16_reg_t; -typedef uint16_t hri_tc_count16_reg_t; -typedef uint16_t hri_tc_ctrla_reg_t; -typedef uint16_t hri_tc_evctrl_reg_t; -typedef uint16_t hri_tc_readreq_reg_t; -typedef uint32_t hri_tc_cc32_reg_t; -typedef uint32_t hri_tc_count32_reg_t; -typedef uint8_t hri_tc_cc8_reg_t; -typedef uint8_t hri_tc_count8_reg_t; -typedef uint8_t hri_tc_ctrlbset_reg_t; -typedef uint8_t hri_tc_ctrlc_reg_t; -typedef uint8_t hri_tc_dbgctrl_reg_t; -typedef uint8_t hri_tc_intenset_reg_t; -typedef uint8_t hri_tc_intflag_reg_t; -typedef uint8_t hri_tc_per_reg_t; -typedef uint8_t hri_tc_status_reg_t; - -static inline void hri_tc_wait_for_sync(const void *const hw) -{ - while (((const Tc *)hw)->COUNT8.STATUS.bit.SYNCBUSY) - ; -} - -static inline bool hri_tc_is_syncing(const void *const hw) -{ - return ((const Tc *)hw)->COUNT8.STATUS.bit.SYNCBUSY; -} - -static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; - tmp |= TC_COUNT16_COUNT_COUNT(data); - ((Tc *)hw)->COUNT16.COUNT.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tc_count16_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.COUNT.reg; -} - -static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp &= ~TC_COUNT16_CC_CC_Msk; - tmp |= TC_COUNT16_CC_CC(data); - ((Tc *)hw)->COUNT16.CC[index].reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) -{ - return ((Tc *)hw)->COUNT16.CC[index].reg; -} - -static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; - tmp |= TC_COUNT32_COUNT_COUNT(data); - ((Tc *)hw)->COUNT32.COUNT.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tc_count32_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT32.COUNT.reg; -} - -static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp &= ~TC_COUNT32_CC_CC_Msk; - tmp |= TC_COUNT32_CC_CC(data); - ((Tc *)hw)->COUNT32.CC[index].reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) -{ - return ((Tc *)hw)->COUNT32.CC[index].reg; -} - -static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR; -} - -static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; -} - -static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR; - } else { - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR; - } -} - -static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR; -} - -static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; -} - -static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; -} - -static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; - } else { - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; - } -} - -static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; -} - -static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; - tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; - tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(data); - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); -} - -static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); -} - -static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = mask; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.CTRLBSET.reg; -} - -static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = data; - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~data; -} - -static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = mask; -} - -static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF; -} - -static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; -} - -static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF; - } else { - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF; - } -} - -static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF; -} - -static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR; -} - -static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; -} - -static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR; - } else { - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR; - } -} - -static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR; -} - -static inline void hri_tc_set_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_SYNCRDY; -} - -static inline bool hri_tc_get_INTEN_SYNCRDY_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_SYNCRDY) >> TC_INTENSET_SYNCRDY_Pos; -} - -static inline void hri_tc_write_INTEN_SYNCRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_SYNCRDY; - } else { - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_SYNCRDY; - } -} - -static inline void hri_tc_clear_INTEN_SYNCRDY_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_SYNCRDY; -} - -static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0; -} - -static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; -} - -static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0; - } else { - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0; - } -} - -static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0; -} - -static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1; -} - -static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; -} - -static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1; - } else { - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1; - } -} - -static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1; -} - -static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = mask; -} - -static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.INTENSET.reg; -} - -static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = data; - ((Tc *)hw)->COUNT8.INTENCLR.reg = ~data; -} - -static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.INTENCLR.reg = mask; -} - -static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; -} - -static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; -} - -static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; -} - -static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; -} - -static inline bool hri_tc_get_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_SYNCRDY) >> TC_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_tc_clear_INTFLAG_SYNCRDY_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_SYNCRDY; -} - -static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; -} - -static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0; -} - -static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; -} - -static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1; -} - -static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; -} - -static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; -} - -static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; -} - -static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; -} - -static inline bool hri_tc_get_interrupt_SYNCRDY_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_SYNCRDY) >> TC_INTFLAG_SYNCRDY_Pos; -} - -static inline void hri_tc_clear_interrupt_SYNCRDY_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_SYNCRDY; -} - -static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; -} - -static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0; -} - -static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; -} - -static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1; -} - -static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.INTFLAG.reg; -} - -static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = mask; -} - -static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_SWRST; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ENABLE; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_ENABLE; - tmp |= value << TC_CTRLA_ENABLE_Pos; - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ENABLE; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ENABLE; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_RUNSTDBY; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_RUNSTDBY; - tmp |= value << TC_CTRLA_RUNSTDBY_Pos; - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_MODE(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_MODE_Msk; - tmp |= TC_CTRLA_MODE(data); - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_MODE(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_MODE(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_WAVEGEN(mask)) >> TC_CTRLA_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_WAVEGEN_Msk; - tmp |= TC_CTRLA_WAVEGEN(data); - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_WAVEGEN_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_WAVEGEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_WAVEGEN_Msk) >> TC_CTRLA_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_PRESCALER_Msk; - tmp |= TC_CTRLA_PRESCALER(data); - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_PRESCSYNC_Msk; - tmp |= TC_CTRLA_PRESCSYNC(data); - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.CTRLA.reg; -} - -static inline void hri_tc_set_READREQ_RCONT_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg |= TC_READREQ_RCONT; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_READREQ_RCONT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.READREQ.reg; - tmp = (tmp & TC_READREQ_RCONT) >> TC_READREQ_RCONT_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_READREQ_RCONT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.READREQ.reg; - tmp &= ~TC_READREQ_RCONT; - tmp |= value << TC_READREQ_RCONT_Pos; - ((Tc *)hw)->COUNT8.READREQ.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_READREQ_RCONT_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg &= ~TC_READREQ_RCONT; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_READREQ_RCONT_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg ^= TC_READREQ_RCONT; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_READREQ_RREQ_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg |= TC_READREQ_RREQ; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_READREQ_RREQ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.READREQ.reg; - tmp = (tmp & TC_READREQ_RREQ) >> TC_READREQ_RREQ_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_READREQ_RREQ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.READREQ.reg; - tmp &= ~TC_READREQ_RREQ; - tmp |= value << TC_READREQ_RREQ_Pos; - ((Tc *)hw)->COUNT8.READREQ.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_READREQ_RREQ_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg &= ~TC_READREQ_RREQ; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_READREQ_RREQ_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg ^= TC_READREQ_RREQ; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg |= TC_READREQ_ADDR(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_readreq_reg_t hri_tc_get_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.READREQ.reg; - tmp = (tmp & TC_READREQ_ADDR(mask)) >> TC_READREQ_ADDR_Pos; - return tmp; -} - -static inline void hri_tc_write_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.READREQ.reg; - tmp &= ~TC_READREQ_ADDR_Msk; - tmp |= TC_READREQ_ADDR(data); - ((Tc *)hw)->COUNT8.READREQ.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg &= ~TC_READREQ_ADDR(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_READREQ_ADDR_bf(const void *const hw, hri_tc_readreq_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg ^= TC_READREQ_ADDR(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_readreq_reg_t hri_tc_read_READREQ_ADDR_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.READREQ.reg; - tmp = (tmp & TC_READREQ_ADDR_Msk) >> TC_READREQ_ADDR_Pos; - return tmp; -} - -static inline void hri_tc_set_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_readreq_reg_t hri_tc_get_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.READREQ.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_READREQ_reg(const void *const hw, hri_tc_readreq_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.READREQ.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_readreq_reg_t hri_tc_read_READREQ_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.READREQ.reg; -} - -static inline void hri_tc_set_CTRLC_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLC_INVEN0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; - tmp = (tmp & TC_CTRLC_INVEN0) >> TC_CTRLC_INVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLC_INVEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; - tmp &= ~TC_CTRLC_INVEN0; - tmp |= value << TC_CTRLC_INVEN0_Pos; - ((Tc *)hw)->COUNT8.CTRLC.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLC_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLC_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLC_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLC_INVEN1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; - tmp = (tmp & TC_CTRLC_INVEN1) >> TC_CTRLC_INVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLC_INVEN1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; - tmp &= ~TC_CTRLC_INVEN1; - tmp |= value << TC_CTRLC_INVEN1_Pos; - ((Tc *)hw)->COUNT8.CTRLC.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLC_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLC_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLC_CPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_CPTEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLC_CPTEN0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; - tmp = (tmp & TC_CTRLC_CPTEN0) >> TC_CTRLC_CPTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLC_CPTEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; - tmp &= ~TC_CTRLC_CPTEN0; - tmp |= value << TC_CTRLC_CPTEN0_Pos; - ((Tc *)hw)->COUNT8.CTRLC.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLC_CPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_CPTEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLC_CPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_CPTEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLC_CPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg |= TC_CTRLC_CPTEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLC_CPTEN1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; - tmp = (tmp & TC_CTRLC_CPTEN1) >> TC_CTRLC_CPTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLC_CPTEN1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; - tmp &= ~TC_CTRLC_CPTEN1; - tmp |= value << TC_CTRLC_CPTEN1_Pos; - ((Tc *)hw)->COUNT8.CTRLC.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLC_CPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg &= ~TC_CTRLC_CPTEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLC_CPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg ^= TC_CTRLC_CPTEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrlc_reg_t hri_tc_get_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLC_reg(const void *const hw, hri_tc_ctrlc_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLC.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrlc_reg_t hri_tc_read_CTRLC_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.CTRLC.reg; -} - -static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; - tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; - tmp &= ~TC_DBGCTRL_DBGRUN; - tmp |= value << TC_DBGCTRL_DBGRUN_Pos; - ((Tc *)hw)->COUNT8.DBGCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.DBGCTRL.reg; -} - -static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_TCINV; - tmp |= value << TC_EVCTRL_TCINV_Pos; - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_TCEI; - tmp |= value << TC_EVCTRL_TCEI_Pos; - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_OVFEO; - tmp |= value << TC_EVCTRL_OVFEO_Pos; - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_MCEO0; - tmp |= value << TC_EVCTRL_MCEO0_Pos; - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_MCEO1; - tmp |= value << TC_EVCTRL_MCEO1_Pos; - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_EVACT_Msk; - tmp |= TC_EVCTRL_EVACT(data); - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.EVCTRL.reg; -} - -static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; - tmp |= TC_COUNT8_COUNT_COUNT(data); - ((Tc *)hw)->COUNT8.COUNT.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tc_count8_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.COUNT.reg; -} - -static inline void hri_tc_set_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_per_reg_t hri_tc_get_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; - return tmp; -} - -static inline void hri_tc_write_PER_PER_bf(const void *const hw, hri_tc_per_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp &= ~TC_COUNT8_PER_PER_Msk; - tmp |= TC_COUNT8_PER_PER(data); - ((Tc *)hw)->COUNT8.PER.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_per_reg_t hri_tc_read_PER_PER_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; - return tmp; -} - -static inline void hri_tc_set_PER_reg(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_per_reg_t hri_tc_get_PER_reg(const void *const hw, hri_tc_per_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_PER_reg(const void *const hw, hri_tc_per_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_PER_reg(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_PER_reg(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_per_reg_t hri_tc_read_PER_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.PER.reg; -} - -static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp &= ~TC_COUNT8_CC_CC_Msk; - tmp |= TC_COUNT8_CC_CC(data); - ((Tc *)hw)->COUNT8.CC[index].reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) -{ - return ((Tc *)hw)->COUNT8.CC[index].reg; -} - -static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; -} - -static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; -} - -static inline bool hri_tc_get_STATUS_SYNCBUSY_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_SYNCBUSY) >> TC_STATUS_SYNCBUSY_Pos; -} - -static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TC_D21_H_INCLUDED */ -#endif /* _SAMD21_TC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_tcc_d21.h b/atmel-samd/asf4/samd21/hri/hri_tcc_d21.h deleted file mode 100644 index 051c8c821..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_tcc_d21.h +++ /dev/null @@ -1,10318 +0,0 @@ -/** - * \file - * - * \brief SAM TCC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_TCC_COMPONENT_ -#ifndef _HRI_TCC_D21_H_INCLUDED_ -#define _HRI_TCC_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TCC_CRITICAL_SECTIONS) -#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TCC_CRITICAL_SECTION_ENTER() -#define TCC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_tcc_patt_reg_t; -typedef uint16_t hri_tcc_pattb_reg_t; -typedef uint32_t hri_tcc_cc_reg_t; -typedef uint32_t hri_tcc_ccb_reg_t; -typedef uint32_t hri_tcc_count_reg_t; -typedef uint32_t hri_tcc_ctrla_reg_t; -typedef uint32_t hri_tcc_drvctrl_reg_t; -typedef uint32_t hri_tcc_evctrl_reg_t; -typedef uint32_t hri_tcc_fctrla_reg_t; -typedef uint32_t hri_tcc_fctrlb_reg_t; -typedef uint32_t hri_tcc_intenset_reg_t; -typedef uint32_t hri_tcc_intflag_reg_t; -typedef uint32_t hri_tcc_per_reg_t; -typedef uint32_t hri_tcc_perb_reg_t; -typedef uint32_t hri_tcc_status_reg_t; -typedef uint32_t hri_tcc_syncbusy_reg_t; -typedef uint32_t hri_tcc_wave_reg_t; -typedef uint32_t hri_tcc_waveb_reg_t; -typedef uint32_t hri_tcc_wexctrl_reg_t; -typedef uint8_t hri_tcc_ctrlbset_reg_t; -typedef uint8_t hri_tcc_dbgctrl_reg_t; - -static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) -{ - while (((Tcc *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) -{ - return ((Tcc *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH4_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH4_COUNT(mask)) >> TCC_COUNT_DITH4_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_DITH4_COUNT_Msk; - tmp |= TCC_COUNT_DITH4_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH4_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH4_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH4_COUNT_Msk) >> TCC_COUNT_DITH4_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH5_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH5_COUNT(mask)) >> TCC_COUNT_DITH5_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_DITH5_COUNT_Msk; - tmp |= TCC_COUNT_DITH5_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH5_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH5_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH5_COUNT_Msk) >> TCC_COUNT_DITH5_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH6_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH6_COUNT(mask)) >> TCC_COUNT_DITH6_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_DITH6_COUNT_Msk; - tmp |= TCC_COUNT_DITH6_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH6_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH6_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH6_COUNT_Msk) >> TCC_COUNT_DITH6_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_reg(const void *const hw) -{ - return ((Tcc *)hw)->COUNT.reg; -} - -static inline void hri_tcc_set_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_reg(const void *const hw) -{ - return ((Tcc *)hw)->COUNT.reg; -} - -static inline void hri_tcc_set_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_reg(const void *const hw) -{ - return ((Tcc *)hw)->COUNT.reg; -} - -static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) -{ - return ((Tcc *)hw)->COUNT.reg; -} - -static inline void hri_tcc_set_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_DITHERCY(mask)) >> TCC_PER_DITH4_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH4_DITHERCY_Msk; - tmp |= TCC_PER_DITH4_DITHERCY(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHERCY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_DITHERCY_Msk) >> TCC_PER_DITH4_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_PER(mask)) >> TCC_PER_DITH4_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH4_PER_Msk; - tmp |= TCC_PER_DITH4_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_PER_Msk) >> TCC_PER_DITH4_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_DITHERCY(mask)) >> TCC_PER_DITH5_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH5_DITHERCY_Msk; - tmp |= TCC_PER_DITH5_DITHERCY(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHERCY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_DITHERCY_Msk) >> TCC_PER_DITH5_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_PER(mask)) >> TCC_PER_DITH5_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH5_PER_Msk; - tmp |= TCC_PER_DITH5_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_PER_Msk) >> TCC_PER_DITH5_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_DITHERCY(mask)) >> TCC_PER_DITH6_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH6_DITHERCY_Msk; - tmp |= TCC_PER_DITH6_DITHERCY(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_DITHERCY_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHERCY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_DITHERCY_Msk) >> TCC_PER_DITH6_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_PER(mask)) >> TCC_PER_DITH6_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH6_PER_Msk; - tmp |= TCC_PER_DITH6_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_PER_Msk) >> TCC_PER_DITH6_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_reg(const void *const hw) -{ - return ((Tcc *)hw)->PER.reg; -} - -static inline void hri_tcc_set_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_reg(const void *const hw) -{ - return ((Tcc *)hw)->PER.reg; -} - -static inline void hri_tcc_set_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_reg(const void *const hw) -{ - return ((Tcc *)hw)->PER.reg; -} - -static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) -{ - return ((Tcc *)hw)->PER.reg; -} - -static inline void hri_tcc_set_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_DITHERCY(mask)) >> TCC_CC_DITH4_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH4_DITHERCY_Msk; - tmp |= TCC_CC_DITH4_DITHERCY(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHERCY_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_DITHERCY_Msk) >> TCC_CC_DITH4_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_CC(mask)) >> TCC_CC_DITH4_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH4_CC_Msk; - tmp |= TCC_CC_DITH4_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_CC_Msk) >> TCC_CC_DITH4_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_DITHERCY(mask)) >> TCC_CC_DITH5_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH5_DITHERCY_Msk; - tmp |= TCC_CC_DITH5_DITHERCY(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHERCY_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_DITHERCY_Msk) >> TCC_CC_DITH5_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_CC(mask)) >> TCC_CC_DITH5_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH5_CC_Msk; - tmp |= TCC_CC_DITH5_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_CC_Msk) >> TCC_CC_DITH5_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_DITHERCY(mask)) >> TCC_CC_DITH6_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH6_DITHERCY_Msk; - tmp |= TCC_CC_DITH6_DITHERCY(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHERCY(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHERCY_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_DITHERCY_Msk) >> TCC_CC_DITH6_DITHERCY_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_CC(mask)) >> TCC_CC_DITH6_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH6_CC_Msk; - tmp |= TCC_CC_DITH6_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_CC_Msk) >> TCC_CC_DITH6_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CC[index].reg; -} - -static inline void hri_tcc_set_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CC[index].reg; -} - -static inline void hri_tcc_set_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CC[index].reg; -} - -static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CC[index].reg; -} - -static inline void hri_tcc_set_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH4_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH4_DITHERCYB(mask)) >> TCC_PERB_DITH4_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERB.reg; - tmp &= ~TCC_PERB_DITH4_DITHERCYB_Msk; - tmp |= TCC_PERB_DITH4_DITHERCYB(data); - ((Tcc *)hw)->PERB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH4_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERB_DITH4_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH4_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH4_DITHERCYB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH4_DITHERCYB_Msk) >> TCC_PERB_DITH4_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH4_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH4_PERB(mask)) >> TCC_PERB_DITH4_PERB_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERB.reg; - tmp &= ~TCC_PERB_DITH4_PERB_Msk; - tmp |= TCC_PERB_DITH4_PERB(data); - ((Tcc *)hw)->PERB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH4_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERB_DITH4_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH4_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH4_PERB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH4_PERB_Msk) >> TCC_PERB_DITH4_PERB_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH5_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH5_DITHERCYB(mask)) >> TCC_PERB_DITH5_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERB.reg; - tmp &= ~TCC_PERB_DITH5_DITHERCYB_Msk; - tmp |= TCC_PERB_DITH5_DITHERCYB(data); - ((Tcc *)hw)->PERB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH5_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERB_DITH5_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH5_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH5_DITHERCYB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH5_DITHERCYB_Msk) >> TCC_PERB_DITH5_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH5_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH5_PERB(mask)) >> TCC_PERB_DITH5_PERB_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERB.reg; - tmp &= ~TCC_PERB_DITH5_PERB_Msk; - tmp |= TCC_PERB_DITH5_PERB(data); - ((Tcc *)hw)->PERB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH5_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERB_DITH5_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH5_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH5_PERB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH5_PERB_Msk) >> TCC_PERB_DITH5_PERB_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH6_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH6_DITHERCYB(mask)) >> TCC_PERB_DITH6_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERB.reg; - tmp &= ~TCC_PERB_DITH6_DITHERCYB_Msk; - tmp |= TCC_PERB_DITH6_DITHERCYB(data); - ((Tcc *)hw)->PERB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH6_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERB_DITH6_DITHERCYB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH6_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH6_DITHERCYB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH6_DITHERCYB_Msk) >> TCC_PERB_DITH6_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg |= TCC_PERB_DITH6_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH6_PERB(mask)) >> TCC_PERB_DITH6_PERB_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERB.reg; - tmp &= ~TCC_PERB_DITH6_PERB_Msk; - tmp |= TCC_PERB_DITH6_PERB(data); - ((Tcc *)hw)->PERB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_DITH6_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERB_DITH6_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg ^= TCC_PERB_DITH6_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH6_PERB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_DITH6_PERB_Msk) >> TCC_PERB_DITH6_PERB_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg |= TCC_PERB_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_PERB(mask)) >> TCC_PERB_PERB_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERB.reg; - tmp &= ~TCC_PERB_PERB_Msk; - tmp |= TCC_PERB_PERB(data); - ((Tcc *)hw)->PERB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg &= ~TCC_PERB_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERB_PERB_bf(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg ^= TCC_PERB_PERB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_PERB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp = (tmp & TCC_PERB_PERB_Msk) >> TCC_PERB_PERB_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERB_DITH4_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH4_reg(const void *const hw) -{ - return ((Tcc *)hw)->PERB.reg; -} - -static inline void hri_tcc_set_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERB_DITH5_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH5_reg(const void *const hw) -{ - return ((Tcc *)hw)->PERB.reg; -} - -static inline void hri_tcc_set_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERB_DITH6_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_DITH6_reg(const void *const hw) -{ - return ((Tcc *)hw)->PERB.reg; -} - -static inline void hri_tcc_set_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_get_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PERB_reg(const void *const hw, hri_tcc_perb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERB_reg(const void *const hw, hri_tcc_perb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERB.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perb_reg_t hri_tcc_read_PERB_reg(const void *const hw) -{ - return ((Tcc *)hw)->PERB.reg; -} - -static inline void hri_tcc_set_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH4_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, - hri_tcc_ccb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH4_DITHERCYB(mask)) >> TCC_CCB_DITH4_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp &= ~TCC_CCB_DITH4_DITHERCYB_Msk; - tmp |= TCC_CCB_DITH4_DITHERCYB(data); - ((Tcc *)hw)->CCB[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH4_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH4_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH4_DITHERCYB_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH4_DITHERCYB_Msk) >> TCC_CCB_DITH4_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH4_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, - hri_tcc_ccb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH4_CCB(mask)) >> TCC_CCB_DITH4_CCB_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp &= ~TCC_CCB_DITH4_CCB_Msk; - tmp |= TCC_CCB_DITH4_CCB(data); - ((Tcc *)hw)->CCB[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH4_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH4_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH4_CCB_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH4_CCB_Msk) >> TCC_CCB_DITH4_CCB_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH5_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, - hri_tcc_ccb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH5_DITHERCYB(mask)) >> TCC_CCB_DITH5_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp &= ~TCC_CCB_DITH5_DITHERCYB_Msk; - tmp |= TCC_CCB_DITH5_DITHERCYB(data); - ((Tcc *)hw)->CCB[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH5_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH5_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH5_DITHERCYB_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH5_DITHERCYB_Msk) >> TCC_CCB_DITH5_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH5_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, - hri_tcc_ccb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH5_CCB(mask)) >> TCC_CCB_DITH5_CCB_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp &= ~TCC_CCB_DITH5_CCB_Msk; - tmp |= TCC_CCB_DITH5_CCB(data); - ((Tcc *)hw)->CCB[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH5_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH5_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH5_CCB_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH5_CCB_Msk) >> TCC_CCB_DITH5_CCB_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH6_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, - hri_tcc_ccb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH6_DITHERCYB(mask)) >> TCC_CCB_DITH6_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp &= ~TCC_CCB_DITH6_DITHERCYB_Msk; - tmp |= TCC_CCB_DITH6_DITHERCYB(data); - ((Tcc *)hw)->CCB[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH6_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH6_DITHERCYB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH6_DITHERCYB_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH6_DITHERCYB_Msk) >> TCC_CCB_DITH6_DITHERCYB_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_DITH6_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, - hri_tcc_ccb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH6_CCB(mask)) >> TCC_CCB_DITH6_CCB_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp &= ~TCC_CCB_DITH6_CCB_Msk; - tmp |= TCC_CCB_DITH6_CCB(data); - ((Tcc *)hw)->CCB[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_DITH6_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_DITH6_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH6_CCB_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_DITH6_CCB_Msk) >> TCC_CCB_DITH6_CCB_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg |= TCC_CCB_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_CCB(mask)) >> TCC_CCB_CCB_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp &= ~TCC_CCB_CCB_Msk; - tmp |= TCC_CCB_CCB(data); - ((Tcc *)hw)->CCB[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg &= ~TCC_CCB_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCB_CCB_bf(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg ^= TCC_CCB_CCB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_CCB_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp = (tmp & TCC_CCB_CCB_Msk) >> TCC_CCB_CCB_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCB_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH4_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CCB[index].reg; -} - -static inline void hri_tcc_set_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCB_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH5_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CCB[index].reg; -} - -static inline void hri_tcc_set_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCB_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_DITH6_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CCB[index].reg; -} - -static inline void hri_tcc_set_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_get_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCB[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCB_reg(const void *const hw, uint8_t index, hri_tcc_ccb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCB[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccb_reg_t hri_tcc_read_CCB_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CCB[index].reg; -} - -static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; -} - -static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; -} - -static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; - } -} - -static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; -} - -static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; -} - -static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; - } -} - -static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; -} - -static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; -} - -static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; -} - -static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; - } -} - -static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; -} - -static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); - ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); -} - -static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); -} - -static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); - ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); -} - -static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); -} - -static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = mask; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) -{ - return ((Tcc *)hw)->CTRLBSET.reg; -} - -static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = data; - ((Tcc *)hw)->CTRLBCLR.reg = ~data; -} - -static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = mask; -} - -static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; -} - -static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; -} - -static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; - } -} - -static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; -} - -static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; -} - -static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; -} - -static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; - } -} - -static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; -} - -static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; -} - -static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; -} - -static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; - } -} - -static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; -} - -static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; -} - -static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; -} - -static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; - } -} - -static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; -} - -static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; -} - -static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; -} - -static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; - } -} - -static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; -} - -static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; -} - -static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; - } -} - -static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; -} - -static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; -} - -static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; - } -} - -static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; -} - -static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; -} - -static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; - } -} - -static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; -} - -static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; -} - -static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; - } -} - -static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; -} - -static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; -} - -static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; -} - -static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; - } -} - -static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; -} - -static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; -} - -static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; -} - -static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; - } -} - -static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; -} - -static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; -} - -static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; -} - -static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; - } -} - -static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; -} - -static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; -} - -static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; -} - -static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; - } -} - -static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; -} - -static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - ((Tcc *)hw)->INTENSET.reg = mask; -} - -static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) -{ - return ((Tcc *)hw)->INTENSET.reg; -} - -static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) -{ - ((Tcc *)hw)->INTENSET.reg = data; - ((Tcc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - ((Tcc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; -} - -static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; -} - -static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; -} - -static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; -} - -static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; -} - -static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; -} - -static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; -} - -static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; -} - -static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; -} - -static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; -} - -static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; -} - -static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; -} - -static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; -} - -static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; -} - -static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; -} - -static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; -} - -static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; -} - -static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; -} - -static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; -} - -static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; -} - -static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; -} - -static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; -} - -static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; -} - -static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; -} - -static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; -} - -static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; -} - -static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; -} - -static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; -} - -static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; -} - -static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; -} - -static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; -} - -static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) -{ - return ((Tcc *)hw)->INTFLAG.reg; -} - -static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) -{ - ((Tcc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_ENABLE; - tmp |= value << TCC_CTRLA_ENABLE_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_RUNSTDBY; - tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_ALOCK; - tmp |= value << TCC_CTRLA_ALOCK_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN0; - tmp |= value << TCC_CTRLA_CPTEN0_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN1; - tmp |= value << TCC_CTRLA_CPTEN1_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN2; - tmp |= value << TCC_CTRLA_CPTEN2_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN3; - tmp |= value << TCC_CTRLA_CPTEN3_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_RESOLUTION_Msk; - tmp |= TCC_CTRLA_RESOLUTION(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_PRESCALER_Msk; - tmp |= TCC_CTRLA_PRESCALER(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; - tmp |= TCC_CTRLA_PRESCSYNC(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) -{ - return ((Tcc *)hw)->CTRLA.reg; -} - -static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_KEEP; - tmp |= value << TCC_FCTRLA_KEEP_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_QUAL; - tmp |= value << TCC_FCTRLA_QUAL_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_RESTART; - tmp |= value << TCC_FCTRLA_RESTART_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_SRC_Msk; - tmp |= TCC_FCTRLA_SRC(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANK_Msk; - tmp |= TCC_FCTRLA_BLANK(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_HALT_Msk; - tmp |= TCC_FCTRLA_HALT(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_CHSEL_Msk; - tmp |= TCC_FCTRLA_CHSEL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_CAPTURE_Msk; - tmp |= TCC_FCTRLA_CAPTURE(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; - tmp |= TCC_FCTRLA_BLANKVAL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; - tmp |= TCC_FCTRLA_FILTERVAL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) -{ - return ((Tcc *)hw)->FCTRLA.reg; -} - -static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_KEEP; - tmp |= value << TCC_FCTRLB_KEEP_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_QUAL; - tmp |= value << TCC_FCTRLB_QUAL_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_RESTART; - tmp |= value << TCC_FCTRLB_RESTART_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_SRC_Msk; - tmp |= TCC_FCTRLB_SRC(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANK_Msk; - tmp |= TCC_FCTRLB_BLANK(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_HALT_Msk; - tmp |= TCC_FCTRLB_HALT(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_CHSEL_Msk; - tmp |= TCC_FCTRLB_CHSEL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_CAPTURE_Msk; - tmp |= TCC_FCTRLB_CAPTURE(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; - tmp |= TCC_FCTRLB_BLANKVAL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; - tmp |= TCC_FCTRLB_FILTERVAL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) -{ - return ((Tcc *)hw)->FCTRLB.reg; -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN0; - tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN1; - tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN2; - tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN3; - tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_OTMX_Msk; - tmp |= TCC_WEXCTRL_OTMX(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTLS_Msk; - tmp |= TCC_WEXCTRL_DTLS(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTHS_Msk; - tmp |= TCC_WEXCTRL_DTHS(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->WEXCTRL.reg; -} - -static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE0; - tmp |= value << TCC_DRVCTRL_NRE0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE1; - tmp |= value << TCC_DRVCTRL_NRE1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE2; - tmp |= value << TCC_DRVCTRL_NRE2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE3; - tmp |= value << TCC_DRVCTRL_NRE3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE4; - tmp |= value << TCC_DRVCTRL_NRE4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE5; - tmp |= value << TCC_DRVCTRL_NRE5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE6; - tmp |= value << TCC_DRVCTRL_NRE6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE7; - tmp |= value << TCC_DRVCTRL_NRE7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV0; - tmp |= value << TCC_DRVCTRL_NRV0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV1; - tmp |= value << TCC_DRVCTRL_NRV1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV2; - tmp |= value << TCC_DRVCTRL_NRV2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV3; - tmp |= value << TCC_DRVCTRL_NRV3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV4; - tmp |= value << TCC_DRVCTRL_NRV4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV5; - tmp |= value << TCC_DRVCTRL_NRV5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV6; - tmp |= value << TCC_DRVCTRL_NRV6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV7; - tmp |= value << TCC_DRVCTRL_NRV7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN0; - tmp |= value << TCC_DRVCTRL_INVEN0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN1; - tmp |= value << TCC_DRVCTRL_INVEN1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN2; - tmp |= value << TCC_DRVCTRL_INVEN2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN3; - tmp |= value << TCC_DRVCTRL_INVEN3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN4; - tmp |= value << TCC_DRVCTRL_INVEN4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN5; - tmp |= value << TCC_DRVCTRL_INVEN5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN6; - tmp |= value << TCC_DRVCTRL_INVEN6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN7; - tmp |= value << TCC_DRVCTRL_INVEN7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; - tmp |= TCC_DRVCTRL_FILTERVAL0(data); - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; - return tmp; -} - -static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; - tmp |= TCC_DRVCTRL_FILTERVAL1(data); - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; - return tmp; -} - -static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->DRVCTRL.reg; -} - -static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= ~TCC_DBGCTRL_DBGRUN; - tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; - ((Tcc *)hw)->DBGCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= ~TCC_DBGCTRL_FDDBD; - tmp |= value << TCC_DBGCTRL_FDDBD_Pos; - ((Tcc *)hw)->DBGCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->DBGCTRL.reg; -} - -static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_OVFEO; - tmp |= value << TCC_EVCTRL_OVFEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TRGEO; - tmp |= value << TCC_EVCTRL_TRGEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_CNTEO; - tmp |= value << TCC_EVCTRL_CNTEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCINV0; - tmp |= value << TCC_EVCTRL_TCINV0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCINV1; - tmp |= value << TCC_EVCTRL_TCINV1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCEI0; - tmp |= value << TCC_EVCTRL_TCEI0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCEI1; - tmp |= value << TCC_EVCTRL_TCEI1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI0; - tmp |= value << TCC_EVCTRL_MCEI0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI1; - tmp |= value << TCC_EVCTRL_MCEI1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI2; - tmp |= value << TCC_EVCTRL_MCEI2_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI3; - tmp |= value << TCC_EVCTRL_MCEI3_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO0; - tmp |= value << TCC_EVCTRL_MCEO0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO1; - tmp |= value << TCC_EVCTRL_MCEO1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO2; - tmp |= value << TCC_EVCTRL_MCEO2_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO3; - tmp |= value << TCC_EVCTRL_MCEO3_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_EVACT0_Msk; - tmp |= TCC_EVCTRL_EVACT0(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_EVACT1_Msk; - tmp |= TCC_EVCTRL_EVACT1(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_CNTSEL_Msk; - tmp |= TCC_EVCTRL_CNTSEL(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->EVCTRL.reg; -} - -static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE0; - tmp |= value << TCC_PATT_PGE0_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE1; - tmp |= value << TCC_PATT_PGE1_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE2; - tmp |= value << TCC_PATT_PGE2_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE3; - tmp |= value << TCC_PATT_PGE3_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE4; - tmp |= value << TCC_PATT_PGE4_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE5; - tmp |= value << TCC_PATT_PGE5_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE6; - tmp |= value << TCC_PATT_PGE6_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE7; - tmp |= value << TCC_PATT_PGE7_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV0; - tmp |= value << TCC_PATT_PGV0_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV1; - tmp |= value << TCC_PATT_PGV1_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV2; - tmp |= value << TCC_PATT_PGV2_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV3; - tmp |= value << TCC_PATT_PGV3_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV4; - tmp |= value << TCC_PATT_PGV4_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV5; - tmp |= value << TCC_PATT_PGV5_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV6; - tmp |= value << TCC_PATT_PGV6_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV7; - tmp |= value << TCC_PATT_PGV7_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) -{ - return ((Tcc *)hw)->PATT.reg; -} - -static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CIPEREN; - tmp |= value << TCC_WAVE_CIPEREN_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN0; - tmp |= value << TCC_WAVE_CICCEN0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN1; - tmp |= value << TCC_WAVE_CICCEN1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN2; - tmp |= value << TCC_WAVE_CICCEN2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN3; - tmp |= value << TCC_WAVE_CICCEN3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL0; - tmp |= value << TCC_WAVE_POL0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL1; - tmp |= value << TCC_WAVE_POL1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL2; - tmp |= value << TCC_WAVE_POL2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL3; - tmp |= value << TCC_WAVE_POL3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP0; - tmp |= value << TCC_WAVE_SWAP0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP1; - tmp |= value << TCC_WAVE_SWAP1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP2; - tmp |= value << TCC_WAVE_SWAP2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP3; - tmp |= value << TCC_WAVE_SWAP3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_WAVEGEN_Msk; - tmp |= TCC_WAVE_WAVEGEN(data); - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_RAMP_Msk; - tmp |= TCC_WAVE_RAMP(data); - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) -{ - return ((Tcc *)hw)->WAVE.reg; -} - -static inline void hri_tcc_set_PATTB_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGEB0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGEB0) >> TCC_PATTB_PGEB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGEB0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGEB0; - tmp |= value << TCC_PATTB_PGEB0_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGEB1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGEB1) >> TCC_PATTB_PGEB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGEB1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGEB1; - tmp |= value << TCC_PATTB_PGEB1_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGEB2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGEB2) >> TCC_PATTB_PGEB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGEB2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGEB2; - tmp |= value << TCC_PATTB_PGEB2_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGEB3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGEB3) >> TCC_PATTB_PGEB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGEB3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGEB3; - tmp |= value << TCC_PATTB_PGEB3_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGEB4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGEB4) >> TCC_PATTB_PGEB4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGEB4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGEB4; - tmp |= value << TCC_PATTB_PGEB4_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGEB5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGEB5) >> TCC_PATTB_PGEB5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGEB5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGEB5; - tmp |= value << TCC_PATTB_PGEB5_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGEB6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGEB6) >> TCC_PATTB_PGEB6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGEB6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGEB6; - tmp |= value << TCC_PATTB_PGEB6_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGEB7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGEB7) >> TCC_PATTB_PGEB7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGEB7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGEB7; - tmp |= value << TCC_PATTB_PGEB7_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGVB0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGVB0) >> TCC_PATTB_PGVB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGVB0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGVB0; - tmp |= value << TCC_PATTB_PGVB0_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGVB1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGVB1) >> TCC_PATTB_PGVB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGVB1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGVB1; - tmp |= value << TCC_PATTB_PGVB1_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGVB2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGVB2) >> TCC_PATTB_PGVB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGVB2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGVB2; - tmp |= value << TCC_PATTB_PGVB2_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGVB3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGVB3) >> TCC_PATTB_PGVB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGVB3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGVB3; - tmp |= value << TCC_PATTB_PGVB3_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGVB4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGVB4) >> TCC_PATTB_PGVB4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGVB4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGVB4; - tmp |= value << TCC_PATTB_PGVB4_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGVB5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGVB5) >> TCC_PATTB_PGVB5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGVB5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGVB5; - tmp |= value << TCC_PATTB_PGVB5_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGVB6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGVB6) >> TCC_PATTB_PGVB6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGVB6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGVB6; - tmp |= value << TCC_PATTB_PGVB6_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= TCC_PATTB_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTB_PGVB7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp = (tmp & TCC_PATTB_PGVB7) >> TCC_PATTB_PGVB7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTB_PGVB7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= ~TCC_PATTB_PGVB7; - tmp |= value << TCC_PATTB_PGVB7_Pos; - ((Tcc *)hw)->PATTB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~TCC_PATTB_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= TCC_PATTB_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_pattb_reg_t hri_tcc_get_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTB_reg(const void *const hw, hri_tcc_pattb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTB.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_pattb_reg_t hri_tcc_read_PATTB_reg(const void *const hw) -{ - return ((Tcc *)hw)->PATTB.reg; -} - -static inline void hri_tcc_set_WAVEB_CIPERENB_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CIPERENB; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_CIPERENB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_CIPERENB) >> TCC_WAVEB_CIPERENB_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_CIPERENB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_CIPERENB; - tmp |= value << TCC_WAVEB_CIPERENB_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_CIPERENB_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CIPERENB; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_CIPERENB_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CIPERENB; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_CICCENB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_CICCENB0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_CICCENB0) >> TCC_WAVEB_CICCENB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_CICCENB0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_CICCENB0; - tmp |= value << TCC_WAVEB_CICCENB0_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_CICCENB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_CICCENB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_CICCENB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_CICCENB1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_CICCENB1) >> TCC_WAVEB_CICCENB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_CICCENB1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_CICCENB1; - tmp |= value << TCC_WAVEB_CICCENB1_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_CICCENB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_CICCENB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_CICCENB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_CICCENB2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_CICCENB2) >> TCC_WAVEB_CICCENB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_CICCENB2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_CICCENB2; - tmp |= value << TCC_WAVEB_CICCENB2_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_CICCENB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_CICCENB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_CICCENB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_CICCENB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_CICCENB3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_CICCENB3) >> TCC_WAVEB_CICCENB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_CICCENB3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_CICCENB3; - tmp |= value << TCC_WAVEB_CICCENB3_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_CICCENB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_CICCENB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_CICCENB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_CICCENB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_POLB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_POLB0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_POLB0) >> TCC_WAVEB_POLB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_POLB0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_POLB0; - tmp |= value << TCC_WAVEB_POLB0_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_POLB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_POLB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_POLB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_POLB1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_POLB1) >> TCC_WAVEB_POLB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_POLB1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_POLB1; - tmp |= value << TCC_WAVEB_POLB1_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_POLB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_POLB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_POLB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_POLB2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_POLB2) >> TCC_WAVEB_POLB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_POLB2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_POLB2; - tmp |= value << TCC_WAVEB_POLB2_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_POLB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_POLB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_POLB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_POLB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_POLB3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_POLB3) >> TCC_WAVEB_POLB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_POLB3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_POLB3; - tmp |= value << TCC_WAVEB_POLB3_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_POLB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_POLB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_POLB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_POLB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_SWAPB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_SWAPB0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_SWAPB0) >> TCC_WAVEB_SWAPB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_SWAPB0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_SWAPB0; - tmp |= value << TCC_WAVEB_SWAPB0_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_SWAPB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_SWAPB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_SWAPB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_SWAPB1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_SWAPB1) >> TCC_WAVEB_SWAPB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_SWAPB1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_SWAPB1; - tmp |= value << TCC_WAVEB_SWAPB1_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_SWAPB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_SWAPB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_SWAPB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_SWAPB2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_SWAPB2) >> TCC_WAVEB_SWAPB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_SWAPB2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_SWAPB2; - tmp |= value << TCC_WAVEB_SWAPB2_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_SWAPB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_SWAPB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_SWAPB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_SWAPB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVEB_SWAPB3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_SWAPB3) >> TCC_WAVEB_SWAPB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVEB_SWAPB3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_SWAPB3; - tmp |= value << TCC_WAVEB_SWAPB3_Pos; - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_SWAPB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_SWAPB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_SWAPB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_SWAPB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_WAVEGENB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_waveb_reg_t hri_tcc_get_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_WAVEGENB(mask)) >> TCC_WAVEB_WAVEGENB_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_WAVEGENB_Msk; - tmp |= TCC_WAVEB_WAVEGENB(data); - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_WAVEGENB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_WAVEGENB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_WAVEGENB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_waveb_reg_t hri_tcc_read_WAVEB_WAVEGENB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_WAVEGENB_Msk) >> TCC_WAVEB_WAVEGENB_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= TCC_WAVEB_RAMPB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_waveb_reg_t hri_tcc_get_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_RAMPB(mask)) >> TCC_WAVEB_RAMPB_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= ~TCC_WAVEB_RAMPB_Msk; - tmp |= TCC_WAVEB_RAMPB(data); - ((Tcc *)hw)->WAVEB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~TCC_WAVEB_RAMPB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_RAMPB_bf(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= TCC_WAVEB_RAMPB(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_waveb_reg_t hri_tcc_read_WAVEB_RAMPB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp = (tmp & TCC_WAVEB_RAMPB_Msk) >> TCC_WAVEB_RAMPB_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_waveb_reg_t hri_tcc_get_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVEB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVEB_reg(const void *const hw, hri_tcc_waveb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVEB.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_waveb_reg_t hri_tcc_read_WAVEB_reg(const void *const hw) -{ - return ((Tcc *)hw)->WAVEB.reg; -} - -static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PATTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATTB) >> TCC_SYNCBUSY_PATTB_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_WAVEB_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVEB) >> TCC_SYNCBUSY_WAVEB_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PERB_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PERB) >> TCC_SYNCBUSY_PERB_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CCB0_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB0) >> TCC_SYNCBUSY_CCB0_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CCB1_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB1) >> TCC_SYNCBUSY_CCB1_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CCB2_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB2) >> TCC_SYNCBUSY_CCB2_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CCB3_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CCB3) >> TCC_SYNCBUSY_CCB3_Pos; -} - -static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Tcc *)hw)->SYNCBUSY.reg; -} - -static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; -} - -static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; -} - -static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; -} - -static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; -} - -static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_PATTBV_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBV) >> TCC_STATUS_PATTBV_Pos; -} - -static inline void hri_tcc_clear_STATUS_PATTBV_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBV; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_WAVEBV_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_WAVEBV) >> TCC_STATUS_WAVEBV_Pos; -} - -static inline void hri_tcc_clear_STATUS_WAVEBV_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_WAVEBV; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_PERBV_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBV) >> TCC_STATUS_PERBV_Pos; -} - -static inline void hri_tcc_clear_STATUS_PERBV_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBV; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBV0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV0) >> TCC_STATUS_CCBV0_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBV1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV1) >> TCC_STATUS_CCBV1_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBV2_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV2) >> TCC_STATUS_CCBV2_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBV3_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBV3) >> TCC_STATUS_CCBV3_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) -{ - return ((Tcc *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TCC_D21_H_INCLUDED */ -#endif /* _SAMD21_TCC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_usb_d21.h b/atmel-samd/asf4/samd21/hri/hri_usb_d21.h deleted file mode 100644 index f0aa01f37..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_usb_d21.h +++ /dev/null @@ -1,9811 +0,0 @@ -/** - * \file - * - * \brief SAM USB - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_USB_COMPONENT_ -#ifndef _HRI_USB_D21_H_INCLUDED_ -#define _HRI_USB_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_USB_CRITICAL_SECTIONS) -#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define USB_CRITICAL_SECTION_ENTER() -#define USB_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; -typedef uint16_t hri_usbdesc_bank_extreg_reg_t; -typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; -typedef uint16_t hri_usbdevice_ctrlb_reg_t; -typedef uint16_t hri_usbdevice_descriptor_extreg_reg_t; -typedef uint16_t hri_usbdevice_epintsmry_reg_t; -typedef uint16_t hri_usbdevice_fnum_reg_t; -typedef uint16_t hri_usbdevice_intenset_reg_t; -typedef uint16_t hri_usbdevice_intflag_reg_t; -typedef uint16_t hri_usbdevice_padcal_reg_t; -typedef uint16_t hri_usbhost_ctrlb_reg_t; -typedef uint16_t hri_usbhost_descriptor_ctrl_pipe_reg_t; -typedef uint16_t hri_usbhost_descriptor_extreg_reg_t; -typedef uint16_t hri_usbhost_descriptor_status_pipe_reg_t; -typedef uint16_t hri_usbhost_fnum_reg_t; -typedef uint16_t hri_usbhost_intenset_reg_t; -typedef uint16_t hri_usbhost_intflag_reg_t; -typedef uint16_t hri_usbhost_padcal_reg_t; -typedef uint16_t hri_usbhost_pintsmry_reg_t; -typedef uint32_t hri_usbdesc_bank_addr_reg_t; -typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; -typedef uint32_t hri_usbdevice_descadd_reg_t; -typedef uint32_t hri_usbdevice_descriptor_addr_reg_t; -typedef uint32_t hri_usbdevice_descriptor_pcksize_reg_t; -typedef uint32_t hri_usbhost_descadd_reg_t; -typedef uint32_t hri_usbhost_descriptor_addr_reg_t; -typedef uint32_t hri_usbhost_descriptor_pcksize_reg_t; -typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; -typedef uint8_t hri_usbdevice_ctrla_reg_t; -typedef uint8_t hri_usbdevice_dadd_reg_t; -typedef uint8_t hri_usbdevice_descriptor_status_bk_reg_t; -typedef uint8_t hri_usbdevice_epcfg_reg_t; -typedef uint8_t hri_usbdevice_epintenset_reg_t; -typedef uint8_t hri_usbdevice_epintflag_reg_t; -typedef uint8_t hri_usbdevice_epstatus_reg_t; -typedef uint8_t hri_usbdevice_fsmstatus_reg_t; -typedef uint8_t hri_usbdevice_qosctrl_reg_t; -typedef uint8_t hri_usbdevice_status_reg_t; -typedef uint8_t hri_usbdevice_syncbusy_reg_t; -typedef uint8_t hri_usbendpoint_epcfg_reg_t; -typedef uint8_t hri_usbendpoint_epintenset_reg_t; -typedef uint8_t hri_usbendpoint_epintflag_reg_t; -typedef uint8_t hri_usbendpoint_epstatus_reg_t; -typedef uint8_t hri_usbhost_binterval_reg_t; -typedef uint8_t hri_usbhost_ctrla_reg_t; -typedef uint8_t hri_usbhost_descriptor_status_bk_reg_t; -typedef uint8_t hri_usbhost_flenhigh_reg_t; -typedef uint8_t hri_usbhost_fsmstatus_reg_t; -typedef uint8_t hri_usbhost_hsofc_reg_t; -typedef uint8_t hri_usbhost_pcfg_reg_t; -typedef uint8_t hri_usbhost_pintenset_reg_t; -typedef uint8_t hri_usbhost_pintflag_reg_t; -typedef uint8_t hri_usbhost_pstatus_reg_t; -typedef uint8_t hri_usbhost_qosctrl_reg_t; -typedef uint8_t hri_usbhost_status_reg_t; -typedef uint8_t hri_usbhost_syncbusy_reg_t; -typedef uint8_t hri_usbpipe_binterval_reg_t; -typedef uint8_t hri_usbpipe_pcfg_reg_t; -typedef uint8_t hri_usbpipe_pintenset_reg_t; -typedef uint8_t hri_usbpipe_pintflag_reg_t; -typedef uint8_t hri_usbpipe_pstatus_reg_t; - -static inline void hri_usbdevice_wait_for_sync(const void *const hw, hri_usbdevice_syncbusy_reg_t reg) -{ - while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_usbdevice_is_syncing(const void *const hw, hri_usbdevice_syncbusy_reg_t reg) -{ - return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; -} - -static inline void hri_usbhost_wait_for_sync(const void *const hw, hri_usbhost_syncbusy_reg_t reg) -{ - while (((Usb *)hw)->HOST.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_usbhost_is_syncing(const void *const hw, hri_usbhost_syncbusy_reg_t reg) -{ - return ((Usb *)hw)->HOST.SYNCBUSY.reg & reg; -} - -static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) - >> USB_HOST_PSTATUS_DTGL_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) - >> USB_HOST_PSTATUS_CURBK_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) - >> USB_HOST_PSTATUS_PFREEZE_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) - >> USB_HOST_PSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) - >> USB_HOST_PSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; -} - -static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; -} - -static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t data) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; -} - -static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; -} - -static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) - >> USB_HOST_PINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) - >> USB_HOST_PINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) - >> USB_HOST_PINTENSET_TRFAIL_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; -} - -static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) - >> USB_HOST_PINTENSET_PERR_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; - } -} - -static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; -} - -static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) - >> USB_HOST_PINTENSET_TXSTP_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; -} - -static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) - >> USB_HOST_PINTENSET_STALL_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; - } -} - -static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; -} - -static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; -} - -static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; -} - -static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t data) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; -} - -static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; -} - -static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintflag_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; -} - -static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; - return (bool)tmp; -} - -static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_BK; - tmp |= value << USB_HOST_PCFG_BK_Pos; - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; - tmp |= USB_HOST_PCFG_PTOKEN(data); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTYPE_Msk; - tmp |= USB_HOST_PCFG_PTYPE(data); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; -} - -static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; - tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; -} - -static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) - >> USB_HOST_PSTATUS_DTGL_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; - } -} - -static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) - >> USB_HOST_PSTATUS_CURBK_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; - } -} - -static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) - >> USB_HOST_PSTATUS_PFREEZE_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; - } -} - -static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) - >> USB_HOST_PSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; - } -} - -static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) - >> USB_HOST_PSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; - } -} - -static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; -} - -static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; -} - -static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t data) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; -} - -static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) - >> USB_HOST_PINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) - >> USB_HOST_PINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) - >> USB_HOST_PINTENSET_TRFAIL_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; -} - -static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) - >> USB_HOST_PINTENSET_PERR_Pos; -} - -static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; - } -} - -static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; -} - -static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) - >> USB_HOST_PINTENSET_TXSTP_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; - } -} - -static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; -} - -static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) - >> USB_HOST_PINTENSET_STALL_Pos; -} - -static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; - } -} - -static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; -} - -static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; -} - -static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; -} - -static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t data) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; -} - -static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintflag_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; -} - -static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_BK; - tmp |= value << USB_HOST_PCFG_BK_Pos; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; - tmp |= USB_HOST_PCFG_PTOKEN(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTYPE_Msk; - tmp |= USB_HOST_PCFG_PTYPE(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; -} - -static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; - tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; -} - -static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; -} - -static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; -} - -static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; - } -} - -static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; -} - -static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; -} - -static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; -} - -static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; - } -} - -static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; -} - -static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; -} - -static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; -} - -static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; - } -} - -static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; -} - -static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; -} - -static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; -} - -static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; - } -} - -static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; -} - -static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; -} - -static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; -} - -static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; - } -} - -static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; -} - -static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; -} - -static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; -} - -static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; - } -} - -static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; -} - -static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; -} - -static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; -} - -static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; - } -} - -static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; -} - -static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; -} - -static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; -} - -static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; - } -} - -static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; -} - -static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) -{ - ((Usb *)hw)->HOST.INTENSET.reg = mask; -} - -static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, - hri_usbhost_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.INTENSET.reg; -} - -static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) -{ - ((Usb *)hw)->HOST.INTENSET.reg = data; - ((Usb *)hw)->HOST.INTENCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = mask; -} - -static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; -} - -static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; -} - -static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; -} - -static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; -} - -static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; -} - -static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; -} - -static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; -} - -static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; -} - -static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; -} - -static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; -} - -static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; -} - -static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; -} - -static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; -} - -static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; -} - -static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; -} - -static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; -} - -static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; -} - -static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; -} - -static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, - hri_usbhost_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.INTFLAG.reg; -} - -static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = mask; -} - -static inline void hri_usbhost_set_CTRLA_SWRST_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_set_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_ENABLE; - tmp |= value << USB_CTRLA_ENABLE_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_RUNSTDBY; - tmp |= value << USB_CTRLA_RUNSTDBY_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLA_MODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLA_MODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_MODE; - tmp |= value << USB_CTRLA_MODE_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrla_reg_t hri_usbhost_get_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrla_reg_t hri_usbhost_read_CTRLA_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.CTRLA.reg; -} - -static inline void hri_usbhost_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_CQOS_bf(const void *const hw, - hri_usbhost_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usbhost_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_CQOS_Msk; - tmp |= USB_QOSCTRL_CQOS(data); - ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_CQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usbhost_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_DQOS_bf(const void *const hw, - hri_usbhost_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usbhost_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_DQOS_Msk; - tmp |= USB_QOSCTRL_DQOS(data); - ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_DQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usbhost_set_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_reg(const void *const hw, - hri_usbhost_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.QOSCTRL.reg; -} - -static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_RESUME; - tmp |= value << USB_HOST_CTRLB_RESUME_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_TSTJ; - tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_TSTK; - tmp |= value << USB_HOST_CTRLB_TSTK_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_SOFE; - tmp |= value << USB_HOST_CTRLB_SOFE_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_BUSRESET; - tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_VBUSOK; - tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_L1RESUME; - tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, - hri_usbhost_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; - tmp |= USB_HOST_CTRLB_SPDCONF(data); - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.CTRLB.reg; -} - -static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= ~USB_HOST_HSOFC_FLENCE; - tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; - ((Usb *)hw)->HOST.HSOFC.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; - return tmp; -} - -static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= ~USB_HOST_HSOFC_FLENC_Msk; - tmp |= USB_HOST_HSOFC_FLENC(data); - ((Usb *)hw)->HOST.HSOFC.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; - return tmp; -} - -static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.HSOFC.reg; -} - -static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= ~USB_HOST_FNUM_MFNUM_Msk; - tmp |= USB_HOST_FNUM_MFNUM(data); - ((Usb *)hw)->HOST.FNUM.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= ~USB_HOST_FNUM_FNUM_Msk; - tmp |= USB_HOST_FNUM_FNUM(data); - ((Usb *)hw)->HOST.FNUM.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FNUM.reg; -} - -static inline void hri_usbhost_set_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descadd_reg_t hri_usbhost_get_DESCADD_DESCADD_bf(const void *const hw, - hri_usbhost_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usbhost_write_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp &= ~USB_DESCADD_DESCADD_Msk; - tmp |= USB_DESCADD_DESCADD(data); - ((Usb *)hw)->HOST.DESCADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descadd_reg_t hri_usbhost_read_DESCADD_DESCADD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usbhost_set_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descadd_reg_t hri_usbhost_get_DESCADD_reg(const void *const hw, - hri_usbhost_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descadd_reg_t hri_usbhost_read_DESCADD_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.DESCADD.reg; -} - -static inline void hri_usbhost_set_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRANSP_bf(const void *const hw, - hri_usbhost_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSP_Msk; - tmp |= USB_PADCAL_TRANSP(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRANSP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRANSN_bf(const void *const hw, - hri_usbhost_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSN_Msk; - tmp |= USB_PADCAL_TRANSN(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRANSN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRIM_bf(const void *const hw, - hri_usbhost_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRIM_Msk; - tmp |= USB_PADCAL_TRIM(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRIM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.PADCAL.reg; -} - -static inline bool hri_usbhost_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_usbhost_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_usbhost_syncbusy_reg_t hri_usbhost_get_SYNCBUSY_reg(const void *const hw, - hri_usbhost_syncbusy_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_syncbusy_reg_t hri_usbhost_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.SYNCBUSY.reg; -} - -static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, - hri_usbhost_fsmstatus_reg_t mask) -{ - return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_get_FSMSTATUS_reg(const void *const hw, - hri_usbhost_fsmstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_read_FSMSTATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FSMSTATUS.reg; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, - hri_usbhost_flenhigh_reg_t mask) -{ - return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, - hri_usbhost_flenhigh_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FLENHIGH.reg; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; -} - -static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, - hri_usbhost_pintsmry_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.PINTSMRY.reg; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, - hri_usbhost_status_reg_t mask) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; -} - -static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, - hri_usbhost_status_reg_t mask) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; -} - -static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.STATUS.reg; -} - -static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; - tmp |= USB_DEVICE_ADDR_ADDR(data); - ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->ADDR.reg; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_SIZE(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; - tmp |= USB_DEVICE_EXTREG_SUBPID(data); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; - tmp |= USB_DEVICE_EXTREG_VARIABLE(data); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->EXTREG.reg; -} - -static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) -{ - return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) - >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t -hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, - hri_usbdesc_bank_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; -} - -static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_addr_reg_t -hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; - tmp |= USB_DEVICE_ADDR_ADDR(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_addr_reg_t -hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void -hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void -hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void -hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_SIZE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; - tmp |= USB_DEVICE_EXTREG_SUBPID(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t -hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; - tmp |= USB_DEVICE_EXTREG_VARIABLE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t -hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; -} - -static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) - >> USB_DEVICE_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) - >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_status_bk_reg_t -hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_status_bk_reg_t -hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; -} - -static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; -} - -static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; -} - -static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; - } -} - -static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; -} - -static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; -} - -static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; -} - -static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; - } -} - -static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; -} - -static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; -} - -static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; -} - -static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; - } -} - -static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; -} - -static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; -} - -static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; -} - -static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; - } -} - -static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; -} - -static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; -} - -static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; -} - -static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; - } -} - -static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; -} - -static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; -} - -static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; -} - -static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; - } -} - -static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; -} - -static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; -} - -static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; -} - -static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; - } -} - -static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; -} - -static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; -} - -static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; -} - -static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; - } -} - -static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; -} - -static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; -} - -static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; -} - -static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; - } -} - -static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; -} - -static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; -} - -static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; - } -} - -static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; -} - -static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = mask; -} - -static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, - hri_usbdevice_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.INTENSET.reg; -} - -static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = data; - ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; -} - -static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; -} - -static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; -} - -static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; -} - -static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; -} - -static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; -} - -static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; -} - -static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; -} - -static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; -} - -static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; -} - -static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; -} - -static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; -} - -static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; -} - -static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; -} - -static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; -} - -static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; -} - -static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; -} - -static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; -} - -static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; -} - -static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; -} - -static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; -} - -static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, - hri_usbdevice_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.INTFLAG.reg; -} - -static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; -} - -static inline void hri_usbdevice_set_CTRLA_SWRST_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_SWRST; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_set_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= ~USB_CTRLA_ENABLE; - tmp |= value << USB_CTRLA_ENABLE_Pos; - ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= ~USB_CTRLA_RUNSTDBY; - tmp |= value << USB_CTRLA_RUNSTDBY_Pos; - ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLA_MODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLA_MODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= ~USB_CTRLA_MODE; - tmp |= value << USB_CTRLA_MODE_Pos; - ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrla_reg_t hri_usbdevice_get_CTRLA_reg(const void *const hw, - hri_usbdevice_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrla_reg_t hri_usbdevice_read_CTRLA_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.CTRLA.reg; -} - -static inline void hri_usbdevice_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_CQOS_bf(const void *const hw, - hri_usbdevice_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_CQOS_Msk; - tmp |= USB_QOSCTRL_CQOS(data); - ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_CQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_DQOS_bf(const void *const hw, - hri_usbdevice_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_DQOS_Msk; - tmp |= USB_QOSCTRL_DQOS(data); - ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_DQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_reg(const void *const hw, - hri_usbdevice_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.QOSCTRL.reg; -} - -static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_DETACH; - tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_UPRSM; - tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_NREPLY; - tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTJ; - tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTK; - tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; - tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_OPMODE2; - tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_GNAK; - tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; - tmp |= USB_DEVICE_CTRLB_SPDCONF(data); - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; - tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.CTRLB.reg; -} - -static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= ~USB_DEVICE_DADD_ADDEN; - tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; - ((Usb *)hw)->DEVICE.DADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, - hri_usbdevice_dadd_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= ~USB_DEVICE_DADD_DADD_Msk; - tmp |= USB_DEVICE_DADD_DADD(data); - ((Usb *)hw)->DEVICE.DADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.DADD.reg; -} - -static inline void hri_usbdevice_set_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg |= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descadd_reg_t hri_usbdevice_get_DESCADD_DESCADD_bf(const void *const hw, - hri_usbdevice_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp &= ~USB_DESCADD_DESCADD_Msk; - tmp |= USB_DESCADD_DESCADD(data); - ((Usb *)hw)->DEVICE.DESCADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descadd_reg_t hri_usbdevice_read_DESCADD_DESCADD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descadd_reg_t hri_usbdevice_get_DESCADD_reg(const void *const hw, - hri_usbdevice_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descadd_reg_t hri_usbdevice_read_DESCADD_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.DESCADD.reg; -} - -static inline void hri_usbdevice_set_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRANSP_bf(const void *const hw, - hri_usbdevice_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSP_Msk; - tmp |= USB_PADCAL_TRANSP(data); - ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRANSP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRANSN_bf(const void *const hw, - hri_usbdevice_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSN_Msk; - tmp |= USB_PADCAL_TRANSN(data); - ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRANSN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRIM_bf(const void *const hw, - hri_usbdevice_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= ~USB_PADCAL_TRIM_Msk; - tmp |= USB_PADCAL_TRIM(data); - ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRIM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_reg(const void *const hw, - hri_usbdevice_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.PADCAL.reg; -} - -static inline bool hri_usbdevice_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_usbdevice_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_usbdevice_syncbusy_reg_t hri_usbdevice_get_SYNCBUSY_reg(const void *const hw, - hri_usbdevice_syncbusy_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_syncbusy_reg_t hri_usbdevice_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.SYNCBUSY.reg; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.STATUS.reg; -} - -static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, - hri_usbdevice_fsmstatus_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_get_FSMSTATUS_reg(const void *const hw, - hri_usbdevice_fsmstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.FSMSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_read_FSMSTATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.FSMSTATUS.reg; -} - -static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, - hri_usbdevice_fnum_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, - hri_usbdevice_fnum_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.FNUM.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.FNUM.reg; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; -} - -static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, - hri_usbdevice_epintsmry_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; -} - -static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) - >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) - >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) - >> USB_DEVICE_EPSTATUS_CURBK_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) - >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) - >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) - >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) - >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; -} - -static inline hri_usbendpoint_epstatus_reg_t -hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; -} - -static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t data) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; -} - -static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) - >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) - >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) - >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) - >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) - >> USB_DEVICE_EPINTENSET_RXSTP_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) - >> USB_DEVICE_EPINTENSET_STALL0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) - >> USB_DEVICE_EPINTENSET_STALL1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; -} - -static inline hri_usbendpoint_epintenset_reg_t -hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; -} - -static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t data) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; -} - -static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline hri_usbendpoint_epintflag_reg_t -hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintflag_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; -} - -static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; - return (bool)tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_NYETDIS; - tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t -hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t -hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; -} - -static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) - >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) - >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) - >> USB_DEVICE_EPSTATUS_CURBK_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) - >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) - >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) - >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) - >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; -} - -static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; -} - -static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t data) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; -} - -static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) - >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) - >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) - >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) - >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) - >> USB_DEVICE_EPINTENSET_RXSTP_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) - >> USB_DEVICE_EPINTENSET_STALL0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) - >> USB_DEVICE_EPINTENSET_STALL1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; -} - -static inline hri_usbdevice_epintenset_reg_t -hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; -} - -static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t data) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline hri_usbdevice_epintflag_reg_t -hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintflag_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; -} - -static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_NYETDIS; - tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t -hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t -hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; -} - -static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp &= ~USB_HOST_ADDR_ADDR_Msk; - tmp |= USB_HOST_ADDR_ADDR(data); - ((UsbHostDescBank *)hw)->ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->ADDR.reg; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_SIZE(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->PCKSIZE.reg; -} - -static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; - tmp |= USB_HOST_EXTREG_SUBPID(data); - ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; - tmp |= USB_HOST_EXTREG_VARIABLE(data); - ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->EXTREG.reg; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; - tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; - tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; - tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; -} - -static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t -hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->STATUS_BK.reg; -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) - >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) - >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t -hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, - hri_usbdesc_bank_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline hri_usbdesc_bank_status_pipe_reg_t -hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, - hri_usbdesc_bank_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; -} - -static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_addr_reg_t -hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp &= ~USB_HOST_ADDR_ADDR_Msk; - tmp |= USB_HOST_ADDR_ADDR(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_addr_reg_t -hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_SIZE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; - tmp |= USB_HOST_EXTREG_SUBPID(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, - uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; - tmp |= USB_HOST_EXTREG_VARIABLE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, - uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; - tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; - tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; - tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; -} - -static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) - >> USB_HOST_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) - >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_status_bk_reg_t -hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) - >> USB_HOST_STATUS_PIPE_DTGLER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) - >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) - >> USB_HOST_STATUS_PIPE_PIDER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) - >> USB_HOST_STATUS_PIPE_TOUTER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) - >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_status_pipe_reg_t -hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_pipe_reg_t mask) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_status_pipe_reg_t -hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline hri_usbhost_descriptor_status_pipe_reg_t -hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_status_pipe_reg_t -hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_USB_D21_H_INCLUDED */ -#endif /* _SAMD21_USB_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/hri/hri_wdt_d21.h b/atmel-samd/asf4/samd21/hri/hri_wdt_d21.h deleted file mode 100644 index 90c307ba6..000000000 --- a/atmel-samd/asf4/samd21/hri/hri_wdt_d21.h +++ /dev/null @@ -1,616 +0,0 @@ -/** - * \file - * - * \brief SAM WDT - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD21_WDT_COMPONENT_ -#ifndef _HRI_WDT_D21_H_INCLUDED_ -#define _HRI_WDT_D21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_WDT_CRITICAL_SECTIONS) -#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define WDT_CRITICAL_SECTION_ENTER() -#define WDT_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint8_t hri_wdt_clear_reg_t; -typedef uint8_t hri_wdt_config_reg_t; -typedef uint8_t hri_wdt_ctrl_reg_t; -typedef uint8_t hri_wdt_ewctrl_reg_t; -typedef uint8_t hri_wdt_intenset_reg_t; -typedef uint8_t hri_wdt_intflag_reg_t; -typedef uint8_t hri_wdt_status_reg_t; - -static inline void hri_wdt_wait_for_sync(const void *const hw) -{ - while (((const Wdt *)hw)->STATUS.bit.SYNCBUSY) - ; -} - -static inline bool hri_wdt_is_syncing(const void *const hw) -{ - return ((const Wdt *)hw)->STATUS.bit.SYNCBUSY; -} - -static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; -} - -static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; -} - -static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; - } else { - ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; - } -} - -static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; -} - -static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - ((Wdt *)hw)->INTENSET.reg = mask; -} - -static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) -{ - return ((Wdt *)hw)->INTENSET.reg; -} - -static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) -{ - ((Wdt *)hw)->INTENSET.reg = data; - ((Wdt *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - ((Wdt *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; -} - -static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; -} - -static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; -} - -static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; -} - -static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) -{ - return ((Wdt *)hw)->INTFLAG.reg; -} - -static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) -{ - ((Wdt *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CLEAR.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRL_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CTRL.reg |= WDT_CTRL_ENABLE; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRL_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CTRL.reg; - tmp = (tmp & WDT_CTRL_ENABLE) >> WDT_CTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CTRL.reg; - tmp &= ~WDT_CTRL_ENABLE; - tmp |= value << WDT_CTRL_ENABLE_Pos; - ((Wdt *)hw)->CTRL.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRL_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CTRL.reg &= ~WDT_CTRL_ENABLE; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRL_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CTRL.reg ^= WDT_CTRL_ENABLE; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRL_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CTRL.reg |= WDT_CTRL_WEN; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRL_WEN_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CTRL.reg; - tmp = (tmp & WDT_CTRL_WEN) >> WDT_CTRL_WEN_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRL_WEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CTRL.reg; - tmp &= ~WDT_CTRL_WEN; - tmp |= value << WDT_CTRL_WEN_Pos; - ((Wdt *)hw)->CTRL.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRL_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CTRL.reg &= ~WDT_CTRL_WEN; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRL_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CTRL.reg ^= WDT_CTRL_WEN; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRL_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CTRL.reg |= WDT_CTRL_ALWAYSON; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRL_ALWAYSON_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CTRL.reg; - tmp = (tmp & WDT_CTRL_ALWAYSON) >> WDT_CTRL_ALWAYSON_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRL_ALWAYSON_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CTRL.reg; - tmp &= ~WDT_CTRL_ALWAYSON; - tmp |= value << WDT_CTRL_ALWAYSON_Pos; - ((Wdt *)hw)->CTRL.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRL_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CTRL.reg &= ~WDT_CTRL_ALWAYSON; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRL_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CTRL.reg ^= WDT_CTRL_ALWAYSON; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRL.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ctrl_reg_t hri_wdt_get_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRL.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRL.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRL_reg(const void *const hw, hri_wdt_ctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRL.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ctrl_reg_t hri_wdt_read_CTRL_reg(const void *const hw) -{ - return ((Wdt *)hw)->CTRL.reg; -} - -static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= ~WDT_CONFIG_PER_Msk; - tmp |= WDT_CONFIG_PER(data); - ((Wdt *)hw)->CONFIG.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; - return tmp; -} - -static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= ~WDT_CONFIG_WINDOW_Msk; - tmp |= WDT_CONFIG_WINDOW(data); - ((Wdt *)hw)->CONFIG.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw); - ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; - return tmp; -} - -static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) -{ - return ((Wdt *)hw)->CONFIG.reg; -} - -static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; - return tmp; -} - -static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; - tmp |= WDT_EWCTRL_EWOFFSET(data); - ((Wdt *)hw)->EWCTRL.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; - return tmp; -} - -static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) -{ - return ((Wdt *)hw)->EWCTRL.reg; -} - -static inline bool hri_wdt_get_STATUS_SYNCBUSY_bit(const void *const hw) -{ - return (((Wdt *)hw)->STATUS.reg & WDT_STATUS_SYNCBUSY) >> WDT_STATUS_SYNCBUSY_Pos; -} - -static inline hri_wdt_status_reg_t hri_wdt_get_STATUS_reg(const void *const hw, hri_wdt_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_status_reg_t hri_wdt_read_STATUS_reg(const void *const hw) -{ - return ((Wdt *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_WDT_D21_H_INCLUDED */ -#endif /* _SAMD21_WDT_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/include/component-version.h b/atmel-samd/asf4/samd21/include/component-version.h deleted file mode 100644 index dcf909bae..000000000 --- a/atmel-samd/asf4/samd21/include/component-version.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * \file - * - * \brief Component version header file - * - * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _COMPONENT_VERSION_H_INCLUDED -#define _COMPONENT_VERSION_H_INCLUDED - -#define COMPONENT_VERSION_MAJOR 1 -#define COMPONENT_VERSION_MINOR 2 - -// -// The COMPONENT_VERSION define is composed of the major and the minor version number. -// -// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. -// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION -// is at least 8 digits long. -// -#define COMPONENT_VERSION 00010002 - -// -// The build number does not refer to the component, but to the build number -// of the device pack that provides the component. -// -#define BUILD_NUMBER 276 - -// -// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. -// -#define COMPONENT_VERSION_STRING "1.2" - -// -// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. -// -// The COMPONENT_DATE_STRING is written out using the following strftime pattern. -// -// "%Y-%m-%d %H:%M:%S" -// -// -#define COMPONENT_DATE_STRING "2017-02-07 19:08:26" - -#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ - diff --git a/atmel-samd/asf4/samd21/include/component/ac.h b/atmel-samd/asf4/samd21/include/component/ac.h deleted file mode 100644 index 80ea1abe1..000000000 --- a/atmel-samd/asf4/samd21/include/component/ac.h +++ /dev/null @@ -1,544 +0,0 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_AC_COMPONENT_ -#define _SAMD21_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_AC Analog Comparators */ -/*@{*/ - -#define AC_U2205 -#define REV_AC 0x111 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE _U(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (_U(0x1) << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (_U(0x1) << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ -#define AC_CTRLA_RUNSTDBY_Msk (_U(0x1) << AC_CTRLA_RUNSTDBY_Pos) -#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)) -#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ -#define AC_CTRLA_LPMUX (_U(0x1) << AC_CTRLA_LPMUX_Pos) -#define AC_CTRLA_MASK _U(0x87) /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE _U(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (_U(0x3) << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK _U(0x03) /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE _U(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (_U(0x3) << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (_U(0x1) << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ -#define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ -#define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ -#define AC_EVCTRL_COMPEI_Msk (_U(0x3) << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_MASK _U(0x0313) /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (_U(0x3) << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (_U(0x1) << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK _U(0x13) /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE _U(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (_U(0x3) << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (_U(0x1) << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK _U(0x13) /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (_U(0x3) << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (_U(0x1) << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK _U(0x13) /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE _U(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (_U(0x3) << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (_U(0x3) << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK _U(0x33) /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE _U(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (_U(0x3) << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ -#define AC_STATUSB_SYNCBUSY (_U(0x1) << AC_STATUSB_SYNCBUSY_Pos) -#define AC_STATUSB_MASK _U(0x83) /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ -#define AC_STATUSC_RESETVALUE _U(0x00) /**< \brief (AC_STATUSC reset_value) Status C */ - -#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ -#define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos) -#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ -#define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos) -#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ -#define AC_STATUSC_STATE_Msk (_U(0x3) << AC_STATUSC_STATE_Pos) -#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)) -#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ -#define AC_STATUSC_WSTATE0_Msk (_U(0x3) << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)) -#define AC_STATUSC_WSTATE0_ABOVE_Val _U(0x0) /**< \brief (AC_STATUSC) Signal is above window */ -#define AC_STATUSC_WSTATE0_INSIDE_Val _U(0x1) /**< \brief (AC_STATUSC) Signal is inside window */ -#define AC_STATUSC_WSTATE0_BELOW_Val _U(0x2) /**< \brief (AC_STATUSC) Signal is below window */ -#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_MASK _U(0x33) /**< \brief (AC_STATUSC) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (_U(0x1) << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (_U(0x3) << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val _U(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK _U(0x07) /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ENABLE:1; /*!< bit: 0 Enable */ - uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ - uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ - uint32_t :1; /*!< bit: 4 Reserved */ - uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ - uint32_t :1; /*!< bit: 14 Reserved */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t OUT:2; /*!< bit: 16..17 Output */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE _U(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (_U(0x1) << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (_U(0x1) << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (_U(0x3) << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_LOW_Val _U(0x0) /**< \brief (AC_COMPCTRL) Low speed */ -#define AC_COMPCTRL_SPEED_HIGH_Val _U(0x1) /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (_U(0x3) << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val _U(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val _U(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val _U(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (_U(0x7) << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val _U(0x4) /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val _U(0x7) /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (_U(0x3) << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (_U(0x1) << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (_U(0x3) << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val _U(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val _U(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYST (_U(0x1) << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (_U(0x7) << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val _U(0x0) /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val _U(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val _U(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_MASK _U(0x070BB76F) /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE _U(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (_U(0x3F) << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK _U(0x3F) /**< \brief (AC_SCALER) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ - __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ - RoReg8 Reserved2[0x1]; - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ - RoReg8 Reserved3[0x3]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved4[0x8]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_AC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/include/component/adc.h b/atmel-samd/asf4/samd21/include/component/adc.h deleted file mode 100644 index fe4152125..000000000 --- a/atmel-samd/asf4/samd21/include/component/adc.h +++ /dev/null @@ -1,684 +0,0 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_ADC_COMPONENT_ -#define _SAMD21_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2204 -#define REV_ADC 0x120 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE _U(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (_U(0x1) << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (_U(0x1) << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ -#define ADC_CTRLA_RUNSTDBY (_U(0x1) << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_MASK _U(0x07) /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (_U(0xF) << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INT1V_Val _U(0x0) /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U(0x1) /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ -#define ADC_REFCTRL_REFSEL_AREFA_Val _U(0x3) /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val _U(0x4) /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (_U(0x1) << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK _U(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (_U(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val _U(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val _U(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val _U(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val _U(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val _U(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val _U(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val _U(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val _U(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val _U(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val _U(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (_U(0x7) << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK _U(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ -#define ADC_SAMPCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (_U(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_MASK _U(0x3F) /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE _U(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ -#define ADC_CTRLB_DIFFMODE (_U(0x1) << ADC_CTRLB_DIFFMODE_Pos) -#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ -#define ADC_CTRLB_LEFTADJ (_U(0x1) << ADC_CTRLB_LEFTADJ_Pos) -#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ -#define ADC_CTRLB_FREERUN (_U(0x1) << ADC_CTRLB_FREERUN_Pos) -#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ -#define ADC_CTRLB_CORREN (_U(0x1) << ADC_CTRLB_CORREN_Pos) -#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ -#define ADC_CTRLB_RESSEL_Msk (_U(0x3) << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) -#define ADC_CTRLB_RESSEL_12BIT_Val _U(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val _U(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val _U(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val _U(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ -#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ -#define ADC_CTRLB_PRESCALER_Msk (_U(0x7) << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) -#define ADC_CTRLB_PRESCALER_DIV4_Val _U(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ -#define ADC_CTRLB_PRESCALER_DIV8_Val _U(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ -#define ADC_CTRLB_PRESCALER_DIV16_Val _U(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ -#define ADC_CTRLB_PRESCALER_DIV32_Val _U(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ -#define ADC_CTRLB_PRESCALER_DIV64_Val _U(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ -#define ADC_CTRLB_PRESCALER_DIV128_Val _U(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ -#define ADC_CTRLB_PRESCALER_DIV256_Val _U(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ -#define ADC_CTRLB_PRESCALER_DIV512_Val _U(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ -#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_MASK _U(0x073F) /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ -#define ADC_WINCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ - -#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ -#define ADC_WINCTRL_WINMODE_Msk (_U(0x7) << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)) -#define ADC_WINCTRL_WINMODE_DISABLE_Val _U(0x0) /**< \brief (ADC_WINCTRL) No window mode (default) */ -#define ADC_WINCTRL_WINMODE_MODE1_Val _U(0x1) /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ -#define ADC_WINCTRL_WINMODE_MODE2_Val _U(0x2) /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE3_Val _U(0x3) /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE4_Val _U(0x4) /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ -#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_MASK _U(0x07) /**< \brief (ADC_WINCTRL) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE _U(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ -#define ADC_SWTRIG_FLUSH (_U(0x1) << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ -#define ADC_SWTRIG_START (_U(0x1) << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK _U(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ - uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ - uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE _U(0x00000000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_PIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN8_Val _U(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN9_Val _U(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN10_Val _U(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN11_Val _U(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN12_Val _U(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN13_Val _U(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN14_Val _U(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN15_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN16_Val _U(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN17_Val _U(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN18_Val _U(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN19_Val _U(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Reference */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U(0x1C) /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (_U(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_PIN0_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN1_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN2_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN3_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN4_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN5_Val _U(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN6_Val _U(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN7_Val _U(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val _U(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_IOGND_Val _U(0x19) /**< \brief (ADC_INPUTCTRL) I/O Ground */ -#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ -#define ADC_INPUTCTRL_INPUTSCAN_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTSCAN_Pos) -#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)) -#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ -#define ADC_INPUTCTRL_INPUTOFFSET_Msk (_U(0xF) << ADC_INPUTCTRL_INPUTOFFSET_Pos) -#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)) -#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ -#define ADC_INPUTCTRL_GAIN_Msk (_U(0xF) << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)) -#define ADC_INPUTCTRL_GAIN_1X_Val _U(0x0) /**< \brief (ADC_INPUTCTRL) 1x */ -#define ADC_INPUTCTRL_GAIN_2X_Val _U(0x1) /**< \brief (ADC_INPUTCTRL) 2x */ -#define ADC_INPUTCTRL_GAIN_4X_Val _U(0x2) /**< \brief (ADC_INPUTCTRL) 4x */ -#define ADC_INPUTCTRL_GAIN_8X_Val _U(0x3) /**< \brief (ADC_INPUTCTRL) 8x */ -#define ADC_INPUTCTRL_GAIN_16X_Val _U(0x4) /**< \brief (ADC_INPUTCTRL) 16x */ -#define ADC_INPUTCTRL_GAIN_DIV2_Val _U(0xF) /**< \brief (ADC_INPUTCTRL) 1/2x */ -#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_MASK _U(0x0FFF1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ - uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ -#define ADC_EVCTRL_STARTEI (_U(0x1) << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ -#define ADC_EVCTRL_SYNCEI (_U(0x1) << ADC_EVCTRL_SYNCEI_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (_U(0x1) << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (_U(0x1) << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK _U(0x33) /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ -#define ADC_INTENCLR_RESRDY (_U(0x1) << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ -#define ADC_INTENCLR_OVERRUN (_U(0x1) << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ -#define ADC_INTENCLR_WINMON (_U(0x1) << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define ADC_INTENCLR_SYNCRDY (_U(0x1) << ADC_INTENCLR_SYNCRDY_Pos) -#define ADC_INTENCLR_MASK _U(0x0F) /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE _U(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (_U(0x1) << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (_U(0x1) << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (_U(0x1) << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ -#define ADC_INTENSET_SYNCRDY (_U(0x1) << ADC_INTENSET_SYNCRDY_Pos) -#define ADC_INTENSET_MASK _U(0x0F) /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ - __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ -#define ADC_INTFLAG_RESRDY (_U(0x1) << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ -#define ADC_INTFLAG_OVERRUN (_U(0x1) << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ -#define ADC_INTFLAG_WINMON (_U(0x1) << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ -#define ADC_INTFLAG_SYNCRDY (_U(0x1) << ADC_INTFLAG_SYNCRDY_Pos) -#define ADC_INTFLAG_MASK _U(0x0F) /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ -#define ADC_STATUS_RESETVALUE _U(0x00) /**< \brief (ADC_STATUS reset_value) Status */ - -#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ -#define ADC_STATUS_SYNCBUSY (_U(0x1) << ADC_STATUS_SYNCBUSY_Pos) -#define ADC_STATUS_MASK _U(0x80) /**< \brief (ADC_STATUS) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ -#define ADC_RESULT_RESETVALUE _U(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ -#define ADC_RESULT_RESULT_Msk (_U(0xFFFF) << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK _U(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (_U(0xFFFF) << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK _U(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE _U(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (_U(0xFFFF) << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK _U(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (_U(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK _U(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE _U(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK _U(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ - uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE _U(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ -#define ADC_CALIB_LINEARITY_CAL_Msk (_U(0xFF) << ADC_CALIB_LINEARITY_CAL_Pos) -#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)) -#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ -#define ADC_CALIB_BIAS_CAL_Msk (_U(0x7) << ADC_CALIB_BIAS_CAL_Pos) -#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)) -#define ADC_CALIB_MASK _U(0x07FF) /**< \brief (ADC_CALIB) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (_U(0x1) << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK _U(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ - RoReg8 Reserved1[0x2]; - __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ - RoReg8 Reserved2[0x3]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ - RoReg8 Reserved3[0x3]; - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ - RoReg8 Reserved4[0x1]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ - RoReg8 Reserved5[0x2]; - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ - RoReg8 Reserved6[0x2]; - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_ADC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/include/component/dac.h b/atmel-samd/asf4/samd21/include/component/dac.h deleted file mode 100644 index ba84975ea..000000000 --- a/atmel-samd/asf4/samd21/include/component/dac.h +++ /dev/null @@ -1,271 +0,0 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_DAC_COMPONENT_ -#define _SAMD21_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_DAC Digital Analog Converter */ -/*@{*/ - -#define DAC_U2214 -#define REV_DAC 0x110 - -/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (_U(0x1) << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ -#define DAC_CTRLA_ENABLE (_U(0x1) << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */ -#define DAC_CTRLA_RUNSTDBY (_U(0x1) << DAC_CTRLA_RUNSTDBY_Pos) -#define DAC_CTRLA_MASK _U(0x07) /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ - uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ - uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ - uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ - uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE _U(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ -#define DAC_CTRLB_EOEN (_U(0x1) << DAC_CTRLB_EOEN_Pos) -#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ -#define DAC_CTRLB_IOEN (_U(0x1) << DAC_CTRLB_IOEN_Pos) -#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ -#define DAC_CTRLB_LEFTADJ (_U(0x1) << DAC_CTRLB_LEFTADJ_Pos) -#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ -#define DAC_CTRLB_VPD (_U(0x1) << DAC_CTRLB_VPD_Pos) -#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */ -#define DAC_CTRLB_BDWP (_U(0x1) << DAC_CTRLB_BDWP_Pos) -#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ -#define DAC_CTRLB_REFSEL_Msk (_U(0x3) << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_INT1V_Val _U(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */ -#define DAC_CTRLB_REFSEL_AVCC_Val _U(0x1) /**< \brief (DAC_CTRLB) AVCC */ -#define DAC_CTRLB_REFSEL_VREFP_Val _U(0x2) /**< \brief (DAC_CTRLB) External reference */ -#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK _U(0xDF) /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ - uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE _U(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ -#define DAC_EVCTRL_STARTEI (_U(0x1) << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ -#define DAC_EVCTRL_EMPTYEO (_U(0x1) << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_MASK _U(0x03) /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN (_U(0x1) << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY (_U(0x1) << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define DAC_INTENCLR_SYNCRDY (_U(0x1) << DAC_INTENCLR_SYNCRDY_Pos) -#define DAC_INTENCLR_MASK _U(0x07) /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE _U(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN (_U(0x1) << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY (_U(0x1) << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */ -#define DAC_INTENSET_SYNCRDY (_U(0x1) << DAC_INTENSET_SYNCRDY_Pos) -#define DAC_INTENSET_MASK _U(0x07) /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ - __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ - __I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ -#define DAC_INTFLAG_UNDERRUN (_U(0x1) << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ -#define DAC_INTFLAG_EMPTY (_U(0x1) << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */ -#define DAC_INTFLAG_SYNCRDY (_U(0x1) << DAC_INTFLAG_SYNCRDY_Pos) -#define DAC_INTFLAG_MASK _U(0x07) /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE _U(0x00) /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */ -#define DAC_STATUS_SYNCBUSY (_U(0x1) << DAC_STATUS_SYNCBUSY_Pos) -#define DAC_STATUS_MASK _U(0x80) /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */ -#define DAC_DATA_RESETVALUE _U(0x0000) /**< \brief (DAC_DATA reset_value) Data */ - -#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ -#define DAC_DATA_DATA_Msk (_U(0xFFFF) << DAC_DATA_DATA_Pos) -#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) -#define DAC_DATA_MASK _U(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ - -/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATABUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */ -#define DAC_DATABUF_RESETVALUE _U(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */ - -#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ -#define DAC_DATABUF_DATABUF_Msk (_U(0xFFFF) << DAC_DATABUF_DATABUF_Pos) -#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) -#define DAC_DATABUF_MASK _U(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ - -/** \brief DAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ - __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ - __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ - RoReg8 Reserved1[0x1]; - __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ - RoReg8 Reserved2[0x2]; - __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ -} Dac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_DAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd21/include/component/dmac.h b/atmel-samd/asf4/samd21/include/component/dmac.h deleted file mode 100644 index 1d7c8c0ea..000000000 --- a/atmel-samd/asf4/samd21/include/component/dmac.h +++ /dev/null @@ -1,1072 +0,0 @@ -/** - * \file - * - * \brief Component description for DMAC - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_DMAC_COMPONENT_ -#define _SAMD21_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2223 -#define REV_DMAC 0x100 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (_U(0x1) << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (_U(0x1) << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ -#define DMAC_CTRL_CRCENABLE (_U(0x1) << DMAC_CTRL_CRCENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (1 << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (1 << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (1 << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (1 << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (_U(0xF) << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) -#define DMAC_CTRL_MASK _U(0x0F07) /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (_U(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (_U(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) -#define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U(0x0) /**< \brief (DMAC_CRCCTRL) No action */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val _U(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_MASK _U(0x3F0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) -#define DMAC_CRCDATAIN_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) -#define DMAC_CRCCHKSUM_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (_U(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (_U(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_MASK _U(0x03) /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (_U(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK _U(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ - uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ - uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_QOSCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ -#define DMAC_QOSCTRL_RESETVALUE _U(0x15) /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ - -#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ -#define DMAC_QOSCTRL_WRBQOS_Msk (_U(0x3) << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) -#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_WRBQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_WRBQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ -#define DMAC_QOSCTRL_FQOS_Msk (_U(0x3) << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) -#define DMAC_QOSCTRL_FQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_FQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_FQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_FQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ -#define DMAC_QOSCTRL_DQOS_Msk (_U(0x3) << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) -#define DMAC_QOSCTRL_DQOS_DISABLE_Val _U(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_DQOS_LOW_Val _U(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_DQOS_MEDIUM_Val _U(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_DQOS_HIGH_Val _U(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_MASK _U(0x3F) /**< \brief (DMAC_QOSCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE _U(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (1 << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (1 << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (1 << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (1 << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (1 << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (1 << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (1 << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (1 << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (1 << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (1 << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (1 << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (1 << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U(0xFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) -#define DMAC_SWTRIGCTRL_MASK _U(0x00000FFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ - uint32_t :3; /*!< bit: 4.. 6 Reserved */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ - uint32_t :3; /*!< bit: 20..22 Reserved */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ - uint32_t :3; /*!< bit: 28..30 Reserved */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (_U(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (_U(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK _U(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :2; /*!< bit: 11..12 Reserved */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE _U(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (_U(0xF) << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (_U(0x1) << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (_U(0x1) << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (_U(0x1) << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (_U(0x1) << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (_U(0x1) << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (_U(0x1) << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK _U(0xE70F) /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE _U(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (1 << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (1 << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (1 << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (1 << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (1 << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (1 << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (1 << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (1 << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (1 << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (1 << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (1 << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (1 << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (_U(0xFFF) << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) -#define DMAC_INTSTATUS_MASK _U(0x00000FFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (1 << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (1 << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (1 << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (1 << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (1 << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (1 << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (1 << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (1 << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (1 << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (1 << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (1 << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (1 << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (_U(0xFFF) << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) -#define DMAC_BUSYCH_MASK _U(0x00000FFF) /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE _U(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (1 << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (1 << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (1 << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (1 << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (1 << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (1 << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (1 << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (1 << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (1 << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (1 << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (1 << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (1 << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (_U(0xFFF) << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) -#define DMAC_PENDCH_MASK _U(0x00000FFF) /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE _U(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (1 << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (1 << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (1 << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (1 << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (_U(0xF) << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (_U(0x1F) << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (_U(0x1) << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (_U(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) -#define DMAC_ACTIVE_MASK _U(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (_U(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) -#define DMAC_BASEADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE _U(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (_U(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) -#define DMAC_WRBADDR_MASK _U(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ -#define DMAC_CHID_RESETVALUE _U(0x00) /**< \brief (DMAC_CHID reset_value) Channel ID */ - -#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ -#define DMAC_CHID_ID_Msk (_U(0xF) << DMAC_CHID_ID_Pos) -#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) -#define DMAC_CHID_MASK _U(0x0F) /**< \brief (DMAC_CHID) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ -#define DMAC_CHCTRLA_RESETVALUE _U(0x00) /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (_U(0x1) << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (_U(0x1) << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_MASK _U(0x03) /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ - uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ - uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ - uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ - uint32_t :8; /*!< bit: 14..21 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ - uint32_t CMD:2; /*!< bit: 24..25 Software Command */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ -#define DMAC_CHCTRLB_RESETVALUE _U(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ - -#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ -#define DMAC_CHCTRLB_EVACT_Msk (_U(0x7) << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) -#define DMAC_CHCTRLB_EVACT_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_EVACT_TRIG_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CTRIG_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ -#define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U(0x4) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_EVACT_RESUME_Val _U(0x5) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_EVACT_SSKIP_Val _U(0x6) /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ -#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ -#define DMAC_CHCTRLB_EVIE (_U(0x1) << DMAC_CHCTRLB_EVIE_Pos) -#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ -#define DMAC_CHCTRLB_EVOE (_U(0x1) << DMAC_CHCTRLB_EVOE_Pos) -#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ -#define DMAC_CHCTRLB_LVL_Msk (_U(0x3) << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) -#define DMAC_CHCTRLB_LVL_LVL0_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */ -#define DMAC_CHCTRLB_LVL_LVL1_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */ -#define DMAC_CHCTRLB_LVL_LVL2_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */ -#define DMAC_CHCTRLB_LVL_LVL3_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */ -#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ -#define DMAC_CHCTRLB_TRIGSRC_Msk (_U(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) -#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ -#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ -#define DMAC_CHCTRLB_TRIGACT_Msk (_U(0x3) << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) -#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ -#define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U(0x3) /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ -#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (_U(0x3) << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) -#define DMAC_CHCTRLB_CMD_NOACT_Val _U(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val _U(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK _U(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (_U(0x1) << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (_U(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (_U(0x1) << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK _U(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (_U(0x1) << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (_U(0x1) << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (_U(0x1) << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK _U(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE _U(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ -#define DMAC_CHINTFLAG_TERR (_U(0x1) << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (_U(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (_U(0x1) << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK _U(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ -#define DMAC_CHSTATUS_RESETVALUE _U(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (_U(0x1) << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (_U(0x1) << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ -#define DMAC_CHSTATUS_FERR (_U(0x1) << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_MASK _U(0x07) /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE _U(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (_U(0x1) << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (_U(0x3) << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ -#define DMAC_BTCTRL_EVOSEL_BEAT_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (_U(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (_U(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (_U(0x1) << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (_U(0x1) << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (_U(0x1) << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val _U(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (_U(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val _U(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x1001030D) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E15A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21e16a.h b/atmel-samd/asf4/samd21/include/samd21e16a.h deleted file mode 100644 index 7bb07c660..000000000 --- a/atmel-samd/asf4/samd21/include/samd21e16a.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E16A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16A_ -#define _SAMD21E16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions - * This file defines all structures and symbols for SAMD21E16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x1001030C) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E16A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21e17a.h b/atmel-samd/asf4/samd21/include/samd21e17a.h deleted file mode 100644 index df037351a..000000000 --- a/atmel-samd/asf4/samd21/include/samd21e17a.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E17A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E17A_ -#define _SAMD21E17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions - * This file defines all structures and symbols for SAMD21E17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x1001030B) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E17A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21e18a.h b/atmel-samd/asf4/samd21/include/samd21e18a.h deleted file mode 100644 index 3b7a5c7a4..000000000 --- a/atmel-samd/asf4/samd21/include/samd21e18a.h +++ /dev/null @@ -1,552 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21E18A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E18A_ -#define _SAMD21E18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions - * This file defines all structures and symbols for SAMD21E18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21E18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -// #define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x1001030A) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E18A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g15a.h b/atmel-samd/asf4/samd21/include/samd21g15a.h deleted file mode 100644 index 5131ac4c9..000000000 --- a/atmel-samd/asf4/samd21/include/samd21g15a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G15A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G15A_ -#define _SAMD21G15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions - * This file defines all structures and symbols for SAMD21G15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010308) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G15A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g16a.h b/atmel-samd/asf4/samd21/include/samd21g16a.h deleted file mode 100644 index 102128025..000000000 --- a/atmel-samd/asf4/samd21/include/samd21g16a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G16A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G16A_ -#define _SAMD21G16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions - * This file defines all structures and symbols for SAMD21G16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010307) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G16A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g17a.h b/atmel-samd/asf4/samd21/include/samd21g17a.h deleted file mode 100644 index dc3b16128..000000000 --- a/atmel-samd/asf4/samd21/include/samd21g17a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G17A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G17A_ -#define _SAMD21G17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions - * This file defines all structures and symbols for SAMD21G17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010306) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G17A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g17au.h b/atmel-samd/asf4/samd21/include/samd21g17au.h deleted file mode 100644 index 46225b3bf..000000000 --- a/atmel-samd/asf4/samd21/include/samd21g17au.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G17AU - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G17AU_ -#define _SAMD21G17AU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions - * This file defines all structures and symbols for SAMD21G17AU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G17AU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g17au.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010310) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G17AU_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g18a.h b/atmel-samd/asf4/samd21/include/samd21g18a.h deleted file mode 100644 index 37480349a..000000000 --- a/atmel-samd/asf4/samd21/include/samd21g18a.h +++ /dev/null @@ -1,564 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G18A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G18A_ -#define _SAMD21G18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions - * This file defines all structures and symbols for SAMD21G18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -//#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010305) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G18A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21g18au.h b/atmel-samd/asf4/samd21/include/samd21g18au.h deleted file mode 100644 index 82c2532b6..000000000 --- a/atmel-samd/asf4/samd21/include/samd21g18au.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21G18AU - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G18AU_ -#define _SAMD21G18AU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions - * This file defines all structures and symbols for SAMD21G18AU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21G18AU-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g18au.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x1001030F) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G18AU_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21j15a.h b/atmel-samd/asf4/samd21/include/samd21j15a.h deleted file mode 100644 index 80aba23ec..000000000 --- a/atmel-samd/asf4/samd21/include/samd21j15a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J15A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J15A_ -#define _SAMD21J15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions - * This file defines all structures and symbols for SAMD21J15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J15A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00008000) /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00001000) /* 4 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010303) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J15A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21j16a.h b/atmel-samd/asf4/samd21/include/samd21j16a.h deleted file mode 100644 index b054d7ed8..000000000 --- a/atmel-samd/asf4/samd21/include/samd21j16a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J16A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J16A_ -#define _SAMD21J16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions - * This file defines all structures and symbols for SAMD21J16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J16A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010302) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J16A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21j17a.h b/atmel-samd/asf4/samd21/include/samd21j17a.h deleted file mode 100644 index bc85d9304..000000000 --- a/atmel-samd/asf4/samd21/include/samd21j17a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J17A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J17A_ -#define _SAMD21J17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions - * This file defines all structures and symbols for SAMD21J17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J17A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010301) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J17A_H */ diff --git a/atmel-samd/asf4/samd21/include/samd21j18a.h b/atmel-samd/asf4/samd21/include/samd21j18a.h deleted file mode 100644 index ee9a8fa1e..000000000 --- a/atmel-samd/asf4/samd21/include/samd21j18a.h +++ /dev/null @@ -1,576 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD21J18A - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J18A_ -#define _SAMD21J18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions - * This file defines all structures and symbols for SAMD21J18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#if !defined(_UL) -#define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#endif -#else -#if !defined(_UL) -#define _U(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L(x) x /**< Assembler: Long integer literal constant value */ -#define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif -#endif - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ - /****** SAMD21J18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void SVC_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define LITTLE_ENDIAN 1 -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL(0x10010300) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J18A_H */ diff --git a/atmel-samd/asf4/samd21/include/system_samd21.h b/atmel-samd/asf4/samd21/include/system_samd21.h deleted file mode 100644 index 223911ce6..000000000 --- a/atmel-samd/asf4/samd21/include/system_samd21.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup - * - * Copyright (c) 2016 Atmel Corporation, - * a wholly owned subsidiary of Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SYSTEM_SAMD21_H_INCLUDED_ -#define _SYSTEM_SAMD21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAMD21_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd21/main.c b/atmel-samd/asf4/samd21/main.c deleted file mode 100644 index 4652da488..000000000 --- a/atmel-samd/asf4/samd21/main.c +++ /dev/null @@ -1,11 +0,0 @@ -#include - -int main(void) -{ - /* Initializes MCU, drivers and middleware */ - atmel_start_init(); - - /* Replace with your application code */ - while (1) { - } -} diff --git a/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.s b/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.s deleted file mode 100644 index 96ef2cdbb..000000000 --- a/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/ARM/startup_SAMD21.s +++ /dev/null @@ -1,247 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.01 -; * @date 25. March 2015 -; * -; * @note -; * Copyright (C) 2014 - 2015 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface - DCD AC1_Handler ; 28 Analog Comparators 1 -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT AC1_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler -AC1_Handler - B . - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/system_samd21.c b/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/system_samd21.c deleted file mode 100644 index a4123b4e6..000000000 --- a/atmel-samd/asf4/samd21/samd21a/armcc/Device/SAMD21/Source/system_samd21.c +++ /dev/null @@ -1,78 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup. - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "samd21.h" - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (1000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} diff --git a/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.c b/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.c deleted file mode 100644 index f0a8de446..000000000 --- a/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.c +++ /dev/null @@ -1,389 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack CDC ACM Function Implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "cdcdf_acm.h" - -#define CDCDF_ACM_VERSION 0x00000001u -#define CDCDF_ACM_COMM_EP_INDEX 0 -#define CDCDF_ACM_DATA_EP_INDEX 1 - -/** USB Device CDC ACM Fucntion Specific Data */ -struct cdcdf_acm_func_data { - /** CDC Device ACM Interface information */ - uint8_t func_iface[2]; - /** CDC Device ACM IN Endpoint */ - uint8_t func_ep_in[2]; - /** CDC Device ACM OUT Endpoint */ - uint8_t func_ep_out; - /** CDC Device ACM Enable Flag */ - bool enabled; -}; - -static struct usbdf_driver _cdcdf_acm; -static struct cdcdf_acm_func_data _cdcdf_acm_funcd; -static struct usb_cdc_line_coding usbd_cdc_line_coding; - -static cdcdf_acm_notify_state_t cdcdf_acm_notify_state = NULL; -static cdcdf_acm_set_line_coding_t cdcdf_acm_set_line_coding = NULL; - -/** - * \brief Enable CDC ACM Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB interface descriptor - * \return Operation status. - */ -static int32_t cdcdf_acm_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct cdcdf_acm_func_data *func_data = (struct cdcdf_acm_func_data *)(drv->func_data); - - usb_ep_desc_t ep_desc; - usb_iface_desc_t ifc_desc; - uint8_t * ifc, *ep; - uint8_t i; - - ifc = desc->sod; - for (i = 0; i < 2; i++) { - if (NULL == ifc) { - return ERR_NOT_FOUND; - } - - ifc_desc.bInterfaceNumber = ifc[2]; - ifc_desc.bInterfaceClass = ifc[5]; - - if ((CDC_CLASS_COMM == ifc_desc.bInterfaceClass) || (CDC_CLASS_DATA == ifc_desc.bInterfaceClass)) { - if (func_data->func_iface[i] == ifc_desc.bInterfaceNumber) { // Initialized - return ERR_ALREADY_INITIALIZED; - } else if (func_data->func_iface[i] != 0xFF) { // Occupied - return ERR_NO_RESOURCE; - } else { - func_data->func_iface[i] = ifc_desc.bInterfaceNumber; - } - } else { // Not supported by this function driver - return ERR_NOT_FOUND; - } - - // Install endpoints - ep = usb_find_desc(ifc, desc->eod, USB_DT_ENDPOINT); - while (NULL != ep) { - ep_desc.bEndpointAddress = ep[2]; - ep_desc.bmAttributes = ep[3]; - ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); - if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { - return ERR_NOT_INITIALIZED; - } - if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { - func_data->func_ep_in[i] = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_in[i]); - } else { - func_data->func_ep_out = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_out); - } - desc->sod = ep; - ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); - } - ifc = usb_find_desc(usb_desc_next(desc->sod), desc->eod, USB_DT_INTERFACE); - } - // Installed - _cdcdf_acm_funcd.enabled = true; - return ERR_NONE; -} - -/** - * \brief Disable CDC ACM Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB device descriptor - * \return Operation status. - */ -static int32_t cdcdf_acm_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct cdcdf_acm_func_data *func_data = (struct cdcdf_acm_func_data *)(drv->func_data); - - usb_iface_desc_t ifc_desc; - uint8_t i; - - if (desc) { - ifc_desc.bInterfaceClass = desc->sod[5]; - // Check interface - if ((ifc_desc.bInterfaceClass != CDC_CLASS_COMM) && (ifc_desc.bInterfaceClass != CDC_CLASS_DATA)) { - return ERR_NOT_FOUND; - } - } - - for (i = 0; i < 2; i++) { - if (func_data->func_iface[i] == 0xFF) { - continue; - } else { - func_data->func_iface[i] = 0xFF; - if (func_data->func_ep_in[i] != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_in[i]); - func_data->func_ep_in[i] = 0xFF; - } - } - } - - if (func_data->func_ep_out != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_out); - func_data->func_ep_out = 0xFF; - } - - _cdcdf_acm_funcd.enabled = false; - return ERR_NONE; -} - -/** - * \brief CDC ACM Control Function - * \param[in] drv Pointer to USB device function driver - * \param[in] ctrl USB device general function control type - * \param[in] param Parameter pointer - * \return Operation status. - */ -static int32_t cdcdf_acm_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) -{ - switch (ctrl) { - case USBDF_ENABLE: - return cdcdf_acm_enable(drv, (struct usbd_descriptors *)param); - - case USBDF_DISABLE: - return cdcdf_acm_disable(drv, (struct usbd_descriptors *)param); - - case USBDF_GET_IFACE: - return ERR_UNSUPPORTED_OP; - - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the CDC class set request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t cdcdf_acm_set_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - struct usb_cdc_line_coding line_coding_tmp; - uint16_t len = req->wLength; - uint8_t * ctrl_buf = usbdc_get_ctrl_buffer(); - - switch (req->bRequest) { - case USB_REQ_CDC_SET_LINE_CODING: - if (sizeof(struct usb_cdc_line_coding) != len) { - return ERR_INVALID_DATA; - } - if (USB_SETUP_STAGE == stage) { - return usbdc_xfer(ep, ctrl_buf, len, false); - } else { - memcpy(&line_coding_tmp, ctrl_buf, sizeof(struct usb_cdc_line_coding)); - if ((NULL == cdcdf_acm_set_line_coding) || (true == cdcdf_acm_set_line_coding(&line_coding_tmp))) { - usbd_cdc_line_coding = line_coding_tmp; - } - return ERR_NONE; - } - case USB_REQ_CDC_SET_CONTROL_LINE_STATE: - usbdc_xfer(0, NULL, 0, 0); - if (NULL != cdcdf_acm_notify_state) { - cdcdf_acm_notify_state(req->wValue); - } - return ERR_NONE; - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the CDC class get request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t cdcdf_acm_get_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - uint16_t len = req->wLength; - - if (USB_DATA_STAGE == stage) { - return ERR_NONE; - } - - switch (req->bRequest) { - case USB_REQ_CDC_GET_LINE_CODING: - if (sizeof(struct usb_cdc_line_coding) != len) { - return ERR_INVALID_DATA; - } - return usbdc_xfer(ep, (uint8_t *)&usbd_cdc_line_coding, len, false); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the CDC class request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t cdcdf_acm_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request - return ERR_NOT_FOUND; - } - if ((req->wIndex == _cdcdf_acm_funcd.func_iface[0]) || (req->wIndex == _cdcdf_acm_funcd.func_iface[1])) { - if (req->bmRequestType & USB_EP_DIR_IN) { - return cdcdf_acm_get_req(ep, req, stage); - } else { - return cdcdf_acm_set_req(ep, req, stage); - } - } else { - return ERR_NOT_FOUND; - } -} - -/** USB Device CDC ACM Handler Struct */ -static struct usbdc_handler cdcdf_acm_req_h = {NULL, (FUNC_PTR)cdcdf_acm_req}; - -/** - * \brief Initialize the USB CDC ACM Function Driver - */ -int32_t cdcdf_acm_init(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _cdcdf_acm.ctrl = cdcdf_acm_ctrl; - _cdcdf_acm.func_data = &_cdcdf_acm_funcd; - - usbdc_register_function(&_cdcdf_acm); - usbdc_register_handler(USBDC_HDL_REQ, &cdcdf_acm_req_h); - return ERR_NONE; -} - -/** - * \brief Deinitialize the USB CDC ACM Function Driver - */ -void cdcdf_acm_deinit(void) -{ - usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_COMM_EP_INDEX]); - usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX]); - usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_out); -} - -/** - * \brief USB CDC ACM Function Read Data - */ -int32_t cdcdf_acm_read(uint8_t *buf, uint32_t size) -{ - if (!cdcdf_acm_is_enabled()) { - return ERR_DENIED; - } - return usbdc_xfer(_cdcdf_acm_funcd.func_ep_out, buf, size, false); -} - -/** - * \brief USB CDC ACM Function Write Data - */ -int32_t cdcdf_acm_write(uint8_t *buf, uint32_t size) -{ - if (!cdcdf_acm_is_enabled()) { - return ERR_DENIED; - } - return usbdc_xfer(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX], buf, size, true); -} - -/** - * \brief USB CDC ACM Stop the data transfer - */ -void cdcdf_acm_stop_xfer(void) -{ - /* Stop transfer. */ - usb_d_ep_abort(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX]); - usb_d_ep_abort(_cdcdf_acm_funcd.func_ep_out); -} - -/** - * \brief USB CDC ACM Function Register Callback - */ -int32_t cdcdf_acm_register_callback(enum cdcdf_acm_cb_type cb_type, FUNC_PTR func) -{ - switch (cb_type) { - case CDCDF_ACM_CB_READ: - usb_d_ep_register_callback(_cdcdf_acm_funcd.func_ep_out, USB_D_EP_CB_XFER, func); - break; - case CDCDF_ACM_CB_WRITE: - usb_d_ep_register_callback(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX], USB_D_EP_CB_XFER, func); - break; - case CDCDF_ACM_CB_LINE_CODING_C: - cdcdf_acm_set_line_coding = (cdcdf_acm_set_line_coding_t)func; - break; - case CDCDF_ACM_CB_STATE_C: - cdcdf_acm_notify_state = (cdcdf_acm_notify_state_t)func; - break; - default: - return ERR_INVALID_ARG; - } - return ERR_NONE; -} - -/** - * \brief Check whether CDC ACM Function is enabled - */ -bool cdcdf_acm_is_enabled(void) -{ - return _cdcdf_acm_funcd.enabled; -} - -/** - * \brief Return the CDC ACM line coding structure start address - */ -const struct usb_cdc_line_coding *cdcdf_acm_get_line_coding(void) -{ - return (const struct usb_cdc_line_coding *)&usbd_cdc_line_coding; -} - -/** - * \brief Return version - */ -uint32_t cdcdf_acm_get_version(void) -{ - return CDCDF_ACM_VERSION; -} diff --git a/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.h b/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.h deleted file mode 100644 index 913e734be..000000000 --- a/atmel-samd/asf4/samd21/usb/class/cdc/device/cdcdf_acm.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack CDC ACM Function Definition. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_CDC_ACM_SER_H_ -#define USBDF_CDC_ACM_SER_H_ - -#include "usbdc.h" -#include "usb_protocol_cdc.h" - -/** CDC ACM Class Callback Type */ -enum cdcdf_acm_cb_type { CDCDF_ACM_CB_READ, CDCDF_ACM_CB_WRITE, CDCDF_ACM_CB_LINE_CODING_C, CDCDF_ACM_CB_STATE_C }; - -/** CDC ACM Notify Line State Callback. */ -typedef void (*cdcdf_acm_notify_state_t)(uint16_t); - -/** CDC ACM Set Line Coding Callback. */ -typedef bool (*cdcdf_acm_set_line_coding_t)(struct usb_cdc_line_coding *); - -/** - * \brief Initialize the USB CDC ACM Function Driver - * \return Operation status. - */ -int32_t cdcdf_acm_init(void); - -/** - * \brief Deinitialize the USB CDC ACM Function Driver - * \return Operation status. - */ -void cdcdf_acm_deinit(void); - -/** - * \brief USB CDC ACM Function Read Data - * \param[in] buf Pointer to the buffer which receives data - * \param[in] size the size of data to be received - * \return Operation status. - */ -int32_t cdcdf_acm_read(uint8_t *buf, uint32_t size); - -/** - * \brief USB CDC ACM Function Write Data - * \param[in] buf Pointer to the buffer which stores data - * \param[in] size the size of data to be sent - * \return Operation status. - */ -int32_t cdcdf_acm_write(uint8_t *buf, uint32_t size); - -/** - * \brief USB CDC ACM Stop the currnet data transfer - */ -void cdcdf_acm_stop_xfer(void); - -/** - * \brief USB CDC ACM Function Register Callback - * \param[in] cb_type Callback type of CDC ACM Function - * \param[in] func Pointer to callback function - * \return Operation status. - */ -int32_t cdcdf_acm_register_callback(enum cdcdf_acm_cb_type cb_type, FUNC_PTR func); - -/** - * \brief Check whether CDC ACM Function is enabled - * \return Operation status. - * \return true CDC ACM Function is enabled - * \return false CDC ACM Function is disabled - */ -bool cdcdf_acm_is_enabled(void); - -/** - * \brief Return the CDC ACM line coding structure start address - * \return Pointer to USB CDC ACM line coding data. - */ -const struct usb_cdc_line_coding *cdcdf_acm_get_line_coding(void); - -/** - * \brief Return version - */ -uint32_t cdcdf_acm_get_version(void); - -#endif /* USBDF_CDC_ACM_SER_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/cdc/usb_protocol_cdc.h b/atmel-samd/asf4/samd21/usb/class/cdc/usb_protocol_cdc.h deleted file mode 100644 index 5213bd843..000000000 --- a/atmel-samd/asf4/samd21/usb/class/cdc/usb_protocol_cdc.h +++ /dev/null @@ -1,436 +0,0 @@ -/** - * \file - * - * \brief USB Communication Device Class (CDC) protocol definitions - * - * Copyright (c) 2015 - 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef _USB_PROTOCOL_CDC_H_ -#define _USB_PROTOCOL_CDC_H_ - -#include "usb_includes.h" - -/** - * \ingroup usb_protocol_group - * \defgroup cdc_protocol_group Communication Device Class Definitions - * @{ - */ - -/** - * \name Possible values of class - */ -//@{ -#define CDC_CLASS_DEVICE 0x02 //!< USB Communication Device Class -#define CDC_CLASS_COMM 0x02 //!< CDC Communication Class Interface -#define CDC_CLASS_DATA 0x0A //!< CDC Data Class Interface -//@} - -//! \name USB CDC Subclass IDs -//@{ -#define CDC_SUBCLASS_DLCM 0x01 //!< Direct Line Control Model -#define CDC_SUBCLASS_ACM 0x02 //!< Abstract Control Model -#define CDC_SUBCLASS_TCM 0x03 //!< Telephone Control Model -#define CDC_SUBCLASS_MCCM 0x04 //!< Multi-Channel Control Model -#define CDC_SUBCLASS_CCM 0x05 //!< CAPI Control Model -#define CDC_SUBCLASS_ETH 0x06 //!< Ethernet Networking Control Model -#define CDC_SUBCLASS_ATM 0x07 //!< ATM Networking Control Model -//@} - -//! \name USB CDC Communication Interface Protocol IDs -//@{ -#define CDC_PROTOCOL_V25TER 0x01 //!< Common AT commands -//@} - -//! \name USB CDC Data Interface Protocol IDs -//@{ -#define CDC_PROTOCOL_I430 0x30 //!< ISDN BRI -#define CDC_PROTOCOL_HDLC 0x31 //!< HDLC -#define CDC_PROTOCOL_TRANS 0x32 //!< Transparent -#define CDC_PROTOCOL_Q921M 0x50 //!< Q.921 management protocol -#define CDC_PROTOCOL_Q921 0x51 //!< Q.931 [sic] Data link protocol -#define CDC_PROTOCOL_Q921TM 0x52 //!< Q.921 TEI-multiplexor -#define CDC_PROTOCOL_V42BIS 0x90 //!< Data compression procedures -#define CDC_PROTOCOL_Q931 0x91 //!< Euro-ISDN protocol control -#define CDC_PROTOCOL_V120 0x92 //!< V.24 rate adaption to ISDN -#define CDC_PROTOCOL_CAPI20 0x93 //!< CAPI Commands -#define CDC_PROTOCOL_HOST 0xFD //!< Host based driver - /** - * \brief Describes the Protocol Unit Functional Descriptors [sic] - * on Communication Class Interface - */ -#define CDC_PROTOCOL_PUFD 0xFE -//@} - -//! \name USB CDC Functional Descriptor Types -//@{ -#define CDC_CS_INTERFACE 0x24 //!< Interface Functional Descriptor -#define CDC_CS_ENDPOINT 0x25 //!< Endpoint Functional Descriptor -//@} - -//! \name USB CDC Functional Descriptor Subtypes -//@{ -#define CDC_SCS_HEADER 0x00 //!< Header Functional Descriptor -#define CDC_SCS_CALL_MGMT 0x01 //!< Call Management -#define CDC_SCS_ACM 0x02 //!< Abstract Control Management -#define CDC_SCS_UNION 0x06 //!< Union Functional Descriptor -//@} - -//! \name USB CDC Request IDs -//@{ -#define USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND 0x00 -#define USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE 0x01 -#define USB_REQ_CDC_SET_COMM_FEATURE 0x02 -#define USB_REQ_CDC_GET_COMM_FEATURE 0x03 -#define USB_REQ_CDC_CLEAR_COMM_FEATURE 0x04 -#define USB_REQ_CDC_SET_AUX_LINE_STATE 0x10 -#define USB_REQ_CDC_SET_HOOK_STATE 0x11 -#define USB_REQ_CDC_PULSE_SETUP 0x12 -#define USB_REQ_CDC_SEND_PULSE 0x13 -#define USB_REQ_CDC_SET_PULSE_TIME 0x14 -#define USB_REQ_CDC_RING_AUX_JACK 0x15 -#define USB_REQ_CDC_SET_LINE_CODING 0x20 -#define USB_REQ_CDC_GET_LINE_CODING 0x21 -#define USB_REQ_CDC_SET_CONTROL_LINE_STATE 0x22 -#define USB_REQ_CDC_SEND_BREAK 0x23 -#define USB_REQ_CDC_SET_RINGER_PARMS 0x30 -#define USB_REQ_CDC_GET_RINGER_PARMS 0x31 -#define USB_REQ_CDC_SET_OPERATION_PARMS 0x32 -#define USB_REQ_CDC_GET_OPERATION_PARMS 0x33 -#define USB_REQ_CDC_SET_LINE_PARMS 0x34 -#define USB_REQ_CDC_GET_LINE_PARMS 0x35 -#define USB_REQ_CDC_DIAL_DIGITS 0x36 -#define USB_REQ_CDC_SET_UNIT_PARAMETER 0x37 -#define USB_REQ_CDC_GET_UNIT_PARAMETER 0x38 -#define USB_REQ_CDC_CLEAR_UNIT_PARAMETER 0x39 -#define USB_REQ_CDC_GET_PROFILE 0x3A -#define USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 -#define USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41 -#define USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42 -#define USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER 0x43 -#define USB_REQ_CDC_GET_ETHERNET_STATISTIC 0x44 -#define USB_REQ_CDC_SET_ATM_DATA_FORMAT 0x50 -#define USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS 0x51 -#define USB_REQ_CDC_SET_ATM_DEFAULT_VC 0x52 -#define USB_REQ_CDC_GET_ATM_VC_STATISTICS 0x53 -// Added bNotification codes according cdc spec 1.1 chapter 6.3 -#define USB_REQ_CDC_NOTIFY_RING_DETECT 0x09 -#define USB_REQ_CDC_NOTIFY_SERIAL_STATE 0x20 -#define USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE 0x28 -#define USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE 0x29 -//@} - -/* - * Need to pack structures tightly, or the compiler might insert padding - * and violate the spec-mandated layout. - */ -COMPILER_PACK_SET(1) - -//! \name USB CDC Descriptors -//@{ - -//! CDC Header Functional Descriptor -typedef struct usb_cdc_hdr_desc { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - le16_t bcdCDC; -} usb_cdc_hdr_desc_t; - -#define USB_CDC_HDR_DESC_LEN 5 -#define USB_CDC_HDR_DESC_BYTES(bcdCDC) \ - USB_CDC_HDR_DESC_LEN, /* bFunctionLength */ \ - CDC_CS_INTERFACE, /* bDescriptorType */ \ - CDC_SCS_HEADER, /* bDescriptorSubtype */ \ - LE_BYTE0(bcdCDC), LE_BYTE1(bcdCDC) /* bcdCDC */ - -//! CDC Call Management Functional Descriptor -typedef struct usb_cdc_call_mgmt_desc { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bmCapabilities; - uint8_t bDataInterface; -} usb_cdc_call_mgmt_desc_t; - -#define USB_CDC_CALL_MGMT_DESC_LEN 5 -#define USB_CDC_CALL_MGMT_DESC_BYTES(bmCapabilities, bDataInterface) \ - USB_CDC_CALL_MGMT_DESC_LEN, /* bFunctionLength */ \ - CDC_CS_INTERFACE, /* bDescriptorType */ \ - CDC_SCS_CALL_MGMT, /* bDescriptorSubtype */ \ - bmCapabilities, bDataInterface - -//! CDC ACM Functional Descriptor -typedef struct usb_cdc_acm_desc { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bmCapabilities; -} usb_cdc_acm_desc_t; - -#define USB_CDC_ACM_DESC_LEN 4 -#define USB_CDC_ACM_DESC_BYTES(bmCapabilities) \ - USB_CDC_ACM_DESC_LEN, /* bFunctionLength */ \ - CDC_CS_INTERFACE, /* bDescriptorType */ \ - CDC_SCS_ACM, /* bDescriptorSubType */ \ - bmCapabilities - -//! CDC Union Functional Descriptor -typedef struct usb_cdc_union_desc { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bMasterInterface; - uint8_t bSlaveInterface0; -} usb_cdc_union_desc_t; - -#define USB_CDC_UNION_DESC_LEN 5 -#define USB_CDC_UNION_DESC_BYTES(bMasterInterface, bSlaveInterface) \ - USB_CDC_UNION_DESC_LEN, CDC_CS_INTERFACE, CDC_SCS_UNION, bMasterInterface, bSlaveInterface - -//! \name USB CDC Call Management Capabilities -//@{ -//! Device handles call management itself -#define CDC_CALL_MGMT_SUPPORTED (1 << 0) -//! Device can send/receive call management info over a Data Class interface -#define CDC_CALL_MGMT_OVER_DCI (1 << 1) -//@} - -//! \name USB CDC ACM Capabilities -//@{ -//! Device supports the request combination of -//! Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature. -#define CDC_ACM_SUPPORT_FEATURE_REQUESTS (1 << 0) -//! Device supports the request combination of -//! Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, -//! and the notification Serial_State. -#define CDC_ACM_SUPPORT_LINE_REQUESTS (1 << 1) -//! Device supports the request Send_Break -#define CDC_ACM_SUPPORT_SENDBREAK_REQUESTS (1 << 2) -//! Device supports the notification Network_Connection. -#define CDC_ACM_SUPPORT_NOTIFY_REQUESTS (1 << 3) -//@} -//@} - -//! \name USB CDC line control -//@{ - -//! \name USB CDC line coding -//@{ - -//! Line Coding structure -typedef struct usb_cdc_line_coding { - le32_t dwDTERate; //!< Data rate, bits per second - uint8_t bCharFormat; //!< 0-1 Stop bit,1-1.5 Stop bits,2-2 Stop bits - uint8_t bParityType; //!< 0-None,1-Odd,2-Even,3-Mark,4-Space - uint8_t bDataBits; //!< 5,6,7,8 or 16 -} usb_cdc_line_coding_t; - -//! Possible values of bCharFormat -enum cdc_char_format { - CDC_STOP_BITS_1 = 0, //!< 1 stop bit - CDC_STOP_BITS_1_5 = 1, //!< 1.5 stop bits - CDC_STOP_BITS_2 = 2 //!< 2 stop bits -}; - -//! Possible values of bParityType -enum cdc_parity { - CDC_PAR_NONE = 0, //!< No parity - CDC_PAR_ODD = 1, //!< Odd parity - CDC_PAR_EVEN = 2, //!< Even parity - CDC_PAR_MARK = 3, //!< Parity forced to 1 (mark) - CDC_PAR_SPACE = 4 //!< Parity forced to 0 (space) -}; -//@} - -//! \name USB CDC control signals -//! spec 1.1 chapter 6.2.14 -//@{ - -//! Control signal structure -typedef struct usb_cdc_control_signal { - union { - le16_t value; - struct { - uint8_t dte_present; - uint8_t carrier_ctrl; - } modem; - struct { - uint8_t DTR : 1; //!< Data Terminal Ready - uint8_t RTS : 1; //!< Request To Send - } rs232; - struct { - uint8_t s108_2 : 1; //!< V.24 signal 108/2 - uint8_t s105 : 1; //!< V.24 signal 105 - } v24; - }; -} usb_cdc_control_signal_t; - -//! \name Possible values in usb_cdc_control_signal_t -//@{ -//! Carrier control for half duplex modems. -//! This signal corresponds to V.24 signal 105 and RS-232 signal RTS. -//! The device ignores the value of this bit -//! when operating in full duplex mode. -#define CDC_CTRL_SIGNAL_ACTIVATE_CARRIER (1 << 1) -//! Indicates to DCE if DTE is present or not. -//! This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR. -#define CDC_CTRL_SIGNAL_DTE_PRESENT (1 << 0) -//@} -//@} - -//! \name USB CDC notification message -//@{ - -typedef struct usb_cdc_notify_msg { - uint8_t bmRequestType; - uint8_t bNotification; - union { - le16_t wValue; - struct { - uint8_t low; - uint8_t high; - } wValueBytes; - }; - union { - le16_t wIndex; - struct { - uint8_t low; - uint8_t high; - } wIndexBytes; - }; - union { - le16_t wLength; - struct { - uint8_t low; - uint8_t high; - } wLengthBytes; - }; -} usb_cdc_notify_msg_t; - -//! \name USB CDC serial state -//@{* - -//! UART State Bitmap (cdc spec 1.1 chapter 6.3.5) -typedef union usb_cdc_uart_state { - le16_t value; - struct { - uint8_t bRxCarrier : 1; - uint8_t bTxCarrier : 1; - uint8_t bBreak : 1; - uint8_t bRingSignal : 1; - uint8_t bFraming : 1; - uint8_t bParity : 1; - uint8_t bOverRun; - } bitmap; - struct { - uint8_t bDCD : 1; - uint8_t bDSR : 1; - uint8_t bBreak : 1; - uint8_t bRingSignal : 1; - uint8_t bFraming : 1; - uint8_t bParity : 1; - uint8_t bOverRun; - } rs232; - struct { - uint8_t bS109 : 1; //!< V.24 signal 109 - uint8_t bS106 : 1; //!< V.24 signal 106 - uint8_t bBreak : 1; - uint8_t bRingSignal : 1; - uint8_t bFraming : 1; - uint8_t bParity : 1; - uint8_t bOverRun; - } v24; -} usb_cdc_uart_state_t; - -//! Hardware handshake support (cdc spec 1.1 chapter 6.3.5) -typedef struct usb_cdc_notify_serial_state { - usb_cdc_notify_msg_t header; - union usb_cdc_uart_state state; -} usb_cdc_notify_serial_state_t; - -//! \name Possible values in usb_cdc_notify_serial_state_t -//@{ -#define CDC_SERIAL_STATE_DCD CPU_TO_LE16((1 << 0)) -#define CDC_SERIAL_STATE_DSR CPU_TO_LE16((1 << 1)) -#define CDC_SERIAL_STATE_BREAK CPU_TO_LE16((1 << 2)) -#define CDC_SERIAL_STATE_RING CPU_TO_LE16((1 << 3)) -#define CDC_SERIAL_STATE_FRAMING CPU_TO_LE16((1 << 4)) -#define CDC_SERIAL_STATE_PARITY CPU_TO_LE16((1 << 5)) -#define CDC_SERIAL_STATE_OVERRUN CPU_TO_LE16((1 << 6)) -//@} -//! @} - -//! @} - -COMPILER_PACK_RESET() - -//! @} - -/** - * \brief Fill a CDC SetLineCoding request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - */ -static inline void usb_fill_SetLineCoding_req(struct usb_req *req, uint8_t iface) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_CDC_SET_LINE_CODING; - req->wValue = 0; - req->wIndex = iface; - req->wLength = sizeof(usb_cdc_line_coding_t); -} - -/** - * \brief Fill a CDC SetControlLineState request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - * \param[in] ctrl Control Signal Bitmap - */ -static inline void usb_fill_SetControlLineState_req(struct usb_req *req, uint8_t iface, uint16_t ctrl) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_CDC_SET_CONTROL_LINE_STATE; - req->wValue = ctrl; - req->wIndex = iface; - req->wLength = 0; -} - -#endif // _USB_PROTOCOL_CDC_H_ diff --git a/atmel-samd/asf4/samd21/usb/class/composite/device/composite_desc.h b/atmel-samd/asf4/samd21/usb/class/composite/device/composite_desc.h deleted file mode 100644 index 9838e40c1..000000000 --- a/atmel-samd/asf4/samd21/usb/class/composite/device/composite_desc.h +++ /dev/null @@ -1,188 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack Composite Class Descriptor Setting. - * - * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_COMPOSITE_DESC_H_ -#define USBDF_COMPOSITE_DESC_H_ - -#include "usb_protocol.h" -#include "usbd_composite_config.h" - -#if CONF_USB_COMPOSITE_CDC_ACM_EN == 1 -#define CONF_CDC_ACM_IFC_LEN 66 -#define CONF_CDC_ACM_IFC_NUM 2 -#define CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM 0 -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM 1 -#define CONF_CDC_ACM_IFC_DESC \ - USB_IAD_DESC_BYTES( \ - CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, 0x02, CDC_CLASS_DEVICE, CDC_SUBCLASS_ACM, CDC_PROTOCOL_V25TER, 0x00) \ - , \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, \ - 0x00, \ - 0x01, \ - CDC_CLASS_DEVICE, \ - CDC_SUBCLASS_ACM, \ - CDC_PROTOCOL_V25TER, \ - 0x00), \ - USB_CDC_HDR_DESC_BYTES(0x1001), USB_CDC_CALL_MGMT_DESC_BYTES(0x01, 0x00), USB_CDC_ACM_DESC_BYTES(0x02), \ - USB_CDC_UNION_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, 0x01), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR, 3, CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ, 10), \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM, 0x00, 2, 0x0A, 0x00, 0x00, 0x00), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR, 2, CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ, 0x00), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR, 2, CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ, 0x00), -#else -#define CONF_CDC_ACM_IFC_LEN 0 -#define CONF_CDC_ACM_IFC_NUM 0 -#define CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM -2 -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM -1 -#define CONF_CDC_ACM_IFC_DESC -#endif - -#if CONF_USB_COMPOSITE_HID_MOUSE_EN == 1 -#define CONF_HID_MOUSE_IFC_LEN 25 -#define CONF_HID_MOUSE_IFC_NUM 1 -#define CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM (CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM + 1) -#define CONF_HID_MOUSE_IFC_DESC \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM, 0x00, 0x01, 0x03, 0x01, 0x02, 0x00) \ - , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, 0x34), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ, 10), -#else -#define CONF_HID_MOUSE_IFC_LEN 0 -#define CONF_HID_MOUSE_IFC_NUM 0 -#define CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM -#define CONF_HID_MOUSE_IFC_DESC -#endif - -#if CONF_USB_COMPOSITE_HID_KEYBOARD_EN == 1 -#define CONF_HID_KEYBOARD_IFC_LEN 32 -#define CONF_HID_KEYBOARD_IFC_NUM 1 -#define CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM (CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM + 1) -#define CONF_HID_KEYBOARD_IFC_DESC \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM, 0x00, 0x02, 0x03, 0x01, 0x01, 0x00) \ - , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, 59), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ, 10), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ, 10), -#else -#define CONF_HID_KEYBOARD_IFC_LEN 0 -#define CONF_HID_KEYBOARD_IFC_NUM 0 -#define CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM -#define CONF_HID_KEYBOARD_IFC_DESC -#endif - -#if CONF_USB_COMPOSITE_HID_GENERIC_EN == 1 -#define CONF_HID_GENERIC_IFC_LEN 32 -#define CONF_HID_GENERIC_IFC_NUM 1 -#define CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM (CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM + 1) -#define CONF_HID_GENERIC_IFC_DESC \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM, 0x00, 0x02, 0x03, 0x00, 0x00, 0x00) \ - , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ, 10), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ, 10), -#else -#define CONF_HID_GENERIC_IFC_LEN 0 -#define CONF_HID_GENERIC_IFC_NUM 0 -#define CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM -#define CONF_HID_GENERIC_IFC_DESC -#endif - -#if CONF_USB_COMPOSITE_MSC_EN == 1 -#define CONF_MSC_IFC_LEN 23 /* (9 + 7 * 2) */ -#define CONF_MSC_IFC_NUM 1 -#define CONF_USB_COMPOSITE_MSC_BIFCNUM (CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM + 1) -#define CONF_MSC_IFC_DESC \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BIFCNUM, 0x00, 0x02, 0x08, 0x06, 0x50, 0x00) \ - , USB_ENDP_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR, 0x02, CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ, 0), \ - USB_ENDP_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR, 0x02, CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ, 0), -#else -#define CONF_MSC_IFC_LEN 0 -#define CONF_MSC_IFC_NUM 0 -#define CONF_USB_COMPOSITE_MSC_BIFCNUM CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM -#define CONF_MSC_IFC_DESC -#endif - -#define CONF_USB_COMPOSITE_TOTAL_LEN \ - (USB_CONFIG_DESC_LEN + CONF_CDC_ACM_IFC_LEN + CONF_HID_MOUSE_IFC_LEN + CONF_HID_KEYBOARD_IFC_LEN \ - + CONF_HID_GENERIC_IFC_LEN \ - + CONF_MSC_IFC_LEN) - -#define CONF_USB_COMPOSITE_IFC_NUM \ - (CONF_CDC_ACM_IFC_NUM + CONF_HID_MOUSE_IFC_NUM + CONF_HID_KEYBOARD_IFC_NUM + CONF_HID_GENERIC_IFC_NUM \ - + CONF_MSC_IFC_NUM) - -#define COMPOSITE_DEV_DESC \ - USB_DEV_DESC_BYTES(CONF_USB_COMPOSITE_BCDUSB, \ - 0xEF, \ - 0x02, \ - 0x01, \ - CONF_USB_COMPOSITE_BMAXPKSZ0, \ - CONF_USB_COMPOSITE_IDVENDER, \ - CONF_USB_COMPOSITE_IDPRODUCT, \ - CONF_USB_COMPOSITE_BCDDEVICE, \ - CONF_USB_COMPOSITE_IMANUFACT, \ - CONF_USB_COMPOSITE_IPRODUCT, \ - CONF_USB_COMPOSITE_ISERIALNUM, \ - CONF_USB_COMPOSITE_BNUMCONFIG) - -#define COMPOSITE_CFG_DESC \ - USB_CONFIG_DESC_BYTES(CONF_USB_COMPOSITE_TOTAL_LEN, \ - CONF_USB_COMPOSITE_IFC_NUM, \ - CONF_USB_COMPOSITE_BCONFIGVAL, \ - CONF_USB_COMPOSITE_ICONFIG, \ - CONF_USB_COMPOSITE_BMATTRI, \ - CONF_USB_COMPOSITE_BMAXPOWER) - -#define COMPOSITE_IFACE_DESCES \ - CONF_CDC_ACM_IFC_DESC \ - CONF_HID_MOUSE_IFC_DESC \ - CONF_HID_KEYBOARD_IFC_DESC \ - CONF_HID_GENERIC_IFC_DESC \ - CONF_MSC_IFC_DESC - -/** USB Device descriptors and configuration descriptors */ -#define COMPOSITE_DESCES_LS_FS \ - COMPOSITE_DEV_DESC, COMPOSITE_CFG_DESC, COMPOSITE_IFACE_DESCES CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC, \ - CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC, CONF_USB_COMPOSITE_PRODUCT_STR_DESC - -#endif /* USBDF_COMPOSITE_DESC_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/composite/device/usbd_composite_config.h b/atmel-samd/asf4/samd21/usb/class/composite/device/usbd_composite_config.h deleted file mode 100644 index 08f43b379..000000000 --- a/atmel-samd/asf4/samd21/usb/class/composite/device/usbd_composite_config.h +++ /dev/null @@ -1,603 +0,0 @@ -/* Auto-generated config file usbd_composite_config.h */ -#ifndef USBD_COMPOSITE_CONFIG_H -#define USBD_COMPOSITE_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Composite Device Descriptor - -// bcdUSB -// <0x0200=> USB 2.0 version -// <0x0210=> USB 2.1 version -// usb_composite_bcdusb -#ifndef CONF_USB_COMPOSITE_BCDUSB -#define CONF_USB_COMPOSITE_BCDUSB 0x200 -#endif - -// bMaxPackeSize0 -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_bmaxpksz0 -#ifndef CONF_USB_COMPOSITE_BMAXPKSZ0 -#define CONF_USB_COMPOSITE_BMAXPKSZ0 0x40 -#endif - -// idVender <0x0000-0xFFFF> -// usb_composite_idvender -#ifndef CONF_USB_COMPOSITE_IDVENDER -#define CONF_USB_COMPOSITE_IDVENDER 0x3eb -#endif - -// idProduct <0x0000-0xFFFF> -// usb_composite_idproduct -#ifndef CONF_USB_COMPOSITE_IDPRODUCT -#define CONF_USB_COMPOSITE_IDPRODUCT 0x2421 -#endif - -// bcdDevice <0x0000-0xFFFF> -// usb_composite_bcddevice -#ifndef CONF_USB_COMPOSITE_BCDDEVICE -#define CONF_USB_COMPOSITE_BCDDEVICE 0x100 -#endif - -// iManufacturer <0x00-0xFF> -// usb_composite_imanufact -#ifndef CONF_USB_COMPOSITE_IMANUFACT -#define CONF_USB_COMPOSITE_IMANUFACT 0x0 -#endif - -#ifndef CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC -#define CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC 0x04, 0x03, 0x09, 0x04 -#endif - -#ifndef CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC -#define CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC \ - 0x14, 0x03, 0x41, 0x00, 0x54, 0x00, 0x4D, 0x00, 0x45, 0x00, 0x4C, 0x00, 0x20, 0x00, 0x41, 0x00, 0x53, 0x00, 0x46, \ - 0x00 -#endif - -// iProduct <0x00-0xFF> -// usb_composite_iproduct -#ifndef CONF_USB_COMPOSITE_IPRODUCT -#define CONF_USB_COMPOSITE_IPRODUCT 0x0 -#endif - -#ifndef CONF_USB_COMPOSITE_PRODUCT_STR_DESC -#define CONF_USB_COMPOSITE_PRODUCT_STR_DESC \ - 0x22, 0x03, 0x43, 0x00, 0x6f, 0x00, 0x6d, 0x00, 0x70, 0x00, 0x6f, 0x00, 0x73, 0x00, 0x69, 0x00, 0x74, 0x00, 0x65, \ - 0x00, 0x20, 0x00, 0x44, 0x00, 0x65, 0x00, 0x76, 0x00, 0x69, 0x00, 0x63, 0x00, 0x65, 0x00 -#endif - -// iSerialNumber <0x00-0xFF> -// usb_composite_iserialnum -#ifndef CONF_USB_COMPOSITE_ISERIALNUM -#define CONF_USB_COMPOSITE_ISERIALNUM 0x0 -#endif - -// bNumConfigurations <0x01-0xFF> -// usb_composite_bnumconfig -#ifndef CONF_USB_COMPOSITE_BNUMCONFIG -#define CONF_USB_COMPOSITE_BNUMCONFIG 0x1 -#endif -// - -// Composite Configuration Descriptor - -// bConfigurationValue <0x01-0xFF> -// usb_composite_bconfigval -#ifndef CONF_USB_COMPOSITE_BCONFIGVAL -#define CONF_USB_COMPOSITE_BCONFIGVAL 0x1 -#endif - -// iConfiguration <0x00-0xFF> -// usb_composite_iconfig -#ifndef CONF_USB_COMPOSITE_ICONFIG -#define CONF_USB_COMPOSITE_ICONFIG 0x0 -#endif - -// bmAttributes -// <0x80=> Bus power supply, not support for remote wakeup -// <0xA0=> Bus power supply, support for remote wakeup -// <0xC0=> Self powered, not support for remote wakeup -// <0xE0=> Self powered, support for remote wakeup -// usb_composite_bmattri -#ifndef CONF_USB_COMPOSITE_BMATTRI -#define CONF_USB_COMPOSITE_BMATTRI 0x80 -#endif - -// bMaxPower <0x00-0xFF> -// usb_composite_bmaxpower -#ifndef CONF_USB_COMPOSITE_BMAXPOWER -#define CONF_USB_COMPOSITE_BMAXPOWER 0x32 -#endif -// - -// CDC ACM Support -// usb_composite_cdc_acm_support -#ifndef CONF_USB_COMPOSITE_CDC_ACM_EN -#define CONF_USB_COMPOSITE_CDC_ACM_EN 1 -#endif - -// CDC ACM Comm Interrupt IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_cdc_acm_epaddr -#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR -#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR 0x82 -#endif - -// CDC ACM Comm Interrupt IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_cdc_acm_comm_int_maxpksz -#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ -#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ 0x40 -#endif - -// CDC ACM Data BULK IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_cdc_acm_data_bulkin_epaddr -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR 0x81 -#endif - -// CDC ACM Data BULK IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_cdc_acm_data_builin_maxpksz -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ 0x40 -#endif - -// CDC ACM Data BULK OUT Endpoint Address -// <0x01=> EndpointAddress = 0x01 -// <0x02=> EndpointAddress = 0x02 -// <0x03=> EndpointAddress = 0x03 -// <0x04=> EndpointAddress = 0x04 -// <0x05=> EndpointAddress = 0x05 -// <0x06=> EndpointAddress = 0x06 -// <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_cdc_acm_data_bulkout_epaddr -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR 0x1 -#endif - -// CDC ACM Data BULK OUT Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_cdc_acm_data_buckout_maxpksz -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ 0x40 -#endif - -// CDC ACM Echo Demo generation -// conf_usb_composite_cdc_echo_demo -// Invoke cdcdf_acm_demo_init(buf[wMaxPacketSize]) to enable the echo demo. -// Buf is packet buffer for data receive and echo back. -// The buffer is 4 byte aligned to support DMA. -#ifndef CONF_USB_COMPOSITE_CDC_ECHO_DEMO -#define CONF_USB_COMPOSITE_CDC_ECHO_DEMO 0 -#endif - -// - -// HID Mouse Support -// usb_composite_hid_mouse_support -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_EN -#define CONF_USB_COMPOSITE_HID_MOUSE_EN 0 -#endif - -// HID Mouse INTERRUPT IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_hid_mouse_intin_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR -#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR 0x83 -#endif - -// HID Mouse INTERRUPT IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_mouse_intin_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ 0x8 -#endif - -// HID Mouse Move Demo generation -// conf_usb_composite_hid_mouse_demo -// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. -// Button1 and button3 are the pins used for mouse moving left and right. -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_DEMO -#define CONF_USB_COMPOSITE_HID_MOUSE_DEMO 0 -#endif - -// - -// HID Keyboard Support -// usb_composite_hid_keyboard_support -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_EN -#define CONF_USB_COMPOSITE_HID_KEYBOARD_EN 0 -#endif - -// HID Keyboard INTERRUPT IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_hid_keyboard_intin_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR 0x84 -#endif - -// HID Keyboard INTERRUPT IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_keyboard_intin_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ 0x8 -#endif - -// HID Keyboard INTERRUPT OUT Endpoint Address -// <0x01=> EndpointAddress = 0x01 -// <0x02=> EndpointAddress = 0x02 -// <0x03=> EndpointAddress = 0x03 -// <0x04=> EndpointAddress = 0x04 -// <0x05=> EndpointAddress = 0x05 -// <0x06=> EndpointAddress = 0x06 -// <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_hid_keyboard_intout_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR 0x2 -#endif - -// HID Keyboard INTERRUPT OUT Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_keyboard_intout_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ 0x8 -#endif - -// HID Keyboard Caps Lock Demo generation -// conf_usb_composite_hid_keyboard_demo -// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. -// Buffon2 is the pin used for keyboard CAPS LOCK simulation. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO -#define CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO 0 -#endif - -// - -// HID Generic Support -// usb_composite_hid_generic_support -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_EN -#define CONF_USB_COMPOSITE_HID_GENERIC_EN 0 -#endif - -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN -#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN 53 -#endif - -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT -#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ - 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ - 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ - 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 -#endif - -// HID Generic INTERRUPT IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_hid_generic_intin_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR -#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR 0x85 -#endif - -// HID Generic INTERRUPT IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_generic_intin_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ 0x40 -#endif - -// HID Generic INTERRUPT OUT Endpoint Address -// <0x01=> EndpointAddress = 0x01 -// <0x02=> EndpointAddress = 0x02 -// <0x03=> EndpointAddress = 0x03 -// <0x04=> EndpointAddress = 0x04 -// <0x05=> EndpointAddress = 0x05 -// <0x06=> EndpointAddress = 0x06 -// <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_hid_generic_intout_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR -#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR 0x3 -#endif - -// HID Generic INTERRUPT OUT Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes -// usb_composite_hid_generic_intout_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ 0x40 -#endif - -// - -// MSC Support -// usb_composite_msc_support -#ifndef CONF_USB_COMPOSITE_MSC_EN -#define CONF_USB_COMPOSITE_MSC_EN 0 -#endif - -// MSC BULK Endpoints wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_msc_bulk_maxpksz -#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ -#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ 0x0040 -#endif - -// MSC BULK IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_msc_bulkin_epaddr -#ifndef CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR -#define CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR 0x86 -#endif - -// MSC BULK OUT Endpoint Address -// <0x01=> EndpointAddress = 0x01 -// <0x02=> EndpointAddress = 0x02 -// <0x03=> EndpointAddress = 0x03 -// <0x04=> EndpointAddress = 0x04 -// <0x05=> EndpointAddress = 0x05 -// <0x06=> EndpointAddress = 0x06 -// <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_msc_bulkout_epaddr -#ifndef CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR -#define CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR 0x04 -#endif - -// Enable Demo code for Disk LUN handling -// usb_composite_msc_demo_en -#ifndef CONF_USB_COMPOSITE_MSC_LUN_DEMO -#define CONF_USB_COMPOSITE_MSC_LUN_DEMO 1 -#endif - -// Disk access cache/buffer of sectors if non-RAM disk enabled <1-64> -// conf_usb_msc_lun_buf_sectors -#ifndef CONF_USB_MSC_LUN_BUF_SECTORS -#define CONF_USB_MSC_LUN_BUF_SECTORS 4 -#endif - -// Enable Demo for RAM Disk -// conf_usb_msc_lun0_enable -#ifndef CONF_USB_MSC_LUN0_ENABLE -#define CONF_USB_MSC_LUN0_ENABLE 1 -#endif - -#ifndef CONF_USB_MSC_LUN0_TYPE -#define CONF_USB_MSC_LUN0_TYPE 0x00 -#endif - -// The disk is removable -// conf_usb_msc_lun0_rmb -#ifndef CONF_USB_MSC_LUN0_RMB -#define CONF_USB_MSC_LUN0_RMB 0x01 -#endif - -#ifndef CONF_USB_MSC_LUN0_ISO -#define CONF_USB_MSC_LUN0_ISO 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN0_ECMA -#define CONF_USB_MSC_LUN0_ECMA 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN0_ANSI -#define CONF_USB_MSC_LUN0_ANSI 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN0_REPO -#define CONF_USB_MSC_LUN0_REPO 0x01 -#endif - -#ifndef CONF_USB_MSC_LUN0_FACTORY -#define CONF_USB_MSC_LUN0_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN0_PRODUCT -#define CONF_USB_MSC_LUN0_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN0_PRODUCT_VERSION -#define CONF_USB_MSC_LUN0_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 -#endif - -// Disk Size (in KB) <1-65535> -// Windows will not show disk less than 20K, so 22K is used to reserve more RAM for app -// conf_usb_msc_lun0_capacity - -#ifndef CONF_USB_MSC_LUN0_CAPACITY -#define CONF_USB_MSC_LUN0_CAPACITY 0x16 -#endif - -#ifndef CONF_USB_MSC_LUN0_BLOCK_SIZE -#define CONF_USB_MSC_LUN0_BLOCK_SIZE 512 -#endif - -#ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR -#define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) -#endif - -// - -// Enable Demo for SD/MMC Disk -// SD/MMC stack must be added before enable SD/MMC demo -// SD/MMC insert/eject not supported by this simple demo -// conf_usb_msc_lun1_enable -#ifndef CONF_USB_MSC_LUN1_ENABLE -#define CONF_USB_MSC_LUN1_ENABLE 0 -#endif - -#ifndef CONF_USB_MSC_LUN1_TYPE -#define CONF_USB_MSC_LUN1_TYPE 0x00 -#endif - -// The disk is removable -// SD/MMC stack must be added before enable SD/MMC demo -// SD/MMC insert/eject not supported by this simple demo -// conf_usb_msc_lun1_rmb -#ifndef CONF_USB_MSC_LUN1_RMB -#define CONF_USB_MSC_LUN1_RMB 0x01 -#endif - -#ifndef CONF_USB_MSC_LUN1_ISO -#define CONF_USB_MSC_LUN1_ISO 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_ECMA -#define CONF_USB_MSC_LUN1_ECMA 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_ANSI -#define CONF_USB_MSC_LUN1_ANSI 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_REPO -#define CONF_USB_MSC_LUN1_REPO 0x01 -#endif - -#ifndef CONF_USB_MSC_LUN1_FACTORY -#define CONF_USB_MSC_LUN1_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_PRODUCT -#define CONF_USB_MSC_LUN1_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_PRODUCT_VERSION -#define CONF_USB_MSC_LUN1_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_CAPACITY -#define CONF_USB_MSC_LUN1_CAPACITY 0x16 -#endif - -#ifndef CONF_USB_MSC_LUN1_BLOCK_SIZE -#define CONF_USB_MSC_LUN1_BLOCK_SIZE 512 -#endif - -#ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR -#define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) -#endif - -// - -// -// - -// <<< end of configuration section >>> - -#endif // USBD_COMPOSITE_CONFIG_H diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.c b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.c deleted file mode 100644 index 2c7cd3584..000000000 --- a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.c +++ /dev/null @@ -1,358 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Generic Function Implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hiddf_generic.h" -#include - -#define HIDDF_GENERIC_VERSION 0x00000001u - -/** USB Device HID Generic Function Specific Data */ -struct hiddf_generic_func_data { - /** HID Device Generic Interface information */ - uint8_t func_iface; - /** HID Device Generic IN Endpoint */ - uint8_t func_ep_in; - /** HID Device Generic OUT Endpoint */ - uint8_t func_ep_out; - /** HID Device Generic Report Descriptor */ - const uint8_t *report_desc; - /** HID Device Generic Report Descriptor Length */ - uint32_t report_desc_len; - /** HID Device Generic Enable Flag */ - bool enabled; -}; - -/* USB Device HID Generic Function Instance */ -static struct usbdf_driver _hiddf_generic; - -/* USB Device HID Generic Function Data Instance */ -static struct hiddf_generic_func_data _hiddf_generic_funcd; - -/* USB Device HID Generic Set Report Function Callback */ -static hiddf_generic_set_report_t hiddf_generic_set_report = NULL; - -/** - * \brief Enable HID Generic Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB interface descriptor - * \return Operation status. - */ -static int32_t hid_generic_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - uint8_t * ifc, *ep, i; - usb_iface_desc_t ifc_desc; - usb_ep_desc_t ep_desc; - - struct hiddf_generic_func_data *func_data = (struct hiddf_generic_func_data *)(drv->func_data); - - ifc = desc->sod; - if (NULL == ifc) { - return ERR_NOT_FOUND; - } - - ifc_desc.bInterfaceNumber = ifc[2]; - ifc_desc.bInterfaceClass = ifc[5]; - - if (HID_CLASS == ifc_desc.bInterfaceClass) { - if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized - return ERR_ALREADY_INITIALIZED; - } else if (func_data->func_iface != 0xFF) { // Occupied - return ERR_NO_RESOURCE; - } else { - func_data->func_iface = ifc_desc.bInterfaceNumber; - } - } else { // Not supported by this function driver - return ERR_NOT_FOUND; - } - - // Install endpoints - for (i = 0; i < 2; i++) { - ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); - desc->sod = ep; - if (NULL != ep) { - ep_desc.bEndpointAddress = ep[2]; - ep_desc.bmAttributes = ep[3]; - ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); - if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { - return ERR_NOT_INITIALIZED; - } - if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { - func_data->func_ep_in = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_in); - } else { - func_data->func_ep_out = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_out); - } - } else { - return ERR_NOT_FOUND; - } - } - - // Installed - _hiddf_generic_funcd.enabled = true; - return ERR_NONE; -} - -/** - * \brief Disable HID Generic Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB device descriptor - * \return Operation status. - */ -static int32_t hid_generic_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct hiddf_generic_func_data *func_data = (struct hiddf_generic_func_data *)(drv->func_data); - - usb_iface_desc_t ifc_desc; - - if (desc) { - ifc_desc.bInterfaceClass = desc->sod[5]; - if (ifc_desc.bInterfaceClass != HID_CLASS) { - return ERR_NOT_FOUND; - } - } - - if (func_data->func_iface != 0xFF) { - func_data->func_iface = 0xFF; - } - - if (func_data->func_ep_in != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_in); - func_data->func_ep_in = 0xFF; - } - - if (func_data->func_ep_out != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_out); - func_data->func_ep_out = 0xFF; - } - - _hiddf_generic_funcd.enabled = false; - return ERR_NONE; -} - -/** - * \brief HID Generic Control Function - * \param[in] drv Pointer to USB device function driver - * \param[in] ctrl USB device general function control type - * \param[in] param Parameter pointer - * \return Operation status. - */ -static int32_t hid_generic_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) -{ - switch (ctrl) { - case USBDF_ENABLE: - return hid_generic_enable(drv, (struct usbd_descriptors *)param); - - case USBDF_DISABLE: - return hid_generic_disable(drv, (struct usbd_descriptors *)param); - - case USBDF_GET_IFACE: - return ERR_UNSUPPORTED_OP; - - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class get descriptor - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_generic_get_desc(uint8_t ep, struct usb_req *req) -{ - switch (req->wValue >> 8) { - case USB_DT_HID_REPORT: - return usbdc_xfer(ep, (uint8_t *)_hiddf_generic_funcd.report_desc, _hiddf_generic_funcd.report_desc_len, false); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_generic_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - uint8_t *ctrl_buf = usbdc_get_ctrl_buffer(); - uint16_t len = req->wLength; - - if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_generic_funcd.func_iface)) { - return hid_generic_get_desc(ep, req); - } else { - if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request - return ERR_NOT_FOUND; - } - if (req->wIndex == _hiddf_generic_funcd.func_iface) { - if (req->bmRequestType & USB_EP_DIR_IN) { - return ERR_INVALID_ARG; - } else { - if (USB_REQ_HID_SET_REPORT == req->bRequest) { - if (USB_SETUP_STAGE == stage) { - return usbdc_xfer(ep, ctrl_buf, len, false); - } else { - if (NULL != hiddf_generic_set_report) { - hiddf_generic_set_report(ctrl_buf, len); - } - return ERR_NONE; - } - } else { - return usbdc_xfer(0, NULL, 0, 0); - } - } - } else { - return ERR_NOT_FOUND; - } - } -} - -/** USB Device HID Generic Handler Struct */ -static struct usbdc_handler hid_generic_req_h = {NULL, (FUNC_PTR)hid_generic_req}; - -/** - * \brief Initialize the USB HID Generic Function Driver - */ -int32_t hiddf_generic_init(const uint8_t *report_desc, uint32_t len) -{ - if (NULL == report_desc || 0 == len) { - return ERR_INVALID_ARG; - } - - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_generic_funcd.report_desc = report_desc; - _hiddf_generic_funcd.report_desc_len = len; - _hiddf_generic.ctrl = hid_generic_ctrl; - _hiddf_generic.func_data = &_hiddf_generic_funcd; - - usbdc_register_function(&_hiddf_generic); - usbdc_register_handler(USBDC_HDL_REQ, &hid_generic_req_h); - - return ERR_NONE; -} - -/** - * \brief Deinitialize the USB HID Generic Function Driver - */ -int32_t hiddf_generic_deinit(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_generic.ctrl = NULL; - _hiddf_generic.func_data = NULL; - - usbdc_unregister_function(&_hiddf_generic); - usbdc_unregister_handler(USBDC_HDL_REQ, &hid_generic_req_h); - return ERR_NONE; -} - -/** - * \brief Check whether HID Generic Function is enabled - */ -bool hiddf_generic_is_enabled(void) -{ - return _hiddf_generic_funcd.enabled; -} - -/** - * \brief USB HID Generic Function Read Data - */ -int32_t hiddf_generic_read(uint8_t *buf, uint32_t size) -{ - if (!hiddf_generic_is_enabled()) { - return ERR_DENIED; - } - return usbdc_xfer(_hiddf_generic_funcd.func_ep_out, buf, size, false); -} - -/** - * \brief USB HID Generic Function Write Data - */ -int32_t hiddf_generic_write(uint8_t *buf, uint32_t size) -{ - if (!hiddf_generic_is_enabled()) { - return ERR_DENIED; - } - return usbdc_xfer(_hiddf_generic_funcd.func_ep_in, buf, size, false); -} - -/** - * \brief USB HID Generic Function Register Callback - */ -int32_t hiddf_generic_register_callback(enum hiddf_generic_cb_type cb_type, FUNC_PTR func) -{ - if (!hiddf_generic_is_enabled()) { - return ERR_DENIED; - } - switch (cb_type) { - case HIDDF_GENERIC_CB_READ: - usb_d_ep_register_callback(_hiddf_generic_funcd.func_ep_out, USB_D_EP_CB_XFER, func); - break; - case HIDDF_GENERIC_CB_WRITE: - usb_d_ep_register_callback(_hiddf_generic_funcd.func_ep_in, USB_D_EP_CB_XFER, func); - break; - case HIDDF_GENERIC_CB_SET_REPORT: - hiddf_generic_set_report = (hiddf_generic_set_report_t)func; - break; - default: - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Return version - */ -uint32_t hiddf_generic_get_version(void) -{ - return HIDDF_GENERIC_VERSION; -} diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.h b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.h deleted file mode 100644 index c12f1575a..000000000 --- a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_generic.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Generic Function Definition. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_HID_GENERIC_H_ -#define USBDF_HID_GENERIC_H_ - -#include "usbdc.h" -#include "usb_protocol_hid.h" - -/** HID Generic Callback Type */ -enum hiddf_generic_cb_type { HIDDF_GENERIC_CB_READ, HIDDF_GENERIC_CB_WRITE, HIDDF_GENERIC_CB_SET_REPORT }; - -/** HID Generic Set Report Callback. */ -typedef bool (*hiddf_generic_set_report_t)(uint8_t *, uint16_t); - -/** - * \brief Initialize the USB HID Generic Function Driver - * \param[in] report_desc Point to usr HID Report Descriptor - * \param[in] len length of usr HID Report Descriptor - * \return Operation status. - */ -int32_t hiddf_generic_init(const uint8_t *report_desc, uint32_t len); - -/** - * \brief Deinitialize the USB HID Generic Function Driver - * \return Operation status. - */ -int32_t hiddf_generic_deinit(void); - -/** - * \brief Check whether HID Generic Function is enabled - * \return Operation status. - * \return true HID Generic Function is enabled - * \return false HID Generic Function is disabled - */ -bool hiddf_generic_is_enabled(void); - -/** - * \brief USB HID Generic Function Read Data - * \param[in] buf Pointer to the buffer which receives data - * \param[in] size the size of data to be received - * \return Operation status. - */ -int32_t hiddf_generic_read(uint8_t *buf, uint32_t size); - -/** - * \brief USB HID Generic Function Write Data - * \param[in] buf Pointer to the buffer which stores data - * \param[in] size the size of data to be sent - * \return Operation status. - */ -int32_t hiddf_generic_write(uint8_t *buf, uint32_t size); - -/** - * \brief USB HID Generic Function Register Callback - * \param[in] cb_type Callback type of HID Generic Function - * \param[in] func Pointer to callback function - * \return Operation status. - */ -int32_t hiddf_generic_register_callback(enum hiddf_generic_cb_type cb_type, FUNC_PTR func); - -/** - * \brief Return version - */ -uint32_t hiddf_generic_get_version(void); - -#endif /* USBDF_HID_GENERIC_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.c b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.c deleted file mode 100644 index 835481e41..000000000 --- a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.c +++ /dev/null @@ -1,365 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Keyboard Function Implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hiddf_keyboard.h" -#include - -#define HIDDF_KEYBOARD_VERSION 0x00000001u - -#define KEYBOARD_REPORT_DESC_LEN 59 - -/** USB Device HID Keyboard Function Specific Data */ -struct hiddf_keyboard_func_data { - /* HID Device Keyboard Report */ - uint8_t kb_report[8]; - /** HID Device Keyboard Interface information */ - uint8_t func_iface; - /** HID Device Keyboard IN Endpoint */ - uint8_t func_ep_in; - /** HID Device Keyboard OUT Endpoint */ - uint8_t func_ep_out; - /** HID Device Keyboard Enable Flag */ - bool enabled; -}; - -/* HID report descriptor for standard HID keyboard */ -const uint8_t keyboard_report_desc[KEYBOARD_REPORT_DESC_LEN] = { - 0x05, 0x01, /* Usage Page (Generic Desktop) */ - 0x09, 0x06, /* Usage (Keyboard) */ - 0xA1, 0x01, /* Collection (Application) */ - 0x05, 0x07, /* Usage Page (Keyboard) */ - 0x19, 0xE0, /* Usage Minimum (224) */ - 0x29, 0xE7, /* Usage Maximum (231) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x08, /* Report Count (8) */ - 0x81, 0x02, /* Input (Data, Variable, Absolute) */ - 0x81, 0x01, /* Input (Constant) */ - 0x19, 0x00, /* Usage Minimum (0) */ - 0x29, 0x65, /* Usage Maximum (101) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x65, /* Logical Maximum (101) */ - 0x75, 0x08, /* Report Size (8) */ - 0x95, 0x06, /* Report Count (6) */ - 0x81, 0x00, /* Input (Data, Array) */ - 0x05, 0x08, /* Usage Page (LED) */ - 0x19, 0x01, /* Usage Minimum (1) */ - 0x29, 0x05, /* Usage Maximum (5) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x05, /* Report Count (5) */ - 0x91, 0x02, /* Output (Data, Variable, Absolute) */ - 0x95, 0x03, /* Report Count (3) */ - 0x91, 0x01, /* Output (Constant) */ - 0xC0 /* End Collection */ -}; - -/* USB Device HID Keyboard Function Instance */ -static struct usbdf_driver _hiddf_keyboard; - -/* USB Device HID Keyboard Function Data Instance */ -static struct hiddf_keyboard_func_data _hiddf_keyboard_funcd; - -/** - * \brief Enable HID Keyboard Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB interface descriptor - * \return Operation status. - */ -static int32_t hid_keyboard_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - uint8_t * ifc, *ep, i; - usb_iface_desc_t ifc_desc; - usb_ep_desc_t ep_desc; - - struct hiddf_keyboard_func_data *func_data = (struct hiddf_keyboard_func_data *)(drv->func_data); - - ifc = desc->sod; - if (NULL == ifc) { - return ERR_NOT_FOUND; - } - - ifc_desc.bInterfaceNumber = ifc[2]; - ifc_desc.bInterfaceClass = ifc[5]; - - if (HID_CLASS == ifc_desc.bInterfaceClass) { - if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized - return ERR_ALREADY_INITIALIZED; - } else if (func_data->func_iface != 0xFF) { // Occupied - return ERR_NO_RESOURCE; - } else { - func_data->func_iface = ifc_desc.bInterfaceNumber; - } - } else { // Not supported by this function driver - return ERR_NOT_FOUND; - } - - // Install endpoints - for (i = 0; i < 2; i++) { - ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); - desc->sod = ep; - if (NULL != ep) { - ep_desc.bEndpointAddress = ep[2]; - ep_desc.bmAttributes = ep[3]; - ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); - if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { - return ERR_NOT_INITIALIZED; - } - if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { - func_data->func_ep_in = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_in); - } else { - func_data->func_ep_out = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_out); - } - } else { - return ERR_NOT_FOUND; - } - } - - // Installed - _hiddf_keyboard_funcd.enabled = true; - return ERR_NONE; -} - -/** - * \brief Disable HID Keyboard Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB device descriptor - * \return Operation status. - */ -static int32_t hid_keyboard_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct hiddf_keyboard_func_data *func_data = (struct hiddf_keyboard_func_data *)(drv->func_data); - - usb_iface_desc_t ifc_desc; - - if (desc) { - ifc_desc.bInterfaceClass = desc->sod[5]; - if (ifc_desc.bInterfaceClass != HID_CLASS) { - return ERR_NOT_FOUND; - } - } - - if (func_data->func_iface != 0xFF) { - func_data->func_iface = 0xFF; - } - - if (func_data->func_ep_in != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_in); - func_data->func_ep_in = 0xFF; - } - - if (func_data->func_ep_out != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_out); - func_data->func_ep_out = 0xFF; - } - - _hiddf_keyboard_funcd.enabled = false; - return ERR_NONE; -} - -/** - * \brief HID Keyboard Control Function - * \param[in] drv Pointer to USB device function driver - * \param[in] ctrl USB device general function control type - * \param[in] param Parameter pointer - * \return Operation status. - */ -static int32_t hid_keyboard_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) -{ - switch (ctrl) { - case USBDF_ENABLE: - return hid_keyboard_enable(drv, (struct usbd_descriptors *)param); - - case USBDF_DISABLE: - return hid_keyboard_disable(drv, (struct usbd_descriptors *)param); - - case USBDF_GET_IFACE: - return ERR_UNSUPPORTED_OP; - - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class get descriptor - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_keyboard_get_desc(uint8_t ep, struct usb_req *req) -{ - switch (req->wValue >> 8) { - case USB_DT_HID_REPORT: - return usbdc_xfer(ep, (uint8_t *)keyboard_report_desc, KEYBOARD_REPORT_DESC_LEN, false); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_keyboard_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_keyboard_funcd.func_iface)) { - return hid_keyboard_get_desc(ep, req); - } else { - if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request - return ERR_NOT_FOUND; - } - if (req->wIndex == _hiddf_keyboard_funcd.func_iface) { - if (req->bmRequestType & USB_EP_DIR_IN) { - return ERR_INVALID_ARG; - } else { - return usbdc_xfer(0, NULL, 0, 0); - } - } else { - return ERR_NOT_FOUND; - } - } - (void)stage; -} - -/** USB Device HID Keyboard Handler Struct */ -static struct usbdc_handler hid_keyboard_req_h = {NULL, (FUNC_PTR)hid_keyboard_req}; - -/** - * \brief Initialize the USB HID Keyboard Function Driver - */ -int32_t hiddf_keyboard_init(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_keyboard.ctrl = hid_keyboard_ctrl; - _hiddf_keyboard.func_data = &_hiddf_keyboard_funcd; - - usbdc_register_function(&_hiddf_keyboard); - usbdc_register_handler(USBDC_HDL_REQ, &hid_keyboard_req_h); - return ERR_NONE; -} - -/** - * \brief Deinitialize the USB HID Keyboard Function Driver - */ -int32_t hiddf_keyboard_deinit(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_keyboard.ctrl = NULL; - _hiddf_keyboard.func_data = NULL; - - usbdc_unregister_function(&_hiddf_keyboard); - usbdc_unregister_handler(USBDC_HDL_REQ, &hid_keyboard_req_h); - return ERR_NONE; -} - -/** - * \brief Check whether HID Keyboard Function is enabled - */ -bool hiddf_keyboard_is_enabled(void) -{ - return _hiddf_keyboard_funcd.enabled; -} - -/** - * \brief Process the HID Keyboard key state change request - * \param keys_desc[] keys_descriptor array for state changing - * \param keys_count total keys amount for state changing - * \return Operation status. - */ -int32_t hiddf_keyboard_keys_state_change(struct hiddf_kb_key_descriptors keys_desc[], uint8_t keys_count) -{ - uint8_t i, j; - uint8_t modifier_keys, regular_keys; - - if (!hiddf_keyboard_is_enabled()) { - return ERR_DENIED; - } - - memset(_hiddf_keyboard_funcd.kb_report, 0x00, 8); - modifier_keys = 0; - - for (i = 0; i < keys_count; i++) { - if (true == keys_desc[i].b_modifier) { - modifier_keys++; - } - } - - regular_keys = keys_count - modifier_keys; - - if (regular_keys > 6) { - memset(&_hiddf_keyboard_funcd.kb_report[2], 0xFF, 6); - } else { - i = 2; - for (j = 0; j < keys_count; j++) { - if (HID_KB_KEY_DOWN == keys_desc[j].state) { - if (true == keys_desc[j].b_modifier) { - _hiddf_keyboard_funcd.kb_report[0] |= keys_desc[j].key_id; - } else { - _hiddf_keyboard_funcd.kb_report[i++] = keys_desc[j].key_id; - } - } - } - } - return usbdc_xfer(_hiddf_keyboard_funcd.func_ep_in, &_hiddf_keyboard_funcd.kb_report[0], 8, false); -} - -/** - * \brief Return version - */ -uint32_t hiddf_keyboard_get_version(void) -{ - return HIDDF_KEYBOARD_VERSION; -} diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.h b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.h deleted file mode 100644 index 3295d1b78..000000000 --- a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_keyboard.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Keyboard Function Definition. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_HID_KEYBOARD_H_ -#define USBDF_HID_KEYBOARD_H_ - -#include "usbdc.h" -#include "usb_protocol_hid.h" - -/** HID Keyboard Class Key State Type */ -enum hiddf_kb_key_state { HID_KB_KEY_UP, HID_KB_KEY_DOWN }; - -/** Describes the USB HID Keyboard Key descriptors. */ -struct hiddf_kb_key_descriptors { - /* HID Key Value, defined in usb_protocol_hid.h */ - uint8_t key_id; - /* Flag whether it is a modifier key */ - bool b_modifier; - /* Key State */ - enum hiddf_kb_key_state state; -}; - -/** - * \brief Initialize the USB HID Keyboard Function Driver - * \return Operation status. - */ -int32_t hiddf_keyboard_init(void); - -/** - * \brief Deinitialize the USB HID Keyboard Function Driver - * \return Operation status. - */ -int32_t hiddf_keyboard_deinit(void); - -/** - * \brief Check whether HID Keyboard Function is enabled - * \return Operation status. - * \return true HID Keyboard Function is enabled - * \return false HID Keyboard Function is disabled - */ -bool hiddf_keyboard_is_enabled(void); - -/** - * \brief Process the HID Keyboard key state change request - * \param keys_desc[] keys_descriptor array for state changing - * \param keys_count total keys amount for state changing - * \return Operation status. - */ -int32_t hiddf_keyboard_keys_state_change(struct hiddf_kb_key_descriptors keys_desc[], uint8_t keys_count); - -/** - * \brief Return version - */ -uint32_t hiddf_keyboard_get_version(void); - -#endif /* USBDF_HID_KEYBOARD_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.c b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.c deleted file mode 100644 index 7a58ce66e..000000000 --- a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.c +++ /dev/null @@ -1,363 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Mouse Function Implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hiddf_mouse.h" - -#define HIDDF_MOUSE_VERSION 0x00000001u - -#define MOUSE_REPORT_DESC_LEN 52 - -/** USB Device HID Mouse Function Specific Data */ -struct hiddf_mouse_func_data { - /* HID Device Mouse Report */ - union { - /** Interpreted by bytes. */ - struct { - /** Button Status. */ - uint8_t button_state; - /** X Axis Variant.*/ - uint8_t x_axis_var; - /** Y Axis Variant.*/ - uint8_t y_axis_var; - /** Scroll Variant.*/ - uint8_t scroll_var; - } bytes; - uint32_t u32; - } mouse_report; - /** HID Device Mouse Interface information */ - uint8_t func_iface; - /** HID Device Mouse IN Endpoint */ - uint8_t func_ep_in; - /** HID Device Mouse Enable Flag */ - bool enabled; -}; - -/* HID report descriptor for standard HID mouse */ -const uint8_t mouse_report_desc[MOUSE_REPORT_DESC_LEN] = { - 0x05, 0x01, /* Usage Page (Generic Desktop), */ - 0x09, 0x02, /* Usage (Mouse), */ - 0xA1, 0x01, /* Collection (Application), */ - 0x09, 0x01, /* Usage (Pointer), */ - 0xA1, 0x00, /* Collection (Physical), */ - 0x05, 0x09, /* Usage Page (Buttons), */ - 0x19, 0x01, /* Usage Minimum (01), */ - 0x29, 0x03, /* Usage Maximum (03), */ - 0x15, 0x00, /* Logical Minimum (0), */ - 0x25, 0x01, /* Logical Maximum (1), */ - 0x75, 0x01, /* Report Size (1), */ - 0x95, 0x03, /* Report Count (3), */ - 0x81, 0x02, /* Input (Data, Variable, Absolute) */ - 0x75, 0x05, /* Report Size (5), */ - 0x95, 0x01, /* Report Count (1), */ - 0x81, 0x01, /* Input (Constant), */ - 0x05, 0x01, /* Usage Page (Generic Desktop), */ - 0x09, 0x30, /* Usage (X), */ - 0x09, 0x31, /* Usage (Y), */ - 0x09, 0x38, /* Usage (Scroll), */ - 0x15, 0x81, /* Logical Minimum (-127), */ - 0x25, 0x7F, /* Logical Maximum (127), */ - 0x75, 0x08, /* Report Size (8), */ - 0x95, 0x03, /* Report Count (3), */ - 0x81, 0x06, /* Input (Data, Variable, Relative) */ - 0xC0, /* End Collection, */ - 0xC0, /* End Collection */ -}; - -/* USB Device HID Mouse Function Instance */ -static struct usbdf_driver _hiddf_mouse; - -/* USB Device HID Mouse Function Data Instance */ -static struct hiddf_mouse_func_data _hiddf_mouse_funcd; - -/** - * \brief Enable HID Mouse Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB interface descriptor - * \return Operation status. - */ -static int32_t hid_mouse_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - uint8_t * ifc, *ep; - usb_iface_desc_t ifc_desc; - usb_ep_desc_t ep_desc; - - struct hiddf_mouse_func_data *func_data = (struct hiddf_mouse_func_data *)(drv->func_data); - - ifc = desc->sod; - if (NULL == ifc) { - return ERR_NOT_FOUND; - } - - ifc_desc.bInterfaceNumber = ifc[2]; - ifc_desc.bInterfaceClass = ifc[5]; - - if (HID_CLASS == ifc_desc.bInterfaceClass) { - if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized - return ERR_ALREADY_INITIALIZED; - } else if (func_data->func_iface != 0xFF) { // Occupied - return ERR_NO_RESOURCE; - } else { - func_data->func_iface = ifc_desc.bInterfaceNumber; - } - } else { // Not supported by this function driver - return ERR_NOT_FOUND; - } - - // Install endpoints - ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); - desc->sod = ep; - if (NULL != ep) { - ep_desc.bEndpointAddress = ep[2]; - ep_desc.bmAttributes = ep[3]; - ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); - if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { - return ERR_NOT_INITIALIZED; - } - if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { - func_data->func_ep_in = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_in); - } else { - return ERR_INVALID_DATA; - } - } else { - return ERR_NOT_FOUND; - } - // Installed - _hiddf_mouse_funcd.enabled = true; - return ERR_NONE; -} - -/** - * \brief Disable HID Mouse Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB device descriptor - * \return Operation status. - */ -static int32_t hid_mouse_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct hiddf_mouse_func_data *func_data = (struct hiddf_mouse_func_data *)(drv->func_data); - - usb_iface_desc_t ifc_desc; - - if (desc) { - ifc_desc.bInterfaceClass = desc->sod[5]; - if (ifc_desc.bInterfaceClass != HID_CLASS) { - return ERR_NOT_FOUND; - } - } - - if (func_data->func_iface != 0xFF) { - func_data->func_iface = 0xFF; - } - - if (func_data->func_ep_in != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_in); - func_data->func_ep_in = 0xFF; - } - - _hiddf_mouse_funcd.enabled = false; - return ERR_NONE; -} - -/** - * \brief HID Mouse Control Function - * \param[in] drv Pointer to USB device function driver - * \param[in] ctrl USB device general function control type - * \param[in] param Parameter pointer - * \return Operation status. - */ -static int32_t hid_mouse_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) -{ - switch (ctrl) { - case USBDF_ENABLE: - return hid_mouse_enable(drv, (struct usbd_descriptors *)param); - - case USBDF_DISABLE: - return hid_mouse_disable(drv, (struct usbd_descriptors *)param); - - case USBDF_GET_IFACE: - return ERR_UNSUPPORTED_OP; - - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class get descriptor - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_mouse_get_desc(uint8_t ep, struct usb_req *req) -{ - switch (req->wValue >> 8) { - case USB_DT_HID_REPORT: - return usbdc_xfer(ep, (uint8_t *)mouse_report_desc, MOUSE_REPORT_DESC_LEN, false); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_mouse_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_mouse_funcd.func_iface)) { - return hid_mouse_get_desc(ep, req); - } else { - if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request - return ERR_NOT_FOUND; - } - if (req->wIndex == _hiddf_mouse_funcd.func_iface) { - if (req->bmRequestType & USB_EP_DIR_IN) { - return ERR_INVALID_ARG; - } else { - return usbdc_xfer(0, NULL, 0, 0); - } - } else { - return ERR_NOT_FOUND; - } - } - (void)stage; -} - -/** USB Device HID Mouse Handler Struct */ -static struct usbdc_handler hid_mouse_req_h = {NULL, (FUNC_PTR)hid_mouse_req}; - -/** - * \brief Initialize the USB HID Mouse Function Driver - */ -int32_t hiddf_mouse_init(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_mouse.ctrl = hid_mouse_ctrl; - _hiddf_mouse.func_data = &_hiddf_mouse_funcd; - - usbdc_register_function(&_hiddf_mouse); - usbdc_register_handler(USBDC_HDL_REQ, &hid_mouse_req_h); - return ERR_NONE; -} - -/** - * \brief Deinitialize the USB HID Mouse Function Driver - */ -int32_t hiddf_mouse_deinit(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_mouse.ctrl = NULL; - _hiddf_mouse.func_data = NULL; - - usbdc_unregister_function(&_hiddf_mouse); - usbdc_unregister_handler(USBDC_HDL_REQ, &hid_mouse_req_h); - return ERR_NONE; -} - -/** - * \brief Check whether HID Mouse Function is enabled - */ -bool hiddf_mouse_is_enabled(void) -{ - return _hiddf_mouse_funcd.enabled; -} - -/** - * \brief Move the mouse pointer - * \param pos Signed value to move - * \param type HID mouse class pointer move type - * \return Operation status. - */ -int32_t hiddf_mouse_move(int8_t pos, enum hiddf_mouse_move_type type) -{ - - _hiddf_mouse_funcd.mouse_report.u32 = 0; - - if (type == HID_MOUSE_X_AXIS_MV) { - _hiddf_mouse_funcd.mouse_report.bytes.x_axis_var = pos; - } else if (type == HID_MOUSE_Y_AXIS_MV) { - _hiddf_mouse_funcd.mouse_report.bytes.y_axis_var = pos; - } else if (type == HID_MOUSE_SCROLL_MV) { - _hiddf_mouse_funcd.mouse_report.bytes.scroll_var = pos; - } else { - return ERR_INVALID_ARG; - } - - return usbdc_xfer(_hiddf_mouse_funcd.func_ep_in, &_hiddf_mouse_funcd.mouse_report.bytes.button_state, 4, false); -} - -/** - * \brief Changes button state - * \param b_state New button state - * \param type Button type - * \return Operation status. - */ -int32_t hiddf_mouse_button_change(enum hiddf_mouse_button_state b_state, enum hiddf_mouse_button_type type) -{ - _hiddf_mouse_funcd.mouse_report.u32 = 0; - - if (b_state == HID_MOUSE_BTN_DOWN) { - _hiddf_mouse_funcd.mouse_report.bytes.button_state = type; - } else { - _hiddf_mouse_funcd.mouse_report.bytes.button_state = 0x00; - } - - return usbdc_xfer(_hiddf_mouse_funcd.func_ep_in, &_hiddf_mouse_funcd.mouse_report.bytes.button_state, 4, false); -} - -/** - * \brief Return version - */ -uint32_t hiddf_mouse_get_version(void) -{ - return HIDDF_MOUSE_VERSION; -} diff --git a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.h b/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.h deleted file mode 100644 index 464b1e92d..000000000 --- a/atmel-samd/asf4/samd21/usb/class/hid/device/hiddf_mouse.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Mouse Function Definition. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_HID_MOUSE_H_ -#define USBDF_HID_MOUSE_H_ - -#include "usbdc.h" -#include "usb_protocol_hid.h" - -/** HID Mouse Class Button State Type */ -enum hiddf_mouse_button_state { HID_MOUSE_BTN_UP, HID_MOUSE_BTN_DOWN }; - -/* HID Mosue Class Button Type */ -enum hiddf_mouse_button_type { HID_MOUSE_LEFT_BTN = 0x01, HID_MOUSE_RIGHT_BTN = 0x02, HID_MOUSE_MIDDLE_BTN = 0x04 }; - -/* HID Mouse Class Pointer Move Type */ -enum hiddf_mouse_move_type { HID_MOUSE_X_AXIS_MV = 0x01, HID_MOUSE_Y_AXIS_MV = 0x02, HID_MOUSE_SCROLL_MV = 0x03 }; - -/** - * \brief Initialize the USB HID Mouse Function Driver - * \return Operation status. - */ -int32_t hiddf_mouse_init(void); - -/** - * \brief Deinitialize the USB HID Mouse Function Driver - * \return Operation status. - */ -int32_t hiddf_mouse_deinit(void); - -/** - * \brief Check whether HID Mouse Function is enabled - * \return Operation status. - * \return true HID Mouse Function is enabled - * \return false HID Mouse Function is disabled - */ -bool hiddf_mouse_is_enabled(void); - -/** - * \brief Move the mouse pointer - * \param pos Signed value to move - * \param type HID mouse class pointer move type - * \return Operation status. - */ -int32_t hiddf_mouse_move(int8_t pos, enum hiddf_mouse_move_type type); - -/** - * \brief Changes button state - * \param b_state New button state - * \param type Button type - * \return Operation status. - */ -int32_t hiddf_mouse_button_change(enum hiddf_mouse_button_state b_state, enum hiddf_mouse_button_type type); - -/** - * \brief Return version - */ -uint32_t hiddf_mouse_get_version(void); - -#endif /* USBDF_CDC_ACM_SER_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/hid/usb_protocol_hid.h b/atmel-samd/asf4/samd21/usb/class/hid/usb_protocol_hid.h deleted file mode 100644 index 71d74e632..000000000 --- a/atmel-samd/asf4/samd21/usb/class/hid/usb_protocol_hid.h +++ /dev/null @@ -1,597 +0,0 @@ -/** - * \file - * - * \brief USB Human Interface Device (HID) protocol definitions. - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _USB_PROTOCOL_HID_H_ -#define _USB_PROTOCOL_HID_H_ - -#include "usb_includes.h" - -/** - * \ingroup usb_protocol_group - * \defgroup usb_hid_protocol USB Human Interface Device (HID) - * protocol definitions - * \brief USB Human Interface Device (HID) protocol definitions - * - * @{ - */ - -//! \name Possible Class value -//@{ -#define HID_CLASS 0x03 -//@} - -//! \name Possible SubClass value -//@{ -//! Interface subclass NO support BOOT protocol -#define HID_SUB_CLASS_NOBOOT 0x00 -//! Interface subclass support BOOT protocol -#define HID_SUB_CLASS_BOOT 0x01 -//@} - -//! \name Possible protocol value -//@{ -//! Protocol generic standard -#define HID_PROTOCOL_GENERIC 0x00 -//! Protocol keyboard standard -#define HID_PROTOCOL_KEYBOARD 0x01 -//! Protocol mouse standard -#define HID_PROTOCOL_MOUSE 0x02 -//@} - -//! \brief Hid USB requests (bRequest) - -#define USB_REQ_HID_GET_REPORT 0x01 -#define USB_REQ_HID_GET_IDLE 0x02 -#define USB_REQ_HID_GET_PROTOCOL 0x03 -#define USB_REQ_HID_SET_REPORT 0x09 -#define USB_REQ_HID_SET_IDLE 0x0A -#define USB_REQ_HID_SET_PROTOCOL 0x0B - -//! \brief HID USB descriptor types -#define USB_DT_HID 0x21 -#define USB_DT_HID_REPORT 0x22 -#define USB_DT_HID_PHYSICAL 0x23 - -//! \brief HID Type for report descriptor -#define USB_HID_ITEM_REPORT_TYPE_MAIN 0 -#define USB_HID_ITEM_REPORT_TYPE_GLOBAL 1 -#define USB_HID_ITEM_REPORT_TYPE_LOCAL 2 -#define USB_HID_ITEM_REPORT_TYPE_LONG 3 - -//! \brief HID report type -#define USB_HID_REPORT_TYPE_INPUT 1 -#define USB_HID_REPORT_TYPE_OUTPUT 2 -#define USB_HID_REPORT_TYPE_FEATURE 3 - -//! \brief HID protocol -#define USB_HID_PROCOTOL_BOOT 0 -#define USB_HID_PROCOTOL_REPORT 1 - -#define USB_HID_DESC_BYTES(bLength, bCountryCode, bNumDescriptors, bDescriptorType, bDescriptorLength) \ - bLength, 0x21, 0x10, 0x01, bCountryCode, bNumDescriptors, bDescriptorType, LE_BYTE0(bDescriptorLength), \ - LE_BYTE1(bDescriptorLength) - -COMPILER_PACK_SET(1) - -//! \brief HID Descriptor -typedef struct usb_hid_descriptor { - uint8_t bLength; //!< Size of this descriptor in bytes - uint8_t bDescriptorType; //!< HID descriptor type - le16_t bcdHID; //!< Binary Coded Decimal Spec. release - uint8_t bCountryCode; //!< Hardware target country - uint8_t bNumDescriptors; //!< Number of HID class descriptors to follow - uint8_t bRDescriptorType; //!< Report descriptor type - le16_t wDescriptorLength; //!< Total length of Report descriptor -} usb_hid_descriptor_t; - -COMPILER_PACK_RESET() - -//! \name HID Report type -//! Used by SETUP_HID_GET_REPORT & SETUP_HID_SET_REPORT -//! @{ -#define REPORT_TYPE_INPUT 0x01 -#define REPORT_TYPE_OUTPUT 0x02 -#define REPORT_TYPE_FEATURE 0x03 -//! @} - -//! \name Constants of field DESCRIPTOR_HID -//! @{ -//! Numeric expression identifying the HID Class -//! Specification release (here V1.11) -#define USB_HID_BDC_V1_11 0x0111 -//! Numeric expression specifying the number of class descriptors -//! Note: Always at least one i.e. Report descriptor. -#define USB_HID_NUM_DESC 0x01 - -//! \name Country code -//! @{ -#define USB_HID_NO_COUNTRY_CODE 0 // Not Supported -#define USB_HID_COUNTRY_ARABIC 1 // Arabic -#define USB_HID_COUNTRY_BELGIAN 2 // Belgian -#define USB_HID_COUNTRY_CANADIAN_BILINGUAL 3 // Canadian-Bilingual -#define USB_HID_COUNTRY_CANADIAN_FRENCH 4 // Canadian-French -#define USB_HID_COUNTRY_CZECH_REPUBLIC 5 // Czech Republic -#define USB_HID_COUNTRY_DANISH 6 // Danish -#define USB_HID_COUNTRY_FINNISH 7 // Finnish -#define USB_HID_COUNTRY_FRENCH 8 // French -#define USB_HID_COUNTRY_GERMAN 9 // German -#define USB_HID_COUNTRY_GREEK 10 // Greek -#define USB_HID_COUNTRY_HEBREW 11 // Hebrew -#define USB_HID_COUNTRY_HUNGARY 12 // Hungary -#define USB_HID_COUNTRY_INTERNATIONAL_ISO 13 // International (ISO) -#define USB_HID_COUNTRY_ITALIAN 14 // Italian -#define USB_HID_COUNTRY_JAPAN_KATAKANA 15 // Japan (Katakana) -#define USB_HID_COUNTRY_KOREAN 16 // Korean -#define USB_HID_COUNTRY_LATIN_AMERICAN 17 // Latin American -#define USB_HID_COUNTRY_NETHERLANDS_DUTCH 18 // Netherlands/Dutch -#define USB_HID_COUNTRY_NORWEGIAN 19 // Norwegian -#define USB_HID_COUNTRY_PERSIAN_FARSI 20 // Persian (Farsi) -#define USB_HID_COUNTRY_POLAND 21 // Poland -#define USB_HID_COUNTRY_PORTUGUESE 22 // Portuguese -#define USB_HID_COUNTRY_RUSSIA 23 // Russia -#define USB_HID_COUNTRY_SLOVAKIA 24 // Slovakia -#define USB_HID_COUNTRY_SPANISH 25 // Spanish -#define USB_HID_COUNTRY_SWEDISH 26 // Swedish -#define USB_HID_COUNTRY_SWISS_FRENCH 27 // Swiss/French -#define USB_HID_COUNTRY_SWISS_GERMAN 28 // Swiss/German -#define USB_HID_COUNTRY_SWITZERLAND 29 // Switzerland -#define USB_HID_COUNTRY_TAIWAN 30 // Taiwan -#define USB_HID_COUNTRY_TURKISH_Q 31 // Turkish-Q -#define USB_HID_COUNTRY_UK 32 // UK -#define USB_HID_COUNTRY_US 33 // US -#define USB_HID_COUNTRY_YUGOSLAVIA 34 // Yugoslavia -#define USB_HID_COUNTRY_TURKISH_F 35 // Turkish-F - //! @} - //! @} -//! @} - -//! \name HID KEYS values -//! @{ -#define HID_A 0x04 -#define HID_B 0x05 -#define HID_C 0x06 -#define HID_D 0x07 -#define HID_E 0x08 -#define HID_F 0x09 -#define HID_G 0x0A -#define HID_H 0x0B -#define HID_I 0x0C -#define HID_J 0x0D -#define HID_K 0x0E -#define HID_L 0x0F -#define HID_M 0x10 -#define HID_N 0x11 -#define HID_O 0x12 -#define HID_P 0x13 -#define HID_Q 0x14 -#define HID_R 0x15 -#define HID_S 0x16 -#define HID_T 0x17 -#define HID_U 0x18 -#define HID_V 0x19 -#define HID_W 0x1A -#define HID_X 0x1B -#define HID_Y 0x1C -#define HID_Z 0x1D -#define HID_1 30 -#define HID_2 31 -#define HID_3 32 -#define HID_4 33 -#define HID_5 34 -#define HID_6 35 -#define HID_7 36 -#define HID_8 37 -#define HID_9 38 -#define HID_0 39 -#define HID_ENTER 40 -#define HID_ESCAPE 41 -#define HID_BACKSPACE 42 -#define HID_TAB 43 -#define HID_SPACEBAR 44 -#define HID_UNDERSCORE 45 -#define HID_PLUS 46 -#define HID_OPEN_BRACKET 47 // { -#define HID_CLOSE_BRACKET 48 // } -#define HID_BACKSLASH 49 -#define HID_ASH 50 // # ~ -#define HID_COLON 51 // ; : -#define HID_QUOTE 52 // ' " -#define HID_TILDE 53 -#define HID_COMMA 54 -#define HID_DOT 55 -#define HID_SLASH 56 -#define HID_CAPS_LOCK 57 -#define HID_F1 58 -#define HID_F2 59 -#define HID_F3 60 -#define HID_F4 61 -#define HID_F5 62 -#define HID_F6 63 -#define HID_F7 64 -#define HID_F8 65 -#define HID_F9 66 -#define HID_F10 67 -#define HID_F11 68 -#define HID_F12 69 -#define HID_PRINTSCREEN 70 -#define HID_SCROLL_LOCK 71 -#define HID_PAUSE 72 -#define HID_INSERT 73 -#define HID_HOME 74 -#define HID_PAGEUP 75 -#define HID_DELETE 76 -#define HID_END 77 -#define HID_PAGEDOWN 78 -#define HID_RIGHT 79 -#define HID_LEFT 80 -#define HID_DOWN 81 -#define HID_UP 82 -#define HID_KEYPAD_NUM_LOCK 83 -#define HID_KEYPAD_DIVIDE 84 -#define HID_KEYPAD_AT 85 -#define HID_KEYPAD_MULTIPLY 85 -#define HID_KEYPAD_MINUS 86 -#define HID_KEYPAD_PLUS 87 -#define HID_KEYPAD_ENTER 88 -#define HID_KEYPAD_1 89 -#define HID_KEYPAD_2 90 -#define HID_KEYPAD_3 91 -#define HID_KEYPAD_4 92 -#define HID_KEYPAD_5 93 -#define HID_KEYPAD_6 94 -#define HID_KEYPAD_7 95 -#define HID_KEYPAD_8 96 -#define HID_KEYPAD_9 97 -#define HID_KEYPAD_0 98 - -//! \name HID modifier values -//! @{ -#define HID_MODIFIER_NONE 0x00 -#define HID_MODIFIER_LEFT_CTRL 0x01 -#define HID_MODIFIER_LEFT_SHIFT 0x02 -#define HID_MODIFIER_LEFT_ALT 0x04 -#define HID_MODIFIER_LEFT_UI 0x08 -#define HID_MODIFIER_RIGHT_CTRL 0x10 -#define HID_MODIFIER_RIGHT_SHIFT 0x20 -#define HID_MODIFIER_RIGHT_ALT 0x40 -#define HID_MODIFIER_RIGHT_UI 0x80 -//! @} -//! @} - -//! \name HID KEYS LED values -//! @{ -#define HID_LED_NUM_LOCK (1 << 0) -#define HID_LED_CAPS_LOCK (1 << 1) -#define HID_LED_SCROLL_LOCK (1 << 2) -#define HID_LED_COMPOSE (1 << 3) -#define HID_LED_KANA (1 << 4) -//! @} - -/** \name Standard HID mouse definitions from HID spec. example */ -/*@{*/ - -/** \brief Structure for standard HID keyboard modified keys */ -typedef union hid_kbd_modifier { - uint8_t byte; - struct { - uint8_t lctrl : 1; /**< Left Ctrl */ - uint8_t lshift : 1; /**< Left Shift */ - uint8_t lalt : 1; /**< Left Alt */ - uint8_t lgui : 1; /**< Left Gui */ - uint8_t rctrl : 1; /**< Right Ctrl */ - uint8_t rshift : 1; /**< Right Shift */ - uint8_t ralt : 1; /**< Right Alt */ - uint8_t rgui : 1; /**< Right Gui */ - } bm; -} hid_kbd_modifier_t; -#define HID_KBD_L_CTRL (1 << 0) /**< Left Ctrl */ -#define HID_KBD_L_SHIFT (1 << 1) /**< Left Shift */ -#define HID_KBD_L_ALT (1 << 2) /**< Left Alt */ -#define HID_KBD_L_GUI (1 << 3) /**< Left Gui */ -#define HID_KBD_R_CTRL (1 << 4) /**< Right Ctrl */ -#define HID_KBD_R_SHIFT (1 << 5) /**< Right Shift */ -#define HID_KBD_R_ALT (1 << 6) /**< Right Alt */ -#define HID_KBD_R_GUI (1 << 7) /**< Right Gui */ - -/** \brief Structure for standard HID keyboard input report */ -typedef union hid_kbd_input_report { - uint8_t byte[8]; - struct { - union hid_kbd_modifier modifier; - uint8_t reserved_oem; - uint8_t key[6]; /** < Key array */ - } field; -} hid_kbd_input_report_t; -/** Access to the modifier keys in HID keyboard report - * \param rpt Pointer to report data of bytes - */ -#define hid_kbd_modifier_keys(rpt) (rpt[0]) -/** Access to the OEM reserved in HID keyboard report - * \param rpt Pointer to report data of bytes - */ -#define hid_kbd_oem(rpt) (rpt[1]) -/** Access to the Key code in HID keyboard report - * \param rpt Pointer to report data of bytes - * \param i Index in the report key array (0~n) - */ -#define hid_kbd_keycode(rpt, i) (rpt[2 + i]) - -/** \brief Structure for standard HID keyboard output report */ -typedef union hid_kbd_output_report { - uint8_t byte; - struct { - uint8_t num_lock : 1; /**< LED of Num Lock */ - uint8_t caps_lock : 1; /**< LED of Caps Lock */ - uint8_t scroll_lock : 1; /**< LED of Scroll Lock */ - uint8_t compose : 1; /**< LED of COMPOSE LOCK */ - uint8_t kana : 1; /**< LED of KANA */ - uint8_t constant : 3; - } field; -} hid_kbd_output_report_t; -#define HID_KBD_NUM_LOCK (1 << 0) /**< LED of Num Lock */ -#define HID_KBD_CAPS_LOCK (1 << 1) /**< LED of Caps Lock */ -#define HID_KBD_SCROLL_LOCK (1 << 2) /**< LED of Scroll Lock */ -#define HID_KBD_COMPOSE (1 << 3) /**< LED of COMPOSE LOCK */ -#define HID_KBD_KANA (1 << 4) /**< LED of KANA */ - -/*@}*/ - -/** \name Standard HID mouse definitions from HID spec. example */ -/*@{*/ -/** \brief Structure for standard HID mouse report */ -typedef union hid_mouse_report { - uint8_t byte[3]; - struct { - uint8_t btn1 : 1; /**< Button 1 */ - uint8_t btn2 : 2; /**< Button 2 */ - uint8_t btn3 : 3; /**< Button 3 */ - uint8_t device_spec : 5; - int8_t x; /**< X displacement */ - int8_t y; /**< Y displacement */ - } field; - /* More bytes are optional */ -} hid_mouse_report_t; -#define HID_MOUSE_BTN1 (1 << 0) /**< Button 1 */ -#define HID_MOUSE_BTN2 (1 << 1) /**< Button 2 */ -#define HID_MOUSE_BTN3 (1 << 2) /**< Button 3 */ - -/** Access to the button state in HID mouse report - * \param rpt Pointer to report data of bytes - */ -#define hid_mouse_btn_state(rpt) (rpt[0]) -/** Check if the button is done in HID mouse report - * \param rpt Pointer to report data of bytes - * \param btn Button bitmap to check - */ -#define hid_mouse_is_btn_down(rpt, btn) (rpt[0] & (btn)) -/** Access to the relative X displacement in HID mouse report - * \param rpt Pointer to report data of bytes - */ -#define hid_mouse_x(rpt) ((int8_t)rpt[1]) -/** Access to the relative Y displacement in HID mouse report - * \param rpt Pointer to report data of bytes - */ -#define hid_mouse_y(rpt) ((int8_t)rpt[2]) - -/*@}*/ - -/** \name Standard HID joystick definitions from HID spec. example */ -/*@{*/ - -/** \brief Structure for standard HID joystick report */ -typedef union hid_joystick_report { - uint8_t byte[4]; - struct { - int8_t x; - int8_t y; - uint8_t hat_sw : 4; /**< Hat switch */ - uint8_t btn1 : 1; /**< Button 1 */ - uint8_t btn2 : 1; /**< Button 2 */ - uint8_t btn3 : 1; /**< Button 3 */ - uint8_t btn4 : 1; /**< Button 4 */ - uint8_t throttle; - } field; -} hid_joystick_report_t; -#define HID_JOYSTICK_BTN1 (1 << 4) /**< Button 1 */ -#define HID_JOYSTICK_BTN2 (1 << 5) /**< Button 2 */ -#define HID_JOYSTICK_BTN3 (1 << 6) /**< Button 3 */ -#define HID_JOYSTICK_BTN4 (1 << 7) /**< Button 4 */ - -/** Access to the absolute X position in HID joystick report - * \param rpt Pointer to report data of bytes - */ -#define hid_joystick_x(rpt) ((int8_t)rpt[0]) -/** Access to the absolute Y position in HID joystick report - * \param rpt Pointer to report data of bytes - */ -#define hid_joystick_y(rpt) ((int8_t)rpt[1]) -/** Access to the button state in HID joystick report - * \param rpt Pointer to report data of bytes - */ -#define hid_joystick_btn_state(rpt) (rpt[2]) -/** Check if the button is done in HID joystick report - * \param rpt Pointer to report data of bytes - * \param btn Button bitmap to check - */ -#define hid_joystick_is_btn_down(rpt, btn) (rpt[2] & (btn)) -/** Get the Hat switch in HID joystick report - * \param rpt Pointer to report data of bytes - */ -#define hid_joystick_hat_sw(rpt) (rpt[2] & 0xF) -/** Access to the throttle in HID joystick report - * \param rpt Pointer to report data of bytes - */ -#define hid_joystick_throttle(rpt) (rpt[3]) - -/*@}*/ - -/** - * \brief Fill a GetHIDDescriptor request - * \param[out] req Pointer to the request to fill - * \param[in] type Descriptor type - * \param[in] index Descriptor index - * \param[in] iface Interface Number - * \param[in] len Descriptor Length - */ -static inline void usb_fill_GetHIDDesc_req(struct usb_req *req, uint8_t type, uint8_t index, uint8_t iface, - uint16_t len) -{ - req->bmRequestType = 0x81; - req->bRequest = USB_REQ_GET_DESC; - req->wValue = (type << 8) | index; - req->wIndex = iface; - req->wLength = len; -} - -/** - * \brief Fill a SetHIDDescriptor request - * \param[out] req Pointer to the request to fill - * \param[in] type Descriptor type - * \param[in] index Descriptor index - * \param[in] iface Interface Number - * \param[in] len Descriptor Length - */ -static inline void usb_fill_SetHIDDesc_req(struct usb_req *req, uint8_t type, uint8_t index, uint8_t iface, - uint16_t len) -{ - req->bmRequestType = 0x01; - req->bRequest = USB_REQ_SET_DESC; - req->wValue = (type << 8) | index; - req->wIndex = iface; - req->wLength = len; -} - -/** - * \brief Fill a GetReport request - * \param[out] req Pointer to the request to fill - * \param[in] type Report type - * \param[in] id Report ID - * \param[in] iface Interface Number - * \param[in] len Report Length - */ -static inline void usb_fill_GetReport_req(struct usb_req *req, uint8_t type, uint8_t id, uint8_t iface, uint16_t len) -{ - req->bmRequestType = 0xA1; - req->bRequest = USB_REQ_HID_GET_REPORT; - req->wValue = (type << 8) | id; - req->wIndex = iface; - req->wLength = len; -} - -/** - * \brief Fill a SetReport request - * \param[out] req Pointer to the request to fill - * \param[in] type Report type - * \param[in] id Report ID - * \param[in] iface Interface Number - * \param[in] len Report Length - */ -static inline void usb_fill_SetReport_req(struct usb_req *req, uint8_t type, uint8_t id, uint8_t iface, uint16_t len) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_HID_GET_REPORT; - req->wValue = (type << 8) | id; - req->wIndex = iface; - req->wLength = len; -} - -/** - * \brief Fill a GetIdle request - * \param[out] req Pointer to the request to fill - * \param[in] id Report ID - * \param[in] iface Interface Number - */ -static inline void usb_fill_GetIdle_req(struct usb_req *req, uint8_t id, uint8_t iface) -{ - req->bmRequestType = 0xA1; - req->bRequest = USB_REQ_HID_GET_IDLE; - req->wValue = id; - req->wIndex = iface; - req->wLength = 1; -} - -/** - * \brief Fill a SetIdle request - * \param[out] req Pointer to the request to fill - * \param[in] duration Duration value - * \param[in] id Report ID - * \param[in] iface Interface Number - */ -static inline void usb_fill_SetIdle_req(struct usb_req *req, uint8_t duration, uint8_t id, uint8_t iface) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_HID_SET_IDLE; - req->wValue = (duration << 8) | id; - req->wIndex = iface; - req->wLength = 0; -} - -/** - * \brief Fill a GetProtocol request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - */ -static inline void usb_fill_GetProtocol_req(struct usb_req *req, uint8_t iface) -{ - req->bmRequestType = 0xA1; - req->bRequest = USB_REQ_HID_GET_PROTOCOL; - req->wValue = 0; - req->wIndex = iface; - req->wLength = 1; -} - -/** - * \brief Fill a SetProtocol request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - */ -static inline void usb_fill_SetProtocol_req(struct usb_req *req, uint8_t protocol, uint8_t iface) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_HID_SET_PROTOCOL; - req->wValue = protocol; - req->wIndex = iface; - req->wLength = 0; -} - -#endif // _USB_PROTOCOL_HID_H_ diff --git a/atmel-samd/asf4/samd21/usb/class/hub/usb_protocol_hub.h b/atmel-samd/asf4/samd21/usb/class/hub/usb_protocol_hub.h deleted file mode 100644 index dbfc04a2c..000000000 --- a/atmel-samd/asf4/samd21/usb/class/hub/usb_protocol_hub.h +++ /dev/null @@ -1,364 +0,0 @@ -/** - * \file - * - * \brief USB hub protocol definitions. - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _USB_PROTOCOL_HUB_H_ -#define _USB_PROTOCOL_HUB_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** \name Possible class value */ -/*@{*/ -#define HUB_CLASS 0x09 -/*@}*/ - -/** \brief Hub USB requests (bRequest) */ -enum usb_reqid_hub { - USB_REQ_HUB_GET_STATUS = 0, - /** CLEAR_FEATURE */ - USB_REQ_HUB_CLR_FTR = 1, - /** SET_FEATURE */ - USB_REQ_HUB_SET_FTR = 3, - /** GET_DESCRIPTOR */ - USB_REQ_HUB_GET_DESC = 6, - /** SET_DESCRIPTOR */ - USB_REQ_HUB_SET_DESC = 7, - /** CLEAR_TT_BUFFER */ - USB_REQ_HUB_CLR_TT_BUF = 8, - /** RESET_TT */ - USB_REQ_HUB_RESET_TT = 9, - /** GET_TT_STATE */ - USB_REQ_HUB_GET_TT_STATE = 10, - /** STOP_TT */ - USB_REQ_HUB_STOP_TT -}; - -/** \brief Hub USB descriptor type */ -enum usb_descriptor_type_hub { USB_DT_HUB = 0x29 }; - -/** \brief Hub feature selector */ -enum usb_hub_ftr_sel { - USB_HUB_FTR_C_HUB_LOCAL_POWER = 0, - USB_HUB_FTR_C_HUB_OVER_CURRENT = 1, - USB_HUB_FTR_PORT_CONNECTION = 0, - USB_HUB_FTR_PORT_ENABLE = 1, - USB_HUB_FTR_PORT_SUSPEND = 2, - USB_HUB_FTR_PORT_OVER_CURRENT = 3, - USB_HUB_FTR_PORT_RESET = 4, - USB_HUB_FTR_PORT_POWER = 8, - USB_HUB_FTR_PORT_LOW_SPEED = 9, - USB_HUB_FTR_PORT_LS = 9, - USB_HUB_FTR_PORT_HIGH_SPEED = 10, - USB_HUB_FTR_PORT_HS = 10, - USB_HUB_FTR_C_PORT_CONNECTION = 16, - USB_HUB_FTR_C_PORT_ENABLE = 17, - USB_HUB_FTR_C_PORT_SUSPEND = 18, - USB_HUB_FTR_C_PORT_OVER_CURRENT = 19, - USB_HUB_FTR_C_PORT_RESET = 20, - USB_HUB_FTR_PORT_TEST = 21, - USB_HUB_FTR_PORT_INDICATOR -}; - -COMPILER_PACK_SET(1) - -/** - * \brief General Hub Descriptor - */ -typedef struct usb_hub_descriptor { - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint16_t wHubCharacteristics; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint32_t variables[1]; -} usb_hub_descriptor_t; - -/** - * \brief Hub Descriptor with no more than 7 ports - */ -typedef struct usb_hub_descriptor_7p { - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint16_t wHubCharacteristics; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint8_t DeviceRemovable[1]; - uint8_t PortPwrCtrlMask[1]; -} usb_hub_descriptor_7p_t; - -/** - * \brief Hub Descriptor with no more than 15 ports - */ -typedef struct usb_hub_descriptor_15p { - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint16_t wHubCharacteristics; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint8_t DeviceRemovable[2]; - uint8_t PortPwrCtrlMask[2]; -} usb_hub_descriptor_15p_t; - -/** - * \brief Hub Descriptor with no more than 23 ports - */ -typedef struct usb_hub_descriptor_23p { - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint16_t wHubCharacteristics; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint8_t DeviceRemovable[3]; - uint8_t PortPwrCtrlMask[3]; -} usb_hub_descriptor_23p_t; - -/** - * \brief Hub Descriptor with no more than 31 ports - */ -typedef struct usb_hub_descriptor_31p { - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint16_t wHubCharacteristics; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint8_t DeviceRemovable[4]; - uint8_t PortPwrCtrlMask[4]; -} usb_hub_descriptor_31p_t; - -COMPILER_PACK_RESET() - -/** - * \brief Check if hub change is detected - * \param[in] bitmap Pointer to the bitmap location - * \return \c true if hub change is detected - */ -static inline bool usb_is_hub_change_detected(const uint8_t *bitmap) -{ - return (*bitmap & 0x1); -} - -/** - * \brief Check if port change is detected - * \param[in] bitmap Pointer to the bitmap location - * \param[in] port Port number ( 1 ~ n ) - * \return \c true if port change is detected - */ -static inline bool usb_is_port_change_detected(const uint8_t *bitmap, const uint8_t port) -{ - uint8_t idx = port >> 3; - uint8_t pos = port & 0x7; - return (bitmap[idx] & (1u << pos)); -} - -/** - * \brief Fill a ClearHubFeature request - * \param[out] req Pointer to the request to fill - * \param[in] ftr Feature selector - */ -static inline void usb_fill_ClrHubFtr_req(struct usb_req *req, uint8_t ftr) -{ - req->bmRequestType = 0x20; - req->bRequest = USB_REQ_CLEAR_FTR; - req->wValue = ftr; - req->wIndex = 0; - req->wLength = 0; -} - -/** - * \brief Fill a ClearPortFeature request - * \param[out] req Pointer to the request to fill - * \param[in] ftr Feature selector - * \param[in] port Port number ( 1 ~ n ) - */ -static inline void usb_fill_ClrPortFtr_req(struct usb_req *req, uint8_t ftr, uint8_t port) -{ - req->bmRequestType = 0x23; - req->bRequest = USB_REQ_CLEAR_FTR; - req->wValue = ftr; - req->wIndex = port; - req->wLength = 0; -} - -/** - * \brief Fill a ClearTTBuffer request - * \param[out] req Pointer to the request to fill - * \param[in] dev Dev_Addr - * \param[in] ep EP_Num - * \param[in] tt_port TT_port - */ -static inline void usb_fill_ClrTTBuf_req(struct usb_req *req, uint8_t dev, uint8_t ep, uint8_t tt_port) -{ - req->bmRequestType = 0x23; - req->bRequest = USB_REQ_HUB_CLR_TT_BUF; - req->wValue = (dev << 8) | ep; - req->wIndex = tt_port; - req->wLength = 0; -} - -/** - * \brief Fill a GetHubDescriptor request - * \param[out] req Pointer to the request to fill - * \param[in] len Length of available buffer for request data - */ -static inline void usb_fill_GetHubDesc_req(struct usb_req *req, uint16_t len) -{ - req->bmRequestType = 0xA0; - req->bRequest = USB_REQ_GET_DESC; - req->wValue = (USB_DT_HUB << 8) | 0; - req->wIndex = 0; - req->wLength = len; -} - -/** - * \brief Fill a GetHubStatus request - * \param[out] req Pointer to the request to fill - */ -static inline void usb_fill_GetHubStatus_req(struct usb_req *req) -{ - req->bmRequestType = 0xA0; - req->bRequest = USB_REQ_GET_STATUS; - req->wValue = 0; - req->wIndex = 0; - req->wLength = 4; -} - -/** - * \brief Fill a GetPortStatus request - * \param[out] req Pointer to the request to fill - * \param[in] port Port number ( 1 ~ n ) - */ -static inline void usb_fill_GetPortStatus_req(struct usb_req *req, uint8_t port) -{ - req->bmRequestType = 0xA3; - req->bRequest = USB_REQ_GET_STATUS; - req->wValue = 0; - req->wIndex = port; - req->wLength = 4; -} - -/** - * \brief Fill a ResetTT request - * \param[out] req Pointer to the request to fill - * \param[in] port Port number ( 1 ~ n ) - */ -static inline void usb_fill_ResetTT_req(struct usb_req *req, uint8_t port) -{ - req->bmRequestType = 0x23; - req->bRequest = USB_REQ_HUB_RESET_TT; - req->wValue = 0; - req->wIndex = port; - req->wLength = 0; -} - -/** - * \brief Fill a SetHubFeature request - * \param[out] req Pointer to the request to fill - * \param[in] ftr Feature selector - */ -static inline void usb_fill_SetHubFtr_req(struct usb_req *req, uint8_t ftr) -{ - req->bmRequestType = 0x20; - req->bRequest = USB_REQ_SET_FTR; - req->wValue = ftr; - req->wIndex = 0; - req->wLength = 0; -} - -/** - * \brief Fill a SetPortFeature request - * \param[out] req Pointer to the request to fill - * \param[in] ftr Feature selector - * \param[in] port Port number ( 1 ~ n ) - */ -static inline void usb_fill_SetPortFtr_req(struct usb_req *req, uint8_t ftr, uint8_t port) -{ - req->bmRequestType = 0x23; - req->bRequest = USB_REQ_SET_FTR; - req->wValue = ftr; - req->wIndex = port; - req->wLength = 0; -} - -/** - * \brief Fill a GetTTState request - * \param[out] req Pointer to the request to fill - * \param[in] tt_flags TT_Flags - * \param[in] port Port number ( 1 ~ n ) - * \param[in] len TT State Length - */ -static inline void usb_fill_GetTTState_req(struct usb_req *req, uint16_t tt_flags, uint8_t port, uint16_t len) -{ - req->bmRequestType = 0xA3; - req->bRequest = USB_REQ_HUB_GET_TT_STATE; - req->wValue = tt_flags; - req->wIndex = port; - req->wLength = len; -} - -/** - * \brief Fill a StopTT request - * \param[out] req Pointer to the request to fill - * \param[in] port Port number ( 1 ~ n ) - */ -static inline void usb_fill_StopTT_req(struct usb_req *req, uint8_t port) -{ - req->bmRequestType = 0x23; - req->bRequest = USB_REQ_HUB_STOP_TT; - req->wValue = 0; - req->wIndex = port; - req->wLength = 0; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _USB_PROTOCOL_HUB_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.c b/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.c deleted file mode 100644 index b398ba609..000000000 --- a/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.c +++ /dev/null @@ -1,754 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack MSC Function Implementation. - * - * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "mscdf.h" -#include - -#define MSCDF_VERSION 0x00000001u - -#define ERR_RPT_ZLP 0 /* Uses ZLP on IN error case */ - -/** MSC Class Transfer Stage Type */ -enum mscdf_xfer_stage_type { MSCDF_CMD_STAGE, MSCDF_DATA_STAGE, MSCDF_STATUS_STAGE }; - -/** USB Device MSC Function Specific Data */ -struct mscdf_func_data { - /** MSC Device Interface information */ - uint8_t func_iface; - /** MSC Device IN Endpoint */ - uint8_t func_ep_in; - /** MSC Device OUT Endpoint */ - uint8_t func_ep_out; - /** MSC Device Max LUN */ - uint8_t func_max_lun; - /** MSC Transfer Block Address */ - uint8_t *xfer_blk_addr; - /** MSC Transfer Block Size */ - uint32_t xfer_blk_size; - /** MSC Transfer Total Bytes */ - uint32_t xfer_tot_bytes; - /** MSC Transfer Stage */ - enum mscdf_xfer_stage_type xfer_stage; - /** MSC Transfer Busy Flag */ - bool xfer_busy; - /** MSC Device Enable Flag */ - bool enabled; -}; - -static struct usbdf_driver _mscdf; -static struct mscdf_func_data _mscdf_funcd; - -/* If callbacks are not registered: - * - Return default inquiry information - * - Return NOT FOUND for all other CBW - */ -static mscdf_inquiry_disk_t mscdf_inquiry_disk = NULL; -static mscdf_get_disk_capacity_t mscdf_get_disk_capacity = NULL; -static mscdf_eject_disk_t mscdf_eject_disk = NULL; -static mscdf_start_read_disk_t mscdf_read_disk = NULL; -static mscdf_start_write_disk_t mscdf_write_disk = NULL; -static mscdf_test_disk_ready_t mscdf_test_disk_ready = NULL; -static mscdf_xfer_blocks_done_t mscdf_xfer_blocks_done = NULL; - -COMPILER_ALIGNED(4) -static struct scsi_inquiry_data _inquiry_default = { - 0x00, /* Peripheral Qual / Peripheral Dev Type */ - SCSI_INQ_RMB, /* Flags 1 */ - 0x00, /* Version */ - 0x01, /* Flags 3 */ - 31, /* Additional Length (n-4) */ - 0x00, /* Flags 5 */ - 0x00, /* Flags 6 */ - 0x00, /* Flags 7 */ - {0, 0, 0, 0, 0, 0, 0, 0}, /* VID[8] */ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* PID[16] */ - {0, 0, 0, 0} /* PREV[4] */ -}; - -COMPILER_ALIGNED(4) -static struct usb_msc_cbw mscdf_cbw; - -COMPILER_ALIGNED(4) -static struct usb_msc_csw mscdf_csw = {USB_CSW_SIGNATURE, 0, 0, 0}; - -COMPILER_ALIGNED(4) -static struct scsi_request_sense_data mscdf_sense_data - = {SCSI_SENSE_CURRENT, 0x00, 0x00, {0x00, 0x00, 0x00, 0x00}, 0x0A}; - -/** - * \brief USB MSC wait Command Block - */ -static bool mscdf_wait_cbw(void) -{ - _mscdf_funcd.xfer_stage = MSCDF_CMD_STAGE; - return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_out, (uint8_t *)&mscdf_cbw, 31, false); -} - -/** - * \brief USB MSC Send Command Status - */ -static bool mscdf_send_csw(void) -{ - _mscdf_funcd.xfer_stage = MSCDF_STATUS_STAGE; - return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_in, (uint8_t *)&mscdf_csw, sizeof(struct usb_msc_csw), false); -} - -#if ERR_RPT_ZLP -/** - * \brief USB MSC Send ZLP data - */ -static bool mscdf_send_zlp(void) -{ - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_in, (uint8_t *)&mscdf_csw, 0, true); -} -#define mscdf_terminate_in() mscdf_send_zlp() -#else -/** - * \brief USB MSC Halt IN endpoint - */ -static bool mscdf_halt_in(void) -{ - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - return ERR_NONE == usb_d_ep_halt(_mscdf_funcd.func_ep_in, USB_EP_HALT_SET); -} -#define mscdf_terminate_in() mscdf_halt_in() -#endif - -/** - * \brief USB MSC Request Sense - * \param[in] err_codes Error code - */ -static void mscdf_request_sense(int32_t err_codes) -{ - switch (err_codes) { - case ERR_NOT_FOUND: - mscdf_sense_data.sense_flag_key = SCSI_SK_NOT_READY; - mscdf_sense_data.AddSense = BE16(SCSI_ASC_MEDIUM_NOT_PRESENT); - break; - - case ERR_BUSY: - mscdf_sense_data.sense_flag_key = SCSI_SK_UNIT_ATTENTION; - mscdf_sense_data.AddSense = BE16(SCSI_ASC_NOT_READY_TO_READY_CHANGE); - break; - - case ERR_DENIED: - mscdf_sense_data.sense_flag_key = SCSI_SK_DATA_PROTECT; - mscdf_sense_data.AddSense = BE16(SCSI_ASC_WRITE_PROTECTED); - break; - - default: - mscdf_sense_data.sense_flag_key = SCSI_SK_ILLEGAL_REQUEST; - mscdf_sense_data.AddSense = BE16(SCSI_ASC_INVALID_COMMAND_OPERATION_CODE); - break; - } -} - -/** - * \brief USB MSC Stack invalid command process - */ -static bool mscdf_invalid_cmd(void) -{ - struct usb_msc_cbw *pcbw = &mscdf_cbw; - struct usb_msc_csw *pcsw = &mscdf_csw; - - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - - mscdf_request_sense(ERR_UNSUPPORTED_OP); - - if ((pcbw->bmCBWFlags & USB_EP_DIR_IN) && pcsw->dCSWDataResidue) { - return mscdf_terminate_in(); - } else { - return mscdf_send_csw(); - } -} - -/** - * \brief USB MSC Function Read / Write Data - * \param[in] count the amount of bytes has been transferred - * \return Operation status. - */ -static bool mscdf_read_write(uint32_t count) -{ - struct usb_msc_cbw *pcbw = &mscdf_cbw; - struct usb_msc_csw *pcsw = &mscdf_csw; - int32_t ret = ERR_UNSUPPORTED_OP; - uint32_t address, nblocks; - uint8_t ep; - - if (_mscdf_funcd.xfer_stage == MSCDF_CMD_STAGE) { - address = (uint32_t)(pcbw->CDB[2] << 24) + (uint32_t)(pcbw->CDB[3] << 16) + (uint32_t)(pcbw->CDB[4] << 8) - + pcbw->CDB[5]; - nblocks = (uint32_t)(pcbw->CDB[7] << 8) + pcbw->CDB[8]; - if (pcbw->CDB[0] == SBC_READ10) { - if (NULL != mscdf_read_disk) { - ret = mscdf_read_disk(pcbw->bCBWLUN, address, nblocks); - } else { - ret = ERR_NOT_FOUND; - } - } else if (pcbw->CDB[0] == SBC_WRITE10) { - if (NULL != mscdf_write_disk) { - ret = mscdf_write_disk(pcbw->bCBWLUN, address, nblocks); - } else { - ret = ERR_NOT_FOUND; - } - } - if (ERR_NONE == ret) { - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - return false; - } - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ret); - return mscdf_terminate_in(); - - } else if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { - if (count == 0) { - return mscdf_send_csw(); - } - if (pcsw->dCSWDataResidue < count || _mscdf_funcd.xfer_tot_bytes < count) { - return true; - } - - pcsw->dCSWDataResidue -= count; - _mscdf_funcd.xfer_tot_bytes -= count; - - if (_mscdf_funcd.xfer_tot_bytes == 0) { - _mscdf_funcd.xfer_busy = false; - if (NULL != mscdf_xfer_blocks_done) { - mscdf_xfer_blocks_done(pcbw->bCBWLUN); - } - if (pcsw->dCSWDataResidue == 0 && pcbw->CDB[0] == SBC_READ10) { - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - return mscdf_send_csw(); - } else { - return false; - } - } else { - _mscdf_funcd.xfer_blk_addr += count; - if (pcbw->CDB[0] == SBC_READ10) { - ep = _mscdf_funcd.func_ep_in; - } else { - ep = _mscdf_funcd.func_ep_out; - } - return usbdc_xfer(ep, _mscdf_funcd.xfer_blk_addr, _mscdf_funcd.xfer_tot_bytes, false); - } - } else { - return true; - } -} - -/** - * \brief Callback invoked when bulk IN data received - * \param[in] ep Endpoint number - * \param[in] rc transfer return status - * \param[in] count the amount of bytes has been transferred - * \return Operation status. - */ -static bool mscdf_cb_ep_bulk_in(const uint8_t ep, const enum usb_xfer_code rc, const uint32_t count) -{ - struct usb_msc_cbw *pcbw = &mscdf_cbw; - (void)ep; - (void)rc; - - if (rc == USB_XFER_UNHALT) { - if (_mscdf_funcd.xfer_stage != MSCDF_CMD_STAGE) { - return mscdf_send_csw(); - } - } - - if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { - if (pcbw->CDB[0] == SBC_READ10) { - return mscdf_read_write(count); - } else { - return mscdf_send_csw(); - } - } else if (_mscdf_funcd.xfer_stage == MSCDF_STATUS_STAGE) { - return mscdf_wait_cbw(); - } else { - return true; - } -} - -/** - * \brief Callback invoked when bulk OUT data received - * \param[in] ep Endpoint number - * \param[in] rc transfer return status - * \param[in] count the amount of bytes has been transferred - * \return Operation status. - */ -static bool mscdf_cb_ep_bulk_out(const uint8_t ep, const enum usb_xfer_code rc, const uint32_t count) -{ - struct usb_msc_cbw *pcbw = &mscdf_cbw; - struct usb_msc_csw *pcsw = &mscdf_csw; - uint8_t * pbuf = NULL; - int32_t ret; - - (void)ep; - if (rc == USB_XFER_UNHALT) { - return mscdf_wait_cbw(); - } - - if (_mscdf_funcd.xfer_stage == MSCDF_CMD_STAGE) { - if (pcbw->dCBWSignature == USB_CBW_SIGNATURE) { - pcsw->dCSWTag = pcbw->dCBWTag; - pcsw->dCSWDataResidue = pcbw->dCBWDataTransferLength; - - switch (pcbw->CDB[0]) { - case SPC_INQUIRY: - if (NULL != mscdf_inquiry_disk) { - pbuf = mscdf_inquiry_disk(pcbw->bCBWLUN); - } - if (NULL == pbuf) { - pbuf = (uint8_t *)&_inquiry_default; - } - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - return usbdc_xfer(_mscdf_funcd.func_ep_in, pbuf, 36, false); - - case SBC_READ_CAPACITY10: - if (NULL != mscdf_get_disk_capacity) { - pbuf = mscdf_get_disk_capacity(pcbw->bCBWLUN); - } - if (NULL != pbuf) { - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - _mscdf_funcd.xfer_blk_size - = (uint32_t)(pbuf[4] << 24) + (uint32_t)(pbuf[5] << 16) + (uint32_t)(pbuf[6] << 8) + pbuf[7]; - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - return usbdc_xfer(_mscdf_funcd.func_ep_in, pbuf, 8, false); - } else { - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ERR_NOT_FOUND); - return mscdf_terminate_in(); - } - - case SBC_READ10: - case SBC_WRITE10: - return mscdf_read_write(count); - - case SPC_PREVENT_ALLOW_MEDIUM_REMOVAL: - if (0x00 == pcbw->CDB[4]) { - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - return mscdf_send_csw(); - } - break; - - case SBC_START_STOP_UNIT: - if (0x02 == pcbw->CDB[4]) { - if (NULL != mscdf_eject_disk) { - ret = mscdf_eject_disk(pcbw->bCBWLUN); - if (ERR_NONE == ret) { - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - } else { - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ret); - } - } else { - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ERR_NOT_FOUND); - } - return mscdf_send_csw(); - } - break; - - case SPC_REQUEST_SENSE: - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - return usbdc_xfer(_mscdf_funcd.func_ep_in, - (uint8_t *)&mscdf_sense_data, - sizeof(struct scsi_request_sense_data), - false); - - case SPC_TEST_UNIT_READY: - if (NULL != mscdf_test_disk_ready) { - ret = mscdf_test_disk_ready(pcbw->bCBWLUN); - if (ERR_NONE == ret) { - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - } else { - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ret); - } - } else { - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ERR_NOT_FOUND); - } - return mscdf_send_csw(); - - default: - break; - } - return mscdf_invalid_cmd(); - } else { - return true; - } - } else if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { - return mscdf_read_write(count); - } else { - return true; - } -} - -/** - * \brief Enable MSC Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB interface descriptor - * \return Operation status. - */ -static int32_t mscdf_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct mscdf_func_data *func_data = (struct mscdf_func_data *)(drv->func_data); - - usb_ep_desc_t ep_desc; - usb_iface_desc_t ifc_desc; - uint8_t * ifc, *ep; - - ifc = desc->sod; - if (NULL == ifc) { - return ERR_NOT_FOUND; - } - - ifc_desc.bInterfaceNumber = ifc[2]; - ifc_desc.bInterfaceClass = ifc[5]; - - if (MSC_CLASS == ifc_desc.bInterfaceClass) { - if (func_data->func_iface == ifc_desc.bInterfaceNumber) { /* Initialized */ - return ERR_ALREADY_INITIALIZED; - } else if (func_data->func_iface != 0xFF) { /* Occupied */ - return ERR_NO_RESOURCE; - } else { - func_data->func_iface = ifc_desc.bInterfaceNumber; - } - } else { /* Not supported by this function driver */ - return ERR_NOT_FOUND; - } - - /* Install endpoints */ - ep = usb_find_desc(ifc, desc->eod, USB_DT_ENDPOINT); - while (NULL != ep) { - ep_desc.bEndpointAddress = ep[2]; - ep_desc.bmAttributes = ep[3]; - ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); - if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { - return ERR_NOT_INITIALIZED; - } - if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { - func_data->func_ep_in = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_in); - usb_d_ep_register_callback(func_data->func_ep_in, USB_D_EP_CB_XFER, (FUNC_PTR)mscdf_cb_ep_bulk_in); - } else { - func_data->func_ep_out = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_out); - usb_d_ep_register_callback(func_data->func_ep_out, USB_D_EP_CB_XFER, (FUNC_PTR)mscdf_cb_ep_bulk_out); - } - desc->sod = ep; - ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); - } - // Installed - _mscdf_funcd.enabled = true; - return mscdf_wait_cbw(); -} - -/** - * \brief Disable MSC Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB device descriptor - * \return Operation status. - */ -static int32_t mscdf_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct mscdf_func_data *func_data = (struct mscdf_func_data *)(drv->func_data); - - usb_iface_desc_t ifc_desc; - - if (desc) { - ifc_desc.bInterfaceClass = desc->sod[5]; - // Check interface - if (ifc_desc.bInterfaceClass != MSC_CLASS) { - return ERR_NOT_FOUND; - } - } - - if (func_data->func_iface != 0xFF) { - func_data->func_iface = 0xFF; - } - - if (func_data->func_ep_in != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_in); - func_data->func_ep_in = 0xFF; - } - - if (func_data->func_ep_out != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_out); - func_data->func_ep_out = 0xFF; - } - - func_data->xfer_stage = MSCDF_CMD_STAGE; - func_data->xfer_busy = false; - func_data->enabled = false; - - return ERR_NONE; -} - -/** - * \brief MSC Control Function - * \param[in] drv Pointer to USB device function driver - * \param[in] ctrl USB device general function control type - * \param[in] param Parameter pointer - * \return Operation status. - */ -static int32_t mscdf_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) -{ - switch (ctrl) { - case USBDF_ENABLE: - return mscdf_enable(drv, (struct usbd_descriptors *)param); - - case USBDF_DISABLE: - return mscdf_disable(drv, (struct usbd_descriptors *)param); - - case USBDF_GET_IFACE: - return ERR_UNSUPPORTED_OP; - - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the MSC class set request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t mscdf_set_req(uint8_t ep, struct usb_req *req) -{ - (void)ep; - switch (req->bRequest) { - case USB_REQ_MSC_BULK_RESET: - _mscdf_funcd.xfer_stage = MSCDF_CMD_STAGE; - usb_d_ep_halt(_mscdf_funcd.func_ep_in, USB_EP_HALT_SET); - usb_d_ep_halt(_mscdf_funcd.func_ep_out, USB_EP_HALT_SET); - return usbdc_xfer(0, NULL, 0, 0); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the MSC class get request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \param[in] stage USB control transfer stages. - * \return Operation status. - */ -static int32_t mscdf_get_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - uint16_t len = req->wLength; - - if (USB_DATA_STAGE == stage) { - return ERR_NONE; - } - - switch (req->bRequest) { - case USB_REQ_MSC_GET_MAX_LUN: - return usbdc_xfer(ep, &_mscdf_funcd.func_max_lun, len, false); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the MSC class request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \param[in] stage USB control transfer stages. - * \return Operation status. - */ -static int32_t mscdf_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { /* class request */ - return ERR_NOT_FOUND; - } - if (req->wIndex == _mscdf_funcd.func_iface) { - if (req->bmRequestType & USB_EP_DIR_IN) { - return mscdf_get_req(ep, req, stage); - } else { - return mscdf_set_req(ep, req); - } - } else { - return ERR_NOT_FOUND; - } -} - -/** USB Device MSC Handler Struct */ -static struct usbdc_handler mscdf_req_h = {NULL, (FUNC_PTR)mscdf_req}; - -/** - * \brief Initialize the USB MSC Function Driver - */ -int32_t mscdf_init(uint8_t max_lun) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _mscdf.ctrl = mscdf_ctrl; - _mscdf.func_data = &_mscdf_funcd; - _mscdf_funcd.func_max_lun = max_lun; - - usbdc_register_function(&_mscdf); - usbdc_register_handler(USBDC_HDL_REQ, &mscdf_req_h); - return ERR_NONE; -} - -/** - * \brief De-initialize the USB MSC Function Driver - */ -int32_t mscdf_deinit(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _mscdf.ctrl = NULL; - _mscdf.func_data = NULL; - - usbdc_unregister_function(&_mscdf); - usbdc_unregister_handler(USBDC_HDL_REQ, &mscdf_req_h); - return ERR_NONE; -} - -/** - * \brief USB MSC Function Register Callback - */ -int32_t mscdf_register_callback(enum mscdf_cb_type cb_type, FUNC_PTR func) -{ - switch (cb_type) { - case MSCDF_CB_INQUIRY_DISK: - mscdf_inquiry_disk = (mscdf_inquiry_disk_t)func; - break; - case MSCDF_CB_GET_DISK_CAPACITY: - mscdf_get_disk_capacity = (mscdf_get_disk_capacity_t)func; - break; - case MSCDF_CB_EJECT_DISK: - mscdf_eject_disk = (mscdf_eject_disk_t)func; - break; - case MSCDF_CB_START_READ_DISK: - mscdf_read_disk = (mscdf_start_read_disk_t)func; - break; - case MSCDF_CB_START_WRITE_DISK: - mscdf_write_disk = (mscdf_start_write_disk_t)func; - break; - case MSCDF_CB_TEST_DISK_READY: - mscdf_test_disk_ready = (mscdf_test_disk_ready_t)func; - break; - case MSCDF_CB_XFER_BLOCKS_DONE: - mscdf_xfer_blocks_done = (mscdf_xfer_blocks_done_t)func; - break; - default: - return ERR_INVALID_ARG; - } - return ERR_NONE; -} - -/** - * \brief Check whether MSC Function is enabled - */ -bool mscdf_is_enabled(void) -{ - return _mscdf_funcd.enabled; -} - -/** - * \brief Process the transfer between USB and Memory. - * - * Routine called by the main loop - */ -int32_t mscdf_xfer_blocks(bool rd, uint8_t *blk_addr, uint32_t blk_cnt) -{ - uint8_t ep; - - if (false == mscdf_is_enabled()) { - return ERR_DENIED; - } else if (true == _mscdf_funcd.xfer_busy) { - return ERR_BUSY; - } else { - _mscdf_funcd.xfer_blk_addr = blk_addr; - _mscdf_funcd.xfer_tot_bytes = _mscdf_funcd.xfer_blk_size * blk_cnt; - if (0 == _mscdf_funcd.xfer_tot_bytes) { - if (false == rd) { - /* For write command, this means no need for more data to receive. - * All the data have been written into disk. - */ - mscdf_csw.bCSWStatus = USB_CSW_STATUS_PASS; - return mscdf_send_csw(); - } else { - return ERR_INVALID_ARG; - } - } else { - if (NULL == blk_addr) { - return ERR_INVALID_ARG; - } - if (true == rd) { - ep = _mscdf_funcd.func_ep_in; - } else { - ep = _mscdf_funcd.func_ep_out; - } - _mscdf_funcd.xfer_busy = true; - usbdc_xfer(ep, blk_addr, _mscdf_funcd.xfer_tot_bytes, false); - return ERR_NONE; - } - } -} - -/** - * \brief Return version - */ -uint32_t mscdf_get_version(void) -{ - return MSCDF_VERSION; -} diff --git a/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.h b/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.h deleted file mode 100644 index 5847a2604..000000000 --- a/atmel-samd/asf4/samd21/usb/class/msc/device/mscdf.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack MSC Function Definition. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_MSC_H_ -#define USBDF_MSC_H_ - -#include "usbdc.h" -#include "usb_protocol_msc.h" -#include "spc_protocol.h" -#include "sbc_protocol.h" - -/** MSC Class Callback Type */ -enum mscdf_cb_type { - MSCDF_CB_INQUIRY_DISK, - MSCDF_CB_GET_DISK_CAPACITY, - MSCDF_CB_START_READ_DISK, - MSCDF_CB_START_WRITE_DISK, - MSCDF_CB_EJECT_DISK, - MSCDF_CB_TEST_DISK_READY, - MSCDF_CB_XFER_BLOCKS_DONE -}; - -/** MSC Inquiry Disk Callback. */ -typedef uint8_t *(*mscdf_inquiry_disk_t)(uint8_t); - -/** MSC Get Disk Capacity Callback. */ -typedef uint8_t *(*mscdf_get_disk_capacity_t)(uint8_t); - -/** MSC Read Data From Disk Callback. */ -typedef int32_t (*mscdf_start_read_disk_t)(uint8_t, uint32_t, uint32_t); - -/** MSC Write Data To Disk Callback. */ -typedef int32_t (*mscdf_start_write_disk_t)(uint8_t, uint32_t, uint32_t); - -/** MSC Eject Disk Callback. */ -typedef int32_t (*mscdf_eject_disk_t)(uint8_t); - -/** MSC Test Disk Ready Callback. */ -typedef int32_t (*mscdf_test_disk_ready_t)(uint8_t); - -/** MSC Tansfer Block Done Callback. */ -typedef int32_t (*mscdf_xfer_blocks_done_t)(uint8_t); - -/** - * \brief Initialize the USB MSC Function Driver - * \param[in] max_lun max logic unit support - * \return Operation status. - */ -int32_t mscdf_init(uint8_t max_lun); - -/** - * \brief Deinitialize the USB MSC Function Driver - * \return Operation status. - */ -int32_t mscdf_deinit(void); - -/** - * \brief USB MSC Function Register Callback - * \param[in] cb_type Callback type of MSC Function - * \param[in] func Pointer to callback function - * \return Operation status. - */ -int32_t mscdf_register_callback(enum mscdf_cb_type cb_type, FUNC_PTR func); - -/** - * \brief Check whether MSC Function is enabled - * \return Operation status. - * \return true MSC Function is enabled - * \return false MSC Function is disabled - */ -bool mscdf_is_enabled(void); - -/** - * \brief USB MSC multi-blocks data transfer between USB and Memory. - * \param[in] rd true read disk command, false write disk command. - * \param[in] blk_addr transfer block address. - * \param[in] blk_cnt transfer block count. It is regarded as disk - * writing done when input blk_cnt as zero. - * \return Operation status. - */ -int32_t mscdf_xfer_blocks(bool rd, uint8_t *blk_addr, uint32_t blk_cnt); - -/** - * \brief Return version - */ -uint32_t mscdf_get_version(void); - -#endif /* USBDF_MSC_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/msc/sbc_protocol.h b/atmel-samd/asf4/samd21/usb/class/msc/sbc_protocol.h deleted file mode 100644 index 925933522..000000000 --- a/atmel-samd/asf4/samd21/usb/class/msc/sbc_protocol.h +++ /dev/null @@ -1,163 +0,0 @@ -/** - * \file - * - * \brief SCSI Block Commands - * - * This file contains definitions of some of the commands found in the - * SCSI SBC-2 standard. - * - * Note that the SBC specification depends on several commands defined - * by the SCSI Primary Commands (SPC) standard. Each version of the SBC - * standard is meant to be used in conjunction with a specific version - * of the SPC standard, as follows: - * - SBC depends on SPC - * - SBC-2 depends on SPC-3 - * - SBC-3 depends on SPC-4 - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _SBC_PROTOCOL_H_ -#define _SBC_PROTOCOL_H_ - -/** - * \ingroup usb_msc_protocol - * \defgroup usb_sbc_protocol SCSI Block Commands protocol definitions - * - * @{ - */ - -/** \name SCSI commands defined by SBC-2 */ -#define SBC_FORMAT_UNIT 0x04 -#define SBC_READ6 0x08 -#define SBC_WRITE6 0x0A -#define SBC_START_STOP_UNIT 0x1B -#define SBC_READ_CAPACITY10 0x25 -#define SBC_READ10 0x28 -#define SBC_WRITE10 0x2A -#define SBC_VERIFY10 0x2F - -/** \name SBC-2 Mode page definitions */ -enum scsi_sbc_mode { - SCSI_MS_MODE_RW_ERR_RECOV = 0x01, /**< Read-Write Error Recovery mode page */ - SCSI_MS_MODE_FORMAT_DEVICE = 0x03, /**< Format Device mode page */ - SCSI_MS_MODE_FLEXIBLE_DISK = 0x05, /**< Flexible Disk mode page */ - SCSI_MS_MODE_CACHING = 0x08 -}; - -/** \name SBC-2 Device-Specific Parameter */ -#define SCSI_MS_SBC_WP 0x80 /**< Write Protected */ -#define SCSI_MS_SBC_DPOFUA 0x10 /**< DPO and FUA supported */ - -/** - * \brief SBC-2 Short LBA mode parameter block descriptor - * \note Fields are MSB first (BE) - */ -struct sbc_slba_block_desc { - be32_t nr_blocks; /**< Number of Blocks (BE32) */ - be32_t block_len; /**< Block Length (BE32) */ -#define SBC_SLBA_BLOCK_LEN_MASK 0x00FFFFFFU /**< Mask reserved bits */ -}; - -/** - * \brief SBC-2 Caching mode page - * \note Fields are MSB first (BE) - */ -struct sbc_caching_mode_page { - uint8_t page_code; - uint8_t page_length; - uint8_t flags2; -#define SBC_MP_CACHE_IC (1 << 7) /**< Initiator Control */ -#define SBC_MP_CACHE_ABPF (1 << 6) /**< Abort Pre-Fetch */ -#define SBC_MP_CACHE_CAP (1 << 5) /**< Catching Analysis Permitted */ -#define SBC_MP_CACHE_DISC (1 << 4) /**< Discontinuity */ -#define SBC_MP_CACHE_SIZE (1 << 3) /**< Size enable */ -#define SBC_MP_CACHE_WCE (1 << 2) /**< Write back Cache Enable */ -#define SBC_MP_CACHE_MF (1 << 1) /**< Multiplication Factor */ -#define SBC_MP_CACHE_RCD (1 << 0) /**< Read Cache Disable */ - uint8_t retention; - be16_t dis_pf_transfer_len; - be16_t min_prefetch; - be16_t max_prefetch; - be16_t max_prefetch_ceil; - uint8_t flags12; -#define SBC_MP_CACHE_FSW (1 << 7) /**< Force Sequential Write */ -#define SBC_MP_CACHE_LBCSS (1 << 6) /**< Logical Blk Cache Seg Sz */ -#define SBC_MP_CACHE_DRA (1 << 5) /**< Disable Read-Ahead */ -#define SBC_MP_CACHE_NV_DIS (1 << 0) /**< Non-Volatile Cache Disable */ - uint8_t nr_cache_segments; - be16_t cache_segment_size; - uint8_t reserved[4]; -}; - -/** - * \brief SBC-2 Read-Write Error Recovery mode page - * \note Fields are MSB first (BE) - */ -struct sbc_rdwr_error_recovery_mode_page { - uint8_t page_code; - uint8_t page_length; -#define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A - uint8_t flags1; -#define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7) -#define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6) -#define SBC_MP_RW_ERR_RECOV_TB (1 << 5) -#define SBC_MP_RW_ERR_RECOV_RC (1 << 4) -#define SBC_MP_RW_ERR_RECOV_ERR (1 << 3) -#define SBC_MP_RW_ERR_RECOV_PER (1 << 2) -#define SBC_MP_RW_ERR_RECOV_DTE (1 << 1) -#define SBC_MP_RW_ERR_RECOV_DCR (1 << 0) - uint8_t read_retry_count; - uint8_t correction_span; - uint8_t head_offset_count; - uint8_t data_strobe_offset_count; - uint8_t flags2; - uint8_t write_retry_count; - uint8_t flags3; - be16_t recovery_time_limit; -}; - -/** - * \brief SBC-2 READ CAPACITY (10) parameter data (8 bytes) - * \note Fields are MSB first (BE) - */ -struct sbc_read_capacity10_data { - be32_t max_lba; /**< LBA of last logical block (BE32) */ - be32_t block_len; /**< Number of bytes in the last logical block (BE32) */ -}; - -#endif /*_SBC_PROTOCOL_H_*/ diff --git a/atmel-samd/asf4/samd21/usb/class/msc/spc_protocol.h b/atmel-samd/asf4/samd21/usb/class/msc/spc_protocol.h deleted file mode 100644 index c44cbef32..000000000 --- a/atmel-samd/asf4/samd21/usb/class/msc/spc_protocol.h +++ /dev/null @@ -1,340 +0,0 @@ -/** - * \file - * - * \brief SCSI Primary Commands - * - * This file contains definitions of some of the commands found in the - * SPC-2 standard. - * - * Copyright (c) 2009-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _SPC_PROTOCOL_H_ -#define _SPC_PROTOCOL_H_ - -/** - * \ingroup usb_msc_protocol - * \defgroup usb_spc_protocol SCSI Primary Commands protocol definitions - * - * - */ - -/**< \name SCSI commands defined by SPC-2 */ -#define SPC_TEST_UNIT_READY 0x00 -#define SPC_REQUEST_SENSE 0x03 -#define SPC_INQUIRY 0x12 -#define SPC_MODE_SELECT6 0x15 -#define SPC_MODE_SENSE6 0x1A -#define SPC_SEND_DIAGNOSTIC 0x1D -#define SPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -#define SPC_MODE_SENSE10 0x5A -#define SPC_REPORT_LUNS 0xA0 - -/**< \brief May be set in byte 0 of the INQUIRY CDB */ -/**< Enable Vital Product Data */ -#define SCSI_INQ_REQ_EVPD 0x01 -/**< Command Support Data specified by the PAGE OR OPERATION CODE field */ -#define SCSI_INQ_REQ_CMDT 0x02 - -COMPILER_PACK_SET(1) - -/** - * \brief SCSI Standard Inquiry data structure - */ -struct scsi_inquiry_data { - uint8_t pq_pdt; /**< Peripheral Qual / Peripheral Dev Type */ -#define SCSI_INQ_PQ_CONNECTED 0x00 /**< Peripheral connected */ -#define SCSI_INQ_PQ_NOT_CONN 0x20 /**< Peripheral not connected */ -#define SCSI_INQ_PQ_NOT_SUPP 0x60 /**< Peripheral not supported */ -#define SCSI_INQ_DT_DIR_ACCESS 0x00 /**< Direct Access (SBC) */ -#define SCSI_INQ_DT_SEQ_ACCESS 0x01 /**< Sequential Access */ -#define SCSI_INQ_DT_PRINTER 0x02 /**< Printer */ -#define SCSI_INQ_DT_PROCESSOR 0x03 /**< Processor device */ -#define SCSI_INQ_DT_WRITE_ONCE 0x04 /**< Write-once device */ -#define SCSI_INQ_DT_CD_DVD 0x05 /**< CD/DVD device */ -#define SCSI_INQ_DT_OPTICAL 0x07 /**< Optical Memory */ -#define SCSI_INQ_DT_MC 0x08 /**< Medium Changer */ -#define SCSI_INQ_DT_ARRAY 0x0c /**< Storage Array Controller */ -#define SCSI_INQ_DT_ENCLOSURE 0x0d /**< Enclosure Services */ -#define SCSI_INQ_DT_RBC 0x0e /**< Simplified Direct Access */ -#define SCSI_INQ_DT_OCRW 0x0f /**< Optical card reader/writer */ -#define SCSI_INQ_DT_BCC 0x10 /**< Bridge Controller Commands */ -#define SCSI_INQ_DT_OSD 0x11 /**< Object-based Storage */ -#define SCSI_INQ_DT_NONE 0x1f /**< No Peripheral */ - uint8_t flags1; /**< Flags (byte 1) */ -#define SCSI_INQ_RMB 0x80 /**< Removable Medium */ - uint8_t version; /**< Version */ -#define SCSI_INQ_VER_NONE 0x00 /**< No standards conformance */ -#define SCSI_INQ_VER_SPC 0x03 /**< SCSI Primary Commands (link to SBC) */ -#define SCSI_INQ_VER_SPC2 0x04 /**< SCSI Primary Commands - 2 (link to SBC-2) */ -#define SCSI_INQ_VER_SPC3 0x05 /**< SCSI Primary Commands - 3 (link to SBC-2) */ -#define SCSI_INQ_VER_SPC4 0x06 /**< SCSI Primary Commands - 4 (link to SBC-3) */ - uint8_t flags3; /**< Flags (byte 3) */ -#define SCSI_INQ_NORMACA 0x20 /**< Normal ACA Supported */ -#define SCSI_INQ_HISUP 0x10 /**< Hierarchal LUN addressing */ -#define SCSI_INQ_RSP_SPC2 0x02 /**< SPC-2 / SPC-3 response format */ - uint8_t addl_len; /**< Additional Length (n-4) */ -#define SCSI_INQ_ADDL_LEN(tot) ((tot)-5) /**< Total length is \a tot */ - uint8_t flags5; /**< Flags (byte 5) */ -#define SCSI_INQ_SCCS 0x80 - uint8_t flags6; /**< Flags (byte 6) */ -#define SCSI_INQ_BQUE 0x80 -#define SCSI_INQ_ENCSERV 0x40 -#define SCSI_INQ_MULTIP 0x10 -#define SCSI_INQ_MCHGR 0x08 -#define SCSI_INQ_ADDR16 0x01 - uint8_t flags7; /**< Flags (byte 7) */ -#define SCSI_INQ_WBUS16 0x20 -#define SCSI_INQ_SYNC 0x10 -#define SCSI_INQ_LINKED 0x08 -#define SCSI_INQ_CMDQUE 0x02 - uint8_t vendor_id[8]; /**< T10 Vendor Identification */ - uint8_t product_id[16]; /**< Product Identification */ - uint8_t product_rev[4]; /**< Product Revision Level */ -}; - -/** - * \brief SCSI Standard Request sense data structure - */ -#define SCSI_SENSE_VALID 0x80 /**< Indicates the INFORMATION field contains valid information */ -#define SCSI_SENSE_RESPONSE_CODE_MASK 0x7F -#define SCSI_SENSE_CURRENT 0x70 /**< Response code 70h (current errors) */ -#define SCSI_SENSE_DEFERRED 0x71 - -#define SCSI_SENSE_FILEMARK 0x80 /**< Indicates that the current command has read a filemark or setmark. */ -#define SCSI_SENSE_EOM 0x40 /**< Indicates that an end-of-medium condition exists. */ -#define SCSI_SENSE_ILI \ - 0x20 /**< Indicates that the requested logical block length did not match the logical block length of the data on \ - the medium. */ -#define SCSI_SENSE_RESERVED 0x10 /**< Reserved */ -#define SCSI_SENSE_KEY(x) (x & 0x0F) /**< Sense Key */ - -#define SCSI_SENSE_ADDL_LEN(total_len) ((total_len)-8) - -#define SCSI_SENSE_SKSV 0x80 /**< Indicates the SENSE-KEY SPECIFIC field contains valid information */ - -struct scsi_request_sense_data { - /** 1st byte: REQUEST SENSE response flags*/ - uint8_t valid_reponse_code; - /** 2nd byte */ - uint8_t obsolete; - /** 3rd byte */ - uint8_t sense_flag_key; - /** 4th to 7th bytes - INFORMATION field */ - uint8_t information[4]; - /** 8th byte - ADDITIONAL SENSE LENGTH field */ - uint8_t AddSenseLen; - /** 9th to 12th byte - COMMAND-SPECIFIC INFORMATION field */ - uint8_t CmdSpecINFO[4]; - /** 13th to 14th byte - ADDITIONAL SENSE CODE and QUALIFIER field */ - union { - struct { - uint8_t code; /**< ADDITIONAL SENSE CODE (ASC) */ - uint8_t qualifier; /**< ADDITIONAL SENSE CODE QUALIFIER (ASCQ) */ - } add_sense; - be16_t AddSense; /**< ASC | ASCQ */ - }; - /** 15th byte - FIELD REPLACEABLE UNIT CODE field */ - uint8_t FldReplUnitCode; - /** 16th byte */ - uint8_t SenseKeySpec[3]; -}; - -COMPILER_PACK_RESET() - -/**< Vital Product Data page codes */ -enum scsi_vpd_page_code { - SCSI_VPD_SUPPORTED_PAGES = 0x00, - SCSI_VPD_UNIT_SERIAL_NUMBER = 0x80, - SCSI_VPD_DEVICE_IDENTIFICATION = 0x83 -}; -#define SCSI_VPD_HEADER_SIZE 4 - -/**< Constants associated with the Device Identification VPD page */ -#define SCSI_VPD_ID_HEADER_SIZE 4 - -#define SCSI_VPD_CODE_SET_BINARY 1 -#define SCSI_VPD_CODE_SET_ASCII 2 -#define SCSI_VPD_CODE_SET_UTF8 3 - -#define SCSI_VPD_ID_TYPE_T10 1 - -/**< Sense keys */ -enum scsi_sense_key { - SCSI_SK_NO_SENSE = 0x0, - SCSI_SK_RECOVERED_ERROR = 0x1, - SCSI_SK_NOT_READY = 0x2, - SCSI_SK_MEDIUM_ERROR = 0x3, - SCSI_SK_HARDWARE_ERROR = 0x4, - SCSI_SK_ILLEGAL_REQUEST = 0x5, - SCSI_SK_UNIT_ATTENTION = 0x6, - SCSI_SK_DATA_PROTECT = 0x7, - SCSI_SK_BLANK_CHECK = 0x8, - SCSI_SK_VENDOR_SPECIFIC = 0x9, - SCSI_SK_COPY_ABORTED = 0xa, - SCSI_SK_ABORTED_COMMAND = 0xb, - SCSI_SK_VOLUME_OVERFLOW = 0xd, - SCSI_SK_MISCOMPARE = 0xe -}; - -/**< Additional Sense Code | Additional Sense Code Qualifier pairs (BE16) */ -enum scsi_asc_ascq { - SCSI_ASC_NO_ADDITIONAL_SENSE_INFO = 0x0000, - SCSI_ASC_LU_NOT_READY_REBUILD_IN_PROGRESS = 0x0405, - SCSI_ASC_WRITE_ERROR = 0x0c00, - SCSI_ASC_UNRECOVERED_READ_ERROR = 0x1100, - SCSI_ASC_INVALID_COMMAND_OPERATION_CODE = 0x2000, - SCSI_ASC_INVALID_FIELD_IN_CDB = 0x2400, - SCSI_ASC_WRITE_PROTECTED = 0x2700, - SCSI_ASC_NOT_READY_TO_READY_CHANGE = 0x2800, - SCSI_ASC_MEDIUM_NOT_PRESENT = 0x3A00, - SCSI_ASC_INTERNAL_TARGET_FAILURE = 0x4400 -}; - -/** - * \brief SPC-2 Mode parameter - * This subclauses describes the block descriptors and the pages - * used with MODE SELECT and MODE SENSE commands - * that are applicable to all SCSI devices. - */ -enum scsi_spc_mode { - SCSI_MS_MODE_VENDOR_SPEC = 0x00, - SCSI_MS_MODE_INFEXP = 0x1C, /**< Informational exceptions control page */ - SCSI_MS_MODE_ALL = 0x3f -}; - -/** - * \brief SPC-2 Informational exceptions control page - * See chapter 8.3.8 - * \note Fields are MSB first (BE) - */ -struct spc_control_page_info_execpt { - uint8_t page_code; - uint8_t page_length; -#define SPC_MP_INFEXP_PAGE_LENGTH 0x0A - uint8_t flags1; -#define SPC_MP_INFEXP_PERF (1 << 7) /**< Initiator Control */ -#define SPC_MP_INFEXP_EBF (1 << 5) /**< Caching Analysis Permitted */ -#define SPC_MP_INFEXP_EWASC (1 << 4) /**< Discontinuity */ -#define SPC_MP_INFEXP_DEXCPT (1 << 3) /**< Size enable */ -#define SPC_MP_INFEXP_TEST (1 << 2) /**< Write-back Cache Enable */ -#define SPC_MP_INFEXP_LOGERR (1 << 0) /**< Log errors bit */ - uint8_t mrie; -#define SPC_MP_INFEXP_MRIE_NO_REPORT 0x00 -#define SPC_MP_INFEXP_MRIE_ASYNC_EVENT 0x01 -#define SPC_MP_INFEXP_MRIE_GEN_UNIT 0x02 -#define SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR 0x03 -#define SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR 0x04 -#define SPC_MP_INFEXP_MRIE_NO_SENSE 0x05 -#define SPC_MP_INFEXP_MRIE_ONLY_REPORT 0x06 - be32_t interval_timer; - be32_t report_count; -}; - -enum scsi_spc_mode_sense_pc { - SCSI_MS_SENSE_PC_CURRENT = 0, - SCSI_MS_SENSE_PC_CHANGEABLE = 1, - SCSI_MS_SENSE_PC_DEFAULT = 2, - SCSI_MS_SENSE_PC_SAVED = 3 -}; - -/** - * \brief Check whether dbd field is set in sense code - * \param[in] cdb pointer to the sense code block - * \return Operation status. - */ -static inline bool scsi_mode_sense_dbd_is_set(const uint8_t *cdb) -{ - return (cdb[1] >> 3) & 1; -} - -/** - * \brief Get page code from mode sense code - * \param[in] cdb pointer to the sense code block - * \return Operation status. - */ -static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t *cdb) -{ - return cdb[2] & 0x3f; -} - -/** - * \brief Get pc from mode sense code - * \param[in] cdb pointer to the sense code block - * \return Operation status. - */ -static inline uint8_t scsi_mode_sense_get_pc(const uint8_t *cdb) -{ - return cdb[2] >> 6; -} - -/** - * \brief SCSI Mode Parameter Header used by MODE SELECT(6) and MODE SENSE(6) - * \note Fields are MSB first (BE) - */ -struct scsi_mode_param_header6 { - uint8_t mode_data_length; /**< Number of bytes after this */ - uint8_t medium_type; /**< Medium Type */ - uint8_t device_specific_parameter; /**< Defined by command set */ - uint8_t block_descriptor_length; /**< Length of block descriptors */ -}; - -/** - * \brief SCSI Mode Parameter Header used by MODE SELECT(10) and MODE SENSE(10) - * \note Fields are MSB first (BE) - */ -struct scsi_mode_param_header10 { - le16_t mode_data_length; /**< Number of bytes after this */ - uint8_t medium_type; /**< Medium Type */ - uint8_t device_specific_parameter; /**< Defined by command set */ - uint8_t flags4; /**< LONGLBA in bit 0 */ - uint8_t reserved; - le16_t block_descriptor_length; /**< Length of block descriptors */ -}; - -/** - * \brief SCSI Page_0 Mode Page header (SPF not set) - */ -struct scsi_mode_page_0_header { - uint8_t page_code; -#define SCSI_PAGE_CODE_PS (1 << 7) /**< Parameters Savable */ -#define SCSI_PAGE_CODE_SPF (1 << 6) /**< SubPage Format */ - uint8_t page_length; /**< Number of bytes after this */ -#define SCSI_MS_PAGE_LEN(total) ((total)-2) -}; - -#endif /**< SPC_PROTOCOL_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/class/msc/usb_protocol_msc.h b/atmel-samd/asf4/samd21/usb/class/msc/usb_protocol_msc.h deleted file mode 100644 index f69eae232..000000000 --- a/atmel-samd/asf4/samd21/usb/class/msc/usb_protocol_msc.h +++ /dev/null @@ -1,177 +0,0 @@ -/** - * \file - * - * \brief USB Mass Storage Class (MSC) protocol definitions. - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _USB_PROTOCOL_MSC_H_ -#define _USB_PROTOCOL_MSC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup usb_protocol_group - * \defgroup usb_msc_protocol USB Mass Storage Class (MSC) protocol definitions - * - * @{ - */ - -/** - * \name Possible Class value - */ -//@{ -#define MSC_CLASS 0x08 -//@} - -/** - * \name Possible SubClass value - * \note In practice, most devices should use - * #MSC_SUBCLASS_TRANSPARENT and specify the actual command set in - * the standard INQUIRY data block, even if the MSC spec indicates - * otherwise. In particular, RBC is not supported by certain major - * operating systems like Windows XP. - */ -//@{ -#define MSC_SUBCLASS_RBC 0x01 /**< Reduced Block Commands */ -#define MSC_SUBCLASS_ATAPI 0x02 /**< CD/DVD devices */ -#define MSC_SUBCLASS_QIC_157 0x03 /**< Tape devices */ -#define MSC_SUBCLASS_UFI 0x04 /**< Floppy disk drives */ -#define MSC_SUBCLASS_SFF_8070I 0x05 /**< Floppy disk drives */ -#define MSC_SUBCLASS_TRANSPARENT 0x06 /**< Determined by INQUIRY */ - //@} - -/** - * \name Possible protocol value - * \note Only the BULK protocol should be used in new designs. - */ -//@{ -#define MSC_PROTOCOL_CBI 0x00 /**< Command/Bulk/Interrupt */ -#define MSC_PROTOCOL_CBI_ALT 0x01 /**< W/o command completion */ -#define MSC_PROTOCOL_BULK 0x50 /**< Bulk-only */ - //@} - -/** - * \brief MSC USB requests (bRequest) - */ - -#define USB_REQ_MSC_BULK_RESET 0xFF /**< Mass Storage Reset */ -#define USB_REQ_MSC_GET_MAX_LUN 0xFE /**< Get Max LUN */ - -COMPILER_PACK_SET(1) - -/** - * \name A Command Block Wrapper (CBW) - * \note Fields are LSB first (LE) - */ -//@{ -struct usb_msc_cbw { - le32_t dCBWSignature; /**< Must contain 'USBC' (0x43425355, LE32) */ - le32_t dCBWTag; /**< Unique command ID (LE32) */ - le32_t dCBWDataTransferLength; /**< Number of bytes to transfer (LE32) */ - uint8_t bmCBWFlags; /**< Direction in bit 7 */ - uint8_t bCBWLUN; /**< Logical Unit Number */ - uint8_t bCBWCBLength; /**< Number of valid CDB bytes */ - uint8_t CDB[16]; /**< SCSI Command Descriptor Block */ -}; - -#define USB_CBW_SIGNATURE 0x43425355 /**< dCBWSignature value */ -#define USB_CBW_DIRECTION_IN (1 << 7) /**< Data from device to host */ -#define USB_CBW_DIRECTION_OUT (0 << 7) /**< Data from host to device */ -#define USB_CBW_LUN_MASK 0x0F /**< Valid bits in bCBWLUN */ -#define USB_CBW_LEN_MASK 0x1F /**< Valid bits in bCBWCBLength */ - //@} - -/** - * \name A Command Status Wrapper (CSW) - * \note Fields are LSB first (LE) - */ -//@{ -struct usb_msc_csw { - le32_t dCSWSignature; /**< Must contain 'USBS' */ - le32_t dCSWTag; /**< Same as dCBWTag */ - le32_t dCSWDataResidue; /**< Number of bytes not transfered */ - uint8_t bCSWStatus; /**< Status code */ -}; - -#define USB_CSW_SIGNATURE 0x53425355 /**< dCSWSignature value */ -#define USB_CSW_STATUS_PASS 0x00 /**< Command Passed */ -#define USB_CSW_STATUS_FAIL 0x01 /**< Command Failed */ -#define USB_CSW_STATUS_PE 0x02 /**< Phase Error */ -//@} - -COMPILER_PACK_RESET() - -//@} - -/** - * \brief Fill a Bulk-Only Mass Storage Reset request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - */ -static inline void usb_fill_BOMSReset_req(struct usb_req *req, uint8_t iface) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_MSC_BULK_RESET; - req->wValue = 0; - req->wIndex = iface; - req->wLength = 0; -} - -/** - * \brief Fill a GetMaxLUN request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - */ -static inline void usb_fill_GetMaxLUN_req(struct usb_req *req, uint8_t iface) -{ - req->bmRequestType = 0xA1; - req->bRequest = USB_REQ_MSC_GET_MAX_LUN; - req->wValue = 0; - req->wIndex = iface; - req->wLength = 1; -} - -#ifdef __cplusplus -} -#endif - -#endif // _USB_PROTOCOL_MSC_H_ diff --git a/atmel-samd/asf4/samd21/usb/class/vendor/usb_protocol_vendor.h b/atmel-samd/asf4/samd21/usb/class/vendor/usb_protocol_vendor.h deleted file mode 100644 index e865fb808..000000000 --- a/atmel-samd/asf4/samd21/usb/class/vendor/usb_protocol_vendor.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * \file - * - * \brief USB Vendor class protocol definitions. - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _USB_PROTOCOL_VENDOR_H_ -#define _USB_PROTOCOL_VENDOR_H_ - -/** - * \ingroup usb_protocol_group - * \defgroup usb_vendor_protocol USB Vendor Class definitions - * - */ - -/** - * \name Vendor class values - */ -#define VENDOR_CLASS 0xFF -#define VENDOR_SUBCLASS 0xFF -#define VENDOR_PROTOCOL 0xFF - -#endif /* _USB_PROTOCOL_VENDOR_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/device/usbdc.c b/atmel-samd/asf4/samd21/usb/device/usbdc.c deleted file mode 100644 index c9645541d..000000000 --- a/atmel-samd/asf4/samd21/usb/device/usbdc.c +++ /dev/null @@ -1,838 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack Core Layer Implementation. - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "usbdc.h" - -#define USBDC_VERSION 0x00000001u - -/** - * \brief USB Device Core Sof Handler - */ -struct usbdc_sof_handler { - struct usbdc_sof_handler *next; - usbdc_sof_cb_t cb; -}; - -/** - * \brief USB Device Core Request Handler - */ -struct usbdc_req_handler { - struct usbdc_req_handler *next; - usbdc_req_cb_t cb; -}; - -/** - * \brief USB Device Core Change Handler - */ -struct usbdc_change_handler { - struct usbdc_change_handler *next; - usbdc_change_cb_t cb; -}; - -/** - * \brief USB Device Core Handler - */ -struct usbdc_handlers { - struct list_descriptor sof_list; - struct list_descriptor req_list; - struct list_descriptor change_list; -}; - -/** - * \brief USB Device Core Driver Structure - */ -struct usbdc_driver { - /** Pointer to descriptions of descriptors. */ - struct usbdc_descriptors desces; - /** Callback handlers. */ - struct usbdc_handlers handlers; - /** list of function drivers. */ - struct list_descriptor func_list; - /** Control buffer. */ - uint8_t *ctrl_buf; - /** Device status. */ - uint16_t status; - /** Device state. */ - uint8_t state; - /** Configuration value. */ - uint8_t cfg_value; - /** Control endpoint size. */ - uint8_t ctrl_size; -}; - -/** - * \brief USB Device Core Driver Instance - */ -static struct usbdc_driver usbdc; - -/** - * \brief Process the GetDescriptor request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_get_desc_req(const uint8_t ep, struct usb_req *req) -{ - uint8_t *cfg_desc, *str_desc; - uint16_t total_len; - uint16_t length = req->wLength; - uint8_t type = (uint8_t)(req->wValue >> 8); - uint8_t index = req->wValue & 0x00FF; - bool need_zlp = !(length & (usbdc.ctrl_size - 1)); - - switch (type) { - case USB_DT_DEVICE: - if (length > 0x12) { - length = 0x12; - } - usbdc_xfer(ep, usbdc.desces.ls_fs->sod, length, false); - return true; - case USB_DT_CONFIG: - cfg_desc = usb_find_cfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, index + 1); - if (NULL == cfg_desc) { - return false; - } - total_len = usb_cfg_desc_total_len(cfg_desc); - if (length <= total_len) { - need_zlp = false; - } else { - length = total_len; - } - usbdc_xfer(ep, cfg_desc, length, need_zlp); - return true; - case USB_DT_STRING: - str_desc = usb_find_str_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, index); - if (NULL == str_desc) { - return false; - } - total_len = str_desc[0]; - if (length <= total_len) { - need_zlp = false; - } else { - length = total_len; - } - usbdc_xfer(ep, str_desc, length, need_zlp); - return true; - - default: - break; - } - return false; -} - -/** - * \brief Process the GetStatus request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_get_status_req(const uint8_t ep, const struct usb_req *req) -{ - int32_t st; - (void)ep; - - switch (req->bmRequestType & USB_REQT_RECIP_MASK) { - case USB_REQT_RECIP_DEVICE: - case USB_REQT_RECIP_INTERFACE: - st = 0; - break; - case USB_REQT_RECIP_ENDPOINT: - st = usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_GET); - if (st < 0) { - return false; - } - st = st & 0x1; - break; - default: - return false; - } - memcpy(usbdc.ctrl_buf, &st, 2); - usbdc_xfer(ep, usbdc.ctrl_buf, 2, false); - return true; -} - -/** - * \brief Process the standard Get Interface - * \param[in] req Point to usb request struct. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_get_interface(struct usb_req *req) -{ - struct usbdf_driver *func = (struct usbdf_driver *)usbdc.func_list.head; - int32_t rc; - - while (NULL != func) { - if (0 > (rc = func->ctrl(func, USBDF_GET_IFACE, req))) { - func = func->next; - } else { - usbdc.ctrl_buf[0] = (uint8_t)rc; - usbdc_xfer(0, usbdc.ctrl_buf, 1, false); - return true; - } - } - return false; -} - -/** - * \brief Process the standard Get request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_get_req(const uint8_t ep, struct usb_req *req) -{ - switch (req->bRequest) { - case USB_REQ_GET_DESC: - return usbdc_get_desc_req(ep, req); - case USB_REQ_GET_CONFIG: - *(uint8_t *)usbdc.ctrl_buf = usbdc.cfg_value; - usbdc_xfer(ep, usbdc.ctrl_buf, 1, false); - return true; - case USB_REQ_GET_STATUS: - return usbdc_get_status_req(ep, req); - case USB_REQ_GET_INTERFACE: - return usbdc_get_interface(req); - default: - return false; - } -} - -/** - * \brief Process the standard ClearFeature request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_clear_ftr_req(const uint8_t ep, const struct usb_req *req) -{ - (void)ep; - switch (req->bmRequestType & USB_REQT_RECIP_MASK) { - case USB_REQT_RECIP_ENDPOINT: - if (req->wLength != 0) { - return false; - } - usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_CLR); - usbdc_xfer(ep, NULL, 0, true); - return true; - default: - return false; - } -} - -/** - * \brief Process the standard SetFeature request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_set_ftr_req(const uint8_t ep, const struct usb_req *req) -{ - (void)ep; - switch (req->bmRequestType & USB_REQT_RECIP_MASK) { - case USB_REQT_RECIP_ENDPOINT: - if (req->wLength != 0) { - return false; - } - usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_SET); - usbdc_xfer(ep, NULL, 0, true); - return true; - default: - return false; - } -} - -/** - * \brief Unconfig, close all interfaces - */ -static void usbdc_unconfig(void) -{ - struct usbdf_driver *func = (struct usbdf_driver *)usbdc.func_list.head; - while (NULL != func) { - func->ctrl(func, USBDF_DISABLE, NULL); - func = func->next; - } -} - -/** - * \brief Apply Set Configuration Value - */ -static void usbdc_set_config(void) -{ - struct usbd_descriptors desc; - struct usbdf_driver * func; - uint8_t * cfg_desc; - uint16_t total_len; - uint8_t last_iface = 0xFF; - - if (usbdc.cfg_value == 0) { - usbdc_unconfig(); - return; - } - - cfg_desc = usb_find_cfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, usbdc.cfg_value); - - if (NULL == cfg_desc) { - return; - } - - total_len = usb_cfg_desc_total_len(cfg_desc); - desc.eod = cfg_desc + total_len; - desc.sod = usb_find_desc(cfg_desc, desc.eod, USB_DT_INTERFACE); - - while (NULL != desc.sod) { - /* Apply very first alternate setting (must be 0) of the interface */ - if (last_iface != desc.sod[2] /* bInterfaceNumber */) { - last_iface = desc.sod[2]; - func = (struct usbdf_driver *)usbdc.func_list.head; - while (NULL != func) { - if (func->ctrl(func, USBDF_ENABLE, &desc)) { - func = func->next; - } else { - break; - } - } - } - desc.sod = usb_desc_next(desc.sod); - desc.sod = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE); - } -} - -/** - * \brief Apply the USB device address - * \param[in] addr address to be set. - */ -static void usbdc_set_address(uint8_t addr) -{ - usb_d_set_address(addr); -} - -/** - * \brief Process the standard Set Interface - * \param[in] alt_set Alternate Setting. - * \param[in] ifc_id Interface Index. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_set_interface(uint16_t alt_set, uint16_t ifc_id) -{ - struct usbd_descriptors desc; - struct usbdf_driver * func; - uint8_t * ifc; - - desc.sod = usbdc.desces.ls_fs->sod; - desc.eod = usbdc.desces.ls_fs->eod; - if (NULL == (ifc = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE))) { - return false; - } - - while (ifc[2] != ifc_id || ifc[3] != alt_set) { - desc.sod = usb_desc_next(desc.sod); - ifc = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE); - if (NULL == ifc) { - return false; - } - } - - desc.sod = ifc; - func = (struct usbdf_driver *)usbdc.func_list.head; - - while (NULL != func) { - if (func->ctrl(func, USBDF_DISABLE, &desc)) { - func = func->next; - } else if (ERR_NONE == func->ctrl(func, USBDF_ENABLE, &desc)) { - usbdc_xfer(0, NULL, 0, 0); - return true; - } else { - return false; - } - } - - return false; -} - -/** - * \brief Process the standard Set request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_set_req(const uint8_t ep, struct usb_req *req) -{ - switch (req->bRequest) { - case USB_REQ_SET_ADDRESS: - case USB_REQ_SET_CONFIG: - if (ERR_NONE == usbdc_xfer(ep, NULL, 0, true)) { - return true; - } else { - return false; - } - case USB_REQ_CLEAR_FTR: - return usbdc_clear_ftr_req(ep, req); - case USB_REQ_SET_FTR: - return usbdc_set_ftr_req(ep, req); - case USB_REQ_SET_INTERFACE: - return usbdc_set_interface(req->wValue, req->wIndex); - default: - return false; - } -} - -/** Invoke all registered SOF callbacks. */ -static void usbdc_sof_notify(void) -{ - struct usbdc_sof_handler *sof = (struct usbdc_sof_handler *)usbdc.handlers.sof_list.head; - - while (sof != NULL) { - if (NULL != sof->cb) { - sof->cb(); - } - sof = sof->next; - } -} - -/** Invoke all registered Change notification callbacks. */ -static void usbdc_change_notify(enum usbdc_change_type change, uint32_t value) -{ - struct usbdc_change_handler *cg = (struct usbdc_change_handler *)usbdc.handlers.change_list.head; - - while (cg != NULL) { - if (NULL != cg->cb) { - cg->cb(change, value); - } - cg = cg->next; - } -} - -/** Invoke all registered request callbacks until request handled. */ -static bool usbdc_request_handler(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - struct usbdc_req_handler *h = (struct usbdc_req_handler *)usbdc.handlers.req_list.head; - int32_t rc; - - while (h != NULL) { - if (NULL != h->cb) { - rc = h->cb(ep, req, stage); - if (0 == rc) { - return true; - } else if (ERR_NOT_FOUND != rc) { - return false; - } - } - h = h->next; - } - return false; -} - -/** - * \brief Callback invoked on USB device SOF - */ -static void usbd_sof_cb(void) -{ - usbdc_sof_notify(); -} - -/** - * \brief Callback invoked when control request is received - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_cb_ctl_req(const uint8_t ep, struct usb_req *req) -{ - if (usbdc_request_handler(ep, req, USB_SETUP_STAGE)) { - return true; - } - - // STD request handling - switch (req->bmRequestType & (USB_REQT_TYPE_MASK | USB_REQT_DIR_IN)) { - case USB_REQT_TYPE_STANDARD: - return usbdc_set_req(ep, req); - case (USB_REQT_TYPE_STANDARD | USB_REQT_DIR_IN): - return usbdc_get_req(ep, req); - default: - return false; - } -} - -/** - * \brief When control status stage is end - * \param[in] req Pointer to the request. - */ -static void usbdc_ctrl_status_end(const struct usb_req *req) -{ - switch (req->bRequest) { - case USB_REQ_SET_CONFIG: - usbdc.cfg_value = req->wValue; - usbdc_set_config(); - usbdc.state = req->wValue ? USBD_S_CONFIG : USBD_S_ADDRESS; - usbdc_change_notify(USBDC_C_STATE, usbdc.state); - break; - case USB_REQ_SET_ADDRESS: - usbdc_set_address(req->wValue); - usbdc.state = req->wValue ? USBD_S_ADDRESS : USBD_S_DEFAULT; - usbdc_change_notify(USBDC_C_STATE, usbdc.state); - break; - default: - break; - } -} - -/** - * \brief When control data stage is end - * \param[in] req Pointer to the request. - */ -static bool usbdc_ctrl_data_end(struct usb_req *req) -{ - usbdc_request_handler(0, req, USB_DATA_STAGE); - return false; -} - -/** - * \brief Callback invoked when control data done or status done - * \param[in] ep Endpoint number with direction on bit 8. - * \param[in] code Status code. - * \param[in] req Pointer to the control setup request. - * \return Data has error or not. - * \retval true There is data error, protocol error. - * \retval false There is no data error. - */ -static bool usbdc_cb_ctl_done(const uint8_t ep, const enum usb_xfer_code code, struct usb_req *req) -{ - (void)ep; - - switch (code) { - case USB_XFER_DONE: - usbdc_ctrl_status_end(req); - break; - case USB_XFER_DATA: - return usbdc_ctrl_data_end(req); - default: - break; - } - return false; -} - -/** - * \brief USB Device Core Reset - */ -void usbdc_reset(void) -{ - usbdc_unconfig(); - - usbdc.state = USBD_S_DEFAULT; - usbdc.cfg_value = 0; - - // Setup EP0 - usb_d_ep_deinit(0); - usb_d_ep0_init(usbdc.ctrl_size); - usb_d_ep_register_callback(0, USB_D_EP_CB_SETUP, (FUNC_PTR)usbdc_cb_ctl_req); - usb_d_ep_register_callback(0, USB_D_EP_CB_XFER, (FUNC_PTR)usbdc_cb_ctl_done); - usb_d_ep_enable(0); -} - -/** - * \brief Callback invoked on USB device events - * \param[in] ev Event code. - * \param[in] param Event parameter for event handling. - */ -static void usbd_event_cb(const enum usb_event ev, const uint32_t param) -{ - (void)param; - - switch (ev) { - case USB_EV_VBUS: - usbdc_change_notify(USBDC_C_CONN, param); - break; - - case USB_EV_RESET: - usbdc_reset(); - break; - - default: - break; - } -} - -/** - * \brief Issue USB device transfer - */ -int32_t usbdc_xfer(uint8_t ep, uint8_t *buf, uint32_t size, bool zlp) -{ - struct usb_d_transfer xfer = {(uint8_t *)buf, size, ep, zlp}; - return usb_d_ep_transfer(&xfer); -} - -/** - * \brief Register the handler - */ -void usbdc_register_handler(enum usbdc_handler_type type, const struct usbdc_handler *h) -{ - switch (type) { - case USBDC_HDL_SOF: - list_insert_at_end(&usbdc.handlers.sof_list, (void *)h); - break; - case USBDC_HDL_REQ: - list_insert_at_end(&usbdc.handlers.req_list, (void *)h); - break; - case USBDC_HDL_CHANGE: - list_insert_at_end(&usbdc.handlers.change_list, (void *)h); - break; - default: - break; - } -} - -/** - * \brief Unregister the handler - */ -void usbdc_unregister_handler(enum usbdc_handler_type type, const struct usbdc_handler *h) -{ - switch (type) { - case USBDC_HDL_SOF: - list_delete_element(&usbdc.handlers.sof_list, (void *)h); - break; - case USBDC_HDL_REQ: - list_delete_element(&usbdc.handlers.req_list, (void *)h); - break; - case USBDC_HDL_CHANGE: - list_delete_element(&usbdc.handlers.change_list, (void *)h); - break; - default: - break; - } -} - -/** - * \brief Initialize the USB device core driver - */ -int32_t usbdc_init(uint8_t *ctrl_buf) -{ - ASSERT(ctrl_buf); - - int32_t rc; - - rc = usb_d_init(); - if (rc < 0) { - return rc; - } - - memset(&usbdc, 0, sizeof(usbdc)); - usbdc.ctrl_buf = ctrl_buf; - usb_d_register_callback(USB_D_CB_SOF, (FUNC_PTR)usbd_sof_cb); - usb_d_register_callback(USB_D_CB_EVENT, (FUNC_PTR)usbd_event_cb); - - return 0; -} - -/** - * \brief De-initialize the USB device core driver - */ -int32_t usbdc_deinit(void) -{ - usb_d_deinit(); - return 0; -} - -/** - * \brief Register/unregister function support of a USB device function - * - * Must be invoked when USB device is stopped. - */ -void usbdc_register_function(struct usbdf_driver *func) -{ - list_insert_at_end(&usbdc.func_list, func); -} - -/** - * \brief Unregister function support of a USB device function - * - * Must be invoked when USB device is stopped. - */ -void usbdc_unregister_function(struct usbdf_driver *func) -{ - list_delete_element(&usbdc.func_list, func); -} - -/** - * \brief Validate the descriptor - */ -int32_t usbdc_validate_desces(struct usbd_descriptors *desces) -{ - uint8_t *sod, *eod; - if (desces == NULL) { - return ERR_NOT_FOUND; - } - sod = usb_find_desc(desces->sod, desces->eod, USB_DT_DEVICE); - if (sod == NULL) { - return ERR_BAD_DATA; - } - sod = usb_find_desc(desces->sod, desces->eod, USB_DT_CONFIG); - if (sod == NULL) { - return ERR_BAD_DATA; - } - eod = sod + usb_cfg_desc_total_len(sod); - if (eod > desces->eod) { - return ERR_BAD_DATA; - } - return 0; -} - -/** - * \brief Validate the descriptor - */ -int32_t usbdc_check_desces(struct usbdc_descriptors *desces) -{ -#ifdef CONF_USBD_HS_SP - int32_t rc; - if (desces->hs == NULL && desces->ls_fs == NULL) { - return ERR_NOT_FOUND; - } - if (desces->hs) { - rc = usbdc_validate_desces(desces->hs); - if (rc < 0) { - return rc; - } - } -#endif - return usbdc_validate_desces(desces->ls_fs); -} - -/** - * \brief Start the USB device driver with specific descriptors set - */ -int32_t usbdc_start(struct usbd_descriptors *desces) -{ - if (usbdc.state >= USBD_S_POWER) { - return ERR_BUSY; - } - - if (desces) { - usbdc.desces.ls_fs = desces; - } else { - return ERR_BAD_DATA; - } - - usbdc.ctrl_size = desces->sod[7]; - usbdc.state = USBD_S_POWER; - usb_d_enable(); - return ERR_NONE; -} - -/** - * \brief Stop the USB device driver - */ -int32_t usbdc_stop(void) -{ - usb_d_disable(); - usbdc.state = USBD_S_OFF; - return ERR_NONE; -} - -/** - * \brief Attach the USB device to host - */ -void usbdc_attach(void) -{ - usb_d_attach(); -} - -/** - * \brief Detach the USB device from host - */ -void usbdc_detach(void) -{ - usb_d_detach(); -} - -/** - * \brief Send remote wakeup to host - */ -void usbdc_remotewakeup(void) -{ - usb_d_send_remotewakeup(); - usbdc.state = USBD_S_POWER; -} - -/** - * \brief Return USB Device endpoint0 buffer - */ -uint8_t *usbdc_get_ctrl_buffer(void) -{ - return usbdc.ctrl_buf; -} - -/** - * \brief Return current USB state - */ -uint8_t usbdc_get_state(void) -{ - if (usbdc.state & USBD_S_SUSPEND) { - return USBD_S_SUSPEND; - } - return usbdc.state; -} - -/** - * \brief Return version - */ -uint32_t usbdc_get_version(void) -{ - return USBDC_VERSION; -} diff --git a/atmel-samd/asf4/samd21/usb/device/usbdc.h b/atmel-samd/asf4/samd21/usb/device/usbdc.h deleted file mode 100644 index 515d28f1b..000000000 --- a/atmel-samd/asf4/samd21/usb/device/usbdc.h +++ /dev/null @@ -1,246 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack Core Layer Definition. - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef _USB_USBDC_H_ -#define _USB_USBDC_H_ - -#include "usb_includes.h" -#include "usb_protocol.h" -#include "hal_usb_device.h" - -/** USB device states. */ -enum usbd_state { - USBD_S_OFF = 0, - USBD_S_POWER = 1, - USBD_S_DEFAULT = 2, - USBD_S_ADDRESS = 3, - USBD_S_CONFIG = 4, - USBD_S_SUSPEND = 0x10 -}; - -/** USB device core handler type. */ -enum usbdc_handler_type { USBDC_HDL_SOF, USBDC_HDL_REQ, USBDC_HDL_CHANGE }; - -/** USB device core change notification type. */ -enum usbdc_change_type { - /** Change of connection, detected by vbus. */ - USBDC_C_CONN, - /** Change of state, by RESET, SetAddress(), SetConfig(). */ - USBDC_C_STATE, - /** Change of power. */ - USBDC_C_POWER, - /** Change of remote wakeup setting. */ - USBDC_C_REMOTE_WAKEUP -}; - -/** Power change. */ -enum usbdc_power_type { USBDC_ACTIVE, USBDC_SLEEP, USBDC_SUSPEND }; - -/** USB device general function control code. */ -enum usbdf_control { - /** Enable the function. - * int32_t ctrl(usbdf, USBDF_ENABLE, struct usbd_descriptors *desc); - * Parameter holds interface descriptor and - * configuration descriptor end position. - */ - USBDF_ENABLE, - /** Disable the function. - * int32_t ctrl(usbdf, USBDF_DISABLE, struct usbd_descriptors *desc); - * Parameter holds interface descriptor and - * configuration descriptor end position. - * Input NULL to force disable the function anyway. - */ - USBDF_DISABLE, - /** Get interface alternate setting. - * int32_t ctrl(usbdf, USBDF_GET_IFACE, struct usb_req *req); - * Parameter holds interface number who should return - * the alternate setting. - */ - USBDF_GET_IFACE -}; - -/** Describes a list of USB descriptors. */ -struct usbd_descriptors { - /** Pointer to Start of Descriptors. */ - uint8_t *sod; - /** Pointer to End of Descriptors. */ - uint8_t *eod; -}; - -/** Describes the USB device core descriptors. */ -struct usbdc_descriptors { - struct usbd_descriptors *ls_fs; -#ifdef CONF_USBD_HS_SP - struct usbd_descriptors *hs; -#endif -}; - -/** Describes a list of core handler descriptor. */ -struct usbdc_handler { - /** Pointer to next handler. */ - struct usbdc_handler *next; - /** Pointer to handler function. */ - FUNC_PTR func; -}; - -/** Forward declaration for USB device function driver. */ -struct usbdf_driver; - -/** SOF handling function. */ -typedef void (*usbdc_sof_cb_t)(void); - -/** REQ handling function. */ -typedef int32_t (*usbdc_req_cb_t)(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage); - -/** Change notification callback function. */ -typedef void (*usbdc_change_cb_t)(enum usbdc_change_type change, uint32_t value); - -/** Control function for USB device general function driver. */ -typedef int32_t (*usbdf_control_cb_t)(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param); - -/** USB device general function driver descriptor. */ -struct usbdf_driver { - /** Pointer to next function.*/ - struct usbdf_driver *next; - /** Pointer to control function.*/ - usbdf_control_cb_t ctrl; - /** Pointer to function driver specific data. */ - void *func_data; -}; - -/** - * \brief Register the handler - * \param[in] type USB device core handler type. - * \param[in] h Pointer to usb device core handler. - */ -void usbdc_register_handler(enum usbdc_handler_type type, const struct usbdc_handler *h); - -/** - * \brief Unregister the handler - * \param[in] type USB device core handler type. - * \param[in] h Pointer to usb device core handler. - */ -void usbdc_unregister_handler(enum usbdc_handler_type type, const struct usbdc_handler *h); - -/** - * \brief Initialize the USB device core driver - * \param[in] ctrl_buf Pointer to a buffer to be used by usb device ctrl endpoint - * Note: the size of ctrl_buf should not be less than the size of EP0 - * \return Operation status. - */ -int32_t usbdc_init(uint8_t *ctrl_buf); - -/** - * \brief Deinitialize the USB device core driver - * \return Operation status. - */ -int32_t usbdc_deinit(void); - -/** - * \brief Register function support of a USB device function - * \param[in] func Pointer to usb device function driver structure - */ -void usbdc_register_function(struct usbdf_driver *func); - -/** - * \brief Unregister function support of a USB device function - * \param[in] func Pointer to usb device function driver structure - */ -void usbdc_unregister_function(struct usbdf_driver *func); - -/** - * \brief Validate the descriptors - * \param[in] desces Pointer to usb device core descriptors - * \return Operation status. - */ -int32_t usbdc_validate_desces(struct usbd_descriptors *desces); - -/** - * \brief Issue USB device data transfer - * \param[in] ep endpointer address. - * \param[in] buf Pointer to data transfer buffer. - * \param[in] size the size of data transfer. - * \param[in] zlp flag to indicate zero length packet. - * \return Operation status. - */ -int32_t usbdc_xfer(uint8_t ep, uint8_t *buf, uint32_t size, bool zlp); - -/** - * \brief Start the USB device driver with specific descriptors set - * \param[in] desces Pointer to usb device core descriptors - * \return Operation status. - */ -int32_t usbdc_start(struct usbd_descriptors *desces); - -/** - * \brief Stop the USB device driver - * \return Operation status. - */ -int32_t usbdc_stop(void); - -/** - * \brief Attach the USB device to host - */ -void usbdc_attach(void); - -/** - * \brief Detach the USB device from host - */ -void usbdc_detach(void); - -/** - * \brief Send remote wakeup to host - */ -void usbdc_remotewakeup(void); - -/** - * \brief Return USB device ctrl end pointer buffer start address - */ -uint8_t *usbdc_get_ctrl_buffer(void); - -/** - * \brief Return current USB state - */ -uint8_t usbdc_get_state(void); - -/** - * \brief Return version - */ -uint32_t usbdc_get_version(void); - -#endif /* USBDC_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/usb_atmel.h b/atmel-samd/asf4/samd21/usb/usb_atmel.h deleted file mode 100644 index 3ca7a2927..000000000 --- a/atmel-samd/asf4/samd21/usb/usb_atmel.h +++ /dev/null @@ -1,189 +0,0 @@ -/** - * \file - * - * \brief All USB VIDs and PIDs from Atmel USB applications - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _USB_ATMEL_H_ -#define _USB_ATMEL_H_ - -/** - * \defgroup usb_group USB Stack - * - * This stack includes the USB Device Stack, USB Host Stack and common - * definitions. - * @{ - */ - -//! @} - -/** - * \ingroup usb_group - * \defgroup usb_atmel_ids_group Atmel USB Identifiers - * - * This module defines Atmel PID and VIDs constants. - * - * @{ - */ - -//! \name Vendor Identifier assigned by USB org to ATMEL -#define USB_VID_ATMEL 0x03EB - -//! \name Product Identifier assigned by ATMEL to AVR applications -//! @{ - -//! \name The range from 2000h to 20FFh is reserved to the old PID for C51, MEGA, and others. -//! @{ -#define USB_PID_ATMEL_MEGA_HIDGENERIC 0x2013 -#define USB_PID_ATMEL_MEGA_HIDKEYBOARD 0x2017 -#define USB_PID_ATMEL_MEGA_CDC 0x2018 -#define USB_PID_ATMEL_MEGA_AUDIO_IN 0x2019 -#define USB_PID_ATMEL_MEGA_MS 0x201A -#define USB_PID_ATMEL_MEGA_AUDIO_IN_OUT 0x201B -#define USB_PID_ATMEL_MEGA_HIDMOUSE 0x201C -#define USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4 0x201D -#define USB_PID_ATMEL_MEGA_CDC_MULTI 0x201E -#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY 0x2022 -#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525 0x2023 -#define USB_PID_ATMEL_MEGA_MS_2 0x2029 -#define USB_PID_ATMEL_MEGA_MS_HIDMS 0x202A -#define USB_PID_ATMEL_MEGA_MS_3 0x2032 -#define USB_PID_ATMEL_MEGA_LIBUSB 0x2050 -//! @} - -//! \name The range 2100h to 21FFh is reserved to PIDs for AVR Tools. -//! @{ -#define USB_PID_ATMEL_XPLAINED 0x2122 -#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ 0x214A -#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ 0x214B -//! @} - -//! \name The range 2300h to 23FFh is reserved to PIDs for demo from ASF1.7=> -//! @{ -#define USB_PID_ATMEL_UC3_ENUM 0x2300 -#define USB_PID_ATMEL_UC3_MS 0x2301 -#define USB_PID_ATMEL_UC3_MS_SDRAM_LOADER 0x2302 -#define USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL 0x2303 -#define USB_PID_ATMEL_UC3_HID 0x2304 -#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID 0x2305 -#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306 -#define USB_PID_ATMEL_UC3_CDC 0x2307 -#define USB_PID_ATMEL_UC3_AUDIO_MICRO 0x2308 -#define USB_PID_ATMEL_UC3_CDC_DEBUG 0x2310 // Virtual Com (debug interface) on EVK11xx -#define USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO 0x2311 -#define USB_PID_ATMEL_UC3_CDC_MSC 0x2312 -//! @} - -//! \name The range 2400h to 24FFh is reserved to PIDs for ASF applications -//! @{ -#define USB_PID_ATMEL_ASF_HIDMOUSE 0x2400 -#define USB_PID_ATMEL_ASF_HIDKEYBOARD 0x2401 -#define USB_PID_ATMEL_ASF_HIDGENERIC 0x2402 -#define USB_PID_ATMEL_ASF_MSC 0x2403 -#define USB_PID_ATMEL_ASF_CDC 0x2404 -#define USB_PID_ATMEL_ASF_PHDC 0x2405 -#define USB_PID_ATMEL_ASF_HIDMTOUCH 0x2406 -#define USB_PID_ATMEL_ASF_MSC_HIDMOUSE 0x2420 -#define USB_PID_ATMEL_ASF_MSC_HIDS_CDC 0x2421 -#define USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD 0x2422 -#define USB_PID_ATMEL_ASF_VENDOR_CLASS 0x2423 -#define USB_PID_ATMEL_ASF_MSC_CDC 0x2424 -#define USB_PID_ATMEL_ASF_TWO_CDC 0x2425 -#define USB_PID_ATMEL_ASF_SEVEN_CDC 0x2426 -#define USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY 0x2430 -#define USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL 0x2431 -#define USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH 0x2432 -#define USB_PID_ATMEL_ASF_AUDIO_SPEAKER 0x2433 -#define USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED 0x2434 -//! @} - -//! \name The range 2F00h to 2FFFh is reserved to official PIDs for AVR bootloaders -//! Note, !!!! don't use this range for demos or examples !!!! -//! @{ -#define USB_PID_ATMEL_DFU_ATXMEGA64C3 0x2FD6 -#define USB_PID_ATMEL_DFU_ATXMEGA128C3 0x2FD7 -#define USB_PID_ATMEL_DFU_ATXMEGA16C4 0x2FD8 -#define USB_PID_ATMEL_DFU_ATXMEGA32C4 0x2FD9 -#define USB_PID_ATMEL_DFU_ATXMEGA256C3 0x2FDA -#define USB_PID_ATMEL_DFU_ATXMEGA384C3 0x2FDB -#define USB_PID_ATMEL_DFU_ATUCL3_L4 0x2FDC -#define USB_PID_ATMEL_DFU_ATXMEGA64A4U 0x2FDD -#define USB_PID_ATMEL_DFU_ATXMEGA128A4U 0x2FDE - -#define USB_PID_ATMEL_DFU_ATXMEGA64B3 0x2FDF -#define USB_PID_ATMEL_DFU_ATXMEGA128B3 0x2FE0 -#define USB_PID_ATMEL_DFU_ATXMEGA64B1 0x2FE1 -#define USB_PID_ATMEL_DFU_ATXMEGA256A3BU 0x2FE2 -#define USB_PID_ATMEL_DFU_ATXMEGA16A4U 0x2FE3 -#define USB_PID_ATMEL_DFU_ATXMEGA32A4U 0x2FE4 -#define USB_PID_ATMEL_DFU_ATXMEGA64A3U 0x2FE5 -#define USB_PID_ATMEL_DFU_ATXMEGA128A3U 0x2FE6 -#define USB_PID_ATMEL_DFU_ATXMEGA192A3U 0x2FE7 -#define USB_PID_ATMEL_DFU_ATXMEGA64A1U 0x2FE8 -#define USB_PID_ATMEL_DFU_ATUC3D 0x2FE9 -#define USB_PID_ATMEL_DFU_ATXMEGA128B1 0x2FEA -#define USB_PID_ATMEL_DFU_AT32UC3C 0x2FEB -#define USB_PID_ATMEL_DFU_ATXMEGA256A3U 0x2FEC -#define USB_PID_ATMEL_DFU_ATXMEGA128A1U 0x2FED -#define USB_PID_ATMEL_DFU_ATMEGA8U2 0x2FEE -#define USB_PID_ATMEL_DFU_ATMEGA16U2 0x2FEF -#define USB_PID_ATMEL_DFU_ATMEGA32U2 0x2FF0 -#define USB_PID_ATMEL_DFU_AT32UC3A3 0x2FF1 -#define USB_PID_ATMEL_DFU_ATMEGA32U6 0x2FF2 -#define USB_PID_ATMEL_DFU_ATMEGA16U4 0x2FF3 -#define USB_PID_ATMEL_DFU_ATMEGA32U4 0x2FF4 -#define USB_PID_ATMEL_DFU_AT32AP7200 0x2FF5 -#define USB_PID_ATMEL_DFU_AT32UC3B 0x2FF6 -#define USB_PID_ATMEL_DFU_AT90USB82 0x2FF7 -#define USB_PID_ATMEL_DFU_AT32UC3A 0x2FF8 -#define USB_PID_ATMEL_DFU_AT90USB64 0x2FF9 -#define USB_PID_ATMEL_DFU_AT90USB162 0x2FFA -#define USB_PID_ATMEL_DFU_AT90USB128 0x2FFB -// 2FFCh to 2FFFh used by C51 family products -//! @} - -//! @} - -//! @} - -#endif // _USB_ATMEL_H_ diff --git a/atmel-samd/asf4/samd21/usb/usb_debug.h b/atmel-samd/asf4/samd21/usb/usb_debug.h deleted file mode 100644 index 4d8893208..000000000 --- a/atmel-samd/asf4/samd21/usb/usb_debug.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * \file - * - * \brief USB Debug Files. - * - * This file contains the USB definitions and data structures provided by the - * USB 2.0 specification. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef _USB_DEBUG_H_ -#define _USB_DEBUG_H_ - -#define udbg_print(...) - -#endif diff --git a/atmel-samd/asf4/samd21/usb/usb_includes.h b/atmel-samd/asf4/samd21/usb/usb_includes.h deleted file mode 100644 index b3874d31e..000000000 --- a/atmel-samd/asf4/samd21/usb/usb_includes.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * \file - * - * \brief USB Include Header Files. - * - * This file contains the USB definitions and data structures provided by the - * USB 2.0 specification. - * - * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef _USB_INCLUDES_H_ -#define _USB_INCLUDES_H_ - -#ifdef USB_USER_INCLUDES - -#include "usb_user_includes.h" - -#else -/* Include START headers */ -#include -#include -#include -#include -#include -#include -#include - -typedef uint16_t le16_t; -typedef uint32_t le32_t; -typedef uint16_t be16_t; -typedef uint32_t be32_t; - -#if (defined __GNUC__) || (defined __CC_ARM) -#define is_constant(exp) __builtin_constant_p(exp) -#else -#define is_constant(exp) (0) -#endif - -/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). - * - * \param u16 U16 of which to toggle the endianism. - * - * \return Value resulting from \a u16 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define swap_u16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) | ((uint16_t)(u16) << 8))) - -/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). - * - * \param u32 U32 of which to toggle the endianism. - * - * \return Value resulting from \a u32 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#if (defined __GNUC__) -#define swap_u32(u32) \ - (is_constant(u32) \ - ? ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16))) \ - : ((uint32_t)__builtin_bswap32((uint32_t)(u32)))) -#else -#define swap_u32(u32) \ - ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16))) -#endif - -/** Get a value from/to LE16 data */ -#define LE16(x) (x) -/** Get a value from/to LE32 data */ -#define LE32(x) (x) -/** Get a value from/to BE16 data */ -#define BE16(x) swap_u16(x) -/** Get a value from/to BE32 data */ -#define BE32(x) swap_u32(x) - -/** Get byte 0 for BE 16-bit value */ -#define BE16B0(a) ((uint8_t)((a) >> 8)) -/** Get byte 1 for BE 16-bit value */ -#define BE16B1(a) ((uint8_t)((a) >> 0)) - -/** Get byte 0 for BE 32-bit value */ -#define BE32B0(a) ((uint8_t)((a) >> 24)) -/** Get byte 1 for BE 32-bit value */ -#define BE32B1(a) ((uint8_t)((a) >> 16)) -/** Get byte 2 for BE 32-bit value */ -#define BE32B2(a) ((uint8_t)((a) >> 8)) -/** Get byte 3 for BE 32-bit value */ -#define BE32B3(a) ((uint8_t)((a) >> 0)) - -/** Get byte 0 for LE 16-bit value */ -#define LE16B0(a) ((uint8_t)((a) >> 0)) -/** Get byte 1 for LE 16-bit value */ -#define LE16B1(a) ((uint8_t)((a) >> 8)) - -/** Get byte 0 for LE 32-bit value */ -#define LE32B0(a) ((uint8_t)((a) >> 0)) -/** Get byte 1 for LE 32-bit value */ -#define LE32B1(a) ((uint8_t)((a) >> 8)) -/** Get byte 2 for LE 32-bit value */ -#define LE32B2(a) ((uint8_t)((a) >> 16)) -/** Get byte 3 for LE 32-bit value */ -#define LE32B3(a) ((uint8_t)((a) >> 24)) - -#endif /* USB_USER_INCLUDES */ - -#endif /* _USB_INCLUDES_H_ */ diff --git a/atmel-samd/asf4/samd21/usb/usb_protocol.c b/atmel-samd/asf4/samd21/usb/usb_protocol.c deleted file mode 100644 index 534e4d1d9..000000000 --- a/atmel-samd/asf4/samd21/usb/usb_protocol.c +++ /dev/null @@ -1,146 +0,0 @@ -/** - * \file - * - * \brief USB protocol implementation. - * - * This file contains the USB definitions and data structures provided by the - * USB 2.0 specification. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#define CONF_NO_ASSERT_CHECK - -#include "usb_protocol.h" - -#ifdef CONF_NO_ASSERT_CHECK -#define _param_error_check(cond) -#define _desc_len_check() \ - if (usb_desc_len(desc) < 2) { \ - /* Encounter an invalid descriptor. */ \ - return NULL; \ - } -#else -#define _param_error_check(cond) ASSERT(cond) -#define _desc_len_check() ASSERT(usb_desc_len(desc) >= 2) -#endif - -uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type) -{ - _param_error_check(desc && eof && (desc < eof)); - - while (desc < eof) { - _desc_len_check(); - if (type == usb_desc_type(desc)) { - return desc; - } - desc = usb_desc_next(desc); - } - return NULL; -} - -uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n) -{ - _param_error_check(desc && eof && (desc < eof)); - - while (desc < eof) { - _desc_len_check(); - if (USB_DT_INTERFACE == usb_desc_type(desc)) { - if (iface_n != desc[2]) { - return desc; - } - } - desc = usb_desc_next(desc); - } - return eof; -} - -uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof) -{ - _param_error_check(desc && eof && (desc < eof)); - - while (desc < eof) { - _desc_len_check(); - if (USB_DT_INTERFACE == usb_desc_type(desc)) { - break; - } - if (USB_DT_ENDPOINT == usb_desc_type(desc)) { - return desc; - } - desc = usb_desc_next(desc); - } - return NULL; -} - -uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value) -{ - _param_error_check(desc && eof && (desc < eof)); - - desc = usb_find_desc(desc, eof, USB_DT_CONFIG); - if (!desc) { - return NULL; - } - while (desc < eof) { - _desc_len_check(); - if (desc[1] != USB_DT_CONFIG) { - break; - } - if (desc[5] == cfg_value) { - return desc; - } - desc = usb_cfg_desc_next(desc); - } - return NULL; -} - -uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index) -{ - uint8_t i; - - _param_error_check(desc && eof && (desc < eof)); - - for (i = 0; desc < eof;) { - desc = usb_find_desc(desc, eof, USB_DT_STRING); - if (desc) { - _desc_len_check(); - if (i == str_index) { - return desc; - } - i++; - desc = usb_desc_next(desc); - } else { - return NULL; - } - } - return NULL; -} diff --git a/atmel-samd/asf4/samd21/usb/usb_protocol.h b/atmel-samd/asf4/samd21/usb/usb_protocol.h deleted file mode 100644 index bb8d1ecd5..000000000 --- a/atmel-samd/asf4/samd21/usb/usb_protocol.h +++ /dev/null @@ -1,765 +0,0 @@ -/** - * \file - * - * \brief USB protocol definitions. - * - * This file contains the USB definitions and data structures provided by the - * USB 2.0 specification. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef _USB_PROTOCOL_H_ -#define _USB_PROTOCOL_H_ - -#include "usb_includes.h" - -/** - * \ingroup usb_group - * \defgroup usb_protocol_group USB Protocol Definitions - * - * This module defines constants and data structures provided by the USB - * 2.0 specification. - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __CC_ARM -#pragma anon_unions -#endif - -/*! Value for field bcdUSB */ -#define USB_V2_0 (0x0200) /*!< USB Specification version 2.00 */ -#define USB_V2_1 (0x0201) /*!< USB Specification version 2.01 (support BOS) */ - -/*! \name Generic definitions (Class, subclass and protocol) - */ -/*! @{ */ -#define USB_CLASS_NO (0x00) -#define USB_SUBCLASS_NO (0x00) -#define USB_PROTOCOL_NO (0x00) -/*! @} */ - -/*! \name IAD (Interface Association Descriptor) constants */ -/*! @{ */ -#define USB_CLASS_IAD (0xEF) -#define USB_SUBCLASS_IAD (0x02) -#define USB_PROTOCOL_IAD (0x01) -/*! @} */ - -/** - * \brief USB request data transfer direction (bmRequestType) - */ -#define USB_REQT_DIR_OUT (0 << 7) /*!< Host to device */ -#define USB_REQT_DIR_H2D (0 << 7) /*!< Host to device */ -#define USB_REQT_DIR_IN (1 << 7) /*!< Device to host */ -#define USB_REQT_DIR_D2H (1 << 7) /*!< Device to host */ -#define USB_REQT_DIR_MASK (1 << 7) /*!< Mask */ - -/** - * \brief USB request types (bmRequestType) - */ -#define USB_REQT_TYPE_STANDARD (0 << 5) /*!< Standard request */ -#define USB_REQT_TYPE_CLASS (1 << 5) /*!< Class-specific request */ -#define USB_REQT_TYPE_VENDOR (2 << 5) /*!< Vendor-specific request */ -#define USB_REQT_TYPE_MASK (3 << 5) /*!< Mask */ - -/** - * \brief USB recipient codes (bmRequestType) - */ -#define USB_REQT_RECIP_DEVICE (0 << 0) /*!< Recipient device */ -#define USB_REQT_RECIP_INTERFACE (1 << 0) /*!< Recipient interface */ -#define USB_REQT_RECIP_ENDPOINT (2 << 0) /*!< Recipient endpoint */ -#define USB_REQT_RECIP_OTHER (3 << 0) /*!< Recipient other */ -#define USB_REQT_RECIP_MASK (0x1F) /*!< Mask */ - -/** - * \brief Standard USB control transfer stages. - */ -enum usb_ctrl_stage { USB_SETUP_STAGE = 0, USB_DATA_STAGE = 1, USB_STATUS_STAGE = 2 }; - -/** - * \brief Standard USB requests (bRequest) - */ -enum usb_req_code { - USB_REQ_GET_STATUS = 0, - USB_REQ_CLEAR_FTR = 1, - USB_REQ_SET_FTR = 3, - USB_REQ_SET_ADDRESS = 5, - USB_REQ_GET_DESC = 6, - USB_REQ_SET_DESC = 7, - USB_REQ_GET_CONFIG = 8, - USB_REQ_SET_CONFIG = 9, - USB_REQ_GET_INTERFACE = 10, - USB_REQ_SET_INTERFACE = 11, - USB_REQ_SYNCH_FRAME = 12, - USB_REQ_SET_SEL = 48, - USB_REQ_ISOCH_DELAY = 49 -}; - -/** - * \brief Standard USB device status flags - * - */ -enum usb_dev_status { - USB_DEV_STAT_BUS_POWERED = 0, - USB_DEV_STAT_SELF_POWERED = 1, - USB_DEV_STAT_REMOTEWAKEUP = 2, - USB_DEV_STAT_U1_ENABLE = 4, - USB_DEV_STAT_U2_ENABLE = 8, - USB_DEV_STAT_LTM_ENABLE = 16 -}; - -/** - * \brief Standard USB Interface status flags - * - */ -enum usb_interface_status { - USB_IFACE_STAT_RESERVED = 0, - USB_IFACE_STAT_REMOTEWAKE_CAP = 1, - USB_IFACE_STAT_REMOTEWAKE = 2 -}; - -/** - * \brief Standard USB endpoint status flags - * - */ -enum usb_endpoint_status { USB_EP_STAT_HALT = 1 }; - -/** - * \brief Standard USB device feature flags - * - * \note valid for SetFeature request. - */ -enum usb_device_feature { - USB_DEV_FTR_REMOTE_WAKEUP = 1, /*!< Remote wakeup enabled */ - USB_DEV_FTR_TEST_MODE = 2, /*!< USB test mode */ - USB_DEV_FTR_OTG_B_HNP_ENABLE = 3, - USB_DEV_FTR_OTG_A_HNP_SP = 4, - USB_DEV_FTR_OTG_A_ALT_HNP_SP = 5, - USB_DEV_FTR_U1_ENABLE = 48, - USB_DEV_FTR_U2_ENABLE = 49, - USB_DEV_FTR_LTM_ENABLE = 50 -}; - -/** - * \brief Test Mode possible on HS USB device - * - * \note valid for USB_DEV_FTR_TEST_MODE request. - */ -enum usb_device_hs_test_mode { - USB_DEV_TEST_MODE_J = 1, - USB_DEV_TEST_MODE_K = 2, - USB_DEV_TEST_MODE_SE0_NAK = 3, - USB_DEV_TEST_MODE_PACKET = 4, - USB_DEV_TEST_MODE_FORCE_ENABLE = 5 -}; - -/** - * \brief Standard Feature Selectors for Interface - */ -enum usb_iface_feature { USB_IFACE_FTR_FUNC_SUSP = 0 }; - -/** - * \brief Standard USB endpoint feature/status flags - */ -enum usb_endpoint_feature { USB_EP_FTR_HALT = 0 }; - -/** - * \brief Standard USB Test Mode Selectors - */ -enum usb_test_mode_selector { - USB_TEST_J = 0x01, - USB_TEST_K = 0x02, - USB_TEST_SE0_NAK = 0x03, - USB_TEST_PACKET = 0x04, - USB_TEST_FORCE_ENABLE = 0x05 -}; - -/** - * \brief Standard USB descriptor types - */ -enum usb_descriptor_type { - USB_DT_DEVICE = 1, - USB_DT_CONFIG = 2, - USB_DT_STRING = 3, - USB_DT_INTERFACE = 4, - USB_DT_ENDPOINT = 5, - USB_DT_DEVICE_QUALIFIER = 6, - USB_DT_OTHER_SPEED_CONFIG = 7, - USB_DT_INTERFACE_POWER = 8, - USB_DT_OTG = 9, - USB_DT_DEBUG = 10, - USB_DT_IAD = 11, - USB_DT_BOS = 15, - USB_DT_DEV_CAP = 16, - USB_DT_SS_EP_COMPANION = 48 -}; - -/** - * \brief Capability types - */ -enum usb_capability_type { - USB_CAPT_WIRELESS = 1, - USB_CAPT_2_0_EXT = 2, - USB_CAPT_SUPER_SPEED = 3, - USB_CAPT_CONTAINER_ID = 4 -}; - -/** - * \brief USB 2.0 Extension attributes - */ -enum usb_2_0_ext_attr { USB_2_0_EXT_LPM_SP = 1 }; - -/** - * \brief USB SuperSpeed Capability attributes - */ -enum usb_ss_cap_attr { USB_SS_LTM_SP }; - -/** - * \brief USB Speed Supports - */ -enum usb_speed_sp { - USB_SPEED_LOW_SP = 1, - USB_SPEED_LS_SP = 1, - USB_SPEED_FULL_SP = 2, - USB_SPEED_FS_SP = 2, - USB_SPEED_HIGH_SP = 4, - USB_SPEED_HS_SP = 4, - USB_SPEED_SUPER_SP = 8, - USB_SPEED_SS_SP = 8 -}; - -/** - * \brief Standard USB endpoint transfer types - */ -enum usb_ep_type { - USB_EP_TYPE_CONTROL = 0x00, - USB_EP_TYPE_ISOCHRONOUS = 0x01, - USB_EP_TYPE_BULK = 0x02, - USB_EP_TYPE_INTERRUPT = 0x03, - USB_EP_TYPE_MASK = 0x03u -}; - -/** - * \brief USB endpoint interrupt types - */ -enum usb_ep_int_type { USB_EP_INT_T_PERIODIC = 0x00u, USB_EP_INT_T_NOTIFICATION = 0x01u, USB_EP_INT_T_MASK = 0x03u }; - -/** - * \brief Standard USB endpoint synchronization types - */ -enum usb_ep_sync_type { - USB_EP_SYNC_T_NO = 0x00u, - USB_EP_SYNC_T_ASYNC = 0x02u, - USB_EP_SYNC_T_ADAPTIVE = 0x02u, - USB_EP_SYNC_T_SYNC = 0x03u, - USB_EP_SYNC_T_MASK = 0x03u -}; - -/** - * \brief Standard USB endpoint usage types - */ -enum usb_ep_usage_type { - USB_EP_USAGE_T_DATA = 0x00u, - USB_EP_USAGE_T_FEEDBACK = 0x01u, - USB_EP_USAGE_T_FEEDBACK_DATA = 0x02u, - USB_EP_USAGE_T_MASK = 0x03u -}; - -/** - * \brief Standard USB language IDs for string descriptors - */ -enum usb_langid { - USB_LANGID_EN_US = 0x0409 /*!< English (United States) */ -}; - -/** - * \brief Mask selecting the index part of an endpoint address - */ -#define USB_EP_ADDR_MASK 0x0f -/** - * \brief Endpoint transfer direction is IN - */ -#define USB_EP_DIR_IN 0x80 -/** - * \brief Endpoint transfer direction is OUT - */ -#define USB_EP_DIR_OUT 0x00 - -/** - * \brief Maximum length in bytes of a USB descriptor - * - * The maximum length of a USB descriptor is limited by the 8-bit - * bLength field. - */ -#define USB_DESC_LEN_MAX 255 - -/* - * 2-byte alignment requested for all USB structures. - */ -COMPILER_PACK_SET(1) - -/** - * \brief A USB Device SETUP request - * - * The data payload of SETUP packets always follows this structure. - */ -typedef struct usb_req { - uint8_t bmRequestType; - uint8_t bRequest; - union { - le16_t wValue; - struct { - uint8_t l; - uint8_t h; - } wValueBytes; - }; - union { - le16_t wIndex; - struct { - uint8_t l; - uint8_t h; - } wIndexBytes; - }; - union { - le16_t wLength; - struct { - uint8_t l; - uint8_t h; - } wLengthBytes; - }; -} usb_req_t; - -/** - * \brief Standard USB device descriptor structure - */ -typedef struct usb_dev_desc { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - le16_t idVendor; - le16_t idProduct; - le16_t bcdDevice; - uint8_t iManufacturer; - uint8_t iProduct; - uint8_t iSerialNumber; - uint8_t bNumConfigurations; -} usb_dev_desc_t; - -/** - * \brief Binary device Object Store (BOS) descriptor structure - */ -typedef struct usb_bos_desc { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t wTotalLength; - uint8_t bNumDeviceCaps; -} usb_bos_desc_t; - -/** - * \brief Device Capability Descriptor structure - */ -typedef struct usb_cap_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; - uint8_t Vars[1]; -} usb_cap_desc_t; - -/** - * \brief USB 2.0 Extension Descriptor structure - */ -typedef struct usb_2_0_ext { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; - uint32_t bmAttributes; -} usb_2_0_ext_t; - -/** - * \brief LPM Device Capabilities descriptor structure - */ -typedef struct usb_2_0_ext usb_lpm_cap_desc_t; - -/** - * \brief SuperSpeed USB Device Capability structure - */ -typedef struct usb_ss_cap_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; - uint8_t bmAttributes; - le16_t wSpeedsSupported; - uint8_t bFunctionalitySupport; - uint8_t bU1DevExitLat; - uint8_t bU2DevExitLat; -} usb_ss_cap_desc_t; - -/** - * \brief USB Container ID Descriptor structure - */ -typedef struct usb_container_id_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; - uint8_t bReserved; - uint8_t ContainerID[16]; -} usb_container_id_desc_t; - -/** - * \brief Standard USB device qualifier descriptor structure - * - * This descriptor contains information about the device when running at - * the "other" speed (i.e. if the device is currently operating at high - * speed, this descriptor can be used to determine what would change if - * the device was operating at full speed.) - */ -typedef struct usb_dev_qual_desc { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint8_t bNumConfigurations; - uint8_t bReserved; -} usb_dev_qual_desc_t; - -/** - * \brief Standard USB configuration descriptor structure - */ -typedef struct usb_config_desc { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t wTotalLength; - uint8_t bNumInterfaces; - uint8_t bConfigurationValue; - uint8_t iConfiguration; - uint8_t bmAttributes; - uint8_t bMaxPower; -} usb_config_desc_t; - -#define USB_CONFIG_ATTR_MUST_SET (1 << 7) /*!< Must always be set */ -#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) /*!< Bus-powered */ -#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) /*!< Self-powered */ -#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) /*!< remote wakeup supported */ - -#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) /*!< Max power in mA */ - -/** - * \brief Standard USB association descriptor structure - */ -typedef struct usb_iad_desc { - uint8_t bLength; /*!< Size of this descriptor in bytes */ - uint8_t bDescriptorType; /*!< Interface descriptor type */ - uint8_t bFirstInterface; /*!< Number of interface */ - uint8_t bInterfaceCount; /*!< value to select alternate setting */ - uint8_t bFunctionClass; /*!< Class code assigned by the USB */ - uint8_t bFunctionSubClass; /*!< Sub-class code assigned by the USB */ - uint8_t bFunctionProtocol; /*!< Protocol code assigned by the USB */ - uint8_t iFunction; /*!< Index of string descriptor */ -} usb_iad_desc_t; - -/** - * \brief Standard USB interface descriptor structure - */ -typedef struct usb_iface_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; - uint8_t bNumEndpoints; - uint8_t bInterfaceClass; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; - uint8_t iInterface; -} usb_iface_desc_t; - -/** - * \brief Standard USB endpoint descriptor structure - */ -typedef struct usb_ep_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - le16_t wMaxPacketSize; - uint8_t bInterval; -} usb_ep_desc_t; - -/** - * \brief SuperSpeed Endpoint Companion descriptor structure - */ -typedef struct usb_ss_ep_comp_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bMaxBurst; - uint8_t bmAttributes; - le16_t wBytesPerInterval; -} usb_ss_ep_comp_desc_t; - -/** - * \brief LPM Token bmAttributes structure - */ -typedef struct usb_lpm_attributes { - uint8_t bLinkState : 4; - uint8_t HIRD : 4; - uint8_t bRemoteWake : 1; - uint8_t Reserved : 2; -} usb_lpm_attributes_t; - -/** - * \brief A standard USB string descriptor structure - */ -typedef struct usb_str_desc { - uint8_t bLength; - uint8_t bDescriptorType; -} usb_str_desc_t; - -typedef struct usb_str_langid_desc { - usb_str_desc_t desc; - le16_t string[1]; -} usb_str_langid_desc_t; - -COMPILER_PACK_RESET() - -/** \name Macros to build USB standard descriptors */ -/*@{*/ - -/** Build bytes for USB device descriptor. */ -#define USB_DEV_DESC_BYTES(bcdUSB, \ - bDeviceClass, \ - bDeviceSubClass, \ - bDeviceProtocol, \ - bMaxPacketSize0, \ - idVendor, \ - idProduct, \ - bcdDevice, \ - iManufacturer, \ - iProduct, \ - iSerialNumber, \ - bNumConfigurations) \ - 18, /* bLength */ \ - 0x01, /* bDescriptorType: DEVICE */ \ - LE_BYTE0(bcdUSB), LE_BYTE1(bcdUSB), bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0, \ - LE_BYTE0(idVendor), LE_BYTE1(idVendor), LE_BYTE0(idProduct), LE_BYTE1(idProduct), LE_BYTE0(bcdDevice), \ - LE_BYTE1(bcdDevice), iManufacturer, iProduct, iSerialNumber, bNumConfigurations - -#define USB_DEV_DESC_LEN 18 - -/** Build bytes for USB configuration descriptor. */ -#define USB_CONFIG_DESC_BYTES( \ - wTotalLength, bNumInterfaces, bConfigurationValue, iConfiguration, bmAttributes, bMaxPower) \ - 9, /* bLength */ \ - 0x02, /* bDescriptorType: CONFIGURATION */ \ - LE_BYTE0(wTotalLength), LE_BYTE1(wTotalLength), bNumInterfaces, bConfigurationValue, iConfiguration, \ - bmAttributes, bMaxPower - -#define USB_CONFIG_DESC_LEN 9 - -/** Build bytes for USB IAD descriptor. */ -#define USB_IAD_DESC_BYTES( \ - bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction) \ - 8, /* bLength */ \ - USB_DT_IAD, /* bDescriptorType */ \ - bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction - -#define USB_IAD_DESC_LEN 8 - -/** Build bytes for USB interface descriptor. */ -#define USB_IFACE_DESC_BYTES(bInterfaceNumber, \ - bAlternateSetting, \ - bNumEndpoints, \ - bInterfaceClass, \ - bInterfaceSubClass, \ - bInterfaceProtocol, \ - iInterface) \ - 9, /* bLength */ \ - 0x04, /* bDescriptorType: INTERFACE */ \ - bInterfaceNumber, bAlternateSetting, bNumEndpoints, bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, \ - iInterface - -#define USB_IFACE_DESC_LEN 9 - -/** Build bytes for USB endpoint descriptor. */ -#define USB_ENDP_DESC_BYTES(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ - 7, /* bLength */ \ - 0x05, /* bDescriptorType: ENDPOINT */ \ - bEndpointAddress, bmAttributes, LE_BYTE0(wMaxPacketSize), LE_BYTE1(wMaxPacketSize), bInterval - -#define USB_ENDP_DESC_LEN 7 - -/*@}*/ - -/** \brief Get a word (calculate by little endian 16-bit data) - * \param[in] ptr Byte pointer to the address to get data - * \return a 16-bit word - */ -static inline uint16_t usb_get_u16(const uint8_t *ptr) -{ - return (ptr[0] + (ptr[1] << 8)); -} - -/** \brief Get a double word (calculate by little endian 32-bit data) - * \param[in] ptr Byte pointer to the address to get data - * \return a 32-bit word - */ -static inline uint32_t usb_get_u32(const uint8_t *ptr) -{ - return (ptr[0] + (ptr[1] << 8) + (ptr[2] << 16) + (ptr[3] << 24)); -} - -/** \brief Get descriptor length - * \param[in] desc Byte pointer to the descriptor start address - * \return descriptor length - */ -static inline uint8_t usb_desc_len(const uint8_t *desc) -{ - return desc[0]; -} - -/** \brief Get descriptor type - * \param[in] desc Byte pointer to the descriptor start address - * \return descriptor type - */ -static inline uint8_t usb_desc_type(const uint8_t *desc) -{ - return desc[1]; -} - -/** \brief Get next USB descriptor - * \param[in] desc Byte pointer to the descriptor start address - * \return Byte pointer to the next descriptor - */ -static inline uint8_t *usb_desc_next(uint8_t *desc) -{ - return (desc + usb_desc_len(desc)); -} - -/** \brief Get idVendor of USB Device Descriptor - * \param[in] dev_desc Byte pointer to the descriptor start address - * \return 16-bit idVendor value - */ -static inline uint16_t usb_dev_desc_vid(const uint8_t *dev_desc) -{ - return usb_get_u16(dev_desc + 8); -} - -/** \brief Get idProduct of USB Device Descriptor - * \param[in] dev_desc Byte pointer to the descriptor start address - * \return 16-bit idProduct value - */ -static inline uint16_t usb_dev_desc_pid(const uint8_t *dev_desc) -{ - return usb_get_u16(dev_desc + 10); -} - -/** \brief Get wTotalLength of USB Configuration Descriptor - * \param[in] cfg_desc Byte pointer to the descriptor start address - * \return 16-bit total length of configuration list - */ -static inline uint16_t usb_cfg_desc_total_len(const uint8_t *cfg_desc) -{ - return usb_get_u16(cfg_desc + 2); -} - -/** \brief Get Next USB Descriptor After the Configuration Descriptors list - * \param[in] cfg_desc Byte pointer to the descriptor start address - * \return Byte pointer to descriptor after configuration end - */ -static inline uint8_t *usb_cfg_desc_next(uint8_t *cfg_desc) -{ - return (cfg_desc + usb_cfg_desc_total_len(cfg_desc)); -} - -/** \brief Find specific USB Descriptor by its type - * \param[in] desc Byte pointer to the descriptor start address - * \param[in] eof Byte pointer to the descriptor end address - * \param[in] type The descriptor type expected - * \return Pointer to the descriptor - * \retval NULL if not found - */ -uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type); - -/** Get interface descriptor next to the specified one (by interface number) - * \param[in] desc Byte pointer to the descriptor start address - * \param[in] eof Byte pointer to the descriptor end address - * \param[in] iface_n The interface number to check - * \return Pointer to the descriptor - * \retval >= eof if not found - */ -uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n); - -/** Find endpoint descriptor, breaks if interface descriptor detected - * \param[in] desc Byte pointer to the descriptor start address - * \param[in] eof Byte pointer to the descriptor end address - * \return Pointer to the descriptor - * \retval NULL if not found - */ -uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof); - -/** Find configuration descriptor by its configuration number - * \param[in] desc Byte pointer to the descriptor start address - * \param[in] eof Byte pointer to the descriptor end address - * \param[in] cfg_value The configure value expected - * \return Pointer to the descriptor - * \retval NULL if not found - */ -uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value); - -/** Find string descriptor by its index - * \param[in] desc Byte pointer to the descriptor start address - * \param[in] eof Byte pointer to the descriptor end address - * \param[in] str_index The string index expected - * \return Pointer to the descriptor - * \retval NULL if not found - */ -uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index); - -#ifdef __cplusplus -} -#endif - -/*! @} */ - -#endif /* _USB_PROTOCOL_H_ */ diff --git a/atmel-samd/asf4/samd21/usb_start.c b/atmel-samd/asf4/samd21/usb_start.c deleted file mode 100644 index 683392806..000000000 --- a/atmel-samd/asf4/samd21/usb_start.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file or main.c - * to avoid loosing it when reconfiguring. - */ -#include "atmel_start.h" -#include "usb_start.h" - -#define CONF_USB_MSC_MAX_LUN 0 - -static uint8_t multi_desc_bytes[] = { - /* Device descriptors and Configuration descriptors list. */ - COMPOSITE_DESCES_LS_FS, -}; - -static struct usbd_descriptors multi_desc = {multi_desc_bytes, multi_desc_bytes + sizeof(multi_desc_bytes)}; - -/** Ctrl endpoint buffer */ -static uint8_t ctrl_buffer[64]; - -void composite_device_init(void) -{ - /* usb stack init */ - usbdc_init(ctrl_buffer); - -/* usbdc_register_funcion inside */ -#if CONF_USB_COMPOSITE_CDC_ACM_EN - cdcdf_acm_init(); -#endif -#if CONF_USB_COMPOSITE_HID_MOUSE_EN - hiddf_mouse_init(); -#endif -#if CONF_USB_COMPOSITE_HID_KEYBOARD_EN - hiddf_keyboard_init(); -#endif -#if CONF_USB_COMPOSITE_MSC_EN - mscdf_init(CONF_USB_MSC_MAX_LUN); -#endif -} - -void composite_device_start(void) -{ - usbdc_start(&multi_desc); - usbdc_attach(); -} - -void composite_device_example(void) -{ - - /* Initialize */ - /* It's done with system init ... */ - - /* Before start do function related initializations */ - /* Add your code here ... */ - - /* Start device */ - composite_device_start(); - - /* Main loop */ - while (1) { - if (cdcdf_acm_is_enabled()) { - /* CDC ACM process*/ - } - if (hiddf_mouse_is_enabled()) { - /* HID Mouse process */ - } - if (hiddf_keyboard_is_enabled()) { - /* HID Keyboard process */ - }; - if (mscdf_is_enabled()) { - /* MSC process */ - } - } -} - -void usb_init(void) -{ - - composite_device_init(); -} diff --git a/atmel-samd/asf4/samd21/usb_start.h b/atmel-samd/asf4/samd21/usb_start.h deleted file mode 100644 index 912bf289c..000000000 --- a/atmel-samd/asf4/samd21/usb_start.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file or main.c - * to avoid loosing it when reconfiguring. - */ -#ifndef USB_DEVICE_MAIN_H -#define USB_DEVICE_MAIN_H - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -#include "cdcdf_acm.h" -#include "hiddf_mouse.h" -#include "hiddf_keyboard.h" -#include "hiddf_generic.h" -#include "mscdf.h" -#include "composite_desc.h" - -/** - * \brief Initialize device and attach functions - */ -void composite_device_init(void); -/** - * \brief Start the device - */ -void composite_device_start(void); -/** - * Example of using Composite Function. - * \note - * In this example, we will use a PC as a USB host: - * - Connect the DEBUG USB on XPLAINED board to PC for program download. - * - Connect the TARGET USB on XPLAINED board to PC for running program. - */ -void composite_device_example(void); - -/** - * \berif Initialize USB - */ -void usb_init(void); - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // USB_DEVICE_MAIN_H diff --git a/atmel-samd/asf4/samd51/CMSIS/Documentation/Core/html/index.html b/atmel-samd/asf4/samd51/CMSIS/Documentation/Core/html/index.html deleted file mode 100644 index 3e7503ea9..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Documentation/Core/html/index.html +++ /dev/null @@ -1,241 +0,0 @@ - - - - - -CMSIS-CORE: Overview - - - - - - - - - - - - - - -
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CMSIS-CORE -  Version 4.00 -
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CMSIS-CORE support for Cortex-M processor-based devices
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Overview
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CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

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  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
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  • System exception names to interface to system exceptions without having compatibility issues.
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  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
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  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
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  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
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  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
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This chapter provides details about the CMSIS-CORE and contains the following sections:

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CMSIS-CORE in ARM::CMSIS Pack

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Files relevant to CMSIS-CORE are present in the following ARM::CMSIS directories:

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File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Include CMSIS-CORE header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device ARM reference implementations of Cortex-M devices
Device\_Template_Vendor Template Files for extension by silicon vendors
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-Cortex-M Reference Manuals

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The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.

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Todo:
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-Tested and Verified Toolchains

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The CMSIS-CORE Template Files supplied by ARM have been tested and verified with the following toolchains:

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  • ARM: MDK-ARM Version 5.12
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  • GNU: GNU Tools ARM Embedded 4.8 2014.q3
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  • IAR: IAR Embedded Workbench Kickstart Edition V6.10
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Revision History of CMSIS-CORE

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Version Description
V4.00 Added: Cortex-M7 support.
- Added: intrinsic functions for __RRX, __LDRBT, __LDRHT, __LDRT, __STRBT, __STRHT, and __STRT
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V3.40 Corrected: C++ include guard settings.
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V3.30 Added: COSMIC tool chain support.
- Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.
- Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.
- Corrected: GCC/CLang warnings.
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V3.20 Added: __BKPT instruction intrinsic.
- Added: __SMMLA instruction intrinsic for Cortex-M4.
- Corrected: ITM_SendChar.
- Corrected: __enable_irq, __disable_irq and inline assembly for GCC Compiler.
- Corrected: NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000. Corrected: rework of in-line assembly functions to remove potential compiler warnings.
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V3.01 Added support for Cortex-M0+ processor.
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V3.00 Added support for GNU GCC ARM Embedded Compiler.
- Added function __ROR.
- Added Register Mapping for TPIU, DWT.
- Added support for SC000 and SC300 processors.
- Corrected ITM_SendChar function.
- Corrected the functions __STREXB, __STREXH, __STREXW for the GNU GCC compiler section.
- Documentation restructured.
V2.10 Updated documentation.
- Updated CMSIS core include files.
- Changed CMSIS/Device folder structure.
- Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.
- Reworked CMSIS DSP library examples.
V2.00 Added support for Cortex-M4 processor.
V1.30 Reworked Startup Concept.
- Added additional Debug Functionality.
- Changed folder structure.
- Added doxygen comments.
- Added definitions for bit.
V1.01 Added support for Cortex-M0 processor.
V1.01 Added intrinsic functions for __LDREXB, __LDREXH, __LDREXW, __STREXB, __STREXH, __STREXW, and __CLREX
V1.00 Initial Release for Cortex-M3 processor.
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- - - - diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/arm_common_tables.h b/atmel-samd/asf4/samd51/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 76aadca49..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 31. July 2014 -* $Revision: V1.4.4 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -//extern const q31_t realCoefAQ31[1024]; -//extern const q31_t realCoefBQ31[1024]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/arm_const_structs.h b/atmel-samd/asf4/samd51/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 217f1d50e..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 31. July 2014 -* $Revision: V1.4.4 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/arm_math.h b/atmel-samd/asf4/samd51/CMSIS/Include/arm_math.h deleted file mode 100644 index 49e23ee66..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7544 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 12. March 2014 -* $Revision: V1.4.4 -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 4.60. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvproj - * - * - * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2014 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY - #elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __ICCARM__ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t __packed -#elif defined __GNUC__ -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __CSMC__ /* Cosmic */ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t -#else -#error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) - -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) - -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ( - q31_t data); - - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + - ((q15_t) x * (q15_t) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } - - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); - -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in > 0) - { - -// #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - -//SMMLAR -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMLSR -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMULR -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -//SMMLA -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -//SMMLS -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) //Keil - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) //IAR - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - - #define LOW_OPTIMIZATION_EXIT - - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) // Cosmic - -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0.h deleted file mode 100644 index 5186cb483..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,711 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0plus.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index 17e43984f..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,822 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm3.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm3.h deleted file mode 100644 index e1357c673..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1650 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm4.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm4.h deleted file mode 100644 index 2ebde319d..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1806 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Warray-bounds" -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ - #pragma GCC diagnostic pop -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm7.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cm7.h deleted file mode 100644 index 242540f8b..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2221 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 01. September 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000 - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0 - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0 - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0 - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x07) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x07) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1]; - __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93]; - __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15]; - __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1]; - __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1]; - __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6]; - __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1]; - __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/* Cache Level ID register */ -#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* Cache Type register */ -#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ - -/* Cache Size ID Register */ -#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ - -/* Cache Size Selection Register */ -#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register */ -#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ - -/* Instruction Tightly-Coupled Memory Control Register*/ -#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Registers */ -#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register */ -#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register */ -#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ - -/* AHBS control register */ -#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register */ -#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## Cache functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) -#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) - - -/** \brief Enable I-Cache - - The function turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0; // invalidate I-Cache - SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache - __DSB(); - __ISB(); - #endif -} - - -/** \brief Disable I-Cache - - The function turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache - SCB->ICIALLU = 0; // invalidate I-Cache - __DSB(); - __ISB(); - #endif -} - - -/** \brief Invalidate I-Cache - - The function invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache(void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0; - __DSB(); - __ISB(); - #endif -} - - -/** \brief Enable D-Cache - - The function turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - __DSB(); - - SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Disable D-Cache - - The function turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache - - do { // clean & invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Invalidate D-Cache - - The function invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Clean D-Cache - - The function cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // clean D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCSW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Clean & Invalidate D-Cache - - The function cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache(void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; - - __DSB(); - - do { // clean & invalidate D-Cache - int32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cmFunc.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 01089f133..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,637 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.00 - * @date 28. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cmInstr.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index d14110b2a..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,880 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.00 - * @date 28. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_cmSimd.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_cmSimd.h deleted file mode 100644 index ee58eee56..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/core_cmSimd.h +++ /dev/null @@ -1,697 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* not yet supported */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_sc000.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_sc000.h deleted file mode 100644 index 5d0219c89..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,842 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000 - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1]; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154]; - __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/* SCB Security Features Register Definitions */ -#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ -#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ - -#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ -#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2]; - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/CMSIS/Include/core_sc300.h b/atmel-samd/asf4/samd51/CMSIS/Include/core_sc300.h deleted file mode 100644 index b6f6e8b5f..000000000 --- a/atmel-samd/asf4/samd51/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1630 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000 - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/atmel-samd/asf4/samd51/armcc/Makefile b/atmel-samd/asf4/samd51/armcc/Makefile deleted file mode 100644 index ff3779b49..000000000 --- a/atmel-samd/asf4/samd51/armcc/Makefile +++ /dev/null @@ -1,291 +0,0 @@ - -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -ifdef SystemRoot - SHELL = cmd.exe - MK_DIR = mkdir -else - ifeq ($(shell uname), Linux) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW32) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW64) - MK_DIR = mkdir -p - endif -endif - -# List the subdirectories for creating object files -SUB_DIRS += \ - \ -hpl/adc \ -usb/class/cdc/device \ -hpl/ramecc \ -hpl/evsys \ -examples \ -hpl/systick \ -hpl/oscctrl \ -hpl/tc \ -hpl/osc32kctrl \ -usb \ -hpl/dmac \ -hal/src \ -hal/utils/src \ -hpl/rtc \ -hpl/trng \ -usb/class/hid/device \ -hpl/usb \ -hpl/mclk \ -hpl/gclk \ -usb/device \ -hpl/pm \ -hpl/dac \ -hpl/sercom \ -hpl/nvmctrl \ -hpl/core \ -usb/class/msc/device - -# List the object files -OBJS += \ -hal/src/hal_io.o \ -hpl/systick/hpl_systick.o \ -usb/usb_protocol.o \ -usb/class/hid/device/hiddf_generic.o \ -hpl/evsys/hpl_evsys.o \ -hpl/core/hpl_core_m4.o \ -usb/class/cdc/device/cdcdf_acm.o \ -hpl/mclk/hpl_mclk.o \ -hpl/nvmctrl/hpl_nvmctrl.o \ -usb/class/msc/device/mscdf.o \ -hal/src/hal_spi_m_sync.o \ -hal/src/hal_timer.o \ -hal/src/hal_pwm.o \ -hpl/usb/hpl_usb.o \ -hal/src/hal_i2c_m_sync.o \ -hal/src/hal_delay.o \ -hpl/pm/hpl_pm.o \ -hpl/core/hpl_init.o \ -hpl/ramecc/hpl_ramecc.o \ -hal/utils/src/utils_list.o \ -usb/class/hid/device/hiddf_mouse.o \ -hal/utils/src/utils_assert.o \ -hpl/dmac/hpl_dmac.o \ -hpl/oscctrl/hpl_oscctrl.o \ -hal/src/hal_rand_sync.o \ -hpl/trng/hpl_trng.o \ -usb/class/hid/device/hiddf_keyboard.o \ -hal/src/hal_usart_sync.o \ -hpl/dac/hpl_dac.o \ -hpl/gclk/hpl_gclk.o \ -hal/src/hal_flash.o \ -hal/src/hal_init.o \ -hal/src/hal_usb_device.o \ -main.o \ -hpl/osc32kctrl/hpl_osc32kctrl.o \ -hpl/rtc/hpl_rtc.o \ -examples/driver_examples.o \ -driver_init.o \ -hal/src/hal_adc_sync.o \ -hal/src/hal_dac_sync.o \ -hpl/sercom/hpl_sercom.o \ -hal/src/hal_gpio.o \ -hal/src/hal_evsys.o \ -hal/utils/src/utils_event.o \ -hal/src/hal_sleep.o \ -usb_start.o \ -atmel_start.o \ -usb/device/usbdc.o \ -hpl/tc/hpl_tc.o \ -hal/src/hal_atomic.o \ -hpl/adc/hpl_adc.o - -OBJS_AS_ARGS += \ -"hal/src/hal_io.o" \ -"hpl/systick/hpl_systick.o" \ -"usb/usb_protocol.o" \ -"usb/class/hid/device/hiddf_generic.o" \ -"hpl/evsys/hpl_evsys.o" \ -"hpl/core/hpl_core_m4.o" \ -"usb/class/cdc/device/cdcdf_acm.o" \ -"hpl/mclk/hpl_mclk.o" \ -"hpl/nvmctrl/hpl_nvmctrl.o" \ -"usb/class/msc/device/mscdf.o" \ -"hal/src/hal_spi_m_sync.o" \ -"hal/src/hal_timer.o" \ -"hal/src/hal_pwm.o" \ -"hpl/usb/hpl_usb.o" \ -"hal/src/hal_i2c_m_sync.o" \ -"hal/src/hal_delay.o" \ -"hpl/pm/hpl_pm.o" \ -"hpl/core/hpl_init.o" \ -"hpl/ramecc/hpl_ramecc.o" \ -"hal/utils/src/utils_list.o" \ -"usb/class/hid/device/hiddf_mouse.o" \ -"hal/utils/src/utils_assert.o" \ -"hpl/dmac/hpl_dmac.o" \ -"hpl/oscctrl/hpl_oscctrl.o" \ -"hal/src/hal_rand_sync.o" \ -"hpl/trng/hpl_trng.o" \ -"usb/class/hid/device/hiddf_keyboard.o" \ -"hal/src/hal_usart_sync.o" \ -"hpl/dac/hpl_dac.o" \ -"hpl/gclk/hpl_gclk.o" \ -"hal/src/hal_flash.o" \ -"hal/src/hal_init.o" \ -"hal/src/hal_usb_device.o" \ -"main.o" \ -"hpl/osc32kctrl/hpl_osc32kctrl.o" \ -"hpl/rtc/hpl_rtc.o" \ -"examples/driver_examples.o" \ -"driver_init.o" \ -"hal/src/hal_adc_sync.o" \ -"hal/src/hal_dac_sync.o" \ -"hpl/sercom/hpl_sercom.o" \ -"hal/src/hal_gpio.o" \ -"hal/src/hal_evsys.o" \ -"hal/utils/src/utils_event.o" \ -"hal/src/hal_sleep.o" \ -"usb_start.o" \ -"atmel_start.o" \ -"usb/device/usbdc.o" \ -"hpl/tc/hpl_tc.o" \ -"hal/src/hal_atomic.o" \ -"hpl/adc/hpl_adc.o" - -# List the dependency files -DEPS := $(OBJS:%.o=%.d) - -DEPS_AS_ARGS += \ -"usb/usb_protocol.d" \ -"hal/utils/src/utils_event.d" \ -"hal/src/hal_io.d" \ -"hpl/ramecc/hpl_ramecc.d" \ -"hpl/systick/hpl_systick.d" \ -"hpl/core/hpl_core_m4.d" \ -"hpl/evsys/hpl_evsys.d" \ -"usb/class/cdc/device/cdcdf_acm.d" \ -"hal/src/hal_i2c_m_sync.d" \ -"hpl/usb/hpl_usb.d" \ -"hal/src/hal_evsys.d" \ -"usb/class/msc/device/mscdf.d" \ -"hpl/nvmctrl/hpl_nvmctrl.d" \ -"hal/src/hal_pwm.d" \ -"hal/src/hal_timer.d" \ -"hal/src/hal_spi_m_sync.d" \ -"usb/class/hid/device/hiddf_mouse.d" \ -"hal/utils/src/utils_list.d" \ -"hpl/dmac/hpl_dmac.d" \ -"hal/utils/src/utils_assert.d" \ -"hpl/mclk/hpl_mclk.d" \ -"hal/src/hal_delay.d" \ -"hpl/core/hpl_init.d" \ -"hpl/pm/hpl_pm.d" \ -"hal/src/hal_flash.d" \ -"hpl/gclk/hpl_gclk.d" \ -"hal/src/hal_usb_device.d" \ -"usb_start.d" \ -"hal/src/hal_init.d" \ -"hal/src/hal_usart_sync.d" \ -"usb/class/hid/device/hiddf_keyboard.d" \ -"hpl/trng/hpl_trng.d" \ -"hal/src/hal_rand_sync.d" \ -"hpl/dac/hpl_dac.d" \ -"driver_init.d" \ -"hal/src/hal_adc_sync.d" \ -"hpl/osc32kctrl/hpl_osc32kctrl.d" \ -"main.d" \ -"examples/driver_examples.d" \ -"hpl/rtc/hpl_rtc.d" \ -"hal/src/hal_sleep.d" \ -"hpl/sercom/hpl_sercom.d" \ -"hal/src/hal_dac_sync.d" \ -"hal/src/hal_gpio.d" \ -"usb/class/hid/device/hiddf_generic.d" \ -"hal/src/hal_atomic.d" \ -"hpl/tc/hpl_tc.d" \ -"usb/device/usbdc.d" \ -"hpl/oscctrl/hpl_oscctrl.d" \ -"hpl/adc/hpl_adc.d" \ -"atmel_start.d" - -OUTPUT_FILE_NAME :=AtmelStart -QUOTE := " -OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf -OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf - -vpath %.c ../ -vpath %.s ../ -vpath %.S ../ - -# All Target -all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) - -# Linker target - -$(OUTPUT_FILE_PATH): $(OBJS) - @echo Building target: $@ - @echo Invoking: ARMCC Linker - $(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \ ---strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \ ---info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \ --o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M4 \ -$(OBJS_AS_ARGS) - - @echo Finished building target: $@ - -# Compiler target(s) - - - - -%.o: %.c - @echo Building file: $< - @echo ARMCC Compiler - $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAMD51G19A__ \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ ---depend "$@" -o "$@" "$<" - - @echo Finished building: $< - -%.o: %.s - @echo Building file: $< - @echo ARMCC Assembler - $(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M4 --pd "D__SAMD51G19A__ SETA 1" \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ ---depend "$(@:%.o=%.d)" -o "$@" "$<" - - @echo Finished building: $< - -%.o: %.S - @echo Building file: $< - @echo ARMCC Preprocessing Assembler - $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAMD51G19A__ \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ ---depend "$@" -o "$@" "$<" - - @echo Finished building: $< - -# Detect changes in the dependent files and recompile the respective object files. -ifneq ($(MAKECMDGOALS),clean) -ifneq ($(strip $(DEPS)),) --include $(DEPS) -endif -endif - -$(SUB_DIRS): - $(MK_DIR) "$@" - -clean: - rm -f $(OBJS_AS_ARGS) - rm -f $(OUTPUT_FILE_PATH) - rm -f $(DEPS_AS_ARGS) - rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf diff --git a/atmel-samd/asf4/samd51/atmel_start.c b/atmel-samd/asf4/samd51/atmel_start.c deleted file mode 100644 index a075fcfa6..000000000 --- a/atmel-samd/asf4/samd51/atmel_start.c +++ /dev/null @@ -1,10 +0,0 @@ -#include - -/** - * Initializes MCU, drivers and middleware in the project -**/ -void atmel_start_init(void) -{ - system_init(); - usb_init(); -} diff --git a/atmel-samd/asf4/samd51/atmel_start.h b/atmel-samd/asf4/samd51/atmel_start.h deleted file mode 100644 index 71d54c217..000000000 --- a/atmel-samd/asf4/samd51/atmel_start.h +++ /dev/null @@ -1,19 +0,0 @@ -#ifndef ATMEL_START_H_INCLUDED -#define ATMEL_START_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include "driver_init.h" -#include "usb_start.h" - -/** - * Initializes MCU, drivers and middleware in the project -**/ -void atmel_start_init(void); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/atmel-samd/asf4/samd51/atmel_start_config.atstart b/atmel-samd/asf4/samd51/atmel_start_config.atstart deleted file mode 100644 index 7a706ff04..000000000 --- a/atmel-samd/asf4/samd51/atmel_start_config.atstart +++ /dev/null @@ -1,1716 +0,0 @@ -format_version: '2' -name: My Project -board: - identifier: CustomBoard - device: SAMD51G19A-MF -details: null -application: null -middlewares: - USB_CHAPTER_9: - user_label: USB_CHAPTER_9 - configuration: {} - definition: Atmel:USB:0.0.1::USB_Chapter_9 - functionality: USB_Chapter_9 - api: USB:Protocol:Core - dependencies: {} - USB_CLASS_HUB: - user_label: USB_CLASS_HUB - configuration: {} - definition: Atmel:USB:0.0.1::USB_Class_HUB - functionality: USB_Class_HUB - api: USB:Protocol:HUB - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB_CLASS_HID: - user_label: USB_CLASS_HID - configuration: {} - definition: Atmel:USB:0.0.1::USB_Class_HID - functionality: USB_Class_HID - api: USB:Protocol:HID - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB_CLASS_CDC: - user_label: USB_CLASS_CDC - configuration: {} - definition: Atmel:USB:0.0.1::USB_Class_CDC - functionality: USB_Class_CDC - api: USB:Protocol:CDC - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB_CLASS_MSC: - user_label: USB_CLASS_MSC - configuration: {} - definition: Atmel:USB:0.0.1::USB_Class_MSC - functionality: USB_Class_Mass_Storage_(MSC) - api: USB:Protocol:MSC - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB_CLASS_VENDOR: - user_label: USB_CLASS_VENDOR - configuration: {} - definition: Atmel:USB:0.0.1::USB_Class_VENDOR - functionality: USB_Class_VENDOR - api: USB:Protocol:VENDOR - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB_DEVICE_STACK_CORE_INSTANCE: - user_label: USB_DEVICE_STACK_CORE_INSTANCE - configuration: {} - definition: Atmel:USB:0.0.1::USB_Device_Core - functionality: USB_Device_Core - api: USB:Device:Core - dependencies: - USB Chapter 9: USB_CHAPTER_9 - USB Device instance: USB_DEVICE_INSTANCE - USB_DEVICE_COMPOSITE_0: - user_label: USB_DEVICE_COMPOSITE_0 - configuration: - conf_usb_composite_cdc_echo_demo: false - conf_usb_composite_hid_keyboard_demo: false - conf_usb_composite_hid_mouse_demo: false - conf_usb_msc_lun0_capacity: 22 - conf_usb_msc_lun0_enable: true - conf_usb_msc_lun0_rmb: true - conf_usb_msc_lun1_enable: false - conf_usb_msc_lun1_rmb: true - conf_usb_msc_lun_buf_sectors: 4 - usb_composite_bcddevice: 256 - usb_composite_bcdusb: USB 2.0 version - usb_composite_bconfigval: 1 - usb_composite_bmattri: Bus power supply, not support for remote wakeup - usb_composite_bmaxpksz0: 64 bytes - usb_composite_bmaxpower: 50 - usb_composite_bnumconfig: 1 - usb_composite_cdc_acm_comm_int_maxpksz: 64 bytes - usb_composite_cdc_acm_data_buckout_maxpksz: 64 bytes - usb_composite_cdc_acm_data_builin_maxpksz: 64 bytes - usb_composite_cdc_acm_data_bulkin_epaddr: EndpointAddress = 0x81 - usb_composite_cdc_acm_data_bulkout_epaddr: EndpointAddress = 0x01 - usb_composite_cdc_acm_epaddr: EndpointAddress = 0x82 - usb_composite_cdc_acm_support: false - usb_composite_hid_generic_intin_epaddr: EndpointAddress = 0x85 - usb_composite_hid_generic_intin_maxpksz: 64 bytes - usb_composite_hid_generic_intout_epaddr: EndpointAddress = 0x03 - usb_composite_hid_generic_intout_maxpksz: 64 bytes - usb_composite_hid_generic_support: false - usb_composite_hid_keyboard_intin_epaddr: EndpointAddress = 0x84 - usb_composite_hid_keyboard_intin_maxpksz: 8 bytes - usb_composite_hid_keyboard_intout_epaddr: EndpointAddress = 0x02 - usb_composite_hid_keyboard_intout_maxpksz: 8 bytes - usb_composite_hid_keyboard_support: false - usb_composite_hid_mouse_intin_epaddr: EndpointAddress = 0x83 - usb_composite_hid_mouse_intin_maxpksz: 8 bytes - usb_composite_hid_mouse_support: false - usb_composite_iconfig: 0 - usb_composite_idproduct: 9249 - usb_composite_idvender: 1003 - usb_composite_imanufact: 0 - usb_composite_iproduct: 0 - usb_composite_iserialnum: 0 - usb_composite_msc_bulk_maxpksz: 64 bytes - usb_composite_msc_bulkin_epaddr: EndpointAddress = 0x86 - usb_composite_msc_bulkout_epaddr: EndpointAddress = 0x04 - usb_composite_msc_demo_en: true - usb_composite_msc_support: false - definition: Atmel:USB:0.0.1::USB_Device_Composite - functionality: USB_Device_COMPOSITE - api: USB:Device:COMPOSITE - dependencies: - USB Class MSC: USB_CLASS_MSC - USB Class CDC: USB_CLASS_CDC - USB Device Stack Core Instance: USB_DEVICE_STACK_CORE_INSTANCE - USB Class VENDOR: USB_CLASS_VENDOR - USB Class HID: USB_CLASS_HID - USB Class HUB: USB_CLASS_HUB -drivers: - ADC_0: - user_label: ADC_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync - functionality: ADC - api: HAL:Driver:ADC_Sync - configuration: - adc_advanced_settings: false - adc_arch_adjres: 0 - adc_arch_corren: false - adc_arch_dbgrun: false - adc_arch_event_settings: false - adc_arch_flushei: false - adc_arch_flushinv: false - adc_arch_gaincorr: 0 - adc_arch_leftadj: false - adc_arch_offcomp: false - adc_arch_offsetcorr: 0 - adc_arch_ondemand: false - adc_arch_refcomp: false - adc_arch_resrdyeo: false - adc_arch_runstdby: false - adc_arch_samplen: 0 - adc_arch_samplenum: 1 sample - adc_arch_seqen: 0 - adc_arch_startei: false - adc_arch_startinv: false - adc_arch_winlt: 0 - adc_arch_winmode: No window mode - adc_arch_winmoneo: false - adc_arch_winut: 0 - adc_differential_mode: false - adc_freerunning_mode: false - adc_pinmux_negative: ADC AIN0 pin - adc_pinmux_positive: ADC AIN0 pin - adc_prescaler: Peripheral clock divided by 2 - adc_reference: Internal bandgap reference - adc_resolution: 12-bit - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: ADC - input: Generic clock generator 0 - configuration: - adc_gclk_selection: Generic clock generator 0 - DAC_0: - user_label: DAC_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::DAC::driver_config_definition::DAC::HAL:Driver:DAC.Sync - functionality: DAC - api: HAL:Driver:DAC_Sync - configuration: - adc_arch_dbgrun: true - dac0_arch_cctrl: GCLK_DAC <= 1.2MHz (100kSPS) - dac0_arch_ditrher: false - dac0_arch_leftadj: false - dac0_arch_refresh: 0 - dac0_arch_runstdby: false - dac1_arch_cctrl: GCLK_DAC <= 1.2MHz (100kSPS) - dac1_arch_ditrher: false - dac1_arch_leftadj: false - dac1_arch_refresh: 0 - dac1_arch_runstdby: false - dac_advanced_settings: false - dac_arch_diff: false - dac_arch_emptyeo_0: false - dac_arch_emptyeo_1: false - dac_arch_invei0: Detection on rising edge pf the input event - dac_arch_invei1: Detection on rising edge pf the input event - dac_arch_refsel: Unbuffered external voltage reference - dac_arch_startei_0: false - dac_arch_startei_1: false - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: DAC - input: Generic clock generator 0 - configuration: - dac_gclk_selection: Generic clock generator 0 - DMAC: - user_label: DMAC - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC - functionality: System - api: HAL:HPL:DMAC - configuration: - dmac_beatsize_0: 8-bit bus transfer - dmac_beatsize_1: 8-bit bus transfer - dmac_beatsize_10: 8-bit bus transfer - dmac_beatsize_11: 8-bit bus transfer - dmac_beatsize_12: 8-bit bus transfer - dmac_beatsize_13: 8-bit bus transfer - dmac_beatsize_14: 8-bit bus transfer - dmac_beatsize_15: 8-bit bus transfer - dmac_beatsize_16: 8-bit bus transfer - dmac_beatsize_17: 8-bit bus transfer - dmac_beatsize_18: 8-bit bus transfer - dmac_beatsize_19: 8-bit bus transfer - dmac_beatsize_2: 8-bit bus transfer - dmac_beatsize_20: 8-bit bus transfer - dmac_beatsize_21: 8-bit bus transfer - dmac_beatsize_22: 8-bit bus transfer - dmac_beatsize_23: 8-bit bus transfer - dmac_beatsize_24: 8-bit bus transfer - dmac_beatsize_25: 8-bit bus transfer - dmac_beatsize_26: 8-bit bus transfer - dmac_beatsize_27: 8-bit bus transfer - dmac_beatsize_28: 8-bit bus transfer - dmac_beatsize_29: 8-bit bus transfer - dmac_beatsize_3: 8-bit bus transfer - dmac_beatsize_30: 8-bit bus transfer - dmac_beatsize_31: 8-bit bus transfer - dmac_beatsize_4: 8-bit bus transfer - dmac_beatsize_5: 8-bit bus transfer - dmac_beatsize_6: 8-bit bus transfer - dmac_beatsize_7: 8-bit bus transfer - dmac_beatsize_8: 8-bit bus transfer - dmac_beatsize_9: 8-bit bus transfer - dmac_blockact_0: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_1: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_10: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_11: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_12: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_13: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_14: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_15: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_16: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_17: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_18: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_19: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_2: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_20: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_21: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_22: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_23: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_24: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_25: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_26: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_27: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_28: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_29: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_3: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_30: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_31: Channel will be disabled if it is the last block transfer - in the transaction - dmac_blockact_4: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_5: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_6: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_7: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_8: Channel will be disabled if it is the last block transfer in - the transaction - dmac_blockact_9: Channel will be disabled if it is the last block transfer in - the transaction - dmac_channel_0_settings: false - dmac_channel_10_settings: false - dmac_channel_11_settings: false - dmac_channel_12_settings: false - dmac_channel_13_settings: false - dmac_channel_14_settings: false - dmac_channel_15_settings: false - dmac_channel_16_settings: false - dmac_channel_17_settings: false - dmac_channel_18_settings: false - dmac_channel_19_settings: false - dmac_channel_1_settings: false - dmac_channel_20_settings: false - dmac_channel_21_settings: false - dmac_channel_22_settings: false - dmac_channel_23_settings: false - dmac_channel_24_settings: false - dmac_channel_25_settings: false - dmac_channel_26_settings: false - dmac_channel_27_settings: false - dmac_channel_28_settings: false - dmac_channel_29_settings: false - dmac_channel_2_settings: false - dmac_channel_30_settings: false - dmac_channel_31_settings: false - dmac_channel_3_settings: false - dmac_channel_4_settings: false - dmac_channel_5_settings: false - dmac_channel_6_settings: false - dmac_channel_7_settings: false - dmac_channel_8_settings: false - dmac_channel_9_settings: false - dmac_dbgrun: false - dmac_dstinc_0: false - dmac_dstinc_1: false - dmac_dstinc_10: false - dmac_dstinc_11: false - dmac_dstinc_12: false - dmac_dstinc_13: false - dmac_dstinc_14: false - dmac_dstinc_15: false - dmac_dstinc_16: false - dmac_dstinc_17: false - dmac_dstinc_18: false - dmac_dstinc_19: false - dmac_dstinc_2: false - dmac_dstinc_20: false - dmac_dstinc_21: false - dmac_dstinc_22: false - dmac_dstinc_23: false - dmac_dstinc_24: false - dmac_dstinc_25: false - dmac_dstinc_26: false - dmac_dstinc_27: false - dmac_dstinc_28: false - dmac_dstinc_29: false - dmac_dstinc_3: false - dmac_dstinc_30: false - dmac_dstinc_31: false - dmac_dstinc_4: false - dmac_dstinc_5: false - dmac_dstinc_6: false - dmac_dstinc_7: false - dmac_dstinc_8: false - dmac_dstinc_9: false - dmac_enable: false - dmac_evact_0: No action - dmac_evact_1: No action - dmac_evact_10: No action - dmac_evact_11: No action - dmac_evact_12: No action - dmac_evact_13: No action - dmac_evact_14: No action - dmac_evact_15: No action - dmac_evact_16: No action - dmac_evact_17: No action - dmac_evact_18: No action - dmac_evact_19: No action - dmac_evact_2: No action - dmac_evact_20: No action - dmac_evact_21: No action - dmac_evact_22: No action - dmac_evact_23: No action - dmac_evact_24: No action - dmac_evact_25: No action - dmac_evact_26: No action - dmac_evact_27: No action - dmac_evact_28: No action - dmac_evact_29: No action - dmac_evact_3: No action - dmac_evact_30: No action - dmac_evact_31: No action - dmac_evact_4: No action - dmac_evact_5: No action - dmac_evact_6: No action - dmac_evact_7: No action - dmac_evact_8: No action - dmac_evact_9: No action - dmac_evie_0: false - dmac_evie_1: false - dmac_evie_10: false - dmac_evie_11: false - dmac_evie_12: false - dmac_evie_13: false - dmac_evie_14: false - dmac_evie_15: false - dmac_evie_16: false - dmac_evie_17: false - dmac_evie_18: false - dmac_evie_19: false - dmac_evie_2: false - dmac_evie_20: false - dmac_evie_21: false - dmac_evie_22: false - dmac_evie_23: false - dmac_evie_24: false - dmac_evie_25: false - dmac_evie_26: false - dmac_evie_27: false - dmac_evie_28: false - dmac_evie_29: false - dmac_evie_3: false - dmac_evie_30: false - dmac_evie_31: false - dmac_evie_4: false - dmac_evie_5: false - dmac_evie_6: false - dmac_evie_7: false - dmac_evie_8: false - dmac_evie_9: false - dmac_evoe_0: false - dmac_evoe_1: false - dmac_evoe_10: false - dmac_evoe_11: false - dmac_evoe_12: false - dmac_evoe_13: false - dmac_evoe_14: false - dmac_evoe_15: false - dmac_evoe_16: false - dmac_evoe_17: false - dmac_evoe_18: false - dmac_evoe_19: false - dmac_evoe_2: false - dmac_evoe_20: false - dmac_evoe_21: false - dmac_evoe_22: false - dmac_evoe_23: false - dmac_evoe_24: false - dmac_evoe_25: false - dmac_evoe_26: false - dmac_evoe_27: false - dmac_evoe_28: false - dmac_evoe_29: false - dmac_evoe_3: false - dmac_evoe_30: false - dmac_evoe_31: false - dmac_evoe_4: false - dmac_evoe_5: false - dmac_evoe_6: false - dmac_evoe_7: false - dmac_evoe_8: false - dmac_evoe_9: false - dmac_evosel_0: Event generation disabled - dmac_evosel_1: Event generation disabled - dmac_evosel_10: Event generation disabled - dmac_evosel_11: Event generation disabled - dmac_evosel_12: Event generation disabled - dmac_evosel_13: Event generation disabled - dmac_evosel_14: Event generation disabled - dmac_evosel_15: Event generation disabled - dmac_evosel_16: Event generation disabled - dmac_evosel_17: Event generation disabled - dmac_evosel_18: Event generation disabled - dmac_evosel_19: Event generation disabled - dmac_evosel_2: Event generation disabled - dmac_evosel_20: Event generation disabled - dmac_evosel_21: Event generation disabled - dmac_evosel_22: Event generation disabled - dmac_evosel_23: Event generation disabled - dmac_evosel_24: Event generation disabled - dmac_evosel_25: Event generation disabled - dmac_evosel_26: Event generation disabled - dmac_evosel_27: Event generation disabled - dmac_evosel_28: Event generation disabled - dmac_evosel_29: Event generation disabled - dmac_evosel_3: Event generation disabled - dmac_evosel_30: Event generation disabled - dmac_evosel_31: Event generation disabled - dmac_evosel_4: Event generation disabled - dmac_evosel_5: Event generation disabled - dmac_evosel_6: Event generation disabled - dmac_evosel_7: Event generation disabled - dmac_evosel_8: Event generation disabled - dmac_evosel_9: Event generation disabled - dmac_lvl_0: Channel priority 0 - dmac_lvl_1: Channel priority 0 - dmac_lvl_10: Channel priority 0 - dmac_lvl_11: Channel priority 0 - dmac_lvl_12: Channel priority 0 - dmac_lvl_13: Channel priority 0 - dmac_lvl_14: Channel priority 0 - dmac_lvl_15: Channel priority 0 - dmac_lvl_16: Channel priority 0 - dmac_lvl_17: Channel priority 0 - dmac_lvl_18: Channel priority 0 - dmac_lvl_19: Channel priority 0 - dmac_lvl_2: Channel priority 0 - dmac_lvl_20: Channel priority 0 - dmac_lvl_21: Channel priority 0 - dmac_lvl_22: Channel priority 0 - dmac_lvl_23: Channel priority 0 - dmac_lvl_24: Channel priority 0 - dmac_lvl_25: Channel priority 0 - dmac_lvl_26: Channel priority 0 - dmac_lvl_27: Channel priority 0 - dmac_lvl_28: Channel priority 0 - dmac_lvl_29: Channel priority 0 - dmac_lvl_3: Channel priority 0 - dmac_lvl_30: Channel priority 0 - dmac_lvl_31: Channel priority 0 - dmac_lvl_4: Channel priority 0 - dmac_lvl_5: Channel priority 0 - dmac_lvl_6: Channel priority 0 - dmac_lvl_7: Channel priority 0 - dmac_lvl_8: Channel priority 0 - dmac_lvl_9: Channel priority 0 - dmac_lvlen0: true - dmac_lvlen1: true - dmac_lvlen2: true - dmac_lvlen3: true - dmac_lvlpri0: 0 - dmac_lvlpri1: 0 - dmac_lvlpri2: 0 - dmac_lvlpri3: 0 - dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 - dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 - dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 - dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 - dmac_runstdby_0: false - dmac_runstdby_1: false - dmac_runstdby_10: false - dmac_runstdby_11: false - dmac_runstdby_12: false - dmac_runstdby_13: false - dmac_runstdby_14: false - dmac_runstdby_15: false - dmac_runstdby_16: false - dmac_runstdby_17: false - dmac_runstdby_18: false - dmac_runstdby_19: false - dmac_runstdby_2: false - dmac_runstdby_20: false - dmac_runstdby_21: false - dmac_runstdby_22: false - dmac_runstdby_23: false - dmac_runstdby_24: false - dmac_runstdby_25: false - dmac_runstdby_26: false - dmac_runstdby_27: false - dmac_runstdby_28: false - dmac_runstdby_29: false - dmac_runstdby_3: false - dmac_runstdby_30: false - dmac_runstdby_31: false - dmac_runstdby_4: false - dmac_runstdby_5: false - dmac_runstdby_6: false - dmac_runstdby_7: false - dmac_runstdby_8: false - dmac_runstdby_9: false - dmac_srcinc_0: false - dmac_srcinc_1: false - dmac_srcinc_10: false - dmac_srcinc_11: false - dmac_srcinc_12: false - dmac_srcinc_13: false - dmac_srcinc_14: false - dmac_srcinc_15: false - dmac_srcinc_16: false - dmac_srcinc_17: false - dmac_srcinc_18: false - dmac_srcinc_19: false - dmac_srcinc_2: false - dmac_srcinc_20: false - dmac_srcinc_21: false - dmac_srcinc_22: false - dmac_srcinc_23: false - dmac_srcinc_24: false - dmac_srcinc_25: false - dmac_srcinc_26: false - dmac_srcinc_27: false - dmac_srcinc_28: false - dmac_srcinc_29: false - dmac_srcinc_3: false - dmac_srcinc_30: false - dmac_srcinc_31: false - dmac_srcinc_4: false - dmac_srcinc_5: false - dmac_srcinc_6: false - dmac_srcinc_7: false - dmac_srcinc_8: false - dmac_srcinc_9: false - dmac_stepsel_0: Step size settings apply to the destination address - dmac_stepsel_1: Step size settings apply to the destination address - dmac_stepsel_10: Step size settings apply to the destination address - dmac_stepsel_11: Step size settings apply to the destination address - dmac_stepsel_12: Step size settings apply to the destination address - dmac_stepsel_13: Step size settings apply to the destination address - dmac_stepsel_14: Step size settings apply to the destination address - dmac_stepsel_15: Step size settings apply to the destination address - dmac_stepsel_16: Step size settings apply to the destination address - dmac_stepsel_17: Step size settings apply to the destination address - dmac_stepsel_18: Step size settings apply to the destination address - dmac_stepsel_19: Step size settings apply to the destination address - dmac_stepsel_2: Step size settings apply to the destination address - dmac_stepsel_20: Step size settings apply to the destination address - dmac_stepsel_21: Step size settings apply to the destination address - dmac_stepsel_22: Step size settings apply to the destination address - dmac_stepsel_23: Step size settings apply to the destination address - dmac_stepsel_24: Step size settings apply to the destination address - dmac_stepsel_25: Step size settings apply to the destination address - dmac_stepsel_26: Step size settings apply to the destination address - dmac_stepsel_27: Step size settings apply to the destination address - dmac_stepsel_28: Step size settings apply to the destination address - dmac_stepsel_29: Step size settings apply to the destination address - dmac_stepsel_3: Step size settings apply to the destination address - dmac_stepsel_30: Step size settings apply to the destination address - dmac_stepsel_31: Step size settings apply to the destination address - dmac_stepsel_4: Step size settings apply to the destination address - dmac_stepsel_5: Step size settings apply to the destination address - dmac_stepsel_6: Step size settings apply to the destination address - dmac_stepsel_7: Step size settings apply to the destination address - dmac_stepsel_8: Step size settings apply to the destination address - dmac_stepsel_9: Step size settings apply to the destination address - dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 - dmac_trifsrc_0: Only software/event triggers - dmac_trifsrc_1: Only software/event triggers - dmac_trifsrc_10: Only software/event triggers - dmac_trifsrc_11: Only software/event triggers - dmac_trifsrc_12: Only software/event triggers - dmac_trifsrc_13: Only software/event triggers - dmac_trifsrc_14: Only software/event triggers - dmac_trifsrc_15: Only software/event triggers - dmac_trifsrc_16: Only software/event triggers - dmac_trifsrc_17: Only software/event triggers - dmac_trifsrc_18: Only software/event triggers - dmac_trifsrc_19: Only software/event triggers - dmac_trifsrc_2: Only software/event triggers - dmac_trifsrc_20: Only software/event triggers - dmac_trifsrc_21: Only software/event triggers - dmac_trifsrc_22: Only software/event triggers - dmac_trifsrc_23: Only software/event triggers - dmac_trifsrc_24: Only software/event triggers - dmac_trifsrc_25: Only software/event triggers - dmac_trifsrc_26: Only software/event triggers - dmac_trifsrc_27: Only software/event triggers - dmac_trifsrc_28: Only software/event triggers - dmac_trifsrc_29: Only software/event triggers - dmac_trifsrc_3: Only software/event triggers - dmac_trifsrc_30: Only software/event triggers - dmac_trifsrc_31: Only software/event triggers - dmac_trifsrc_4: Only software/event triggers - dmac_trifsrc_5: Only software/event triggers - dmac_trifsrc_6: Only software/event triggers - dmac_trifsrc_7: Only software/event triggers - dmac_trifsrc_8: Only software/event triggers - dmac_trifsrc_9: Only software/event triggers - dmac_trigact_0: One trigger required for each block transfer - dmac_trigact_1: One trigger required for each block transfer - dmac_trigact_10: One trigger required for each block transfer - dmac_trigact_11: One trigger required for each block transfer - dmac_trigact_12: One trigger required for each block transfer - dmac_trigact_13: One trigger required for each block transfer - dmac_trigact_14: One trigger required for each block transfer - dmac_trigact_15: One trigger required for each block transfer - dmac_trigact_16: One trigger required for each block transfer - dmac_trigact_17: One trigger required for each block transfer - dmac_trigact_18: One trigger required for each block transfer - dmac_trigact_19: One trigger required for each block transfer - dmac_trigact_2: One trigger required for each block transfer - dmac_trigact_20: One trigger required for each block transfer - dmac_trigact_21: One trigger required for each block transfer - dmac_trigact_22: One trigger required for each block transfer - dmac_trigact_23: One trigger required for each block transfer - dmac_trigact_24: One trigger required for each block transfer - dmac_trigact_25: One trigger required for each block transfer - dmac_trigact_26: One trigger required for each block transfer - dmac_trigact_27: One trigger required for each block transfer - dmac_trigact_28: One trigger required for each block transfer - dmac_trigact_29: One trigger required for each block transfer - dmac_trigact_3: One trigger required for each block transfer - dmac_trigact_30: One trigger required for each block transfer - dmac_trigact_31: One trigger required for each block transfer - dmac_trigact_4: One trigger required for each block transfer - dmac_trigact_5: One trigger required for each block transfer - dmac_trigact_6: One trigger required for each block transfer - dmac_trigact_7: One trigger required for each block transfer - dmac_trigact_8: One trigger required for each block transfer - dmac_trigact_9: One trigger required for each block transfer - optional_signals: [] - variant: null - clocks: - domain_group: null - EVENT_SYSTEM_0: - user_label: EVENT_SYSTEM_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::EVSYS::driver_config_definition::Event.System::HAL:Driver:Event.system - functionality: Event_System - api: HAL:Driver:Event_system - configuration: - evsys_channel_0: No channel output selected - evsys_channel_1: No channel output selected - evsys_channel_10: No channel output selected - evsys_channel_11: No channel output selected - evsys_channel_12: No channel output selected - evsys_channel_17: No channel output selected - evsys_channel_18: No channel output selected - evsys_channel_19: No channel output selected - evsys_channel_2: No channel output selected - evsys_channel_20: No channel output selected - evsys_channel_21: No channel output selected - evsys_channel_22: No channel output selected - evsys_channel_23: No channel output selected - evsys_channel_24: No channel output selected - evsys_channel_25: No channel output selected - evsys_channel_26: No channel output selected - evsys_channel_27: No channel output selected - evsys_channel_28: No channel output selected - evsys_channel_29: No channel output selected - evsys_channel_3: No channel output selected - evsys_channel_30: No channel output selected - evsys_channel_31: No channel output selected - evsys_channel_32: No channel output selected - evsys_channel_33: No channel output selected - evsys_channel_34: No channel output selected - evsys_channel_35: No channel output selected - evsys_channel_36: No channel output selected - evsys_channel_37: No channel output selected - evsys_channel_38: No channel output selected - evsys_channel_39: No channel output selected - evsys_channel_4: No channel output selected - evsys_channel_40: No channel output selected - evsys_channel_41: No channel output selected - evsys_channel_42: No channel output selected - evsys_channel_43: No channel output selected - evsys_channel_44: No channel output selected - evsys_channel_45: No channel output selected - evsys_channel_46: No channel output selected - evsys_channel_47: No channel output selected - evsys_channel_48: No channel output selected - evsys_channel_49: No channel output selected - evsys_channel_5: No channel output selected - evsys_channel_50: No channel output selected - evsys_channel_51: No channel output selected - evsys_channel_52: No channel output selected - evsys_channel_53: No channel output selected - evsys_channel_54: No channel output selected - evsys_channel_55: No channel output selected - evsys_channel_56: No channel output selected - evsys_channel_57: No channel output selected - evsys_channel_58: No channel output selected - evsys_channel_59: No channel output selected - evsys_channel_6: No channel output selected - evsys_channel_60: No channel output selected - evsys_channel_61: No channel output selected - evsys_channel_62: No channel output selected - evsys_channel_63: No channel output selected - evsys_channel_64: No channel output selected - evsys_channel_65: No channel output selected - evsys_channel_66: No channel output selected - evsys_channel_7: No channel output selected - evsys_channel_8: No channel output selected - evsys_channel_9: No channel output selected - evsys_channel_setting_0: false - evsys_channel_setting_1: false - evsys_channel_setting_10: false - evsys_channel_setting_11: false - evsys_channel_setting_12: false - evsys_channel_setting_13: false - evsys_channel_setting_14: false - evsys_channel_setting_15: false - evsys_channel_setting_16: false - evsys_channel_setting_17: false - evsys_channel_setting_18: false - evsys_channel_setting_19: false - evsys_channel_setting_2: false - evsys_channel_setting_20: false - evsys_channel_setting_21: false - evsys_channel_setting_22: false - evsys_channel_setting_23: false - evsys_channel_setting_24: false - evsys_channel_setting_25: false - evsys_channel_setting_26: false - evsys_channel_setting_27: false - evsys_channel_setting_28: false - evsys_channel_setting_29: false - evsys_channel_setting_3: false - evsys_channel_setting_30: false - evsys_channel_setting_31: false - evsys_channel_setting_4: false - evsys_channel_setting_5: false - evsys_channel_setting_6: false - evsys_channel_setting_7: false - evsys_channel_setting_8: false - evsys_channel_setting_9: false - evsys_edgsel_0: No event output when using the resynchronized or synchronous - path - evsys_edgsel_1: No event output when using the resynchronized or synchronous - path - evsys_edgsel_10: No event output when using the resynchronized or synchronous - path - evsys_edgsel_11: No event output when using the resynchronized or synchronous - path - evsys_edgsel_12: No event output when using the resynchronized or synchronous - path - evsys_edgsel_13: No event output when using the resynchronized or synchronous - path - evsys_edgsel_14: No event output when using the resynchronized or synchronous - path - evsys_edgsel_15: No event output when using the resynchronized or synchronous - path - evsys_edgsel_16: No event output when using the resynchronized or synchronous - path - evsys_edgsel_17: No event output when using the resynchronized or synchronous - path - evsys_edgsel_18: No event output when using the resynchronized or synchronous - path - evsys_edgsel_19: No event output when using the resynchronized or synchronous - path - evsys_edgsel_2: No event output when using the resynchronized or synchronous - path - evsys_edgsel_20: No event output when using the resynchronized or synchronous - path - evsys_edgsel_21: No event output when using the resynchronized or synchronous - path - evsys_edgsel_22: No event output when using the resynchronized or synchronous - path - evsys_edgsel_23: No event output when using the resynchronized or synchronous - path - evsys_edgsel_24: No event output when using the resynchronized or synchronous - path - evsys_edgsel_25: No event output when using the resynchronized or synchronous - path - evsys_edgsel_26: No event output when using the resynchronized or synchronous - path - evsys_edgsel_27: No event output when using the resynchronized or synchronous - path - evsys_edgsel_28: No event output when using the resynchronized or synchronous - path - evsys_edgsel_29: No event output when using the resynchronized or synchronous - path - evsys_edgsel_3: No event output when using the resynchronized or synchronous - path - evsys_edgsel_30: No event output when using the resynchronized or synchronous - path - evsys_edgsel_31: No event output when using the resynchronized or synchronous - path - evsys_edgsel_4: No event output when using the resynchronized or synchronous - path - evsys_edgsel_5: No event output when using the resynchronized or synchronous - path - evsys_edgsel_6: No event output when using the resynchronized or synchronous - path - evsys_edgsel_7: No event output when using the resynchronized or synchronous - path - evsys_edgsel_8: No event output when using the resynchronized or synchronous - path - evsys_edgsel_9: No event output when using the resynchronized or synchronous - path - evsys_evd_0: false - evsys_evd_1: false - evsys_evd_10: false - evsys_evd_11: false - evsys_evd_12: false - evsys_evd_13: false - evsys_evd_14: false - evsys_evd_15: false - evsys_evd_16: false - evsys_evd_17: false - evsys_evd_18: false - evsys_evd_19: false - evsys_evd_2: false - evsys_evd_20: false - evsys_evd_21: false - evsys_evd_22: false - evsys_evd_23: false - evsys_evd_24: false - evsys_evd_25: false - evsys_evd_26: false - evsys_evd_27: false - evsys_evd_28: false - evsys_evd_29: false - evsys_evd_3: false - evsys_evd_30: false - evsys_evd_31: false - evsys_evd_4: false - evsys_evd_5: false - evsys_evd_6: false - evsys_evd_7: false - evsys_evd_8: false - evsys_evd_9: false - evsys_evgen_0: No event generator - evsys_evgen_1: No event generator - evsys_evgen_10: No event generator - evsys_evgen_11: No event generator - evsys_evgen_12: No event generator - evsys_evgen_13: No event generator - evsys_evgen_14: No event generator - evsys_evgen_15: No event generator - evsys_evgen_16: No event generator - evsys_evgen_17: No event generator - evsys_evgen_18: No event generator - evsys_evgen_19: No event generator - evsys_evgen_2: No event generator - evsys_evgen_20: No event generator - evsys_evgen_21: No event generator - evsys_evgen_22: No event generator - evsys_evgen_23: No event generator - evsys_evgen_24: No event generator - evsys_evgen_25: No event generator - evsys_evgen_26: No event generator - evsys_evgen_27: No event generator - evsys_evgen_28: No event generator - evsys_evgen_29: No event generator - evsys_evgen_3: No event generator - evsys_evgen_30: No event generator - evsys_evgen_31: No event generator - evsys_evgen_4: No event generator - evsys_evgen_5: No event generator - evsys_evgen_6: No event generator - evsys_evgen_7: No event generator - evsys_evgen_8: No event generator - evsys_evgen_9: No event generator - evsys_ondemand_0: false - evsys_ondemand_1: false - evsys_ondemand_10: false - evsys_ondemand_11: false - evsys_ondemand_12: false - evsys_ondemand_13: false - evsys_ondemand_14: false - evsys_ondemand_15: false - evsys_ondemand_16: false - evsys_ondemand_17: false - evsys_ondemand_18: false - evsys_ondemand_19: false - evsys_ondemand_2: false - evsys_ondemand_20: false - evsys_ondemand_21: false - evsys_ondemand_22: false - evsys_ondemand_23: false - evsys_ondemand_24: false - evsys_ondemand_25: false - evsys_ondemand_26: false - evsys_ondemand_27: false - evsys_ondemand_28: false - evsys_ondemand_29: false - evsys_ondemand_3: false - evsys_ondemand_30: false - evsys_ondemand_31: false - evsys_ondemand_4: false - evsys_ondemand_5: false - evsys_ondemand_6: false - evsys_ondemand_7: false - evsys_ondemand_8: false - evsys_ondemand_9: false - evsys_ovr_0: false - evsys_ovr_1: false - evsys_ovr_10: false - evsys_ovr_11: false - evsys_ovr_12: false - evsys_ovr_13: false - evsys_ovr_14: false - evsys_ovr_15: false - evsys_ovr_16: false - evsys_ovr_17: false - evsys_ovr_18: false - evsys_ovr_19: false - evsys_ovr_2: false - evsys_ovr_20: false - evsys_ovr_21: false - evsys_ovr_22: false - evsys_ovr_23: false - evsys_ovr_24: false - evsys_ovr_25: false - evsys_ovr_26: false - evsys_ovr_27: false - evsys_ovr_28: false - evsys_ovr_29: false - evsys_ovr_3: false - evsys_ovr_30: false - evsys_ovr_31: false - evsys_ovr_4: false - evsys_ovr_5: false - evsys_ovr_6: false - evsys_ovr_7: false - evsys_ovr_8: false - evsys_ovr_9: false - evsys_path_0: Synchronous path - evsys_path_1: Synchronous path - evsys_path_10: Synchronous path - evsys_path_11: Synchronous path - evsys_path_12: Synchronous path - evsys_path_13: Synchronous path - evsys_path_14: Synchronous path - evsys_path_15: Synchronous path - evsys_path_16: Synchronous path - evsys_path_17: Synchronous path - evsys_path_18: Synchronous path - evsys_path_19: Synchronous path - evsys_path_2: Synchronous path - evsys_path_20: Synchronous path - evsys_path_21: Synchronous path - evsys_path_22: Synchronous path - evsys_path_23: Synchronous path - evsys_path_24: Synchronous path - evsys_path_25: Synchronous path - evsys_path_26: Synchronous path - evsys_path_27: Synchronous path - evsys_path_28: Synchronous path - evsys_path_29: Synchronous path - evsys_path_3: Synchronous path - evsys_path_30: Synchronous path - evsys_path_31: Synchronous path - evsys_path_4: Synchronous path - evsys_path_5: Synchronous path - evsys_path_6: Synchronous path - evsys_path_7: Synchronous path - evsys_path_8: Synchronous path - evsys_path_9: Synchronous path - evsys_runstdby_0: false - evsys_runstdby_1: false - evsys_runstdby_10: false - evsys_runstdby_11: false - evsys_runstdby_12: false - evsys_runstdby_13: false - evsys_runstdby_14: false - evsys_runstdby_15: false - evsys_runstdby_16: false - evsys_runstdby_17: false - evsys_runstdby_18: false - evsys_runstdby_19: false - evsys_runstdby_2: false - evsys_runstdby_20: false - evsys_runstdby_21: false - evsys_runstdby_22: false - evsys_runstdby_23: false - evsys_runstdby_24: false - evsys_runstdby_25: false - evsys_runstdby_26: false - evsys_runstdby_27: false - evsys_runstdby_28: false - evsys_runstdby_29: false - evsys_runstdby_3: false - evsys_runstdby_30: false - evsys_runstdby_31: false - evsys_runstdby_4: false - evsys_runstdby_5: false - evsys_runstdby_6: false - evsys_runstdby_7: false - evsys_runstdby_8: false - evsys_runstdby_9: false - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: Channel 0 - input: Generic clock generator 0 - - name: Channel 1 - input: Generic clock generator 0 - - name: Channel 2 - input: Generic clock generator 0 - - name: Channel 3 - input: Generic clock generator 0 - - name: Channel 4 - input: Generic clock generator 0 - - name: Channel 5 - input: Generic clock generator 0 - - name: Channel 6 - input: Generic clock generator 0 - - name: Channel 7 - input: Generic clock generator 0 - - name: Channel 8 - input: Generic clock generator 0 - - name: Channel 9 - input: Generic clock generator 0 - - name: Channel 10 - input: Generic clock generator 0 - - name: Channel 11 - input: Generic clock generator 0 - configuration: - evsys_clk_selection_0: Generic clock generator 0 - evsys_clk_selection_1: Generic clock generator 0 - evsys_clk_selection_10: Generic clock generator 0 - evsys_clk_selection_11: Generic clock generator 0 - evsys_clk_selection_2: Generic clock generator 0 - evsys_clk_selection_3: Generic clock generator 0 - evsys_clk_selection_4: Generic clock generator 0 - evsys_clk_selection_5: Generic clock generator 0 - evsys_clk_selection_6: Generic clock generator 0 - evsys_clk_selection_7: Generic clock generator 0 - evsys_clk_selection_8: Generic clock generator 0 - evsys_clk_selection_9: Generic clock generator 0 - GCLK: - user_label: GCLK - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK - functionality: System - api: HAL:HPL:GCLK - configuration: - enable_gclk_gen_0: true - enable_gclk_gen_1: false - enable_gclk_gen_10: false - enable_gclk_gen_11: false - enable_gclk_gen_2: false - enable_gclk_gen_3: false - enable_gclk_gen_4: false - enable_gclk_gen_5: false - enable_gclk_gen_6: false - enable_gclk_gen_7: false - enable_gclk_gen_8: false - enable_gclk_gen_9: false - gclk_arch_gen_0_enable: true - gclk_arch_gen_0_idc: false - gclk_arch_gen_0_oe: false - gclk_arch_gen_0_oov: false - gclk_arch_gen_0_runstdby: false - gclk_arch_gen_10_enable: false - gclk_arch_gen_10_idc: false - gclk_arch_gen_10_oe: false - gclk_arch_gen_10_oov: false - gclk_arch_gen_10_runstdby: false - gclk_arch_gen_11_enable: false - gclk_arch_gen_11_idc: false - gclk_arch_gen_11_oe: false - gclk_arch_gen_11_oov: false - gclk_arch_gen_11_runstdby: false - gclk_arch_gen_1_enable: false - gclk_arch_gen_1_idc: false - gclk_arch_gen_1_oe: false - gclk_arch_gen_1_oov: false - gclk_arch_gen_1_runstdby: false - gclk_arch_gen_2_enable: false - gclk_arch_gen_2_idc: false - gclk_arch_gen_2_oe: false - gclk_arch_gen_2_oov: false - gclk_arch_gen_2_runstdby: false - gclk_arch_gen_3_enable: false - gclk_arch_gen_3_idc: false - gclk_arch_gen_3_oe: false - gclk_arch_gen_3_oov: false - gclk_arch_gen_3_runstdby: false - gclk_arch_gen_4_enable: false - gclk_arch_gen_4_idc: false - gclk_arch_gen_4_oe: false - gclk_arch_gen_4_oov: false - gclk_arch_gen_4_runstdby: false - gclk_arch_gen_5_enable: false - gclk_arch_gen_5_idc: false - gclk_arch_gen_5_oe: false - gclk_arch_gen_5_oov: false - gclk_arch_gen_5_runstdby: false - gclk_arch_gen_6_enable: false - gclk_arch_gen_6_idc: false - gclk_arch_gen_6_oe: false - gclk_arch_gen_6_oov: false - gclk_arch_gen_6_runstdby: false - gclk_arch_gen_7_enable: false - gclk_arch_gen_7_idc: false - gclk_arch_gen_7_oe: false - gclk_arch_gen_7_oov: false - gclk_arch_gen_7_runstdby: false - gclk_arch_gen_8_enable: false - gclk_arch_gen_8_idc: false - gclk_arch_gen_8_oe: false - gclk_arch_gen_8_oov: false - gclk_arch_gen_8_runstdby: false - gclk_arch_gen_9_enable: false - gclk_arch_gen_9_idc: false - gclk_arch_gen_9_oe: false - gclk_arch_gen_9_oov: false - gclk_arch_gen_9_runstdby: false - gclk_gen_0_div: 1 - gclk_gen_0_div_sel: false - gclk_gen_0_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_10_div: 1 - gclk_gen_10_div_sel: false - gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_11_div: 1 - gclk_gen_11_div_sel: false - gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_1_div: 1 - gclk_gen_1_div_sel: false - gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) - gclk_gen_2_div: 1 - gclk_gen_2_div_sel: true - gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_3_div: 1 - gclk_gen_3_div_sel: false - gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) - gclk_gen_4_div: 1 - gclk_gen_4_div_sel: false - gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_5_div: 1 - gclk_gen_5_div_sel: false - gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_6_div: 1 - gclk_gen_6_div_sel: false - gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_7_div: 1 - gclk_gen_7_div_sel: false - gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_8_div: 1 - gclk_gen_8_div_sel: false - gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - gclk_gen_9_div: 1 - gclk_gen_9_div_sel: false - gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) - optional_signals: [] - variant: null - clocks: - domain_group: null - MCLK: - user_label: MCLK - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK - functionality: System - api: HAL:HPL:MCLK - configuration: - cpu_clock_source: Generic clock generator 0 - cpu_div: '1' - enable_cpu_clock: true - mclk_arch_bupdiv: Divide by 8 - mclk_arch_hsdiv: Divide by 1 - mclk_arch_lpdiv: Divide by 4 - nvm_wait_states: '0' - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: CPU - input: CPU - configuration: {} - FLASH_0: - user_label: FLASH_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::NVMCTRL::driver_config_definition::Flash::HAL:Driver:FLASH - functionality: Flash - api: HAL:Driver:FLASH - configuration: - nvm_arch_cache0: false - nvm_arch_cache1: false - nvm_arch_sleepprm: Wake On Access - optional_signals: [] - variant: null - clocks: - domain_group: null - OSC32KCTRL: - user_label: OSC32KCTRL - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL - functionality: System - api: HAL:HPL:OSC32KCTRL - configuration: - enable_osculp32k: true - enable_rtc_source: false - enable_xosc32k: false - osculp32k_calib: 0 - osculp32k_calib_enable: false - rtc_1khz_selection: true - rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) - xosc32k_arch_cfden: false - xosc32k_arch_cfdeo: false - xosc32k_arch_cgm: Standard mode - xosc32k_arch_en1k: false - xosc32k_arch_en32k: false - xosc32k_arch_enable: false - xosc32k_arch_ondemand: true - xosc32k_arch_runstdby: false - xosc32k_arch_startup: 62592us - xosc32k_arch_swben: false - xosc32k_arch_xtalen: false - optional_signals: [] - variant: null - clocks: - domain_group: null - OSCCTRL: - user_label: OSCCTRL - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL - functionality: System - api: HAL:HPL:OSCCTRL - configuration: - dfll_arch_bplckc: false - dfll_arch_calibration: false - dfll_arch_ccdis: false - dfll_arch_coarse: 31 - dfll_arch_cstep: 1 - dfll_arch_enable: false - dfll_arch_fine: 128 - dfll_arch_fstep: 1 - dfll_arch_llaw: false - dfll_arch_ondemand: false - dfll_arch_qldis: false - dfll_arch_runstdby: false - dfll_arch_stable: false - dfll_arch_usbcrm: false - dfll_arch_waitlock: true - dfll_mode: Open Loop Mode - dfll_mul: 0 - dfll_ref_clock: Generic clock generator 3 - enable_dfll: false - enable_fdpll0: false - enable_fdpll1: false - enable_xosc0: false - enable_xosc1: true - fdpll0_arch_dcoen: false - fdpll0_arch_enable: false - fdpll0_arch_filter: 0 - fdpll0_arch_lbypass: false - fdpll0_arch_ltime: No time-out, automatic lock - fdpll0_arch_ondemand: false - fdpll0_arch_refclk: XOSC32K clock reference - fdpll0_arch_runstdby: false - fdpll0_arch_wuf: false - fdpll0_clock_dcofilter: 0 - fdpll0_clock_div: 0 - fdpll0_ldr: 1463 - fdpll0_ldrfrac: 13 - fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) - fdpll1_arch_dcoen: false - fdpll1_arch_enable: false - fdpll1_arch_filter: 0 - fdpll1_arch_lbypass: false - fdpll1_arch_ltime: No time-out, automatic lock - fdpll1_arch_ondemand: false - fdpll1_arch_refclk: XOSC32K clock reference - fdpll1_arch_runstdby: false - fdpll1_arch_wuf: false - fdpll1_clock_dcofilter: 0 - fdpll1_clock_div: 0 - fdpll1_ldr: 1463 - fdpll1_ldrfrac: 13 - fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) - xosc0_arch_cfden: false - xosc0_arch_enable: false - xosc0_arch_enalc: false - xosc0_arch_lowbufgain: false - xosc0_arch_ondemand: false - xosc0_arch_runstdby: false - xosc0_arch_startup: 31us - xosc0_arch_swben: false - xosc0_arch_xtalen: false - xosc0_frequency: 12000000 - xosc1_arch_cfden: false - xosc1_arch_enable: true - xosc1_arch_enalc: false - xosc1_arch_lowbufgain: false - xosc1_arch_ondemand: false - xosc1_arch_runstdby: false - xosc1_arch_startup: 31us - xosc1_arch_swben: false - xosc1_arch_xtalen: true - xosc1_frequency: 12000000 - optional_signals: [] - variant: null - clocks: - domain_group: null - RAMECC: - user_label: RAMECC - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC - functionality: System - api: HAL:HPL:RAMECC - configuration: {} - optional_signals: [] - variant: null - clocks: - domain_group: null - TIMER_0: - user_label: TIMER_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::RTC::driver_config_definition::Timer::HAL:Driver:Timer - functionality: Timer - api: HAL:Driver:Timer - configuration: - rtc_arch_comp_val: 1 - rtc_arch_prescaler: OFF(Peripheral clock divided by 1) - rtc_cmpeo0: false - rtc_cmpeo1: false - rtc_event_control: false - rtc_ovfeo: false - rtc_pereo0: false - rtc_pereo1: false - rtc_pereo2: false - rtc_pereo3: false - rtc_pereo4: false - rtc_pereo5: false - rtc_pereo6: false - rtc_pereo7: false - rtc_tampereo: false - rtc_tampevei: false - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: RTC - input: RTC source - configuration: - rtc_clk_selection: RTC source - SPI_0: - user_label: SPI_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM0::driver_config_definition::SPI.Master::HAL:Driver:SPI.Master.Sync - functionality: SPI - api: HAL:Driver:SPI_Master_Sync - configuration: - spi_master_advanced: false - spi_master_arch_cpha: Sample input on leading edge - spi_master_arch_cpol: SCK is low when idle - spi_master_arch_dbgstop: Keep running - spi_master_arch_dord: MSB first - spi_master_arch_ibon: In data stream - spi_master_arch_runstdby: false - spi_master_baud_rate: 50000 - spi_master_character_size: 8 bits - spi_master_dummybyte: 511 - spi_master_rx_enable: true - optional_signals: [] - variant: - specification: TXPO=0, RXPO=2 - required_signals: - - name: SERCOM0/PAD/0 - pad: PA04 - label: MOSI - - name: SERCOM0/PAD/1 - pad: PA05 - label: SCK - - name: SERCOM0/PAD/2 - pad: PA06 - label: MISO - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - - name: Slow - input: Generic clock generator 3 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 - USART_0: - user_label: USART_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM1::driver_config_definition::UART::HAL:Driver:USART.Sync - functionality: USART - api: HAL:Driver:USART_Sync - configuration: - usart_advanced: false - usart_arch_clock_mode: USART with internal clock - usart_arch_cloden: false - usart_arch_dbgstop: Keep running - usart_arch_dord: LSB is transmitted first - usart_arch_enc: No encoding - usart_arch_fractional: 0 - usart_arch_ibon: false - usart_arch_runstdby: false - usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) - usart_arch_sampr: 16x arithmetic - usart_arch_sfde: false - usart_baud_rate: 9600 - usart_character_size: 8 bits - usart_parity: No parity - usart_rx_enable: true - usart_stop_bit: One stop bit - usart_tx_enable: true - optional_signals: [] - variant: - specification: TXPO=0, RXPO=1, CMODE=0 - required_signals: - - name: SERCOM1/PAD/0 - pad: PA00 - label: TX - - name: SERCOM1/PAD/1 - pad: PA01 - label: RX - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - - name: Slow - input: Generic clock generator 3 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 - I2C_0: - user_label: I2C_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SERCOM2::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync - functionality: I2C - api: HAL:Driver:I2C_Master_Sync - configuration: - i2c_master_advanced: false - i2c_master_arch_dbgstop: Keep running - i2c_master_arch_inactout: Disabled - i2c_master_arch_lowtout: false - i2c_master_arch_mexttoen: false - i2c_master_arch_runstdby: false - i2c_master_arch_sdahold: 300-600ns hold time - i2c_master_arch_sexttoen: false - i2c_master_arch_trise: 215 - i2c_master_baud_rate: 100000 - optional_signals: [] - variant: - specification: SDA=0, SCL=1 - required_signals: - - name: SERCOM2/PAD/0 - pad: PA09 - label: SDA - - name: SERCOM2/PAD/1 - pad: PA08 - label: SCL - clocks: - domain_group: - nodes: - - name: Core - input: Generic clock generator 0 - - name: Slow - input: Generic clock generator 3 - configuration: - core_gclk_selection: Generic clock generator 0 - slow_gclk_selection: Generic clock generator 3 - DELAY_0: - user_label: DELAY_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::SysTick::driver_config_definition::Delay::HAL:Driver:Delay - functionality: Delay - api: HAL:Driver:Delay - configuration: - systick_arch_tickint: false - optional_signals: [] - variant: null - clocks: - domain_group: null - PWM_0: - user_label: PWM_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::TC0::driver_config_definition::PWM::HAL:Driver:PWM - functionality: PWM - api: HAL:Driver:PWM - configuration: - tc_arch_alock: The Lock Update bit is not affected on overflow/underflow and - re-trigger event - tc_arch_dbgrun: false - tc_arch_evact: Event action disabled - tc_arch_mceo0: false - tc_arch_mceo1: false - tc_arch_ondemand: false - tc_arch_ovfeo: false - tc_arch_presync: Reload or reset counter on next GCLK - tc_arch_runstdby: false - tc_arch_tcei: false - tc_arch_tcinv: false - tc_arch_wave_duty_val: 500 - tc_arch_wave_per_val: 1000 - tc_mode: Counter in 16-bit mode - tc_per: 50 - tc_prescaler: No division - timer_event_control: false - optional_signals: [] - variant: null - clocks: - domain_group: - nodes: - - name: TC - input: Generic clock generator 0 - configuration: - tc_gclk_selection: Generic clock generator 0 - RAND_0: - user_label: RAND_0 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::TRNG::driver_config_definition::RAND::HAL:Driver:RAND.Sync - functionality: RAND - api: HAL:Driver:RAND_Sync - configuration: - trng_datardyeo: false - trng_runstdby: false - optional_signals: [] - variant: null - clocks: - domain_group: null - USB_DEVICE_INSTANCE: - user_label: USB_DEVICE_INSTANCE - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::USB::driver_config_definition::USB.Device::HAL:Driver:USB.Device - functionality: USB - api: HAL:Driver:USB_Device - configuration: - usb_arch_ep0_cache: Cached by 64 bytes buffer - usb_arch_ep1_cache: Cached by 64 bytes buffer - usb_arch_ep2_cache: Cached by 64 bytes buffer - usb_arch_ep3_cache: Cached by 64 bytes buffer - usb_arch_ep4_cache: Cached by 64 bytes buffer - usb_arch_ep5_cache: Cached by 64 bytes buffer - usb_arch_ep6_cache: Cached by 64 bytes buffer - usb_arch_ep7_cache: Cached by 64 bytes buffer - usb_ep1_I_CACHE: No cache - usb_ep2_I_CACHE: No cache - usb_ep3_I_CACHE: No cache - usb_ep4_I_CACHE: No cache - usb_ep5_I_CACHE: No cache - usb_ep6_I_CACHE: No cache - usb_ep7_I_CACHE: No cache - usbd_arch_max_ep_n: 2 (EP 0x82 or 0x02) - usbd_arch_speed: Full speed - usbd_num_ep_sp: 4 (EP0 + 3 endpoints) - optional_signals: [] - variant: - specification: default - required_signals: - - name: USB/DM - pad: PA24 - label: Data- - - name: USB/DP - pad: PA25 - label: Data+ - clocks: - domain_group: - nodes: - - name: USB - input: Generic clock generator 0 - configuration: - usb_gclk_selection: Generic clock generator 0 -pads: - PA00: - name: PA00 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA00 - mode: Peripheral IO - user_label: PA00 - configuration: null - PA01: - name: PA01 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA01 - mode: Peripheral IO - user_label: PA01 - configuration: null - PA04: - name: PA04 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA04 - mode: Digital output - user_label: PA04 - configuration: null - PA05: - name: PA05 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA05 - mode: Digital output - user_label: PA05 - configuration: null - PA06: - name: PA06 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA06 - mode: Digital input - user_label: PA06 - configuration: null - PA08: - name: PA08 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA08 - mode: I2C - user_label: PA08 - configuration: null - PA09: - name: PA09 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA09 - mode: I2C - user_label: PA09 - configuration: null - PA24: - name: PA24 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA24 - mode: Advanced - user_label: PA24 - configuration: null - PA25: - name: PA25 - definition: Atmel:SAMD51_Drivers:0.0.1::SAMD51G19A-MF::pad::PA25 - mode: Advanced - user_label: PA25 - configuration: null -toolchain_options: [] diff --git a/atmel-samd/asf4/samd51/atmel_start_pins.h b/atmel-samd/asf4/samd51/atmel_start_pins.h deleted file mode 100644 index edfe88877..000000000 --- a/atmel-samd/asf4/samd51/atmel_start_pins.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef ATMEL_START_PINS_H_INCLUDED -#define ATMEL_START_PINS_H_INCLUDED - -#include - -// SAMD51 has 14 pin functions - -#define GPIO_PIN_FUNCTION_A 0 -#define GPIO_PIN_FUNCTION_B 1 -#define GPIO_PIN_FUNCTION_C 2 -#define GPIO_PIN_FUNCTION_D 3 -#define GPIO_PIN_FUNCTION_E 4 -#define GPIO_PIN_FUNCTION_F 5 -#define GPIO_PIN_FUNCTION_G 6 -#define GPIO_PIN_FUNCTION_H 7 -#define GPIO_PIN_FUNCTION_I 8 -#define GPIO_PIN_FUNCTION_J 9 -#define GPIO_PIN_FUNCTION_K 10 -#define GPIO_PIN_FUNCTION_L 11 -#define GPIO_PIN_FUNCTION_M 12 -#define GPIO_PIN_FUNCTION_N 13 - -#define PA00 GPIO(GPIO_PORTA, 0) -#define PA01 GPIO(GPIO_PORTA, 1) -#define PA04 GPIO(GPIO_PORTA, 4) -#define PA05 GPIO(GPIO_PORTA, 5) -#define PA06 GPIO(GPIO_PORTA, 6) -#define PA08 GPIO(GPIO_PORTA, 8) -#define PA09 GPIO(GPIO_PORTA, 9) -#define PA24 GPIO(GPIO_PORTA, 24) -#define PA25 GPIO(GPIO_PORTA, 25) - -#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/atmel-samd/asf4/samd51/config/hpl_adc_config.h b/atmel-samd/asf4/samd51/config/hpl_adc_config.h deleted file mode 100644 index 941c3ffdb..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_adc_config.h +++ /dev/null @@ -1,303 +0,0 @@ -/* Auto-generated config file hpl_adc_config.h */ -#ifndef HPL_ADC_CONFIG_H -#define HPL_ADC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#ifndef CONF_ADC_0_ENABLE -#define CONF_ADC_0_ENABLE 1 -#endif - -// Basic Configuration - -// Conversion Result Resolution -// <0x0=>12-bit -// <0x1=>16-bit (averaging must be enabled) -// <0x2=>10-bit -// <0x3=>8-bit -// Defines the bit resolution for the ADC sample values (RESSEL) -// adc_resolution -#ifndef CONF_ADC_0_RESSEL -#define CONF_ADC_0_RESSEL 0x0 -#endif - -// Reference Selection -// <0x0=>Internal bandgap reference -// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V) -// <0x3=>VDDANA -// <0x4=>External reference A -// <0x5=>External reference B -// <0x6=>External reference C -// Select the reference for the ADC (REFSEL) -// adc_reference -#ifndef CONF_ADC_0_REFSEL -#define CONF_ADC_0_REFSEL 0x0 -#endif - -// Prescaler configuration -// <0x0=>Peripheral clock divided by 2 -// <0x1=>Peripheral clock divided by 4 -// <0x2=>Peripheral clock divided by 8 -// <0x3=>Peripheral clock divided by 16 -// <0x4=>Peripheral clock divided by 32 -// <0x5=>Peripheral clock divided by 64 -// <0x6=>Peripheral clock divided by 128 -// <0x7=>Peripheral clock divided by 256 -// These bits define the ADC clock relative to the peripheral clock (PRESCALER) -// adc_prescaler -#ifndef CONF_ADC_0_PRESCALER -#define CONF_ADC_0_PRESCALER 0x0 -#endif - -// Free Running Mode -// When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN) -// adc_freerunning_mode -#ifndef CONF_ADC_0_FREERUN -#define CONF_ADC_0_FREERUN 0 -#endif - -// Differential Mode -// In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE) -// adc_differential_mode -#ifndef CONF_ADC_0_DIFFMODE -#define CONF_ADC_0_DIFFMODE 0 -#endif - -// Positive Mux Input Selection -// <0x00=>ADC AIN0 pin -// <0x01=>ADC AIN1 pin -// <0x02=>ADC AIN2 pin -// <0x03=>ADC AIN3 pin -// <0x04=>ADC AIN4 pin -// <0x05=>ADC AIN5 pin -// <0x06=>ADC AIN6 pin -// <0x07=>ADC AIN7 pin -// <0x08=>ADC AIN8 pin -// <0x09=>ADC AIN9 pin -// <0x0A=>ADC AIN10 pin -// <0x0B=>ADC AIN11 pin -// <0x0C=>ADC AIN12 pin -// <0x0D=>ADC AIN13 pin -// <0x0E=>ADC AIN14 pin -// <0x0F=>ADC AIN15 pin -// <0x18=>1/4 scaled core supply -// <0x19=>1/4 Scaled VBAT Supply -// <0x1A=>1/4 scaled I/O supply -// <0x1B=>Bandgap voltage -// <0x1C=>Temperature reference (PTAT) -// <0x1D=>Temperature reference (CTAT) -// <0x1E=>DAC Output -// These bits define the Mux selection for the positive ADC input. (MUXPOS) -// adc_pinmux_positive -#ifndef CONF_ADC_0_MUXPOS -#define CONF_ADC_0_MUXPOS 0x0 -#endif - -// Negative Mux Input Selection -// <0x00=>ADC AIN0 pin -// <0x01=>ADC AIN1 pin -// <0x02=>ADC AIN2 pin -// <0x03=>ADC AIN3 pin -// <0x04=>ADC AIN4 pin -// <0x05=>ADC AIN5 pin -// <0x06=>ADC AIN6 pin -// <0x07=>ADC AIN7 pin -// <0x18=>Internal ground -// <0x19=>I/O ground -// These bits define the Mux selection for the negative ADC input. (MUXNEG) -// adc_pinmux_negative -#ifndef CONF_ADC_0_MUXNEG -#define CONF_ADC_0_MUXNEG 0x0 -#endif - -// - -// Advanced Configuration -// adc_advanced_settings -#ifndef CONF_ADC_0_ADVANCED -#define CONF_ADC_0_ADVANCED 0 -#endif - -// Run in standby -// Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY) -// adc_arch_runstdby -#ifndef CONF_ADC_0_RUNSTDBY -#define CONF_ADC_0_RUNSTDBY 0 -#endif - -// Debug Run -// If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN) -// adc_arch_dbgrun -#ifndef CONF_ADC_0_DBGRUN -#define CONF_ADC_0_DBGRUN 0 -#endif - -// On Demand Control -// Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND) -// adc_arch_ondemand -#ifndef CONF_ADC_0_ONDEMAND -#define CONF_ADC_0_ONDEMAND 0 -#endif - -// Left-Adjusted Result -// When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ) -// adc_arch_leftadj -#ifndef CONF_ADC_0_LEFTADJ -#define CONF_ADC_0_LEFTADJ 0 -#endif - -// Reference Buffer Offset Compensation Enable -// The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP) -// adc_arch_refcomp -#ifndef CONF_ADC_0_REFCOMP -#define CONF_ADC_0_REFCOMP 0 -#endif - -// Comparator Offset Compensation Enable -// This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP) -// adc_arch_offcomp -#ifndef CONF_ADC_0_OFFCOMP -#define CONF_ADC_0_OFFCOMP 0 -#endif - -// Digital Correction Logic Enabled -// When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN) -// adc_arch_corren -#ifndef CONF_ADC_0_CORREN -#define CONF_ADC_0_CORREN 0 -#endif - -// Offset Correction Value <0-4095> -// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR) -// adc_arch_offsetcorr -#ifndef CONF_ADC_0_OFFSETCORR -#define CONF_ADC_0_OFFSETCORR 0 -#endif - -// Gain Correction Value <0-4095> -// If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR) -// adc_arch_gaincorr -#ifndef CONF_ADC_0_GAINCORR -#define CONF_ADC_0_GAINCORR 0 -#endif - -// Adjusting Result / Division Coefficient <0-7> -// These bits define the division coefficient in 2n steps. (ADJRES) -// adc_arch_adjres -#ifndef CONF_ADC_0_ADJRES -#define CONF_ADC_0_ADJRES 0x0 -#endif - -// Number of Samples to be Collected -// <0x0=>1 sample -// <0x1=>2 samples -// <0x2=>4 samples -// <0x3=>8 samples -// <0x4=>16 samples -// <0x5=>32 samples -// <0x6=>64 samples -// <0x7=>128 samples -// <0x8=>256 samples -// <0x9=>512 samples -// <0xA=>1024 samples -// Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM) -// adc_arch_samplenum -#ifndef CONF_ADC_0_SAMPLENUM -#define CONF_ADC_0_SAMPLENUM 0x0 -#endif - -// Sampling Time Length <0-63> -// These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN) -// adc_arch_samplen -#ifndef CONF_ADC_0_SAMPLEN -#define CONF_ADC_0_SAMPLEN 0 -#endif - -// Window Monitor Mode -// <0x0=>No window mode -// <0x1=>Mode 1: RESULT above lower threshold -// <0x2=>Mode 2: RESULT beneath upper threshold -// <0x3=>Mode 3: RESULT inside lower and upper threshold -// <0x4=>Mode 4: RESULT outside lower and upper threshold -// These bits enable and define the window monitor mode. (WINMODE) -// adc_arch_winmode -#ifndef CONF_ADC_0_WINMODE -#define CONF_ADC_0_WINMODE 0x0 -#endif - -// Window Monitor Lower Threshold <0-65535> -// If the window monitor is enabled, these bits define the lower threshold value. (WINLT) -// adc_arch_winlt -#ifndef CONF_ADC_0_WINLT -#define CONF_ADC_0_WINLT 0 -#endif - -// Window Monitor Upper Threshold <0-65535> -// If the window monitor is enabled, these bits define the lower threshold value. (WINUT) -// adc_arch_winut -#ifndef CONF_ADC_0_WINUT -#define CONF_ADC_0_WINUT 0 -#endif - -// Bitmask for positive input sequence <0-524288> -// Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device). -// adc_arch_seqen -#ifndef CONF_ADC_0_SEQEN -#define CONF_ADC_0_SEQEN 0x0 -#endif - -// - -// Event Control -// adc_arch_event_settings -#ifndef CONF_ADC_0_EVENT_CONTROL -#define CONF_ADC_0_EVENT_CONTROL 0 -#endif - -// Window Monitor Event Out -// Enables event output on window event (WINMONEO) -// adc_arch_winmoneo -#ifndef CONF_ADC_0_WINMONEO -#define CONF_ADC_0_WINMONEO 0 -#endif - -// Result Ready Event Out -// Enables event output on result ready event (RESRDEO) -// adc_arch_resrdyeo -#ifndef CONF_ADC_0_RESRDYEO -#define CONF_ADC_0_RESRDYEO 0 -#endif - -// Invert flush Event Signal -// Invert the flush event input signal (FLUSHINV) -// adc_arch_flushinv -#ifndef CONF_ADC_0_FLUSHINV -#define CONF_ADC_0_FLUSHINV 0 -#endif - -// Trigger Flush On Event -// Trigger an ADC pipeline flush on event (FLUSHEI) -// adc_arch_flushei -#ifndef CONF_ADC_0_FLUSHEI -#define CONF_ADC_0_FLUSHEI 0 -#endif - -// Invert Start Conversion Event Signal -// Invert the start conversion event input signal (STARTINV) -// adc_arch_startinv -#ifndef CONF_ADC_0_STARTINV -#define CONF_ADC_0_STARTINV 0 -#endif - -// Trigger Conversion On Event -// Trigger a conversion on event. (STARTEI) -// adc_arch_startei -#ifndef CONF_ADC_0_STARTEI -#define CONF_ADC_0_STARTEI 0 -#endif - -// - -// <<< end of configuration section >>> - -#endif // HPL_ADC_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_dac_config.h b/atmel-samd/asf4/samd51/config/hpl_dac_config.h deleted file mode 100644 index 24a8a116c..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_dac_config.h +++ /dev/null @@ -1,169 +0,0 @@ -/* Auto-generated config file hpl_dac_config.h */ -#ifndef HPL_DAC_CONFIG_H -#define HPL_DAC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic configuration -// Reference Selection -// <0x00=> Unbuffered external voltage reference -// <0x01=> Voltage supply -// <0x02=> Buffered external voltage reference -// <0x03=> Internal bandgap reference -// dac_arch_refsel -#ifndef CONF_DAC_REFSEL -#define CONF_DAC_REFSEL 0 -#endif - -// Differential mode -// Indicates whether the differential mode is enabled or not -// dac_arch_diff -#ifndef CONF_DAC_DIFF -#define CONF_DAC_DIFF 0 -#endif -// - -// Advanced Configuration -// dac_advanced_settings -#ifndef CONF_DAC_ADVANCED_CONFIG -#define CONF_DAC_ADVANCED_CONFIG 0 -#endif - -// Debug Run -// Indicate whether running when CPU is halted -// adc_arch_dbgrun -#ifndef CONF_DAC_DBGRUN -#define CONF_DAC_DBGRUN 1 -#endif - -// Channel 0 configuration -// Left Adjusted Data -// Indicate how the data is adjusted in the Data and Data Buffer register -// dac0_arch_leftadj -#ifndef CONF_DAC0_LEFTADJ -#define CONF_DAC0_LEFTADJ 0 -#endif - -// Current control -// <0=> GCLK_DAC <= 1.2MHz (100kSPS) -// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) -// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS) -// This defines the current in output buffer according to conversion rate -// dac0_arch_cctrl -#ifndef CONF_DAC0_CCTRL -#define CONF_DAC0_CCTRL 0 -#endif - -// Run in standby -// Indicates whether the DAC channel will continue running in standby sleep mode or not -// dac0_arch_runstdby -#ifndef CONF_DAC0_RUNSTDBY -#define CONF_DAC0_RUNSTDBY 0 -#endif - -// Dithering Mode -// Indicate whether dithering mode is enabled -// dac0_arch_ditrher -#ifndef CONF_DAC0_DITHER -#define CONF_DAC0_DITHER 0 -#endif - -// Refresh period <0x00-0xFF> -// This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us -// dac0_arch_refresh -#ifndef CONF_DAC0_REFRESH -#define CONF_DAC0_REFRESH 0 -#endif -// -// Channel 1 configuration -// Left Adjusted Data -// Indicate how the data is adjusted in the Data and Data Buffer register -// dac1_arch_leftadj -#ifndef CONF_DAC1_LEFTADJ -#define CONF_DAC1_LEFTADJ 0 -#endif - -// Current control -// <0=> GCLK_DAC <= 1.2MHz (100kSPS) -// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) -// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS) -// This defines the current in output buffer according to conversion rate -// dac1_arch_cctrl -#ifndef CONF_DAC1_CCTRL -#define CONF_DAC1_CCTRL 0 -#endif - -// Run in standby -// Indicates whether the DAC channel will continue running in standby sleep mode or not -// dac1_arch_runstdby -#ifndef CONF_DAC1_RUNSTDBY -#define CONF_DAC1_RUNSTDBY 0 -#endif - -// Dithering Mode -// Indicate whether dithering mode is enabled -// dac1_arch_ditrher -#ifndef CONF_DAC1_DITHER -#define CONF_DAC1_DITHER 0 -#endif - -// Refresh period <0x00-0xFF> -// This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us -// dac1_arch_refresh -#ifndef CONF_DAC1_REFRESH -#define CONF_DAC1_REFRESH 0 -#endif -// - -// Event configuration -// Inversion of DAC 0 event -// <0=> Detection on rising edge pf the input event -// <1=> Detection on falling edge pf the input event -// This defines the edge detection of the input event -// dac_arch_invei0 -#ifndef CONF_DAC_INVEI0 -#define CONF_DAC_INVEI0 0 -#endif - -// Data Buffer of DAC 0 Empty Event Output -// Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not -// dac_arch_emptyeo_0 -#ifndef CONF_DAC_EMPTYEO0 -#define CONF_DAC_EMPTYEO0 0 -#endif - -// Start Conversion Event Input DAC 0 -// Indicate whether Start input event is enabled -// dac_arch_startei_0 -#ifndef CONF_DAC_STARTEI0 -#define CONF_DAC_STARTEI0 0 -#endif -// Inversion of DAC 1 event -// <0=> Detection on rising edge pf the input event -// <1=> Detection on falling edge pf the input event -// This defines the edge detection of the input event -// dac_arch_invei1 -#ifndef CONF_DAC_INVEI1 -#define CONF_DAC_INVEI1 0 -#endif - -// Data Buffer of DAC 1 Empty Event Output -// Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not -// dac_arch_emptyeo_1 -#ifndef CONF_DAC_EMPTYEO1 -#define CONF_DAC_EMPTYEO1 0 -#endif - -// Start Conversion Event Input DAC 1 -// Indicate whether Start input event is enabled -// dac_arch_startei_1 -#ifndef CONF_DAC_STARTEI1 -#define CONF_DAC_STARTEI1 0 -#endif - -// -// - -// <<< end of configuration section >>> - -#endif // HPL_DAC_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_dmac_config.h b/atmel-samd/asf4/samd51/config/hpl_dmac_config.h deleted file mode 100644 index 90499fc27..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_dmac_config.h +++ /dev/null @@ -1,7277 +0,0 @@ -/* Auto-generated config file hpl_dmac_config.h */ -#ifndef HPL_DMAC_CONFIG_H -#define HPL_DMAC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// DMAC enable -// Indicates whether dmac is enabled or not -// dmac_enable -#ifndef CONF_DMAC_ENABLE -#define CONF_DMAC_ENABLE 0 -#endif - -// Priority Level 0 -// Indicates whether Priority Level 0 is enabled or not -// dmac_lvlen0 -#ifndef CONF_DMAC_LVLEN0 -#define CONF_DMAC_LVLEN0 1 -#endif - -// Level 0 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 0 -// <1=> Round-robin arbitration scheme for channel with priority 0 -// Defines Level 0 Arbitration for DMA channels -// dmac_rrlvlen0 -#ifndef CONF_DMAC_RRLVLEN0 -#define CONF_DMAC_RRLVLEN0 0 -#endif - -// Level 0 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri0 -#ifndef CONF_DMAC_LVLPRI0 -#define CONF_DMAC_LVLPRI0 0 -#endif -// Priority Level 1 -// Indicates whether Priority Level 1 is enabled or not -// dmac_lvlen1 -#ifndef CONF_DMAC_LVLEN1 -#define CONF_DMAC_LVLEN1 1 -#endif - -// Level 1 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 1 -// <1=> Round-robin arbitration scheme for channel with priority 1 -// Defines Level 1 Arbitration for DMA channels -// dmac_rrlvlen1 -#ifndef CONF_DMAC_RRLVLEN1 -#define CONF_DMAC_RRLVLEN1 0 -#endif - -// Level 1 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri1 -#ifndef CONF_DMAC_LVLPRI1 -#define CONF_DMAC_LVLPRI1 0 -#endif -// Priority Level 2 -// Indicates whether Priority Level 2 is enabled or not -// dmac_lvlen2 -#ifndef CONF_DMAC_LVLEN2 -#define CONF_DMAC_LVLEN2 1 -#endif - -// Level 2 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 2 -// <1=> Round-robin arbitration scheme for channel with priority 2 -// Defines Level 2 Arbitration for DMA channels -// dmac_rrlvlen2 -#ifndef CONF_DMAC_RRLVLEN2 -#define CONF_DMAC_RRLVLEN2 0 -#endif - -// Level 2 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri2 -#ifndef CONF_DMAC_LVLPRI2 -#define CONF_DMAC_LVLPRI2 0 -#endif -// Priority Level 3 -// Indicates whether Priority Level 3 is enabled or not -// dmac_lvlen3 -#ifndef CONF_DMAC_LVLEN3 -#define CONF_DMAC_LVLEN3 1 -#endif - -// Level 3 Round-Robin Arbitration -// <0=> Static arbitration scheme for channel with priority 3 -// <1=> Round-robin arbitration scheme for channel with priority 3 -// Defines Level 3 Arbitration for DMA channels -// dmac_rrlvlen3 -#ifndef CONF_DMAC_RRLVLEN3 -#define CONF_DMAC_RRLVLEN3 0 -#endif - -// Level 3 Channel Priority Number <0x00-0xFF> -// dmac_lvlpri3 -#ifndef CONF_DMAC_LVLPRI3 -#define CONF_DMAC_LVLPRI3 0 -#endif -// Debug Run -// Indicates whether Debug Run is enabled or not -// dmac_dbgrun -#ifndef CONF_DMAC_DBGRUN -#define CONF_DMAC_DBGRUN 0 -#endif - -// Channel 0 settings -// dmac_channel_0_settings -#ifndef CONF_DMAC_CHANNEL_0_SETTINGS -#define CONF_DMAC_CHANNEL_0_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 0 is running in standby mode or not -// dmac_runstdby_0 -#ifndef CONF_DMAC_RUNSTDBY_0 -#define CONF_DMAC_RUNSTDBY_0 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_0 -#ifndef CONF_DMAC_TRIGACT_0 -#define CONF_DMAC_TRIGACT_0 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_0 -#ifndef CONF_DMAC_TRIGSRC_0 -#define CONF_DMAC_TRIGSRC_0 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_0 -#ifndef CONF_DMAC_LVL_0 -#define CONF_DMAC_LVL_0 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_0 -#ifndef CONF_DMAC_EVOE_0 -#define CONF_DMAC_EVOE_0 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_0 -#ifndef CONF_DMAC_EVIE_0 -#define CONF_DMAC_EVIE_0 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_0 -#ifndef CONF_DMAC_EVACT_0 -#define CONF_DMAC_EVACT_0 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_0 -#ifndef CONF_DMAC_STEPSIZE_0 -#define CONF_DMAC_STEPSIZE_0 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_0 -#ifndef CONF_DMAC_STEPSEL_0 -#define CONF_DMAC_STEPSEL_0 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_0 -#ifndef CONF_DMAC_SRCINC_0 -#define CONF_DMAC_SRCINC_0 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_0 -#ifndef CONF_DMAC_DSTINC_0 -#define CONF_DMAC_DSTINC_0 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_0 -#ifndef CONF_DMAC_BEATSIZE_0 -#define CONF_DMAC_BEATSIZE_0 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_0 -#ifndef CONF_DMAC_BLOCKACT_0 -#define CONF_DMAC_BLOCKACT_0 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_0 -#ifndef CONF_DMAC_EVOSEL_0 -#define CONF_DMAC_EVOSEL_0 0 -#endif -// - -// Channel 1 settings -// dmac_channel_1_settings -#ifndef CONF_DMAC_CHANNEL_1_SETTINGS -#define CONF_DMAC_CHANNEL_1_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 1 is running in standby mode or not -// dmac_runstdby_1 -#ifndef CONF_DMAC_RUNSTDBY_1 -#define CONF_DMAC_RUNSTDBY_1 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_1 -#ifndef CONF_DMAC_TRIGACT_1 -#define CONF_DMAC_TRIGACT_1 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_1 -#ifndef CONF_DMAC_TRIGSRC_1 -#define CONF_DMAC_TRIGSRC_1 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_1 -#ifndef CONF_DMAC_LVL_1 -#define CONF_DMAC_LVL_1 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_1 -#ifndef CONF_DMAC_EVOE_1 -#define CONF_DMAC_EVOE_1 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_1 -#ifndef CONF_DMAC_EVIE_1 -#define CONF_DMAC_EVIE_1 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_1 -#ifndef CONF_DMAC_EVACT_1 -#define CONF_DMAC_EVACT_1 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_1 -#ifndef CONF_DMAC_STEPSIZE_1 -#define CONF_DMAC_STEPSIZE_1 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_1 -#ifndef CONF_DMAC_STEPSEL_1 -#define CONF_DMAC_STEPSEL_1 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_1 -#ifndef CONF_DMAC_SRCINC_1 -#define CONF_DMAC_SRCINC_1 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_1 -#ifndef CONF_DMAC_DSTINC_1 -#define CONF_DMAC_DSTINC_1 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_1 -#ifndef CONF_DMAC_BEATSIZE_1 -#define CONF_DMAC_BEATSIZE_1 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_1 -#ifndef CONF_DMAC_BLOCKACT_1 -#define CONF_DMAC_BLOCKACT_1 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_1 -#ifndef CONF_DMAC_EVOSEL_1 -#define CONF_DMAC_EVOSEL_1 0 -#endif -// - -// Channel 2 settings -// dmac_channel_2_settings -#ifndef CONF_DMAC_CHANNEL_2_SETTINGS -#define CONF_DMAC_CHANNEL_2_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 2 is running in standby mode or not -// dmac_runstdby_2 -#ifndef CONF_DMAC_RUNSTDBY_2 -#define CONF_DMAC_RUNSTDBY_2 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_2 -#ifndef CONF_DMAC_TRIGACT_2 -#define CONF_DMAC_TRIGACT_2 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_2 -#ifndef CONF_DMAC_TRIGSRC_2 -#define CONF_DMAC_TRIGSRC_2 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_2 -#ifndef CONF_DMAC_LVL_2 -#define CONF_DMAC_LVL_2 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_2 -#ifndef CONF_DMAC_EVOE_2 -#define CONF_DMAC_EVOE_2 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_2 -#ifndef CONF_DMAC_EVIE_2 -#define CONF_DMAC_EVIE_2 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_2 -#ifndef CONF_DMAC_EVACT_2 -#define CONF_DMAC_EVACT_2 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_2 -#ifndef CONF_DMAC_STEPSIZE_2 -#define CONF_DMAC_STEPSIZE_2 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_2 -#ifndef CONF_DMAC_STEPSEL_2 -#define CONF_DMAC_STEPSEL_2 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_2 -#ifndef CONF_DMAC_SRCINC_2 -#define CONF_DMAC_SRCINC_2 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_2 -#ifndef CONF_DMAC_DSTINC_2 -#define CONF_DMAC_DSTINC_2 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_2 -#ifndef CONF_DMAC_BEATSIZE_2 -#define CONF_DMAC_BEATSIZE_2 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_2 -#ifndef CONF_DMAC_BLOCKACT_2 -#define CONF_DMAC_BLOCKACT_2 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_2 -#ifndef CONF_DMAC_EVOSEL_2 -#define CONF_DMAC_EVOSEL_2 0 -#endif -// - -// Channel 3 settings -// dmac_channel_3_settings -#ifndef CONF_DMAC_CHANNEL_3_SETTINGS -#define CONF_DMAC_CHANNEL_3_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 3 is running in standby mode or not -// dmac_runstdby_3 -#ifndef CONF_DMAC_RUNSTDBY_3 -#define CONF_DMAC_RUNSTDBY_3 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_3 -#ifndef CONF_DMAC_TRIGACT_3 -#define CONF_DMAC_TRIGACT_3 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_3 -#ifndef CONF_DMAC_TRIGSRC_3 -#define CONF_DMAC_TRIGSRC_3 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_3 -#ifndef CONF_DMAC_LVL_3 -#define CONF_DMAC_LVL_3 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_3 -#ifndef CONF_DMAC_EVOE_3 -#define CONF_DMAC_EVOE_3 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_3 -#ifndef CONF_DMAC_EVIE_3 -#define CONF_DMAC_EVIE_3 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_3 -#ifndef CONF_DMAC_EVACT_3 -#define CONF_DMAC_EVACT_3 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_3 -#ifndef CONF_DMAC_STEPSIZE_3 -#define CONF_DMAC_STEPSIZE_3 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_3 -#ifndef CONF_DMAC_STEPSEL_3 -#define CONF_DMAC_STEPSEL_3 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_3 -#ifndef CONF_DMAC_SRCINC_3 -#define CONF_DMAC_SRCINC_3 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_3 -#ifndef CONF_DMAC_DSTINC_3 -#define CONF_DMAC_DSTINC_3 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_3 -#ifndef CONF_DMAC_BEATSIZE_3 -#define CONF_DMAC_BEATSIZE_3 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_3 -#ifndef CONF_DMAC_BLOCKACT_3 -#define CONF_DMAC_BLOCKACT_3 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_3 -#ifndef CONF_DMAC_EVOSEL_3 -#define CONF_DMAC_EVOSEL_3 0 -#endif -// - -// Channel 4 settings -// dmac_channel_4_settings -#ifndef CONF_DMAC_CHANNEL_4_SETTINGS -#define CONF_DMAC_CHANNEL_4_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 4 is running in standby mode or not -// dmac_runstdby_4 -#ifndef CONF_DMAC_RUNSTDBY_4 -#define CONF_DMAC_RUNSTDBY_4 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_4 -#ifndef CONF_DMAC_TRIGACT_4 -#define CONF_DMAC_TRIGACT_4 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_4 -#ifndef CONF_DMAC_TRIGSRC_4 -#define CONF_DMAC_TRIGSRC_4 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_4 -#ifndef CONF_DMAC_LVL_4 -#define CONF_DMAC_LVL_4 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_4 -#ifndef CONF_DMAC_EVOE_4 -#define CONF_DMAC_EVOE_4 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_4 -#ifndef CONF_DMAC_EVIE_4 -#define CONF_DMAC_EVIE_4 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_4 -#ifndef CONF_DMAC_EVACT_4 -#define CONF_DMAC_EVACT_4 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_4 -#ifndef CONF_DMAC_STEPSIZE_4 -#define CONF_DMAC_STEPSIZE_4 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_4 -#ifndef CONF_DMAC_STEPSEL_4 -#define CONF_DMAC_STEPSEL_4 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_4 -#ifndef CONF_DMAC_SRCINC_4 -#define CONF_DMAC_SRCINC_4 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_4 -#ifndef CONF_DMAC_DSTINC_4 -#define CONF_DMAC_DSTINC_4 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_4 -#ifndef CONF_DMAC_BEATSIZE_4 -#define CONF_DMAC_BEATSIZE_4 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_4 -#ifndef CONF_DMAC_BLOCKACT_4 -#define CONF_DMAC_BLOCKACT_4 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_4 -#ifndef CONF_DMAC_EVOSEL_4 -#define CONF_DMAC_EVOSEL_4 0 -#endif -// - -// Channel 5 settings -// dmac_channel_5_settings -#ifndef CONF_DMAC_CHANNEL_5_SETTINGS -#define CONF_DMAC_CHANNEL_5_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 5 is running in standby mode or not -// dmac_runstdby_5 -#ifndef CONF_DMAC_RUNSTDBY_5 -#define CONF_DMAC_RUNSTDBY_5 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_5 -#ifndef CONF_DMAC_TRIGACT_5 -#define CONF_DMAC_TRIGACT_5 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_5 -#ifndef CONF_DMAC_TRIGSRC_5 -#define CONF_DMAC_TRIGSRC_5 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_5 -#ifndef CONF_DMAC_LVL_5 -#define CONF_DMAC_LVL_5 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_5 -#ifndef CONF_DMAC_EVOE_5 -#define CONF_DMAC_EVOE_5 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_5 -#ifndef CONF_DMAC_EVIE_5 -#define CONF_DMAC_EVIE_5 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_5 -#ifndef CONF_DMAC_EVACT_5 -#define CONF_DMAC_EVACT_5 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_5 -#ifndef CONF_DMAC_STEPSIZE_5 -#define CONF_DMAC_STEPSIZE_5 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_5 -#ifndef CONF_DMAC_STEPSEL_5 -#define CONF_DMAC_STEPSEL_5 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_5 -#ifndef CONF_DMAC_SRCINC_5 -#define CONF_DMAC_SRCINC_5 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_5 -#ifndef CONF_DMAC_DSTINC_5 -#define CONF_DMAC_DSTINC_5 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_5 -#ifndef CONF_DMAC_BEATSIZE_5 -#define CONF_DMAC_BEATSIZE_5 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_5 -#ifndef CONF_DMAC_BLOCKACT_5 -#define CONF_DMAC_BLOCKACT_5 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_5 -#ifndef CONF_DMAC_EVOSEL_5 -#define CONF_DMAC_EVOSEL_5 0 -#endif -// - -// Channel 6 settings -// dmac_channel_6_settings -#ifndef CONF_DMAC_CHANNEL_6_SETTINGS -#define CONF_DMAC_CHANNEL_6_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 6 is running in standby mode or not -// dmac_runstdby_6 -#ifndef CONF_DMAC_RUNSTDBY_6 -#define CONF_DMAC_RUNSTDBY_6 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_6 -#ifndef CONF_DMAC_TRIGACT_6 -#define CONF_DMAC_TRIGACT_6 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_6 -#ifndef CONF_DMAC_TRIGSRC_6 -#define CONF_DMAC_TRIGSRC_6 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_6 -#ifndef CONF_DMAC_LVL_6 -#define CONF_DMAC_LVL_6 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_6 -#ifndef CONF_DMAC_EVOE_6 -#define CONF_DMAC_EVOE_6 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_6 -#ifndef CONF_DMAC_EVIE_6 -#define CONF_DMAC_EVIE_6 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_6 -#ifndef CONF_DMAC_EVACT_6 -#define CONF_DMAC_EVACT_6 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_6 -#ifndef CONF_DMAC_STEPSIZE_6 -#define CONF_DMAC_STEPSIZE_6 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_6 -#ifndef CONF_DMAC_STEPSEL_6 -#define CONF_DMAC_STEPSEL_6 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_6 -#ifndef CONF_DMAC_SRCINC_6 -#define CONF_DMAC_SRCINC_6 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_6 -#ifndef CONF_DMAC_DSTINC_6 -#define CONF_DMAC_DSTINC_6 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_6 -#ifndef CONF_DMAC_BEATSIZE_6 -#define CONF_DMAC_BEATSIZE_6 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_6 -#ifndef CONF_DMAC_BLOCKACT_6 -#define CONF_DMAC_BLOCKACT_6 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_6 -#ifndef CONF_DMAC_EVOSEL_6 -#define CONF_DMAC_EVOSEL_6 0 -#endif -// - -// Channel 7 settings -// dmac_channel_7_settings -#ifndef CONF_DMAC_CHANNEL_7_SETTINGS -#define CONF_DMAC_CHANNEL_7_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 7 is running in standby mode or not -// dmac_runstdby_7 -#ifndef CONF_DMAC_RUNSTDBY_7 -#define CONF_DMAC_RUNSTDBY_7 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_7 -#ifndef CONF_DMAC_TRIGACT_7 -#define CONF_DMAC_TRIGACT_7 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_7 -#ifndef CONF_DMAC_TRIGSRC_7 -#define CONF_DMAC_TRIGSRC_7 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_7 -#ifndef CONF_DMAC_LVL_7 -#define CONF_DMAC_LVL_7 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_7 -#ifndef CONF_DMAC_EVOE_7 -#define CONF_DMAC_EVOE_7 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_7 -#ifndef CONF_DMAC_EVIE_7 -#define CONF_DMAC_EVIE_7 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_7 -#ifndef CONF_DMAC_EVACT_7 -#define CONF_DMAC_EVACT_7 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_7 -#ifndef CONF_DMAC_STEPSIZE_7 -#define CONF_DMAC_STEPSIZE_7 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_7 -#ifndef CONF_DMAC_STEPSEL_7 -#define CONF_DMAC_STEPSEL_7 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_7 -#ifndef CONF_DMAC_SRCINC_7 -#define CONF_DMAC_SRCINC_7 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_7 -#ifndef CONF_DMAC_DSTINC_7 -#define CONF_DMAC_DSTINC_7 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_7 -#ifndef CONF_DMAC_BEATSIZE_7 -#define CONF_DMAC_BEATSIZE_7 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_7 -#ifndef CONF_DMAC_BLOCKACT_7 -#define CONF_DMAC_BLOCKACT_7 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_7 -#ifndef CONF_DMAC_EVOSEL_7 -#define CONF_DMAC_EVOSEL_7 0 -#endif -// - -// Channel 8 settings -// dmac_channel_8_settings -#ifndef CONF_DMAC_CHANNEL_8_SETTINGS -#define CONF_DMAC_CHANNEL_8_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 8 is running in standby mode or not -// dmac_runstdby_8 -#ifndef CONF_DMAC_RUNSTDBY_8 -#define CONF_DMAC_RUNSTDBY_8 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_8 -#ifndef CONF_DMAC_TRIGACT_8 -#define CONF_DMAC_TRIGACT_8 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_8 -#ifndef CONF_DMAC_TRIGSRC_8 -#define CONF_DMAC_TRIGSRC_8 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_8 -#ifndef CONF_DMAC_LVL_8 -#define CONF_DMAC_LVL_8 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_8 -#ifndef CONF_DMAC_EVOE_8 -#define CONF_DMAC_EVOE_8 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_8 -#ifndef CONF_DMAC_EVIE_8 -#define CONF_DMAC_EVIE_8 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_8 -#ifndef CONF_DMAC_EVACT_8 -#define CONF_DMAC_EVACT_8 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_8 -#ifndef CONF_DMAC_STEPSIZE_8 -#define CONF_DMAC_STEPSIZE_8 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_8 -#ifndef CONF_DMAC_STEPSEL_8 -#define CONF_DMAC_STEPSEL_8 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_8 -#ifndef CONF_DMAC_SRCINC_8 -#define CONF_DMAC_SRCINC_8 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_8 -#ifndef CONF_DMAC_DSTINC_8 -#define CONF_DMAC_DSTINC_8 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_8 -#ifndef CONF_DMAC_BEATSIZE_8 -#define CONF_DMAC_BEATSIZE_8 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_8 -#ifndef CONF_DMAC_BLOCKACT_8 -#define CONF_DMAC_BLOCKACT_8 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_8 -#ifndef CONF_DMAC_EVOSEL_8 -#define CONF_DMAC_EVOSEL_8 0 -#endif -// - -// Channel 9 settings -// dmac_channel_9_settings -#ifndef CONF_DMAC_CHANNEL_9_SETTINGS -#define CONF_DMAC_CHANNEL_9_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 9 is running in standby mode or not -// dmac_runstdby_9 -#ifndef CONF_DMAC_RUNSTDBY_9 -#define CONF_DMAC_RUNSTDBY_9 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_9 -#ifndef CONF_DMAC_TRIGACT_9 -#define CONF_DMAC_TRIGACT_9 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_9 -#ifndef CONF_DMAC_TRIGSRC_9 -#define CONF_DMAC_TRIGSRC_9 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_9 -#ifndef CONF_DMAC_LVL_9 -#define CONF_DMAC_LVL_9 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_9 -#ifndef CONF_DMAC_EVOE_9 -#define CONF_DMAC_EVOE_9 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_9 -#ifndef CONF_DMAC_EVIE_9 -#define CONF_DMAC_EVIE_9 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_9 -#ifndef CONF_DMAC_EVACT_9 -#define CONF_DMAC_EVACT_9 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_9 -#ifndef CONF_DMAC_STEPSIZE_9 -#define CONF_DMAC_STEPSIZE_9 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_9 -#ifndef CONF_DMAC_STEPSEL_9 -#define CONF_DMAC_STEPSEL_9 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_9 -#ifndef CONF_DMAC_SRCINC_9 -#define CONF_DMAC_SRCINC_9 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_9 -#ifndef CONF_DMAC_DSTINC_9 -#define CONF_DMAC_DSTINC_9 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_9 -#ifndef CONF_DMAC_BEATSIZE_9 -#define CONF_DMAC_BEATSIZE_9 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_9 -#ifndef CONF_DMAC_BLOCKACT_9 -#define CONF_DMAC_BLOCKACT_9 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_9 -#ifndef CONF_DMAC_EVOSEL_9 -#define CONF_DMAC_EVOSEL_9 0 -#endif -// - -// Channel 10 settings -// dmac_channel_10_settings -#ifndef CONF_DMAC_CHANNEL_10_SETTINGS -#define CONF_DMAC_CHANNEL_10_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 10 is running in standby mode or not -// dmac_runstdby_10 -#ifndef CONF_DMAC_RUNSTDBY_10 -#define CONF_DMAC_RUNSTDBY_10 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_10 -#ifndef CONF_DMAC_TRIGACT_10 -#define CONF_DMAC_TRIGACT_10 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_10 -#ifndef CONF_DMAC_TRIGSRC_10 -#define CONF_DMAC_TRIGSRC_10 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_10 -#ifndef CONF_DMAC_LVL_10 -#define CONF_DMAC_LVL_10 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_10 -#ifndef CONF_DMAC_EVOE_10 -#define CONF_DMAC_EVOE_10 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_10 -#ifndef CONF_DMAC_EVIE_10 -#define CONF_DMAC_EVIE_10 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_10 -#ifndef CONF_DMAC_EVACT_10 -#define CONF_DMAC_EVACT_10 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_10 -#ifndef CONF_DMAC_STEPSIZE_10 -#define CONF_DMAC_STEPSIZE_10 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_10 -#ifndef CONF_DMAC_STEPSEL_10 -#define CONF_DMAC_STEPSEL_10 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_10 -#ifndef CONF_DMAC_SRCINC_10 -#define CONF_DMAC_SRCINC_10 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_10 -#ifndef CONF_DMAC_DSTINC_10 -#define CONF_DMAC_DSTINC_10 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_10 -#ifndef CONF_DMAC_BEATSIZE_10 -#define CONF_DMAC_BEATSIZE_10 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_10 -#ifndef CONF_DMAC_BLOCKACT_10 -#define CONF_DMAC_BLOCKACT_10 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_10 -#ifndef CONF_DMAC_EVOSEL_10 -#define CONF_DMAC_EVOSEL_10 0 -#endif -// - -// Channel 11 settings -// dmac_channel_11_settings -#ifndef CONF_DMAC_CHANNEL_11_SETTINGS -#define CONF_DMAC_CHANNEL_11_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 11 is running in standby mode or not -// dmac_runstdby_11 -#ifndef CONF_DMAC_RUNSTDBY_11 -#define CONF_DMAC_RUNSTDBY_11 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_11 -#ifndef CONF_DMAC_TRIGACT_11 -#define CONF_DMAC_TRIGACT_11 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_11 -#ifndef CONF_DMAC_TRIGSRC_11 -#define CONF_DMAC_TRIGSRC_11 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_11 -#ifndef CONF_DMAC_LVL_11 -#define CONF_DMAC_LVL_11 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_11 -#ifndef CONF_DMAC_EVOE_11 -#define CONF_DMAC_EVOE_11 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_11 -#ifndef CONF_DMAC_EVIE_11 -#define CONF_DMAC_EVIE_11 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_11 -#ifndef CONF_DMAC_EVACT_11 -#define CONF_DMAC_EVACT_11 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_11 -#ifndef CONF_DMAC_STEPSIZE_11 -#define CONF_DMAC_STEPSIZE_11 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_11 -#ifndef CONF_DMAC_STEPSEL_11 -#define CONF_DMAC_STEPSEL_11 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_11 -#ifndef CONF_DMAC_SRCINC_11 -#define CONF_DMAC_SRCINC_11 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_11 -#ifndef CONF_DMAC_DSTINC_11 -#define CONF_DMAC_DSTINC_11 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_11 -#ifndef CONF_DMAC_BEATSIZE_11 -#define CONF_DMAC_BEATSIZE_11 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_11 -#ifndef CONF_DMAC_BLOCKACT_11 -#define CONF_DMAC_BLOCKACT_11 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_11 -#ifndef CONF_DMAC_EVOSEL_11 -#define CONF_DMAC_EVOSEL_11 0 -#endif -// - -// Channel 12 settings -// dmac_channel_12_settings -#ifndef CONF_DMAC_CHANNEL_12_SETTINGS -#define CONF_DMAC_CHANNEL_12_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 12 is running in standby mode or not -// dmac_runstdby_12 -#ifndef CONF_DMAC_RUNSTDBY_12 -#define CONF_DMAC_RUNSTDBY_12 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_12 -#ifndef CONF_DMAC_TRIGACT_12 -#define CONF_DMAC_TRIGACT_12 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_12 -#ifndef CONF_DMAC_TRIGSRC_12 -#define CONF_DMAC_TRIGSRC_12 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_12 -#ifndef CONF_DMAC_LVL_12 -#define CONF_DMAC_LVL_12 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_12 -#ifndef CONF_DMAC_EVOE_12 -#define CONF_DMAC_EVOE_12 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_12 -#ifndef CONF_DMAC_EVIE_12 -#define CONF_DMAC_EVIE_12 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_12 -#ifndef CONF_DMAC_EVACT_12 -#define CONF_DMAC_EVACT_12 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_12 -#ifndef CONF_DMAC_STEPSIZE_12 -#define CONF_DMAC_STEPSIZE_12 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_12 -#ifndef CONF_DMAC_STEPSEL_12 -#define CONF_DMAC_STEPSEL_12 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_12 -#ifndef CONF_DMAC_SRCINC_12 -#define CONF_DMAC_SRCINC_12 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_12 -#ifndef CONF_DMAC_DSTINC_12 -#define CONF_DMAC_DSTINC_12 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_12 -#ifndef CONF_DMAC_BEATSIZE_12 -#define CONF_DMAC_BEATSIZE_12 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_12 -#ifndef CONF_DMAC_BLOCKACT_12 -#define CONF_DMAC_BLOCKACT_12 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_12 -#ifndef CONF_DMAC_EVOSEL_12 -#define CONF_DMAC_EVOSEL_12 0 -#endif -// - -// Channel 13 settings -// dmac_channel_13_settings -#ifndef CONF_DMAC_CHANNEL_13_SETTINGS -#define CONF_DMAC_CHANNEL_13_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 13 is running in standby mode or not -// dmac_runstdby_13 -#ifndef CONF_DMAC_RUNSTDBY_13 -#define CONF_DMAC_RUNSTDBY_13 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_13 -#ifndef CONF_DMAC_TRIGACT_13 -#define CONF_DMAC_TRIGACT_13 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_13 -#ifndef CONF_DMAC_TRIGSRC_13 -#define CONF_DMAC_TRIGSRC_13 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_13 -#ifndef CONF_DMAC_LVL_13 -#define CONF_DMAC_LVL_13 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_13 -#ifndef CONF_DMAC_EVOE_13 -#define CONF_DMAC_EVOE_13 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_13 -#ifndef CONF_DMAC_EVIE_13 -#define CONF_DMAC_EVIE_13 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_13 -#ifndef CONF_DMAC_EVACT_13 -#define CONF_DMAC_EVACT_13 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_13 -#ifndef CONF_DMAC_STEPSIZE_13 -#define CONF_DMAC_STEPSIZE_13 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_13 -#ifndef CONF_DMAC_STEPSEL_13 -#define CONF_DMAC_STEPSEL_13 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_13 -#ifndef CONF_DMAC_SRCINC_13 -#define CONF_DMAC_SRCINC_13 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_13 -#ifndef CONF_DMAC_DSTINC_13 -#define CONF_DMAC_DSTINC_13 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_13 -#ifndef CONF_DMAC_BEATSIZE_13 -#define CONF_DMAC_BEATSIZE_13 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_13 -#ifndef CONF_DMAC_BLOCKACT_13 -#define CONF_DMAC_BLOCKACT_13 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_13 -#ifndef CONF_DMAC_EVOSEL_13 -#define CONF_DMAC_EVOSEL_13 0 -#endif -// - -// Channel 14 settings -// dmac_channel_14_settings -#ifndef CONF_DMAC_CHANNEL_14_SETTINGS -#define CONF_DMAC_CHANNEL_14_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 14 is running in standby mode or not -// dmac_runstdby_14 -#ifndef CONF_DMAC_RUNSTDBY_14 -#define CONF_DMAC_RUNSTDBY_14 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_14 -#ifndef CONF_DMAC_TRIGACT_14 -#define CONF_DMAC_TRIGACT_14 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_14 -#ifndef CONF_DMAC_TRIGSRC_14 -#define CONF_DMAC_TRIGSRC_14 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_14 -#ifndef CONF_DMAC_LVL_14 -#define CONF_DMAC_LVL_14 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_14 -#ifndef CONF_DMAC_EVOE_14 -#define CONF_DMAC_EVOE_14 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_14 -#ifndef CONF_DMAC_EVIE_14 -#define CONF_DMAC_EVIE_14 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_14 -#ifndef CONF_DMAC_EVACT_14 -#define CONF_DMAC_EVACT_14 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_14 -#ifndef CONF_DMAC_STEPSIZE_14 -#define CONF_DMAC_STEPSIZE_14 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_14 -#ifndef CONF_DMAC_STEPSEL_14 -#define CONF_DMAC_STEPSEL_14 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_14 -#ifndef CONF_DMAC_SRCINC_14 -#define CONF_DMAC_SRCINC_14 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_14 -#ifndef CONF_DMAC_DSTINC_14 -#define CONF_DMAC_DSTINC_14 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_14 -#ifndef CONF_DMAC_BEATSIZE_14 -#define CONF_DMAC_BEATSIZE_14 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_14 -#ifndef CONF_DMAC_BLOCKACT_14 -#define CONF_DMAC_BLOCKACT_14 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_14 -#ifndef CONF_DMAC_EVOSEL_14 -#define CONF_DMAC_EVOSEL_14 0 -#endif -// - -// Channel 15 settings -// dmac_channel_15_settings -#ifndef CONF_DMAC_CHANNEL_15_SETTINGS -#define CONF_DMAC_CHANNEL_15_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 15 is running in standby mode or not -// dmac_runstdby_15 -#ifndef CONF_DMAC_RUNSTDBY_15 -#define CONF_DMAC_RUNSTDBY_15 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_15 -#ifndef CONF_DMAC_TRIGACT_15 -#define CONF_DMAC_TRIGACT_15 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_15 -#ifndef CONF_DMAC_TRIGSRC_15 -#define CONF_DMAC_TRIGSRC_15 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_15 -#ifndef CONF_DMAC_LVL_15 -#define CONF_DMAC_LVL_15 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_15 -#ifndef CONF_DMAC_EVOE_15 -#define CONF_DMAC_EVOE_15 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_15 -#ifndef CONF_DMAC_EVIE_15 -#define CONF_DMAC_EVIE_15 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_15 -#ifndef CONF_DMAC_EVACT_15 -#define CONF_DMAC_EVACT_15 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_15 -#ifndef CONF_DMAC_STEPSIZE_15 -#define CONF_DMAC_STEPSIZE_15 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_15 -#ifndef CONF_DMAC_STEPSEL_15 -#define CONF_DMAC_STEPSEL_15 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_15 -#ifndef CONF_DMAC_SRCINC_15 -#define CONF_DMAC_SRCINC_15 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_15 -#ifndef CONF_DMAC_DSTINC_15 -#define CONF_DMAC_DSTINC_15 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_15 -#ifndef CONF_DMAC_BEATSIZE_15 -#define CONF_DMAC_BEATSIZE_15 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_15 -#ifndef CONF_DMAC_BLOCKACT_15 -#define CONF_DMAC_BLOCKACT_15 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_15 -#ifndef CONF_DMAC_EVOSEL_15 -#define CONF_DMAC_EVOSEL_15 0 -#endif -// - -// Channel 16 settings -// dmac_channel_16_settings -#ifndef CONF_DMAC_CHANNEL_16_SETTINGS -#define CONF_DMAC_CHANNEL_16_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 16 is running in standby mode or not -// dmac_runstdby_16 -#ifndef CONF_DMAC_RUNSTDBY_16 -#define CONF_DMAC_RUNSTDBY_16 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_16 -#ifndef CONF_DMAC_TRIGACT_16 -#define CONF_DMAC_TRIGACT_16 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_16 -#ifndef CONF_DMAC_TRIGSRC_16 -#define CONF_DMAC_TRIGSRC_16 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_16 -#ifndef CONF_DMAC_LVL_16 -#define CONF_DMAC_LVL_16 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_16 -#ifndef CONF_DMAC_EVOE_16 -#define CONF_DMAC_EVOE_16 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_16 -#ifndef CONF_DMAC_EVIE_16 -#define CONF_DMAC_EVIE_16 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_16 -#ifndef CONF_DMAC_EVACT_16 -#define CONF_DMAC_EVACT_16 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_16 -#ifndef CONF_DMAC_STEPSIZE_16 -#define CONF_DMAC_STEPSIZE_16 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_16 -#ifndef CONF_DMAC_STEPSEL_16 -#define CONF_DMAC_STEPSEL_16 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_16 -#ifndef CONF_DMAC_SRCINC_16 -#define CONF_DMAC_SRCINC_16 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_16 -#ifndef CONF_DMAC_DSTINC_16 -#define CONF_DMAC_DSTINC_16 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_16 -#ifndef CONF_DMAC_BEATSIZE_16 -#define CONF_DMAC_BEATSIZE_16 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_16 -#ifndef CONF_DMAC_BLOCKACT_16 -#define CONF_DMAC_BLOCKACT_16 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_16 -#ifndef CONF_DMAC_EVOSEL_16 -#define CONF_DMAC_EVOSEL_16 0 -#endif -// - -// Channel 17 settings -// dmac_channel_17_settings -#ifndef CONF_DMAC_CHANNEL_17_SETTINGS -#define CONF_DMAC_CHANNEL_17_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 17 is running in standby mode or not -// dmac_runstdby_17 -#ifndef CONF_DMAC_RUNSTDBY_17 -#define CONF_DMAC_RUNSTDBY_17 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_17 -#ifndef CONF_DMAC_TRIGACT_17 -#define CONF_DMAC_TRIGACT_17 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_17 -#ifndef CONF_DMAC_TRIGSRC_17 -#define CONF_DMAC_TRIGSRC_17 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_17 -#ifndef CONF_DMAC_LVL_17 -#define CONF_DMAC_LVL_17 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_17 -#ifndef CONF_DMAC_EVOE_17 -#define CONF_DMAC_EVOE_17 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_17 -#ifndef CONF_DMAC_EVIE_17 -#define CONF_DMAC_EVIE_17 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_17 -#ifndef CONF_DMAC_EVACT_17 -#define CONF_DMAC_EVACT_17 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_17 -#ifndef CONF_DMAC_STEPSIZE_17 -#define CONF_DMAC_STEPSIZE_17 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_17 -#ifndef CONF_DMAC_STEPSEL_17 -#define CONF_DMAC_STEPSEL_17 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_17 -#ifndef CONF_DMAC_SRCINC_17 -#define CONF_DMAC_SRCINC_17 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_17 -#ifndef CONF_DMAC_DSTINC_17 -#define CONF_DMAC_DSTINC_17 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_17 -#ifndef CONF_DMAC_BEATSIZE_17 -#define CONF_DMAC_BEATSIZE_17 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_17 -#ifndef CONF_DMAC_BLOCKACT_17 -#define CONF_DMAC_BLOCKACT_17 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_17 -#ifndef CONF_DMAC_EVOSEL_17 -#define CONF_DMAC_EVOSEL_17 0 -#endif -// - -// Channel 18 settings -// dmac_channel_18_settings -#ifndef CONF_DMAC_CHANNEL_18_SETTINGS -#define CONF_DMAC_CHANNEL_18_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 18 is running in standby mode or not -// dmac_runstdby_18 -#ifndef CONF_DMAC_RUNSTDBY_18 -#define CONF_DMAC_RUNSTDBY_18 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_18 -#ifndef CONF_DMAC_TRIGACT_18 -#define CONF_DMAC_TRIGACT_18 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_18 -#ifndef CONF_DMAC_TRIGSRC_18 -#define CONF_DMAC_TRIGSRC_18 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_18 -#ifndef CONF_DMAC_LVL_18 -#define CONF_DMAC_LVL_18 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_18 -#ifndef CONF_DMAC_EVOE_18 -#define CONF_DMAC_EVOE_18 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_18 -#ifndef CONF_DMAC_EVIE_18 -#define CONF_DMAC_EVIE_18 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_18 -#ifndef CONF_DMAC_EVACT_18 -#define CONF_DMAC_EVACT_18 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_18 -#ifndef CONF_DMAC_STEPSIZE_18 -#define CONF_DMAC_STEPSIZE_18 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_18 -#ifndef CONF_DMAC_STEPSEL_18 -#define CONF_DMAC_STEPSEL_18 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_18 -#ifndef CONF_DMAC_SRCINC_18 -#define CONF_DMAC_SRCINC_18 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_18 -#ifndef CONF_DMAC_DSTINC_18 -#define CONF_DMAC_DSTINC_18 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_18 -#ifndef CONF_DMAC_BEATSIZE_18 -#define CONF_DMAC_BEATSIZE_18 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_18 -#ifndef CONF_DMAC_BLOCKACT_18 -#define CONF_DMAC_BLOCKACT_18 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_18 -#ifndef CONF_DMAC_EVOSEL_18 -#define CONF_DMAC_EVOSEL_18 0 -#endif -// - -// Channel 19 settings -// dmac_channel_19_settings -#ifndef CONF_DMAC_CHANNEL_19_SETTINGS -#define CONF_DMAC_CHANNEL_19_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 19 is running in standby mode or not -// dmac_runstdby_19 -#ifndef CONF_DMAC_RUNSTDBY_19 -#define CONF_DMAC_RUNSTDBY_19 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_19 -#ifndef CONF_DMAC_TRIGACT_19 -#define CONF_DMAC_TRIGACT_19 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_19 -#ifndef CONF_DMAC_TRIGSRC_19 -#define CONF_DMAC_TRIGSRC_19 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_19 -#ifndef CONF_DMAC_LVL_19 -#define CONF_DMAC_LVL_19 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_19 -#ifndef CONF_DMAC_EVOE_19 -#define CONF_DMAC_EVOE_19 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_19 -#ifndef CONF_DMAC_EVIE_19 -#define CONF_DMAC_EVIE_19 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_19 -#ifndef CONF_DMAC_EVACT_19 -#define CONF_DMAC_EVACT_19 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_19 -#ifndef CONF_DMAC_STEPSIZE_19 -#define CONF_DMAC_STEPSIZE_19 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_19 -#ifndef CONF_DMAC_STEPSEL_19 -#define CONF_DMAC_STEPSEL_19 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_19 -#ifndef CONF_DMAC_SRCINC_19 -#define CONF_DMAC_SRCINC_19 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_19 -#ifndef CONF_DMAC_DSTINC_19 -#define CONF_DMAC_DSTINC_19 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_19 -#ifndef CONF_DMAC_BEATSIZE_19 -#define CONF_DMAC_BEATSIZE_19 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_19 -#ifndef CONF_DMAC_BLOCKACT_19 -#define CONF_DMAC_BLOCKACT_19 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_19 -#ifndef CONF_DMAC_EVOSEL_19 -#define CONF_DMAC_EVOSEL_19 0 -#endif -// - -// Channel 20 settings -// dmac_channel_20_settings -#ifndef CONF_DMAC_CHANNEL_20_SETTINGS -#define CONF_DMAC_CHANNEL_20_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 20 is running in standby mode or not -// dmac_runstdby_20 -#ifndef CONF_DMAC_RUNSTDBY_20 -#define CONF_DMAC_RUNSTDBY_20 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_20 -#ifndef CONF_DMAC_TRIGACT_20 -#define CONF_DMAC_TRIGACT_20 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_20 -#ifndef CONF_DMAC_TRIGSRC_20 -#define CONF_DMAC_TRIGSRC_20 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_20 -#ifndef CONF_DMAC_LVL_20 -#define CONF_DMAC_LVL_20 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_20 -#ifndef CONF_DMAC_EVOE_20 -#define CONF_DMAC_EVOE_20 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_20 -#ifndef CONF_DMAC_EVIE_20 -#define CONF_DMAC_EVIE_20 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_20 -#ifndef CONF_DMAC_EVACT_20 -#define CONF_DMAC_EVACT_20 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_20 -#ifndef CONF_DMAC_STEPSIZE_20 -#define CONF_DMAC_STEPSIZE_20 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_20 -#ifndef CONF_DMAC_STEPSEL_20 -#define CONF_DMAC_STEPSEL_20 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_20 -#ifndef CONF_DMAC_SRCINC_20 -#define CONF_DMAC_SRCINC_20 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_20 -#ifndef CONF_DMAC_DSTINC_20 -#define CONF_DMAC_DSTINC_20 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_20 -#ifndef CONF_DMAC_BEATSIZE_20 -#define CONF_DMAC_BEATSIZE_20 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_20 -#ifndef CONF_DMAC_BLOCKACT_20 -#define CONF_DMAC_BLOCKACT_20 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_20 -#ifndef CONF_DMAC_EVOSEL_20 -#define CONF_DMAC_EVOSEL_20 0 -#endif -// - -// Channel 21 settings -// dmac_channel_21_settings -#ifndef CONF_DMAC_CHANNEL_21_SETTINGS -#define CONF_DMAC_CHANNEL_21_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 21 is running in standby mode or not -// dmac_runstdby_21 -#ifndef CONF_DMAC_RUNSTDBY_21 -#define CONF_DMAC_RUNSTDBY_21 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_21 -#ifndef CONF_DMAC_TRIGACT_21 -#define CONF_DMAC_TRIGACT_21 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_21 -#ifndef CONF_DMAC_TRIGSRC_21 -#define CONF_DMAC_TRIGSRC_21 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_21 -#ifndef CONF_DMAC_LVL_21 -#define CONF_DMAC_LVL_21 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_21 -#ifndef CONF_DMAC_EVOE_21 -#define CONF_DMAC_EVOE_21 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_21 -#ifndef CONF_DMAC_EVIE_21 -#define CONF_DMAC_EVIE_21 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_21 -#ifndef CONF_DMAC_EVACT_21 -#define CONF_DMAC_EVACT_21 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_21 -#ifndef CONF_DMAC_STEPSIZE_21 -#define CONF_DMAC_STEPSIZE_21 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_21 -#ifndef CONF_DMAC_STEPSEL_21 -#define CONF_DMAC_STEPSEL_21 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_21 -#ifndef CONF_DMAC_SRCINC_21 -#define CONF_DMAC_SRCINC_21 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_21 -#ifndef CONF_DMAC_DSTINC_21 -#define CONF_DMAC_DSTINC_21 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_21 -#ifndef CONF_DMAC_BEATSIZE_21 -#define CONF_DMAC_BEATSIZE_21 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_21 -#ifndef CONF_DMAC_BLOCKACT_21 -#define CONF_DMAC_BLOCKACT_21 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_21 -#ifndef CONF_DMAC_EVOSEL_21 -#define CONF_DMAC_EVOSEL_21 0 -#endif -// - -// Channel 22 settings -// dmac_channel_22_settings -#ifndef CONF_DMAC_CHANNEL_22_SETTINGS -#define CONF_DMAC_CHANNEL_22_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 22 is running in standby mode or not -// dmac_runstdby_22 -#ifndef CONF_DMAC_RUNSTDBY_22 -#define CONF_DMAC_RUNSTDBY_22 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_22 -#ifndef CONF_DMAC_TRIGACT_22 -#define CONF_DMAC_TRIGACT_22 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_22 -#ifndef CONF_DMAC_TRIGSRC_22 -#define CONF_DMAC_TRIGSRC_22 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_22 -#ifndef CONF_DMAC_LVL_22 -#define CONF_DMAC_LVL_22 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_22 -#ifndef CONF_DMAC_EVOE_22 -#define CONF_DMAC_EVOE_22 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_22 -#ifndef CONF_DMAC_EVIE_22 -#define CONF_DMAC_EVIE_22 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_22 -#ifndef CONF_DMAC_EVACT_22 -#define CONF_DMAC_EVACT_22 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_22 -#ifndef CONF_DMAC_STEPSIZE_22 -#define CONF_DMAC_STEPSIZE_22 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_22 -#ifndef CONF_DMAC_STEPSEL_22 -#define CONF_DMAC_STEPSEL_22 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_22 -#ifndef CONF_DMAC_SRCINC_22 -#define CONF_DMAC_SRCINC_22 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_22 -#ifndef CONF_DMAC_DSTINC_22 -#define CONF_DMAC_DSTINC_22 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_22 -#ifndef CONF_DMAC_BEATSIZE_22 -#define CONF_DMAC_BEATSIZE_22 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_22 -#ifndef CONF_DMAC_BLOCKACT_22 -#define CONF_DMAC_BLOCKACT_22 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_22 -#ifndef CONF_DMAC_EVOSEL_22 -#define CONF_DMAC_EVOSEL_22 0 -#endif -// - -// Channel 23 settings -// dmac_channel_23_settings -#ifndef CONF_DMAC_CHANNEL_23_SETTINGS -#define CONF_DMAC_CHANNEL_23_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 23 is running in standby mode or not -// dmac_runstdby_23 -#ifndef CONF_DMAC_RUNSTDBY_23 -#define CONF_DMAC_RUNSTDBY_23 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_23 -#ifndef CONF_DMAC_TRIGACT_23 -#define CONF_DMAC_TRIGACT_23 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_23 -#ifndef CONF_DMAC_TRIGSRC_23 -#define CONF_DMAC_TRIGSRC_23 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_23 -#ifndef CONF_DMAC_LVL_23 -#define CONF_DMAC_LVL_23 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_23 -#ifndef CONF_DMAC_EVOE_23 -#define CONF_DMAC_EVOE_23 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_23 -#ifndef CONF_DMAC_EVIE_23 -#define CONF_DMAC_EVIE_23 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_23 -#ifndef CONF_DMAC_EVACT_23 -#define CONF_DMAC_EVACT_23 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_23 -#ifndef CONF_DMAC_STEPSIZE_23 -#define CONF_DMAC_STEPSIZE_23 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_23 -#ifndef CONF_DMAC_STEPSEL_23 -#define CONF_DMAC_STEPSEL_23 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_23 -#ifndef CONF_DMAC_SRCINC_23 -#define CONF_DMAC_SRCINC_23 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_23 -#ifndef CONF_DMAC_DSTINC_23 -#define CONF_DMAC_DSTINC_23 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_23 -#ifndef CONF_DMAC_BEATSIZE_23 -#define CONF_DMAC_BEATSIZE_23 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_23 -#ifndef CONF_DMAC_BLOCKACT_23 -#define CONF_DMAC_BLOCKACT_23 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_23 -#ifndef CONF_DMAC_EVOSEL_23 -#define CONF_DMAC_EVOSEL_23 0 -#endif -// - -// Channel 24 settings -// dmac_channel_24_settings -#ifndef CONF_DMAC_CHANNEL_24_SETTINGS -#define CONF_DMAC_CHANNEL_24_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 24 is running in standby mode or not -// dmac_runstdby_24 -#ifndef CONF_DMAC_RUNSTDBY_24 -#define CONF_DMAC_RUNSTDBY_24 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_24 -#ifndef CONF_DMAC_TRIGACT_24 -#define CONF_DMAC_TRIGACT_24 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_24 -#ifndef CONF_DMAC_TRIGSRC_24 -#define CONF_DMAC_TRIGSRC_24 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_24 -#ifndef CONF_DMAC_LVL_24 -#define CONF_DMAC_LVL_24 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_24 -#ifndef CONF_DMAC_EVOE_24 -#define CONF_DMAC_EVOE_24 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_24 -#ifndef CONF_DMAC_EVIE_24 -#define CONF_DMAC_EVIE_24 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_24 -#ifndef CONF_DMAC_EVACT_24 -#define CONF_DMAC_EVACT_24 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_24 -#ifndef CONF_DMAC_STEPSIZE_24 -#define CONF_DMAC_STEPSIZE_24 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_24 -#ifndef CONF_DMAC_STEPSEL_24 -#define CONF_DMAC_STEPSEL_24 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_24 -#ifndef CONF_DMAC_SRCINC_24 -#define CONF_DMAC_SRCINC_24 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_24 -#ifndef CONF_DMAC_DSTINC_24 -#define CONF_DMAC_DSTINC_24 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_24 -#ifndef CONF_DMAC_BEATSIZE_24 -#define CONF_DMAC_BEATSIZE_24 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_24 -#ifndef CONF_DMAC_BLOCKACT_24 -#define CONF_DMAC_BLOCKACT_24 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_24 -#ifndef CONF_DMAC_EVOSEL_24 -#define CONF_DMAC_EVOSEL_24 0 -#endif -// - -// Channel 25 settings -// dmac_channel_25_settings -#ifndef CONF_DMAC_CHANNEL_25_SETTINGS -#define CONF_DMAC_CHANNEL_25_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 25 is running in standby mode or not -// dmac_runstdby_25 -#ifndef CONF_DMAC_RUNSTDBY_25 -#define CONF_DMAC_RUNSTDBY_25 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_25 -#ifndef CONF_DMAC_TRIGACT_25 -#define CONF_DMAC_TRIGACT_25 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_25 -#ifndef CONF_DMAC_TRIGSRC_25 -#define CONF_DMAC_TRIGSRC_25 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_25 -#ifndef CONF_DMAC_LVL_25 -#define CONF_DMAC_LVL_25 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_25 -#ifndef CONF_DMAC_EVOE_25 -#define CONF_DMAC_EVOE_25 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_25 -#ifndef CONF_DMAC_EVIE_25 -#define CONF_DMAC_EVIE_25 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_25 -#ifndef CONF_DMAC_EVACT_25 -#define CONF_DMAC_EVACT_25 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_25 -#ifndef CONF_DMAC_STEPSIZE_25 -#define CONF_DMAC_STEPSIZE_25 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_25 -#ifndef CONF_DMAC_STEPSEL_25 -#define CONF_DMAC_STEPSEL_25 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_25 -#ifndef CONF_DMAC_SRCINC_25 -#define CONF_DMAC_SRCINC_25 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_25 -#ifndef CONF_DMAC_DSTINC_25 -#define CONF_DMAC_DSTINC_25 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_25 -#ifndef CONF_DMAC_BEATSIZE_25 -#define CONF_DMAC_BEATSIZE_25 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_25 -#ifndef CONF_DMAC_BLOCKACT_25 -#define CONF_DMAC_BLOCKACT_25 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_25 -#ifndef CONF_DMAC_EVOSEL_25 -#define CONF_DMAC_EVOSEL_25 0 -#endif -// - -// Channel 26 settings -// dmac_channel_26_settings -#ifndef CONF_DMAC_CHANNEL_26_SETTINGS -#define CONF_DMAC_CHANNEL_26_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 26 is running in standby mode or not -// dmac_runstdby_26 -#ifndef CONF_DMAC_RUNSTDBY_26 -#define CONF_DMAC_RUNSTDBY_26 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_26 -#ifndef CONF_DMAC_TRIGACT_26 -#define CONF_DMAC_TRIGACT_26 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_26 -#ifndef CONF_DMAC_TRIGSRC_26 -#define CONF_DMAC_TRIGSRC_26 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_26 -#ifndef CONF_DMAC_LVL_26 -#define CONF_DMAC_LVL_26 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_26 -#ifndef CONF_DMAC_EVOE_26 -#define CONF_DMAC_EVOE_26 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_26 -#ifndef CONF_DMAC_EVIE_26 -#define CONF_DMAC_EVIE_26 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_26 -#ifndef CONF_DMAC_EVACT_26 -#define CONF_DMAC_EVACT_26 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_26 -#ifndef CONF_DMAC_STEPSIZE_26 -#define CONF_DMAC_STEPSIZE_26 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_26 -#ifndef CONF_DMAC_STEPSEL_26 -#define CONF_DMAC_STEPSEL_26 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_26 -#ifndef CONF_DMAC_SRCINC_26 -#define CONF_DMAC_SRCINC_26 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_26 -#ifndef CONF_DMAC_DSTINC_26 -#define CONF_DMAC_DSTINC_26 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_26 -#ifndef CONF_DMAC_BEATSIZE_26 -#define CONF_DMAC_BEATSIZE_26 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_26 -#ifndef CONF_DMAC_BLOCKACT_26 -#define CONF_DMAC_BLOCKACT_26 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_26 -#ifndef CONF_DMAC_EVOSEL_26 -#define CONF_DMAC_EVOSEL_26 0 -#endif -// - -// Channel 27 settings -// dmac_channel_27_settings -#ifndef CONF_DMAC_CHANNEL_27_SETTINGS -#define CONF_DMAC_CHANNEL_27_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 27 is running in standby mode or not -// dmac_runstdby_27 -#ifndef CONF_DMAC_RUNSTDBY_27 -#define CONF_DMAC_RUNSTDBY_27 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_27 -#ifndef CONF_DMAC_TRIGACT_27 -#define CONF_DMAC_TRIGACT_27 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_27 -#ifndef CONF_DMAC_TRIGSRC_27 -#define CONF_DMAC_TRIGSRC_27 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_27 -#ifndef CONF_DMAC_LVL_27 -#define CONF_DMAC_LVL_27 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_27 -#ifndef CONF_DMAC_EVOE_27 -#define CONF_DMAC_EVOE_27 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_27 -#ifndef CONF_DMAC_EVIE_27 -#define CONF_DMAC_EVIE_27 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_27 -#ifndef CONF_DMAC_EVACT_27 -#define CONF_DMAC_EVACT_27 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_27 -#ifndef CONF_DMAC_STEPSIZE_27 -#define CONF_DMAC_STEPSIZE_27 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_27 -#ifndef CONF_DMAC_STEPSEL_27 -#define CONF_DMAC_STEPSEL_27 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_27 -#ifndef CONF_DMAC_SRCINC_27 -#define CONF_DMAC_SRCINC_27 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_27 -#ifndef CONF_DMAC_DSTINC_27 -#define CONF_DMAC_DSTINC_27 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_27 -#ifndef CONF_DMAC_BEATSIZE_27 -#define CONF_DMAC_BEATSIZE_27 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_27 -#ifndef CONF_DMAC_BLOCKACT_27 -#define CONF_DMAC_BLOCKACT_27 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_27 -#ifndef CONF_DMAC_EVOSEL_27 -#define CONF_DMAC_EVOSEL_27 0 -#endif -// - -// Channel 28 settings -// dmac_channel_28_settings -#ifndef CONF_DMAC_CHANNEL_28_SETTINGS -#define CONF_DMAC_CHANNEL_28_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 28 is running in standby mode or not -// dmac_runstdby_28 -#ifndef CONF_DMAC_RUNSTDBY_28 -#define CONF_DMAC_RUNSTDBY_28 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_28 -#ifndef CONF_DMAC_TRIGACT_28 -#define CONF_DMAC_TRIGACT_28 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_28 -#ifndef CONF_DMAC_TRIGSRC_28 -#define CONF_DMAC_TRIGSRC_28 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_28 -#ifndef CONF_DMAC_LVL_28 -#define CONF_DMAC_LVL_28 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_28 -#ifndef CONF_DMAC_EVOE_28 -#define CONF_DMAC_EVOE_28 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_28 -#ifndef CONF_DMAC_EVIE_28 -#define CONF_DMAC_EVIE_28 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_28 -#ifndef CONF_DMAC_EVACT_28 -#define CONF_DMAC_EVACT_28 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_28 -#ifndef CONF_DMAC_STEPSIZE_28 -#define CONF_DMAC_STEPSIZE_28 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_28 -#ifndef CONF_DMAC_STEPSEL_28 -#define CONF_DMAC_STEPSEL_28 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_28 -#ifndef CONF_DMAC_SRCINC_28 -#define CONF_DMAC_SRCINC_28 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_28 -#ifndef CONF_DMAC_DSTINC_28 -#define CONF_DMAC_DSTINC_28 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_28 -#ifndef CONF_DMAC_BEATSIZE_28 -#define CONF_DMAC_BEATSIZE_28 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_28 -#ifndef CONF_DMAC_BLOCKACT_28 -#define CONF_DMAC_BLOCKACT_28 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_28 -#ifndef CONF_DMAC_EVOSEL_28 -#define CONF_DMAC_EVOSEL_28 0 -#endif -// - -// Channel 29 settings -// dmac_channel_29_settings -#ifndef CONF_DMAC_CHANNEL_29_SETTINGS -#define CONF_DMAC_CHANNEL_29_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 29 is running in standby mode or not -// dmac_runstdby_29 -#ifndef CONF_DMAC_RUNSTDBY_29 -#define CONF_DMAC_RUNSTDBY_29 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_29 -#ifndef CONF_DMAC_TRIGACT_29 -#define CONF_DMAC_TRIGACT_29 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_29 -#ifndef CONF_DMAC_TRIGSRC_29 -#define CONF_DMAC_TRIGSRC_29 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_29 -#ifndef CONF_DMAC_LVL_29 -#define CONF_DMAC_LVL_29 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_29 -#ifndef CONF_DMAC_EVOE_29 -#define CONF_DMAC_EVOE_29 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_29 -#ifndef CONF_DMAC_EVIE_29 -#define CONF_DMAC_EVIE_29 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_29 -#ifndef CONF_DMAC_EVACT_29 -#define CONF_DMAC_EVACT_29 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_29 -#ifndef CONF_DMAC_STEPSIZE_29 -#define CONF_DMAC_STEPSIZE_29 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_29 -#ifndef CONF_DMAC_STEPSEL_29 -#define CONF_DMAC_STEPSEL_29 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_29 -#ifndef CONF_DMAC_SRCINC_29 -#define CONF_DMAC_SRCINC_29 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_29 -#ifndef CONF_DMAC_DSTINC_29 -#define CONF_DMAC_DSTINC_29 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_29 -#ifndef CONF_DMAC_BEATSIZE_29 -#define CONF_DMAC_BEATSIZE_29 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_29 -#ifndef CONF_DMAC_BLOCKACT_29 -#define CONF_DMAC_BLOCKACT_29 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_29 -#ifndef CONF_DMAC_EVOSEL_29 -#define CONF_DMAC_EVOSEL_29 0 -#endif -// - -// Channel 30 settings -// dmac_channel_30_settings -#ifndef CONF_DMAC_CHANNEL_30_SETTINGS -#define CONF_DMAC_CHANNEL_30_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 30 is running in standby mode or not -// dmac_runstdby_30 -#ifndef CONF_DMAC_RUNSTDBY_30 -#define CONF_DMAC_RUNSTDBY_30 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_30 -#ifndef CONF_DMAC_TRIGACT_30 -#define CONF_DMAC_TRIGACT_30 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_30 -#ifndef CONF_DMAC_TRIGSRC_30 -#define CONF_DMAC_TRIGSRC_30 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_30 -#ifndef CONF_DMAC_LVL_30 -#define CONF_DMAC_LVL_30 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_30 -#ifndef CONF_DMAC_EVOE_30 -#define CONF_DMAC_EVOE_30 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_30 -#ifndef CONF_DMAC_EVIE_30 -#define CONF_DMAC_EVIE_30 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_30 -#ifndef CONF_DMAC_EVACT_30 -#define CONF_DMAC_EVACT_30 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_30 -#ifndef CONF_DMAC_STEPSIZE_30 -#define CONF_DMAC_STEPSIZE_30 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_30 -#ifndef CONF_DMAC_STEPSEL_30 -#define CONF_DMAC_STEPSEL_30 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_30 -#ifndef CONF_DMAC_SRCINC_30 -#define CONF_DMAC_SRCINC_30 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_30 -#ifndef CONF_DMAC_DSTINC_30 -#define CONF_DMAC_DSTINC_30 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_30 -#ifndef CONF_DMAC_BEATSIZE_30 -#define CONF_DMAC_BEATSIZE_30 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_30 -#ifndef CONF_DMAC_BLOCKACT_30 -#define CONF_DMAC_BLOCKACT_30 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_30 -#ifndef CONF_DMAC_EVOSEL_30 -#define CONF_DMAC_EVOSEL_30 0 -#endif -// - -// Channel 31 settings -// dmac_channel_31_settings -#ifndef CONF_DMAC_CHANNEL_31_SETTINGS -#define CONF_DMAC_CHANNEL_31_SETTINGS 0 -#endif - -// Channel Run in Standby -// Indicates whether channel 31 is running in standby mode or not -// dmac_runstdby_31 -#ifndef CONF_DMAC_RUNSTDBY_31 -#define CONF_DMAC_RUNSTDBY_31 0 -#endif - -// Trigger action -// <0=> One trigger required for each block transfer -// <2=> One trigger required for each beat transfer -// <3=> One trigger required for each transaction -// Defines the trigger action used for a transfer -// dmac_trigact_31 -#ifndef CONF_DMAC_TRIGACT_31 -#define CONF_DMAC_TRIGACT_31 0 -#endif - -// Trigger source -// <0x00=> Only software/event triggers -// <0x01=> RTC Time Stamp Trigger -// <0x02=> DSU Debug Communication Channel 0 Trigger -// <0x03=> DSU Debug Communication Channel 1 Trigger -// <0x04=> SERCOM0 RX Trigger -// <0x05=> SERCOM0 TX Trigger -// <0x06=> SERCOM1 RX Trigger -// <0x07=> SERCOM1 TX Trigger -// <0x08=> SERCOM2 RX Trigger -// <0x09=> SERCOM2 TX Trigger -// <0x0A=> SERCOM3 RX Trigger -// <0x0B=> SERCOM3 TX Trigger -// <0x0C=> SERCOM4 RX Trigger -// <0x0D=> SERCOM4 TX Trigger -// <0x0E=> SERCOM5 RX Trigger -// <0x0F=> SERCOM5 TX Trigger -// <0x10=> SERCOM6 RX Trigger -// <0x11=> SERCOM6 TX Trigger -// <0x12=> SERCOM7 RX Trigger -// <0x13=> SERCOM7 TX Trigger -// <0x14=> CAN0 DEBUG Trigger -// <0x15=> CAN1 DEBUG Trigger -// <0x16=> TCC0 Overflow Trigger Trigger -// <0x17=> TCC0 Match/Compare 0 Trigger Trigger -// <0x18=> TCC0 Match/Compare 1 Trigger Trigger -// <0x19=> TCC0 Match/Compare 2 Trigger Trigger -// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger -// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger -// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger -// <0x1D=> TCC1 Overflow Trigger Trigger -// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger -// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger -// <0x20=> TCC1 Match/Compare 2 Trigger Trigger -// <0x21=> TCC1 Match/Compare 3 Trigger Trigger -// <0x22=> TCC2 Overflow Trigger Trigger -// <0x23=> TCC2 Match/Compare 0 Trigger Trigger -// <0x24=> TCC2 Match/Compare 1 Trigger Trigger -// <0x25=> TCC2 Match/Compare 2 Trigger Trigger -// <0x26=> TCC3 Overflow Trigger Trigger -// <0x27=> TCC3 Match/Compare 0 Trigger Trigger -// <0x28=> TCC3 Match/Compare 1 Trigger Trigger -// <0x29=> TCC4 Overflow Trigger Trigger -// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger -// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger -// <0x2C=> TC0 Overflow Trigger -// <0x2D=> TC0 Match/Compare 0 Trigger -// <0x2E=> TC0 Match/Compare 1 Trigger -// <0x2F=> TC1 Overflow Trigger -// <0x30=> TC1 Match/Compare 0 Trigger -// <0x31=> TC1 Match/Compare 1 Trigger -// <0x32=> TC2 Overflow Trigger -// <0x33=> TC2 Match/Compare 0 Trigger -// <0x34=> TC2 Match/Compare 1 Trigger -// <0x35=> TC3 Overflow Trigger -// <0x36=> TC3 Match/Compare 0 Trigger -// <0x37=> TC3 Match/Compare 1 Trigger -// <0x38=> TC4 Overflow Trigger -// <0x39=> TC4 Match/Compare 0 Trigger -// <0x3A=> TC4 Match/Compare 1 Trigger -// <0x3B=> TC5 Overflow Trigger -// <0x3C=> TC5 Match/Compare 0 Trigger -// <0x3D=> TC5 Match/Compare 1 Trigger -// <0x3E=> TC6 Overflow Trigger -// <0x3F=> TC6 Match/Compare 0 Trigger -// <0x40=> TC6 Match/Compare 1 Trigger -// <0x41=> TC7 Overflow Trigger -// <0x42=> TC7 Match/Compare 0 Trigger -// <0x43=> TC7 Match/Compare 1 Trigger -// <0x44=> ADC0 Result Ready Trigger -// <0x45=> ADC0 Sequencing Trigger -// <0x46=> ADC1 Result Ready Trigger -// <0x47=> ADC1 Sequencing Trigger -// <0x48=> DAC Empty 0 Trigger -// <0x49=> DAC Empty 1 Trigger -// <0x4A=> DAC Result Ready 0 Trigger -// <0x4B=> DAC Result Ready 1 Trigger -// <0x4C=> I2S Rx 0 Trigger -// <0x4D=> I2S Rx 1 Trigger -// <0x4E=> I2S Tx 0 Trigger -// <0x4F=> I2S Tx 1 Trigger -// <0x50=> PCC RX Trigger -// <0x51=> AES Write Trigger -// <0x52=> AES Read Trigger -// <0x53=> QSPI Rx Trigger -// <0x54=> QSPI Tx Trigger -// Defines the peripheral trigger which is source of the transfer -// dmac_trifsrc_31 -#ifndef CONF_DMAC_TRIGSRC_31 -#define CONF_DMAC_TRIGSRC_31 0 -#endif - -// Channel Arbitration Level -// <0=> Channel priority 0 -// <1=> Channel priority 1 -// <2=> Channel priority 2 -// <3=> Channel priority 3 -// Defines the arbitration level for this channel -// dmac_lvl_31 -#ifndef CONF_DMAC_LVL_31 -#define CONF_DMAC_LVL_31 0 -#endif - -// Channel Event Output -// Indicates whether channel event generation is enabled or not -// dmac_evoe_31 -#ifndef CONF_DMAC_EVOE_31 -#define CONF_DMAC_EVOE_31 0 -#endif - -// Channel Event Input -// Indicates whether channel event reception is enabled or not -// dmac_evie_31 -#ifndef CONF_DMAC_EVIE_31 -#define CONF_DMAC_EVIE_31 0 -#endif - -// Event Input Action -// <0=> No action -// <1=> Normal transfer and conditional transfer on strobe trigger -// <2=> Conditional transfer trigger -// <3=> Conditional block transfer -// <4=> Channel suspend operation -// <5=> Channel resume operation -// <6=> Skip next block suspend action -// Defines the event input action -// dmac_evact_31 -#ifndef CONF_DMAC_EVACT_31 -#define CONF_DMAC_EVACT_31 0 -#endif - -// Address Increment Step Size -// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 -// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 -// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 -// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 -// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 -// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 -// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 -// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 -// Defines the address increment step size, applies to source or destination address -// dmac_stepsize_31 -#ifndef CONF_DMAC_STEPSIZE_31 -#define CONF_DMAC_STEPSIZE_31 0 -#endif - -// Step Selection -// <0=> Step size settings apply to the destination address -// <1=> Step size settings apply to the source address -// Defines whether source or destination addresses are using the step size settings -// dmac_stepsel_31 -#ifndef CONF_DMAC_STEPSEL_31 -#define CONF_DMAC_STEPSEL_31 0 -#endif - -// Source Address Increment -// Indicates whether the source address incrementation is enabled or not -// dmac_srcinc_31 -#ifndef CONF_DMAC_SRCINC_31 -#define CONF_DMAC_SRCINC_31 0 -#endif - -// Destination Address Increment -// Indicates whether the destination address incrementation is enabled or not -// dmac_dstinc_31 -#ifndef CONF_DMAC_DSTINC_31 -#define CONF_DMAC_DSTINC_31 0 -#endif - -// Beat Size -// <0=> 8-bit bus transfer -// <1=> 16-bit bus transfer -// <2=> 32-bit bus transfer -// Defines the size of one beat -// dmac_beatsize_31 -#ifndef CONF_DMAC_BEATSIZE_31 -#define CONF_DMAC_BEATSIZE_31 0 -#endif - -// Block Action -// <0=> Channel will be disabled if it is the last block transfer in the transaction -// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt -// <2=> Channel suspend operation is complete -// <3=> Both channel suspend operation and block interrupt -// Defines the the DMAC should take after a block transfer has completed -// dmac_blockact_31 -#ifndef CONF_DMAC_BLOCKACT_31 -#define CONF_DMAC_BLOCKACT_31 0 -#endif - -// Event Output Selection -// <0=> Event generation disabled -// <1=> Event strobe when block transfer complete -// <3=> Event strobe when beat transfer complete -// Defines the event output selection -// dmac_evosel_31 -#ifndef CONF_DMAC_EVOSEL_31 -#define CONF_DMAC_EVOSEL_31 0 -#endif -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_DMAC_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_evsys_config.h b/atmel-samd/asf4/samd51/config/hpl_evsys_config.h deleted file mode 100644 index d4c465d63..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_evsys_config.h +++ /dev/null @@ -1,8359 +0,0 @@ -/* Auto-generated config file hpl_evsys_config.h */ -#ifndef HPL_EVSYS_CONFIG_H -#define HPL_EVSYS_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Channel 0 settings -// evsys_channel_setting_0 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_0 -#define CONF_EVSYS_CHANNEL_SETTINGS_0 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_0 -#ifndef CONF_EDGSEL_0 -#define CONF_EDGSEL_0 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_0 -#ifndef CONF_PATH_0 -#define CONF_PATH_0 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_0 -#ifndef CONF_EVGEN_0 -#define CONF_EVGEN_0 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_0 -#ifndef CONF_OVR_0 -#define CONF_OVR_0 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_0 -#ifndef CONF_EVD_0 -#define CONF_EVD_0 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_0 -#ifndef CONF_ONDEMAND_0 -#define CONF_ONDEMAND_0 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_0 -#ifndef CONF_RUNSTDBY_0 -#define CONF_RUNSTDBY_0 0 -#endif - -// - -// Channel 1 settings -// evsys_channel_setting_1 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_1 -#define CONF_EVSYS_CHANNEL_SETTINGS_1 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_1 -#ifndef CONF_EDGSEL_1 -#define CONF_EDGSEL_1 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_1 -#ifndef CONF_PATH_1 -#define CONF_PATH_1 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_1 -#ifndef CONF_EVGEN_1 -#define CONF_EVGEN_1 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_1 -#ifndef CONF_OVR_1 -#define CONF_OVR_1 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_1 -#ifndef CONF_EVD_1 -#define CONF_EVD_1 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_1 -#ifndef CONF_ONDEMAND_1 -#define CONF_ONDEMAND_1 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_1 -#ifndef CONF_RUNSTDBY_1 -#define CONF_RUNSTDBY_1 0 -#endif - -// - -// Channel 2 settings -// evsys_channel_setting_2 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_2 -#define CONF_EVSYS_CHANNEL_SETTINGS_2 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_2 -#ifndef CONF_EDGSEL_2 -#define CONF_EDGSEL_2 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_2 -#ifndef CONF_PATH_2 -#define CONF_PATH_2 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_2 -#ifndef CONF_EVGEN_2 -#define CONF_EVGEN_2 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_2 -#ifndef CONF_OVR_2 -#define CONF_OVR_2 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_2 -#ifndef CONF_EVD_2 -#define CONF_EVD_2 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_2 -#ifndef CONF_ONDEMAND_2 -#define CONF_ONDEMAND_2 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_2 -#ifndef CONF_RUNSTDBY_2 -#define CONF_RUNSTDBY_2 0 -#endif - -// - -// Channel 3 settings -// evsys_channel_setting_3 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_3 -#define CONF_EVSYS_CHANNEL_SETTINGS_3 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_3 -#ifndef CONF_EDGSEL_3 -#define CONF_EDGSEL_3 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_3 -#ifndef CONF_PATH_3 -#define CONF_PATH_3 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_3 -#ifndef CONF_EVGEN_3 -#define CONF_EVGEN_3 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_3 -#ifndef CONF_OVR_3 -#define CONF_OVR_3 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_3 -#ifndef CONF_EVD_3 -#define CONF_EVD_3 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_3 -#ifndef CONF_ONDEMAND_3 -#define CONF_ONDEMAND_3 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_3 -#ifndef CONF_RUNSTDBY_3 -#define CONF_RUNSTDBY_3 0 -#endif - -// - -// Channel 4 settings -// evsys_channel_setting_4 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_4 -#define CONF_EVSYS_CHANNEL_SETTINGS_4 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_4 -#ifndef CONF_EDGSEL_4 -#define CONF_EDGSEL_4 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_4 -#ifndef CONF_PATH_4 -#define CONF_PATH_4 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_4 -#ifndef CONF_EVGEN_4 -#define CONF_EVGEN_4 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_4 -#ifndef CONF_OVR_4 -#define CONF_OVR_4 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_4 -#ifndef CONF_EVD_4 -#define CONF_EVD_4 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_4 -#ifndef CONF_ONDEMAND_4 -#define CONF_ONDEMAND_4 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_4 -#ifndef CONF_RUNSTDBY_4 -#define CONF_RUNSTDBY_4 0 -#endif - -// - -// Channel 5 settings -// evsys_channel_setting_5 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_5 -#define CONF_EVSYS_CHANNEL_SETTINGS_5 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_5 -#ifndef CONF_EDGSEL_5 -#define CONF_EDGSEL_5 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_5 -#ifndef CONF_PATH_5 -#define CONF_PATH_5 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_5 -#ifndef CONF_EVGEN_5 -#define CONF_EVGEN_5 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_5 -#ifndef CONF_OVR_5 -#define CONF_OVR_5 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_5 -#ifndef CONF_EVD_5 -#define CONF_EVD_5 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_5 -#ifndef CONF_ONDEMAND_5 -#define CONF_ONDEMAND_5 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_5 -#ifndef CONF_RUNSTDBY_5 -#define CONF_RUNSTDBY_5 0 -#endif - -// - -// Channel 6 settings -// evsys_channel_setting_6 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_6 -#define CONF_EVSYS_CHANNEL_SETTINGS_6 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_6 -#ifndef CONF_EDGSEL_6 -#define CONF_EDGSEL_6 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_6 -#ifndef CONF_PATH_6 -#define CONF_PATH_6 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_6 -#ifndef CONF_EVGEN_6 -#define CONF_EVGEN_6 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_6 -#ifndef CONF_OVR_6 -#define CONF_OVR_6 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_6 -#ifndef CONF_EVD_6 -#define CONF_EVD_6 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_6 -#ifndef CONF_ONDEMAND_6 -#define CONF_ONDEMAND_6 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_6 -#ifndef CONF_RUNSTDBY_6 -#define CONF_RUNSTDBY_6 0 -#endif - -// - -// Channel 7 settings -// evsys_channel_setting_7 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_7 -#define CONF_EVSYS_CHANNEL_SETTINGS_7 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_7 -#ifndef CONF_EDGSEL_7 -#define CONF_EDGSEL_7 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_7 -#ifndef CONF_PATH_7 -#define CONF_PATH_7 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_7 -#ifndef CONF_EVGEN_7 -#define CONF_EVGEN_7 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_7 -#ifndef CONF_OVR_7 -#define CONF_OVR_7 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_7 -#ifndef CONF_EVD_7 -#define CONF_EVD_7 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_7 -#ifndef CONF_ONDEMAND_7 -#define CONF_ONDEMAND_7 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_7 -#ifndef CONF_RUNSTDBY_7 -#define CONF_RUNSTDBY_7 0 -#endif - -// - -// Channel 8 settings -// evsys_channel_setting_8 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_8 -#define CONF_EVSYS_CHANNEL_SETTINGS_8 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_8 -#ifndef CONF_EDGSEL_8 -#define CONF_EDGSEL_8 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_8 -#ifndef CONF_PATH_8 -#define CONF_PATH_8 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_8 -#ifndef CONF_EVGEN_8 -#define CONF_EVGEN_8 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_8 -#ifndef CONF_OVR_8 -#define CONF_OVR_8 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_8 -#ifndef CONF_EVD_8 -#define CONF_EVD_8 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_8 -#ifndef CONF_ONDEMAND_8 -#define CONF_ONDEMAND_8 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_8 -#ifndef CONF_RUNSTDBY_8 -#define CONF_RUNSTDBY_8 0 -#endif - -// - -// Channel 9 settings -// evsys_channel_setting_9 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_9 -#define CONF_EVSYS_CHANNEL_SETTINGS_9 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_9 -#ifndef CONF_EDGSEL_9 -#define CONF_EDGSEL_9 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_9 -#ifndef CONF_PATH_9 -#define CONF_PATH_9 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_9 -#ifndef CONF_EVGEN_9 -#define CONF_EVGEN_9 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_9 -#ifndef CONF_OVR_9 -#define CONF_OVR_9 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_9 -#ifndef CONF_EVD_9 -#define CONF_EVD_9 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_9 -#ifndef CONF_ONDEMAND_9 -#define CONF_ONDEMAND_9 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_9 -#ifndef CONF_RUNSTDBY_9 -#define CONF_RUNSTDBY_9 0 -#endif - -// - -// Channel 10 settings -// evsys_channel_setting_10 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_10 -#define CONF_EVSYS_CHANNEL_SETTINGS_10 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_10 -#ifndef CONF_EDGSEL_10 -#define CONF_EDGSEL_10 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_10 -#ifndef CONF_PATH_10 -#define CONF_PATH_10 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_10 -#ifndef CONF_EVGEN_10 -#define CONF_EVGEN_10 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_10 -#ifndef CONF_OVR_10 -#define CONF_OVR_10 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_10 -#ifndef CONF_EVD_10 -#define CONF_EVD_10 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_10 -#ifndef CONF_ONDEMAND_10 -#define CONF_ONDEMAND_10 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_10 -#ifndef CONF_RUNSTDBY_10 -#define CONF_RUNSTDBY_10 0 -#endif - -// - -// Channel 11 settings -// evsys_channel_setting_11 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_11 -#define CONF_EVSYS_CHANNEL_SETTINGS_11 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_11 -#ifndef CONF_EDGSEL_11 -#define CONF_EDGSEL_11 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_11 -#ifndef CONF_PATH_11 -#define CONF_PATH_11 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_11 -#ifndef CONF_EVGEN_11 -#define CONF_EVGEN_11 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_11 -#ifndef CONF_OVR_11 -#define CONF_OVR_11 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_11 -#ifndef CONF_EVD_11 -#define CONF_EVD_11 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_11 -#ifndef CONF_ONDEMAND_11 -#define CONF_ONDEMAND_11 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_11 -#ifndef CONF_RUNSTDBY_11 -#define CONF_RUNSTDBY_11 0 -#endif - -// - -// Channel 12 settings -// evsys_channel_setting_12 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_12 -#define CONF_EVSYS_CHANNEL_SETTINGS_12 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_12 -#ifndef CONF_EDGSEL_12 -#define CONF_EDGSEL_12 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_12 -#ifndef CONF_PATH_12 -#define CONF_PATH_12 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_12 -#ifndef CONF_EVGEN_12 -#define CONF_EVGEN_12 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_12 -#ifndef CONF_OVR_12 -#define CONF_OVR_12 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_12 -#ifndef CONF_EVD_12 -#define CONF_EVD_12 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_12 -#ifndef CONF_ONDEMAND_12 -#define CONF_ONDEMAND_12 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_12 -#ifndef CONF_RUNSTDBY_12 -#define CONF_RUNSTDBY_12 0 -#endif - -// - -// Channel 13 settings -// evsys_channel_setting_13 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_13 -#define CONF_EVSYS_CHANNEL_SETTINGS_13 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_13 -#ifndef CONF_EDGSEL_13 -#define CONF_EDGSEL_13 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_13 -#ifndef CONF_PATH_13 -#define CONF_PATH_13 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_13 -#ifndef CONF_EVGEN_13 -#define CONF_EVGEN_13 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_13 -#ifndef CONF_OVR_13 -#define CONF_OVR_13 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_13 -#ifndef CONF_EVD_13 -#define CONF_EVD_13 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_13 -#ifndef CONF_ONDEMAND_13 -#define CONF_ONDEMAND_13 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_13 -#ifndef CONF_RUNSTDBY_13 -#define CONF_RUNSTDBY_13 0 -#endif - -// - -// Channel 14 settings -// evsys_channel_setting_14 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_14 -#define CONF_EVSYS_CHANNEL_SETTINGS_14 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_14 -#ifndef CONF_EDGSEL_14 -#define CONF_EDGSEL_14 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_14 -#ifndef CONF_PATH_14 -#define CONF_PATH_14 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_14 -#ifndef CONF_EVGEN_14 -#define CONF_EVGEN_14 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_14 -#ifndef CONF_OVR_14 -#define CONF_OVR_14 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_14 -#ifndef CONF_EVD_14 -#define CONF_EVD_14 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_14 -#ifndef CONF_ONDEMAND_14 -#define CONF_ONDEMAND_14 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_14 -#ifndef CONF_RUNSTDBY_14 -#define CONF_RUNSTDBY_14 0 -#endif - -// - -// Channel 15 settings -// evsys_channel_setting_15 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_15 -#define CONF_EVSYS_CHANNEL_SETTINGS_15 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_15 -#ifndef CONF_EDGSEL_15 -#define CONF_EDGSEL_15 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_15 -#ifndef CONF_PATH_15 -#define CONF_PATH_15 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_15 -#ifndef CONF_EVGEN_15 -#define CONF_EVGEN_15 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_15 -#ifndef CONF_OVR_15 -#define CONF_OVR_15 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_15 -#ifndef CONF_EVD_15 -#define CONF_EVD_15 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_15 -#ifndef CONF_ONDEMAND_15 -#define CONF_ONDEMAND_15 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_15 -#ifndef CONF_RUNSTDBY_15 -#define CONF_RUNSTDBY_15 0 -#endif - -// - -// Channel 16 settings -// evsys_channel_setting_16 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_16 -#define CONF_EVSYS_CHANNEL_SETTINGS_16 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_16 -#ifndef CONF_EDGSEL_16 -#define CONF_EDGSEL_16 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_16 -#ifndef CONF_PATH_16 -#define CONF_PATH_16 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_16 -#ifndef CONF_EVGEN_16 -#define CONF_EVGEN_16 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_16 -#ifndef CONF_OVR_16 -#define CONF_OVR_16 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_16 -#ifndef CONF_EVD_16 -#define CONF_EVD_16 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_16 -#ifndef CONF_ONDEMAND_16 -#define CONF_ONDEMAND_16 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_16 -#ifndef CONF_RUNSTDBY_16 -#define CONF_RUNSTDBY_16 0 -#endif - -// - -// Channel 17 settings -// evsys_channel_setting_17 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_17 -#define CONF_EVSYS_CHANNEL_SETTINGS_17 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_17 -#ifndef CONF_EDGSEL_17 -#define CONF_EDGSEL_17 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_17 -#ifndef CONF_PATH_17 -#define CONF_PATH_17 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_17 -#ifndef CONF_EVGEN_17 -#define CONF_EVGEN_17 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_17 -#ifndef CONF_OVR_17 -#define CONF_OVR_17 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_17 -#ifndef CONF_EVD_17 -#define CONF_EVD_17 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_17 -#ifndef CONF_ONDEMAND_17 -#define CONF_ONDEMAND_17 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_17 -#ifndef CONF_RUNSTDBY_17 -#define CONF_RUNSTDBY_17 0 -#endif - -// - -// Channel 18 settings -// evsys_channel_setting_18 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_18 -#define CONF_EVSYS_CHANNEL_SETTINGS_18 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_18 -#ifndef CONF_EDGSEL_18 -#define CONF_EDGSEL_18 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_18 -#ifndef CONF_PATH_18 -#define CONF_PATH_18 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_18 -#ifndef CONF_EVGEN_18 -#define CONF_EVGEN_18 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_18 -#ifndef CONF_OVR_18 -#define CONF_OVR_18 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_18 -#ifndef CONF_EVD_18 -#define CONF_EVD_18 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_18 -#ifndef CONF_ONDEMAND_18 -#define CONF_ONDEMAND_18 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_18 -#ifndef CONF_RUNSTDBY_18 -#define CONF_RUNSTDBY_18 0 -#endif - -// - -// Channel 19 settings -// evsys_channel_setting_19 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_19 -#define CONF_EVSYS_CHANNEL_SETTINGS_19 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_19 -#ifndef CONF_EDGSEL_19 -#define CONF_EDGSEL_19 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_19 -#ifndef CONF_PATH_19 -#define CONF_PATH_19 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_19 -#ifndef CONF_EVGEN_19 -#define CONF_EVGEN_19 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_19 -#ifndef CONF_OVR_19 -#define CONF_OVR_19 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_19 -#ifndef CONF_EVD_19 -#define CONF_EVD_19 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_19 -#ifndef CONF_ONDEMAND_19 -#define CONF_ONDEMAND_19 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_19 -#ifndef CONF_RUNSTDBY_19 -#define CONF_RUNSTDBY_19 0 -#endif - -// - -// Channel 20 settings -// evsys_channel_setting_20 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_20 -#define CONF_EVSYS_CHANNEL_SETTINGS_20 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_20 -#ifndef CONF_EDGSEL_20 -#define CONF_EDGSEL_20 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_20 -#ifndef CONF_PATH_20 -#define CONF_PATH_20 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_20 -#ifndef CONF_EVGEN_20 -#define CONF_EVGEN_20 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_20 -#ifndef CONF_OVR_20 -#define CONF_OVR_20 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_20 -#ifndef CONF_EVD_20 -#define CONF_EVD_20 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_20 -#ifndef CONF_ONDEMAND_20 -#define CONF_ONDEMAND_20 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_20 -#ifndef CONF_RUNSTDBY_20 -#define CONF_RUNSTDBY_20 0 -#endif - -// - -// Channel 21 settings -// evsys_channel_setting_21 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_21 -#define CONF_EVSYS_CHANNEL_SETTINGS_21 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_21 -#ifndef CONF_EDGSEL_21 -#define CONF_EDGSEL_21 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_21 -#ifndef CONF_PATH_21 -#define CONF_PATH_21 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_21 -#ifndef CONF_EVGEN_21 -#define CONF_EVGEN_21 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_21 -#ifndef CONF_OVR_21 -#define CONF_OVR_21 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_21 -#ifndef CONF_EVD_21 -#define CONF_EVD_21 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_21 -#ifndef CONF_ONDEMAND_21 -#define CONF_ONDEMAND_21 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_21 -#ifndef CONF_RUNSTDBY_21 -#define CONF_RUNSTDBY_21 0 -#endif - -// - -// Channel 22 settings -// evsys_channel_setting_22 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_22 -#define CONF_EVSYS_CHANNEL_SETTINGS_22 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_22 -#ifndef CONF_EDGSEL_22 -#define CONF_EDGSEL_22 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_22 -#ifndef CONF_PATH_22 -#define CONF_PATH_22 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_22 -#ifndef CONF_EVGEN_22 -#define CONF_EVGEN_22 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_22 -#ifndef CONF_OVR_22 -#define CONF_OVR_22 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_22 -#ifndef CONF_EVD_22 -#define CONF_EVD_22 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_22 -#ifndef CONF_ONDEMAND_22 -#define CONF_ONDEMAND_22 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_22 -#ifndef CONF_RUNSTDBY_22 -#define CONF_RUNSTDBY_22 0 -#endif - -// - -// Channel 23 settings -// evsys_channel_setting_23 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_23 -#define CONF_EVSYS_CHANNEL_SETTINGS_23 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_23 -#ifndef CONF_EDGSEL_23 -#define CONF_EDGSEL_23 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_23 -#ifndef CONF_PATH_23 -#define CONF_PATH_23 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_23 -#ifndef CONF_EVGEN_23 -#define CONF_EVGEN_23 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_23 -#ifndef CONF_OVR_23 -#define CONF_OVR_23 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_23 -#ifndef CONF_EVD_23 -#define CONF_EVD_23 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_23 -#ifndef CONF_ONDEMAND_23 -#define CONF_ONDEMAND_23 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_23 -#ifndef CONF_RUNSTDBY_23 -#define CONF_RUNSTDBY_23 0 -#endif - -// - -// Channel 24 settings -// evsys_channel_setting_24 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_24 -#define CONF_EVSYS_CHANNEL_SETTINGS_24 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_24 -#ifndef CONF_EDGSEL_24 -#define CONF_EDGSEL_24 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_24 -#ifndef CONF_PATH_24 -#define CONF_PATH_24 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_24 -#ifndef CONF_EVGEN_24 -#define CONF_EVGEN_24 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_24 -#ifndef CONF_OVR_24 -#define CONF_OVR_24 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_24 -#ifndef CONF_EVD_24 -#define CONF_EVD_24 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_24 -#ifndef CONF_ONDEMAND_24 -#define CONF_ONDEMAND_24 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_24 -#ifndef CONF_RUNSTDBY_24 -#define CONF_RUNSTDBY_24 0 -#endif - -// - -// Channel 25 settings -// evsys_channel_setting_25 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_25 -#define CONF_EVSYS_CHANNEL_SETTINGS_25 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_25 -#ifndef CONF_EDGSEL_25 -#define CONF_EDGSEL_25 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_25 -#ifndef CONF_PATH_25 -#define CONF_PATH_25 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_25 -#ifndef CONF_EVGEN_25 -#define CONF_EVGEN_25 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_25 -#ifndef CONF_OVR_25 -#define CONF_OVR_25 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_25 -#ifndef CONF_EVD_25 -#define CONF_EVD_25 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_25 -#ifndef CONF_ONDEMAND_25 -#define CONF_ONDEMAND_25 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_25 -#ifndef CONF_RUNSTDBY_25 -#define CONF_RUNSTDBY_25 0 -#endif - -// - -// Channel 26 settings -// evsys_channel_setting_26 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_26 -#define CONF_EVSYS_CHANNEL_SETTINGS_26 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_26 -#ifndef CONF_EDGSEL_26 -#define CONF_EDGSEL_26 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_26 -#ifndef CONF_PATH_26 -#define CONF_PATH_26 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_26 -#ifndef CONF_EVGEN_26 -#define CONF_EVGEN_26 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_26 -#ifndef CONF_OVR_26 -#define CONF_OVR_26 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_26 -#ifndef CONF_EVD_26 -#define CONF_EVD_26 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_26 -#ifndef CONF_ONDEMAND_26 -#define CONF_ONDEMAND_26 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_26 -#ifndef CONF_RUNSTDBY_26 -#define CONF_RUNSTDBY_26 0 -#endif - -// - -// Channel 27 settings -// evsys_channel_setting_27 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_27 -#define CONF_EVSYS_CHANNEL_SETTINGS_27 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_27 -#ifndef CONF_EDGSEL_27 -#define CONF_EDGSEL_27 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_27 -#ifndef CONF_PATH_27 -#define CONF_PATH_27 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_27 -#ifndef CONF_EVGEN_27 -#define CONF_EVGEN_27 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_27 -#ifndef CONF_OVR_27 -#define CONF_OVR_27 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_27 -#ifndef CONF_EVD_27 -#define CONF_EVD_27 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_27 -#ifndef CONF_ONDEMAND_27 -#define CONF_ONDEMAND_27 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_27 -#ifndef CONF_RUNSTDBY_27 -#define CONF_RUNSTDBY_27 0 -#endif - -// - -// Channel 28 settings -// evsys_channel_setting_28 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_28 -#define CONF_EVSYS_CHANNEL_SETTINGS_28 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_28 -#ifndef CONF_EDGSEL_28 -#define CONF_EDGSEL_28 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_28 -#ifndef CONF_PATH_28 -#define CONF_PATH_28 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_28 -#ifndef CONF_EVGEN_28 -#define CONF_EVGEN_28 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_28 -#ifndef CONF_OVR_28 -#define CONF_OVR_28 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_28 -#ifndef CONF_EVD_28 -#define CONF_EVD_28 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_28 -#ifndef CONF_ONDEMAND_28 -#define CONF_ONDEMAND_28 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_28 -#ifndef CONF_RUNSTDBY_28 -#define CONF_RUNSTDBY_28 0 -#endif - -// - -// Channel 29 settings -// evsys_channel_setting_29 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_29 -#define CONF_EVSYS_CHANNEL_SETTINGS_29 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_29 -#ifndef CONF_EDGSEL_29 -#define CONF_EDGSEL_29 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_29 -#ifndef CONF_PATH_29 -#define CONF_PATH_29 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_29 -#ifndef CONF_EVGEN_29 -#define CONF_EVGEN_29 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_29 -#ifndef CONF_OVR_29 -#define CONF_OVR_29 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_29 -#ifndef CONF_EVD_29 -#define CONF_EVD_29 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_29 -#ifndef CONF_ONDEMAND_29 -#define CONF_ONDEMAND_29 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_29 -#ifndef CONF_RUNSTDBY_29 -#define CONF_RUNSTDBY_29 0 -#endif - -// - -// Channel 30 settings -// evsys_channel_setting_30 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_30 -#define CONF_EVSYS_CHANNEL_SETTINGS_30 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_30 -#ifndef CONF_EDGSEL_30 -#define CONF_EDGSEL_30 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_30 -#ifndef CONF_PATH_30 -#define CONF_PATH_30 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_30 -#ifndef CONF_EVGEN_30 -#define CONF_EVGEN_30 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_30 -#ifndef CONF_OVR_30 -#define CONF_OVR_30 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_30 -#ifndef CONF_EVD_30 -#define CONF_EVD_30 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_30 -#ifndef CONF_ONDEMAND_30 -#define CONF_ONDEMAND_30 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_30 -#ifndef CONF_RUNSTDBY_30 -#define CONF_RUNSTDBY_30 0 -#endif - -// - -// Channel 31 settings -// evsys_channel_setting_31 -#ifndef CONF_EVSYS_CHANNEL_SETTINGS_31 -#define CONF_EVSYS_CHANNEL_SETTINGS_31 0 -#endif - -// Edge detection -// Indicates whether channel is enabled in standby sleep mode -// No event output when using the resynchronized or synchronous path -// Event is detected on the rising edge of the signal from event generator -// Event is detected on the falling edge of the signal from event generator -// Event is detected on the rising and falling edge of the signal from event generator -// evsys_edgsel_31 -#ifndef CONF_EDGSEL_31 -#define CONF_EDGSEL_31 EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val -#endif - -// Path selection -// Indicates which path for the event signal is chosen -// Synchronous path -// Resynchronized path -// Asynchronous path -// evsys_path_31 -#ifndef CONF_PATH_31 -#define CONF_PATH_31 EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val -#endif - -// Event generator -// Determines event generator for channel -// <0x0=>No event generator -// <0x1=>XOSC Clock Failure 0 -// <0x2=>XOSC Clock Failure 1 -// <0x3=>XOSC32K Clock Failure -// <0x4=>RTC period 0 -// <0x5=>RTC period 1 -// <0x6=>RTC period 2 -// <0x7=>RTC period 3 -// <0x8=>RTC period 4 -// <0x9=>RTC period 5 -// <0xA=>RTC period 6 -// <0xB=>RTC period 7 -// <0xC=>RTC compare 0 -// <0xD=>RTC compare 1 -// <0xE=>RTC compare 2 -// <0xF=>RTC compare 3 -// <0x10=>RTC Tamper Detection -// <0x11=>RTC overflow -// <0x12=>EIC external interrupt 0 -// <0x13=>EIC external interrupt 1 -// <0x14=>EIC external interrupt 2 -// <0x15=>EIC external interrupt 3 -// <0x16=>EIC external interrupt 4 -// <0x17=>EIC external interrupt 5 -// <0x18=>EIC external interrupt 6 -// <0x19=>EIC external interrupt 7 -// <0x1A=>EIC external interrupt 8 -// <0x1B=>EIC external interrupt 9 -// <0x1C=>EIC external interrupt 10 -// <0x1D=>EIC external interrupt 11 -// <0x1E=>EIC external interrupt 12 -// <0x1F=>EIC external interrupt 13 -// <0x20=>EIC external interrupt 14 -// <0x21=>EIC external interrupt 15 -// <0x22=>DMAC channel 0 -// <0x23=>DMAC channel 1 -// <0x24=>DMAC channel 2 -// <0x25=>DMAC channel 3 -// <0x28=>PAC access error -// <0x29=>TCC0 overflow -// <0x2A=>TCC0 trig -// <0x2B=>TCC0 counter -// <0x2C=>TCC0 match/capture 0 -// <0x2D=>TCC0 match/capture 1 -// <0x2E=>TCC0 match/capture 2 -// <0x2F=>TCC0 match/capture 3 -// <0x30=>TCC0 match/capture 4 -// <0x31=>TCC0 match/capture 5 -// <0x32=>TCC1 overflow -// <0x33=>TCC1 trig -// <0x34=>TCC1 counter -// <0x35=>TCC1 match/capture 0 -// <0x36=>TCC1 match/capture 1 -// <0x37=>TCC1 match/capture 2 -// <0x38=>TCC1 match/capture 3 -// <0x39=>TCC2 overflow -// <0x3A=>TCC2 trig -// <0x3B=>TCC2 counter -// <0x3C=>TCC2 match/capture 0 -// <0x3D=>TCC2 match/capture 1 -// <0x3E=>TCC2 match/capture 2 -// <0x3F=>TCC3 overflow -// <0x40=>TCC3 trig -// <0x41=>TCC3 counter -// <0x42=>TCC3 match/capture 0 -// <0x43=>TCC3 match/capture 1 -// <0x44=>TCC4 overflow -// <0x45=>TCC4 trig -// <0x46=>TCC4 counter -// <0x47=>TCC4 match/capture 0 -// <0x48=>TCC4 match/capture 1 -// <0x49=>TC0 overflow -// <0x4A=>TC0 match/capture 0 -// <0x4B=>TC0 match/capture 1 -// <0x4C=>TC1 overflow -// <0x4D=>TC1 match/capture 0 -// <0x4E=>TC1 match/capture 1 -// <0x4F=>TC2 overflow -// <0x50=>TC2 match/capture 0 -// <0x51=>TC2 match/capture 1 -// <0x52=>TC3 overflow -// <0x53=>TC3 match/capture 0 -// <0x54=>TC3 match/capture 1 -// <0x55=>TC4 overflow -// <0x56=>TC4 match/capture 0 -// <0x57=>TC4 match/capture 1 -// <0x58=>TC5 overflow -// <0x59=>TC5 match/capture 0 -// <0x5A=>TC5 match/capture 1 -// <0x5B=>TC6 overflow -// <0x5C=>TC6 match/capture 0 -// <0x5D=>TC6 match/capture 1 -// <0x5E=>TC7 overflow -// <0x5F=>TC7 match/capture 0 -// <0x60=>TC7 match/capture 1 -// <0x61=>PDEC overflow -// <0x62=>PDEC error -// <0x63=>PDEC direction -// <0x64=>PDEC VLC -// <0x65=>PDEC match channel 0 -// <0x66=>PDEC match channel 1 -// <0x67=>ADC0 result ready -// <0x68=>ADC0 window monitor -// <0x69=>ADC1 result ready -// <0x6A=>ADC1 window monitor -// <0x6B=>AC comparator 0 -// <0x6C=>AC comparator 1 -// <0x6D=>AC window 0 -// <0x6E=>DAC data buffer empty 0 -// <0x6F=>DAC data buffer empty 1 -// <0x70=>DAC result ready 0 -// <0x71=>DAC result ready 1 -// <0x73=>TRNG Data Ready -// <0x74=>CCL LUT output 0 -// <0x75=>CCL LUT output 1 -// <0x76=>CCL LUT output 2 -// <0x77=>CCL LUT output 3 -// evsys_evgen_31 -#ifndef CONF_EVGEN_31 -#define CONF_EVGEN_31 0 -#endif - -// Overrun channel interrupt -// Indicates whether overrun channel interrupt is enabled or not -// evsys_ovr_31 -#ifndef CONF_OVR_31 -#define CONF_OVR_31 0 -#endif - -// Event detected interrupt -// Indicates whether event detected interrupt is enabled or not -// evsys_evd_31 -#ifndef CONF_EVD_31 -#define CONF_EVD_31 0 -#endif - -// On demand clock -// Indicates whether clock for channel is requested on demand or not -// evsys_ondemand_31 -#ifndef CONF_ONDEMAND_31 -#define CONF_ONDEMAND_31 0 -#endif - -// Run is standby mode -// Indicates whether channel is enabled in standby sleep mode -// evsys_runstdby_31 -#ifndef CONF_RUNSTDBY_31 -#define CONF_RUNSTDBY_31 0 -#endif - -// - -// RTC events -// Channel selection for RTC Tamper Event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_0 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_0 -#define CONF_CHANNEL_0 0 -#endif -// - -// PORT events -// Channel selection for PORT event 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_1 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_1 -#define CONF_CHANNEL_1 0 -#endif - -// Channel selection for PORT event 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_2 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_2 -#define CONF_CHANNEL_2 0 -#endif - -// Channel selection for PORT event 2 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_3 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_3 -#define CONF_CHANNEL_3 0 -#endif - -// Channel selection for PORT event 3 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_4 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_4 -#define CONF_CHANNEL_4 0 -#endif -// - -// DMAC events -// Channel selection for DMAC channel 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_5 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_5 -#define CONF_CHANNEL_5 0 -#endif - -// Channel selection for DMAC channel 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_6 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_6 -#define CONF_CHANNEL_6 0 -#endif - -// Channel selection for DMAC channel 2 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_7 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_7 -#define CONF_CHANNEL_7 0 -#endif - -// Channel selection for DMAC channel 3 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_8 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_8 -#define CONF_CHANNEL_8 0 -#endif - -// Channel selection for DMAC channel 4 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_9 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_9 -#define CONF_CHANNEL_9 0 -#endif - -// Channel selection for DMAC channel 5 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_10 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_10 -#define CONF_CHANNEL_10 0 -#endif - -// Channel selection for DMAC channel 6 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_11 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_11 -#define CONF_CHANNEL_11 0 -#endif - -// Channel selection for DMAC channel 7 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_12 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_12 -#define CONF_CHANNEL_12 0 -#endif -// - -// Reserved -#ifndef CONF_CHANNEL_13 -#define CONF_CHANNEL_13 0 -#endif - -#ifndef CONF_CHANNEL_14 -#define CONF_CHANNEL_14 0 -#endif - -#ifndef CONF_CHANNEL_15 -#define CONF_CHANNEL_15 0 -#endif - -#ifndef CONF_CHANNEL_16 -#define CONF_CHANNEL_16 0 -#endif -// - -// TCC events -// Channel selection for TCC0 Event 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_17 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_17 -#define CONF_CHANNEL_17 0 -#endif - -// Channel selection for TCC0 Event 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_18 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_18 -#define CONF_CHANNEL_18 0 -#endif - -// Channel selection for TCC0 match/capture 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_19 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_19 -#define CONF_CHANNEL_19 0 -#endif - -// Channel selection for TCC0 match/capture 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_20 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_20 -#define CONF_CHANNEL_20 0 -#endif - -// Channel selection for TCC0 match/capture 2 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_21 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_21 -#define CONF_CHANNEL_21 0 -#endif - -// Channel selection for TCC0 match/capture 3 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_22 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_22 -#define CONF_CHANNEL_22 0 -#endif - -// Channel selection for TCC0 match/capture 4 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_23 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_23 -#define CONF_CHANNEL_23 0 -#endif - -// Channel selection for TCC0 match/capture 5 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_24 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_24 -#define CONF_CHANNEL_24 0 -#endif - -// Channel selection for TCC1 Event 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_25 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_25 -#define CONF_CHANNEL_25 0 -#endif - -// Channel selection for TCC1 Event 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_26 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_26 -#define CONF_CHANNEL_26 0 -#endif - -// Channel selection for TCC1 match/capture 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_27 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_27 -#define CONF_CHANNEL_27 0 -#endif - -// Channel selection for TCC1 match/capture 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_28 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_28 -#define CONF_CHANNEL_28 0 -#endif - -// Channel selection for TCC1 match/capture 2 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_29 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_29 -#define CONF_CHANNEL_29 0 -#endif - -// Channel selection for TCC1 match/capture 3 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_30 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_30 -#define CONF_CHANNEL_30 0 -#endif - -// Channel selection for TCC2 Event 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_31 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_31 -#define CONF_CHANNEL_31 0 -#endif - -// Channel selection for TCC2 Event 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_32 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_32 -#define CONF_CHANNEL_32 0 -#endif - -// Channel selection for TCC2 match/capture 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_33 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_33 -#define CONF_CHANNEL_33 0 -#endif - -// Channel selection for TCC2 match/capture 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_34 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_34 -#define CONF_CHANNEL_34 0 -#endif - -// Channel selection for TCC2 match/capture 2 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_35 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_35 -#define CONF_CHANNEL_35 0 -#endif - -// Channel selection for TCC3 Event 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_36 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_36 -#define CONF_CHANNEL_36 0 -#endif - -// Channel selection for TCC3 Event 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_37 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_37 -#define CONF_CHANNEL_37 0 -#endif - -// Channel selection for TCC3 match/capture 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_38 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_38 -#define CONF_CHANNEL_38 0 -#endif - -// Channel selection for TCC3 match/capture 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_39 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_39 -#define CONF_CHANNEL_39 0 -#endif - -// Channel selection for TCC4 Event 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_40 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_40 -#define CONF_CHANNEL_40 0 -#endif - -// Channel selection for TCC4 Event 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_41 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_41 -#define CONF_CHANNEL_41 0 -#endif - -// Channel selection for TCC4 match/capture 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_42 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_42 -#define CONF_CHANNEL_42 0 -#endif - -// Channel selection for TCC4 match/capture 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_43 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_43 -#define CONF_CHANNEL_43 0 -#endif -// - -// TC events -// Channel selection for TC0 event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_44 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_44 -#define CONF_CHANNEL_44 0 -#endif - -// Channel selection for TC1 event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_45 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_45 -#define CONF_CHANNEL_45 0 -#endif - -// Channel selection for TC2 event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_46 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_46 -#define CONF_CHANNEL_46 0 -#endif - -// Channel selection for TC3 event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_47 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_47 -#define CONF_CHANNEL_47 0 -#endif - -// Channel selection for TC4 event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_48 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_48 -#define CONF_CHANNEL_48 0 -#endif - -// Channel selection for TC5 event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_49 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_49 -#define CONF_CHANNEL_49 0 -#endif - -// Channel selection for TC6 event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_50 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_50 -#define CONF_CHANNEL_50 0 -#endif - -// Channel selection for TC7 event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_51 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_51 -#define CONF_CHANNEL_51 0 -#endif -// - -// PDEC events -// Channel selection for PDEC event 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_52 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_52 -#define CONF_CHANNEL_52 0 -#endif - -// Channel selection for PDEC event 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_53 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_53 -#define CONF_CHANNEL_53 0 -#endif - -// Channel selection for PDEC event 2 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_54 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_54 -#define CONF_CHANNEL_54 0 -#endif -// - -// ADC events -// Channel selection for ADC0 start conversion event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_55 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_55 -#define CONF_CHANNEL_55 0 -#endif - -// Channel selection for ADC0 flush event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_56 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_56 -#define CONF_CHANNEL_56 0 -#endif - -// Channel selection for ADC1 start conversion event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_57 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_57 -#define CONF_CHANNEL_57 0 -#endif - -// Channel selection for ADC1 flush event -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_58 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_58 -#define CONF_CHANNEL_58 0 -#endif -// - -// AC events -// Channel selection for Start comparator event 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_59 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_59 -#define CONF_CHANNEL_59 0 -#endif - -// Channel selection for Start comparator event 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_60 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_60 -#define CONF_CHANNEL_60 0 -#endif -// - -// DAC events -// Channel selection for DAC Start event 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_61 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_61 -#define CONF_CHANNEL_61 0 -#endif - -// Channel selection for DAC Start event 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_62 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_62 -#define CONF_CHANNEL_62 0 -#endif -// - -// CCL events -// Channel selection for CCL input event 0 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_63 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_63 -#define CONF_CHANNEL_63 0 -#endif - -// Channel selection for CCL input event 1 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_64 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_64 -#define CONF_CHANNEL_64 0 -#endif - -// Channel selection for CCL input event 2 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_65 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_65 -#define CONF_CHANNEL_65 0 -#endif - -// Channel selection for CCL input event 3 -// <0x0=>No channel output selected -// <0x1=>Channel 0 -// <0x2=>Channel 1 -// <0x3=>Channel 2 -// <0x4=>Channel 3 -// <0x5=>Channel 4 -// <0x6=>Channel 5 -// <0x7=>Channel 6 -// <0x8=>Channel 7 -// <0x9=>Channel 8 -// <0xA=>Channel 9 -// <0xB=>Channel 10 -// <0xC=>Channel 11 -// <0xD=>Channel 12 -// <0xE=>Channel 13 -// <0xF=>Channel 14 -// <0x10=>Channel 15 -// <0x11=>Channel 16 -// <0x12=>Channel 17 -// <0x13=>Channel 18 -// <0x14=>Channel 19 -// <0x15=>Channel 20 -// <0x16=>Channel 21 -// <0x17=>Channel 22 -// <0x18=>Channel 23 -// <0x19=>Channel 24 -// <0x1A=>Channel 25 -// <0x1B=>Channel 26 -// <0x1C=>Channel 27 -// <0x1D=>Channel 28 -// <0x1E=>Channel 29 -// <0x1F=>Channel 30 -// <0x20=>Channel 31 -// evsys_channel_66 -// Indicates which channel is chosen for user -#ifndef CONF_CHANNEL_66 -#define CONF_CHANNEL_66 0 -#endif -// - -// <<< end of configuration section >>> - -#endif // HPL_EVSYS_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_gclk_config.h b/atmel-samd/asf4/samd51/config/hpl_gclk_config.h deleted file mode 100644 index ca1bfbdd2..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_gclk_config.h +++ /dev/null @@ -1,908 +0,0 @@ -/* Auto-generated config file hpl_gclk_config.h */ -#ifndef HPL_GCLK_CONFIG_H -#define HPL_GCLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Generic clock generator 0 configuration -// Indicates whether generic clock 0 configuration is enabled or not -// enable_gclk_gen_0 -#ifndef CONF_GCLK_GENERATOR_0_CONFIG -#define CONF_GCLK_GENERATOR_0_CONFIG 1 -#endif - -// Generic Clock Generator Control -// Generic clock generator 0 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 0 -// gclk_gen_0_oscillator -#ifndef CONF_GCLK_GEN_0_SOURCE -#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_0_runstdby -#ifndef CONF_GCLK_GEN_0_RUNSTDBY -#define CONF_GCLK_GEN_0_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_0_div_sel -#ifndef CONF_GCLK_GEN_0_DIVSEL -#define CONF_GCLK_GEN_0_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_0_oe -#ifndef CONF_GCLK_GEN_0_OE -#define CONF_GCLK_GEN_0_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_0_oov -#ifndef CONF_GCLK_GEN_0_OOV -#define CONF_GCLK_GEN_0_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_0_idc -#ifndef CONF_GCLK_GEN_0_IDC -#define CONF_GCLK_GEN_0_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_0_enable -#ifndef CONF_GCLK_GEN_0_GENEN -#define CONF_GCLK_GEN_0_GENEN 1 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 0 division <0x0000-0xFFFF> -// gclk_gen_0_div -#ifndef CONF_GCLK_GEN_0_DIV -#define CONF_GCLK_GEN_0_DIV 1 -#endif -// -// - -// Generic clock generator 1 configuration -// Indicates whether generic clock 1 configuration is enabled or not -// enable_gclk_gen_1 -#ifndef CONF_GCLK_GENERATOR_1_CONFIG -#define CONF_GCLK_GENERATOR_1_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 1 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 1 -// gclk_gen_1_oscillator -#ifndef CONF_GCLK_GEN_1_SOURCE -#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_1_runstdby -#ifndef CONF_GCLK_GEN_1_RUNSTDBY -#define CONF_GCLK_GEN_1_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_1_div_sel -#ifndef CONF_GCLK_GEN_1_DIVSEL -#define CONF_GCLK_GEN_1_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_1_oe -#ifndef CONF_GCLK_GEN_1_OE -#define CONF_GCLK_GEN_1_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_1_oov -#ifndef CONF_GCLK_GEN_1_OOV -#define CONF_GCLK_GEN_1_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_1_idc -#ifndef CONF_GCLK_GEN_1_IDC -#define CONF_GCLK_GEN_1_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_1_enable -#ifndef CONF_GCLK_GEN_1_GENEN -#define CONF_GCLK_GEN_1_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 1 division <0x0000-0xFFFF> -// gclk_gen_1_div -#ifndef CONF_GCLK_GEN_1_DIV -#define CONF_GCLK_GEN_1_DIV 1 -#endif -// -// - -// Generic clock generator 2 configuration -// Indicates whether generic clock 2 configuration is enabled or not -// enable_gclk_gen_2 -#ifndef CONF_GCLK_GENERATOR_2_CONFIG -#define CONF_GCLK_GENERATOR_2_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 2 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 2 -// gclk_gen_2_oscillator -#ifndef CONF_GCLK_GEN_2_SOURCE -#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_2_runstdby -#ifndef CONF_GCLK_GEN_2_RUNSTDBY -#define CONF_GCLK_GEN_2_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_2_div_sel -#ifndef CONF_GCLK_GEN_2_DIVSEL -#define CONF_GCLK_GEN_2_DIVSEL 1 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_2_oe -#ifndef CONF_GCLK_GEN_2_OE -#define CONF_GCLK_GEN_2_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_2_oov -#ifndef CONF_GCLK_GEN_2_OOV -#define CONF_GCLK_GEN_2_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_2_idc -#ifndef CONF_GCLK_GEN_2_IDC -#define CONF_GCLK_GEN_2_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_2_enable -#ifndef CONF_GCLK_GEN_2_GENEN -#define CONF_GCLK_GEN_2_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 2 division <0x0000-0xFFFF> -// gclk_gen_2_div -#ifndef CONF_GCLK_GEN_2_DIV -#define CONF_GCLK_GEN_2_DIV 1 -#endif -// -// - -// Generic clock generator 3 configuration -// Indicates whether generic clock 3 configuration is enabled or not -// enable_gclk_gen_3 -#ifndef CONF_GCLK_GENERATOR_3_CONFIG -#define CONF_GCLK_GENERATOR_3_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 3 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 3 -// gclk_gen_3_oscillator -#ifndef CONF_GCLK_GEN_3_SOURCE -#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_3_runstdby -#ifndef CONF_GCLK_GEN_3_RUNSTDBY -#define CONF_GCLK_GEN_3_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_3_div_sel -#ifndef CONF_GCLK_GEN_3_DIVSEL -#define CONF_GCLK_GEN_3_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_3_oe -#ifndef CONF_GCLK_GEN_3_OE -#define CONF_GCLK_GEN_3_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_3_oov -#ifndef CONF_GCLK_GEN_3_OOV -#define CONF_GCLK_GEN_3_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_3_idc -#ifndef CONF_GCLK_GEN_3_IDC -#define CONF_GCLK_GEN_3_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_3_enable -#ifndef CONF_GCLK_GEN_3_GENEN -#define CONF_GCLK_GEN_3_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 3 division <0x0000-0xFFFF> -// gclk_gen_3_div -#ifndef CONF_GCLK_GEN_3_DIV -#define CONF_GCLK_GEN_3_DIV 1 -#endif -// -// - -// Generic clock generator 4 configuration -// Indicates whether generic clock 4 configuration is enabled or not -// enable_gclk_gen_4 -#ifndef CONF_GCLK_GENERATOR_4_CONFIG -#define CONF_GCLK_GENERATOR_4_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 4 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 4 -// gclk_gen_4_oscillator -#ifndef CONF_GCLK_GEN_4_SOURCE -#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_4_runstdby -#ifndef CONF_GCLK_GEN_4_RUNSTDBY -#define CONF_GCLK_GEN_4_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_4_div_sel -#ifndef CONF_GCLK_GEN_4_DIVSEL -#define CONF_GCLK_GEN_4_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_4_oe -#ifndef CONF_GCLK_GEN_4_OE -#define CONF_GCLK_GEN_4_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_4_oov -#ifndef CONF_GCLK_GEN_4_OOV -#define CONF_GCLK_GEN_4_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_4_idc -#ifndef CONF_GCLK_GEN_4_IDC -#define CONF_GCLK_GEN_4_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_4_enable -#ifndef CONF_GCLK_GEN_4_GENEN -#define CONF_GCLK_GEN_4_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 4 division <0x0000-0xFFFF> -// gclk_gen_4_div -#ifndef CONF_GCLK_GEN_4_DIV -#define CONF_GCLK_GEN_4_DIV 1 -#endif -// -// - -// Generic clock generator 5 configuration -// Indicates whether generic clock 5 configuration is enabled or not -// enable_gclk_gen_5 -#ifndef CONF_GCLK_GENERATOR_5_CONFIG -#define CONF_GCLK_GENERATOR_5_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 5 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 5 -// gclk_gen_5_oscillator -#ifndef CONF_GCLK_GEN_5_SOURCE -#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_5_runstdby -#ifndef CONF_GCLK_GEN_5_RUNSTDBY -#define CONF_GCLK_GEN_5_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_5_div_sel -#ifndef CONF_GCLK_GEN_5_DIVSEL -#define CONF_GCLK_GEN_5_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_5_oe -#ifndef CONF_GCLK_GEN_5_OE -#define CONF_GCLK_GEN_5_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_5_oov -#ifndef CONF_GCLK_GEN_5_OOV -#define CONF_GCLK_GEN_5_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_5_idc -#ifndef CONF_GCLK_GEN_5_IDC -#define CONF_GCLK_GEN_5_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_5_enable -#ifndef CONF_GCLK_GEN_5_GENEN -#define CONF_GCLK_GEN_5_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 5 division <0x0000-0xFFFF> -// gclk_gen_5_div -#ifndef CONF_GCLK_GEN_5_DIV -#define CONF_GCLK_GEN_5_DIV 1 -#endif -// -// - -// Generic clock generator 6 configuration -// Indicates whether generic clock 6 configuration is enabled or not -// enable_gclk_gen_6 -#ifndef CONF_GCLK_GENERATOR_6_CONFIG -#define CONF_GCLK_GENERATOR_6_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 6 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 6 -// gclk_gen_6_oscillator -#ifndef CONF_GCLK_GEN_6_SOURCE -#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_6_runstdby -#ifndef CONF_GCLK_GEN_6_RUNSTDBY -#define CONF_GCLK_GEN_6_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_6_div_sel -#ifndef CONF_GCLK_GEN_6_DIVSEL -#define CONF_GCLK_GEN_6_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_6_oe -#ifndef CONF_GCLK_GEN_6_OE -#define CONF_GCLK_GEN_6_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_6_oov -#ifndef CONF_GCLK_GEN_6_OOV -#define CONF_GCLK_GEN_6_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_6_idc -#ifndef CONF_GCLK_GEN_6_IDC -#define CONF_GCLK_GEN_6_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_6_enable -#ifndef CONF_GCLK_GEN_6_GENEN -#define CONF_GCLK_GEN_6_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 6 division <0x0000-0xFFFF> -// gclk_gen_6_div -#ifndef CONF_GCLK_GEN_6_DIV -#define CONF_GCLK_GEN_6_DIV 1 -#endif -// -// - -// Generic clock generator 7 configuration -// Indicates whether generic clock 7 configuration is enabled or not -// enable_gclk_gen_7 -#ifndef CONF_GCLK_GENERATOR_7_CONFIG -#define CONF_GCLK_GENERATOR_7_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 7 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 7 -// gclk_gen_7_oscillator -#ifndef CONF_GCLK_GEN_7_SOURCE -#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_7_runstdby -#ifndef CONF_GCLK_GEN_7_RUNSTDBY -#define CONF_GCLK_GEN_7_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_7_div_sel -#ifndef CONF_GCLK_GEN_7_DIVSEL -#define CONF_GCLK_GEN_7_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_7_oe -#ifndef CONF_GCLK_GEN_7_OE -#define CONF_GCLK_GEN_7_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_7_oov -#ifndef CONF_GCLK_GEN_7_OOV -#define CONF_GCLK_GEN_7_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_7_idc -#ifndef CONF_GCLK_GEN_7_IDC -#define CONF_GCLK_GEN_7_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_7_enable -#ifndef CONF_GCLK_GEN_7_GENEN -#define CONF_GCLK_GEN_7_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 7 division <0x0000-0xFFFF> -// gclk_gen_7_div -#ifndef CONF_GCLK_GEN_7_DIV -#define CONF_GCLK_GEN_7_DIV 1 -#endif -// -// - -// Generic clock generator 8 configuration -// Indicates whether generic clock 8 configuration is enabled or not -// enable_gclk_gen_8 -#ifndef CONF_GCLK_GENERATOR_8_CONFIG -#define CONF_GCLK_GENERATOR_8_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 8 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 8 -// gclk_gen_8_oscillator -#ifndef CONF_GCLK_GEN_8_SOURCE -#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_8_runstdby -#ifndef CONF_GCLK_GEN_8_RUNSTDBY -#define CONF_GCLK_GEN_8_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_8_div_sel -#ifndef CONF_GCLK_GEN_8_DIVSEL -#define CONF_GCLK_GEN_8_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_8_oe -#ifndef CONF_GCLK_GEN_8_OE -#define CONF_GCLK_GEN_8_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_8_oov -#ifndef CONF_GCLK_GEN_8_OOV -#define CONF_GCLK_GEN_8_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_8_idc -#ifndef CONF_GCLK_GEN_8_IDC -#define CONF_GCLK_GEN_8_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_8_enable -#ifndef CONF_GCLK_GEN_8_GENEN -#define CONF_GCLK_GEN_8_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 8 division <0x0000-0xFFFF> -// gclk_gen_8_div -#ifndef CONF_GCLK_GEN_8_DIV -#define CONF_GCLK_GEN_8_DIV 1 -#endif -// -// - -// Generic clock generator 9 configuration -// Indicates whether generic clock 9 configuration is enabled or not -// enable_gclk_gen_9 -#ifndef CONF_GCLK_GENERATOR_9_CONFIG -#define CONF_GCLK_GENERATOR_9_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 9 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 9 -// gclk_gen_9_oscillator -#ifndef CONF_GCLK_GEN_9_SOURCE -#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_9_runstdby -#ifndef CONF_GCLK_GEN_9_RUNSTDBY -#define CONF_GCLK_GEN_9_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_9_div_sel -#ifndef CONF_GCLK_GEN_9_DIVSEL -#define CONF_GCLK_GEN_9_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_9_oe -#ifndef CONF_GCLK_GEN_9_OE -#define CONF_GCLK_GEN_9_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_9_oov -#ifndef CONF_GCLK_GEN_9_OOV -#define CONF_GCLK_GEN_9_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_9_idc -#ifndef CONF_GCLK_GEN_9_IDC -#define CONF_GCLK_GEN_9_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_9_enable -#ifndef CONF_GCLK_GEN_9_GENEN -#define CONF_GCLK_GEN_9_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 9 division <0x0000-0xFFFF> -// gclk_gen_9_div -#ifndef CONF_GCLK_GEN_9_DIV -#define CONF_GCLK_GEN_9_DIV 1 -#endif -// -// - -// Generic clock generator 10 configuration -// Indicates whether generic clock 10 configuration is enabled or not -// enable_gclk_gen_10 -#ifndef CONF_GCLK_GENERATOR_10_CONFIG -#define CONF_GCLK_GENERATOR_10_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 10 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 10 -// gclk_gen_10_oscillator -#ifndef CONF_GCLK_GEN_10_SOURCE -#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_10_runstdby -#ifndef CONF_GCLK_GEN_10_RUNSTDBY -#define CONF_GCLK_GEN_10_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_10_div_sel -#ifndef CONF_GCLK_GEN_10_DIVSEL -#define CONF_GCLK_GEN_10_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_10_oe -#ifndef CONF_GCLK_GEN_10_OE -#define CONF_GCLK_GEN_10_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_10_oov -#ifndef CONF_GCLK_GEN_10_OOV -#define CONF_GCLK_GEN_10_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_10_idc -#ifndef CONF_GCLK_GEN_10_IDC -#define CONF_GCLK_GEN_10_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_10_enable -#ifndef CONF_GCLK_GEN_10_GENEN -#define CONF_GCLK_GEN_10_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 10 division <0x0000-0xFFFF> -// gclk_gen_10_div -#ifndef CONF_GCLK_GEN_10_DIV -#define CONF_GCLK_GEN_10_DIV 1 -#endif -// -// - -// Generic clock generator 11 configuration -// Indicates whether generic clock 11 configuration is enabled or not -// enable_gclk_gen_11 -#ifndef CONF_GCLK_GENERATOR_11_CONFIG -#define CONF_GCLK_GENERATOR_11_CONFIG 0 -#endif - -// Generic Clock Generator Control -// Generic clock generator 11 source// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator input pad -// Generic clock generator 1 -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// Digital Frequency Locked Loop (DFLL48M) -// Digital Phase Locked Loop (DPLL0) -// Digital Phase Locked Loop (DPLL1) -// This defines the clock source for generic clock generator 11 -// gclk_gen_11_oscillator -#ifndef CONF_GCLK_GEN_11_SOURCE -#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// gclk_arch_gen_11_runstdby -#ifndef CONF_GCLK_GEN_11_RUNSTDBY -#define CONF_GCLK_GEN_11_RUNSTDBY 0 -#endif - -// Divide Selection -// Indicates whether Divide Selection is enabled or not -// gclk_gen_11_div_sel -#ifndef CONF_GCLK_GEN_11_DIVSEL -#define CONF_GCLK_GEN_11_DIVSEL 0 -#endif - -// Output Enable -// Indicates whether Output Enable is enabled or not -// gclk_arch_gen_11_oe -#ifndef CONF_GCLK_GEN_11_OE -#define CONF_GCLK_GEN_11_OE 0 -#endif - -// Output Off Value -// Indicates whether Output Off Value is enabled or not -// gclk_arch_gen_11_oov -#ifndef CONF_GCLK_GEN_11_OOV -#define CONF_GCLK_GEN_11_OOV 0 -#endif - -// Improve Duty Cycle -// Indicates whether Improve Duty Cycle is enabled or not -// gclk_arch_gen_11_idc -#ifndef CONF_GCLK_GEN_11_IDC -#define CONF_GCLK_GEN_11_IDC 0 -#endif - -// Generic Clock Generator Enable -// Indicates whether Generic Clock Generator Enable is enabled or not -// gclk_arch_gen_11_enable -#ifndef CONF_GCLK_GEN_11_GENEN -#define CONF_GCLK_GEN_11_GENEN 0 -#endif -// - -// Generic Clock Generator Division -// Generic clock generator 11 division <0x0000-0xFFFF> -// gclk_gen_11_div -#ifndef CONF_GCLK_GEN_11_DIV -#define CONF_GCLK_GEN_11_DIV 1 -#endif -// -// - -// <<< end of configuration section >>> - -#endif // HPL_GCLK_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_mclk_config.h b/atmel-samd/asf4/samd51/config/hpl_mclk_config.h deleted file mode 100644 index a5a7de53c..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_mclk_config.h +++ /dev/null @@ -1,104 +0,0 @@ -/* Auto-generated config file hpl_mclk_config.h */ -#ifndef HPL_MCLK_CONFIG_H -#define HPL_MCLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -// System Configuration -// Indicates whether configuration for system is enabled or not -// enable_cpu_clock -#ifndef CONF_SYSTEM_CONFIG -#define CONF_SYSTEM_CONFIG 1 -#endif - -// Basic settings -// CPU Clock source -// Generic clock generator 0 -// This defines the clock source for the CPU -// cpu_clock_source -#ifndef CONF_CPU_SRC -#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// CPU Clock Division Factor -// 1 -// 2 -// 4 -// 8 -// 16 -// 32 -// 64 -// 128 -// Prescalar for CPU clock -// cpu_div -#ifndef CONF_MCLK_CPUDIV -#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val -#endif -// Low Power Clock Division -// Divide by 1 -// Divide by 2 -// Divide by 4 -// Divide by 8 -// Divide by 16 -// Divide by 32 -// Divide by 64 -// Divide by 128 -// mclk_arch_lpdiv -#ifndef CONF_MCLK_LPDIV -#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val -#endif - -// Backup Clock Division -// Divide by 1 -// Divide by 2 -// Divide by 4 -// Divide by 8 -// Divide by 16 -// Divide by 32 -// Divide by 64 -// Divide by 128 -// mclk_arch_bupdiv -#ifndef CONF_MCLK_BUPDIV -#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val -#endif -// High-Speed Clock Division -// Divide by 1 -// mclk_arch_hsdiv -#ifndef CONF_MCLK_HSDIV -#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val -#endif -// - -// NVM Settings -// NVM Wait States -// These bits select the number of wait states for a read operation. -// <0=> 0 -// <1=> 1 -// <2=> 2 -// <3=> 3 -// <4=> 4 -// <5=> 5 -// <6=> 6 -// <7=> 7 -// <8=> 8 -// <9=> 9 -// <10=> 10 -// <11=> 11 -// <12=> 12 -// <13=> 13 -// <14=> 14 -// <15=> 15 -// nvm_wait_states -#ifndef CONF_NVM_WAIT_STATE -#define CONF_NVM_WAIT_STATE 0 -#endif - -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_MCLK_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_nvmctrl_config.h b/atmel-samd/asf4/samd51/config/hpl_nvmctrl_config.h deleted file mode 100644 index daaba85d4..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_nvmctrl_config.h +++ /dev/null @@ -1,36 +0,0 @@ -/* Auto-generated config file hpl_nvmctrl_config.h */ -#ifndef HPL_NVMCTRL_CONFIG_H -#define HPL_NVMCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic Settings - -// Power Reduction Mode During Sleep -// <0x00=> Wake On Access -// <0x01=> Wake Up Instant -// <0x03=> Disabled -// nvm_arch_sleepprm -#ifndef CONF_NVM_SLEEPPRM -#define CONF_NVM_SLEEPPRM 0 -#endif - -// AHB0 Cache Disable -// Indicate whether AHB0 cache is disable or not -// nvm_arch_cache0 -#ifndef CONF_NVM_CACHE0 -#define CONF_NVM_CACHE0 0 -#endif - -// AHB1 Cache Disable -// Indicate whether AHB1 cache is disable or not -// nvm_arch_cache1 -#ifndef CONF_NVM_CACHE1 -#define CONF_NVM_CACHE1 0 -#endif - -// - -// <<< end of configuration section >>> - -#endif // HPL_NVMCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_osc32kctrl_config.h b/atmel-samd/asf4/samd51/config/hpl_osc32kctrl_config.h deleted file mode 100644 index b6a74aaa7..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_osc32kctrl_config.h +++ /dev/null @@ -1,163 +0,0 @@ -/* Auto-generated config file hpl_osc32kctrl_config.h */ -#ifndef HPL_OSC32KCTRL_CONFIG_H -#define HPL_OSC32KCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// RTC Source configuration -// enable_rtc_source -#ifndef CONF_RTCCTRL_CONFIG -#define CONF_RTCCTRL_CONFIG 0 -#endif - -// RTC source control -// RTC Clock Source Selection -// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) -// 32kHz External Crystal Oscillator (XOSC32K) -// This defines the clock source for RTC -// rtc_source_oscillator -#ifndef CONF_RTCCTRL_SRC -#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K -#endif - -// Use 1 kHz output -// rtc_1khz_selection -#ifndef CONF_RTCCTRL_1KHZ -#define CONF_RTCCTRL_1KHZ 1 -#endif - -#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K -#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) -#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K -#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) -#else -#error unexpected CONF_RTCCTRL_SRC -#endif - -// -// - -// 32kHz External Crystal Oscillator Configuration -// Indicates whether configuration for External 32K Osc is enabled or not -// enable_xosc32k -#ifndef CONF_XOSC32K_CONFIG -#define CONF_XOSC32K_CONFIG 0 -#endif - -// 32kHz External Crystal Oscillator Control -// Oscillator enable -// Indicates whether 32kHz External Crystal Oscillator is enabled or not -// xosc32k_arch_enable -#ifndef CONF_XOSC32K_ENABLE -#define CONF_XOSC32K_ENABLE 0 -#endif - -// Start-Up Time -// <0x0=>62592us -// <0x1=>125092us -// <0x2=>500092us -// <0x3=>1000092us -// <0x4=>2000092us -// <0x5=>4000092us -// <0x6=>8000092us -// xosc32k_arch_startup -#ifndef CONF_XOSC32K_STARTUP -#define CONF_XOSC32K_STARTUP 0x0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// xosc32k_arch_ondemand -#ifndef CONF_XOSC32K_ONDEMAND -#define CONF_XOSC32K_ONDEMAND 1 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// xosc32k_arch_runstdby -#ifndef CONF_XOSC32K_RUNSTDBY -#define CONF_XOSC32K_RUNSTDBY 0 -#endif - -// 1kHz Output Enable -// Indicates whether 1kHz Output is enabled or not -// xosc32k_arch_en1k -#ifndef CONF_XOSC32K_EN1K -#define CONF_XOSC32K_EN1K 0 -#endif - -// 32kHz Output Enable -// Indicates whether 32kHz Output is enabled or not -// xosc32k_arch_en32k -#ifndef CONF_XOSC32K_EN32K -#define CONF_XOSC32K_EN32K 0 -#endif - -// Clock Switch Back -// Indicates whether Clock Switch Back is enabled or not -// xosc32k_arch_swben -#ifndef CONF_XOSC32K_SWBEN -#define CONF_XOSC32K_SWBEN 0 -#endif - -// Clock Failure Detector -// Indicates whether Clock Failure Detector is enabled or not -// xosc32k_arch_cfden -#ifndef CONF_XOSC32K_CFDEN -#define CONF_XOSC32K_CFDEN 0 -#endif - -// Clock Failure Detector Event Out -// Indicates whether Clock Failure Detector Event Out is enabled or not -// xosc32k_arch_cfdeo -#ifndef CONF_XOSC32K_CFDEO -#define CONF_XOSC32K_CFDEO 0 -#endif - -// Crystal connected to XIN32/XOUT32 Enable -// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// xosc32k_arch_xtalen -#ifndef CONF_XOSC32K_XTALEN -#define CONF_XOSC32K_XTALEN 0 -#endif - -// Control Gain Mode -// <0x0=>Low Power mode -// <0x1=>Standard mode -// <0x2=>High Speed mode -// xosc32k_arch_cgm -#ifndef CONF_XOSC32K_CGM -#define CONF_XOSC32K_CGM 0x1 -#endif - -// -// - -// 32kHz Ultra Low Power Internal Oscillator Configuration -// Indicates whether configuration for OSCULP32K is enabled or not -// enable_osculp32k -#ifndef CONF_OSCULP32K_CONFIG -#define CONF_OSCULP32K_CONFIG 1 -#endif - -// 32kHz Ultra Low Power Internal Oscillator Control - -// Oscillator Calibration Control -// Indicates whether Oscillator Calibration is enabled or not -// osculp32k_calib_enable -#ifndef CONF_OSCULP32K_CALIB_ENABLE -#define CONF_OSCULP32K_CALIB_ENABLE 0 -#endif - -// Oscillator Calibration <0x0-0x3F> -// osculp32k_calib -#ifndef CONF_OSCULP32K_CALIB -#define CONF_OSCULP32K_CALIB 0x0 -#endif - -// -// - -// <<< end of configuration section >>> - -#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_oscctrl_config.h b/atmel-samd/asf4/samd51/config/hpl_oscctrl_config.h deleted file mode 100644 index 63173629e..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_oscctrl_config.h +++ /dev/null @@ -1,634 +0,0 @@ -/* Auto-generated config file hpl_oscctrl_config.h */ -#ifndef HPL_OSCCTRL_CONFIG_H -#define HPL_OSCCTRL_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// External Multipurpose Crystal Oscillator Configuration -// Indicates whether configuration for XOSC0 is enabled or not -// enable_xosc0 -#ifndef CONF_XOSC0_CONFIG -#define CONF_XOSC0_CONFIG 0 -#endif - -// Frequency <8000000-48000000> -// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. -// xosc0_frequency -#ifndef CONF_XOSC_FREQUENCY -#define CONF_XOSC0_FREQUENCY 12000000 -#endif - -// External Multipurpose Crystal Oscillator Control -// Oscillator enable -// Indicates whether External Multipurpose Crystal Oscillator is enabled or not -// xosc0_arch_enable -#ifndef CONF_XOSC0_ENABLE -#define CONF_XOSC0_ENABLE 0 -#endif - -// Start-Up Time -// <0x0=>31us -// <0x1=>61us -// <0x2=>122us -// <0x3=>244us -// <0x4=>488us -// <0x5=>977us -// <0x6=>1953us -// <0x7=>3906us -// <0x8=>7813us -// <0x9=>15625us -// <0xA=>31250us -// <0xB=>62500us -// <0xC=>125000us -// <0xD=>250000us -// <0xE=>500000us -// <0xF=>1000000us -// xosc0_arch_startup -#ifndef CONF_XOSC0_STARTUP -#define CONF_XOSC0_STARTUP 0 -#endif - -// Clock Switch Back -// Indicates whether Clock Switch Back is enabled or not -// xosc0_arch_swben -#ifndef CONF_XOSC0_SWBEN -#define CONF_XOSC0_SWBEN 0 -#endif - -// Clock Failure Detector -// Indicates whether Clock Failure Detector is enabled or not -// xosc0_arch_cfden -#ifndef CONF_XOSC0_CFDEN -#define CONF_XOSC0_CFDEN 0 -#endif - -// Automatic Loop Control Enable -// Indicates whether Automatic Loop Control is enabled or not -// xosc0_arch_enalc -#ifndef CONF_XOSC0_ENALC -#define CONF_XOSC0_ENALC 0 -#endif - -// Low Buffer Gain Enable -// Indicates whether Low Buffer Gain is enabled or not -// xosc0_arch_lowbufgain -#ifndef CONF_XOSC0_LOWBUFGAIN -#define CONF_XOSC0_LOWBUFGAIN 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// xosc0_arch_ondemand -#ifndef CONF_XOSC0_ONDEMAND -#define CONF_XOSC0_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// xosc0_arch_runstdby -#ifndef CONF_XOSC0_RUNSTDBY -#define CONF_XOSC0_RUNSTDBY 0 -#endif - -// Crystal connected to XIN/XOUT Enable -// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// xosc0_arch_xtalen -#ifndef CONF_XOSC0_XTALEN -#define CONF_XOSC0_XTALEN 0 -#endif -// -// - -#if CONF_XOSC0_FREQUENCY >= 32000000 -#define CONF_XOSC0_CFDPRESC 0x0 -#define CONF_XOSC0_IMULT 0x7 -#define CONF_XOSC0_IPTAT 0x3 -#elif CONF_XOSC0_FREQUENCY >= 24000000 -#define CONF_XOSC0_CFDPRESC 0x1 -#define CONF_XOSC0_IMULT 0x6 -#define CONF_XOSC0_IPTAT 0x3 -#elif CONF_XOSC0_FREQUENCY >= 16000000 -#define CONF_XOSC0_CFDPRESC 0x2 -#define CONF_XOSC0_IMULT 0x5 -#define CONF_XOSC0_IPTAT 0x3 -#elif CONF_XOSC0_FREQUENCY >= 8000000 -#define CONF_XOSC0_CFDPRESC 0x3 -#define CONF_XOSC0_IMULT 0x4 -#define CONF_XOSC0_IPTAT 0x3 -#endif - -// External Multipurpose Crystal Oscillator Configuration -// Indicates whether configuration for XOSC1 is enabled or not -// enable_xosc1 -#ifndef CONF_XOSC1_CONFIG -#define CONF_XOSC1_CONFIG 1 -#endif - -// Frequency <8000000-48000000> -// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. -// xosc1_frequency -#ifndef CONF_XOSC_FREQUENCY -#define CONF_XOSC1_FREQUENCY 12000000 -#endif - -// External Multipurpose Crystal Oscillator Control -// Oscillator enable -// Indicates whether External Multipurpose Crystal Oscillator is enabled or not -// xosc1_arch_enable -#ifndef CONF_XOSC1_ENABLE -#define CONF_XOSC1_ENABLE 1 -#endif - -// Start-Up Time -// <0x0=>31us -// <0x1=>61us -// <0x2=>122us -// <0x3=>244us -// <0x4=>488us -// <0x5=>977us -// <0x6=>1953us -// <0x7=>3906us -// <0x8=>7813us -// <0x9=>15625us -// <0xA=>31250us -// <0xB=>62500us -// <0xC=>125000us -// <0xD=>250000us -// <0xE=>500000us -// <0xF=>1000000us -// xosc1_arch_startup -#ifndef CONF_XOSC1_STARTUP -#define CONF_XOSC1_STARTUP 0 -#endif - -// Clock Switch Back -// Indicates whether Clock Switch Back is enabled or not -// xosc1_arch_swben -#ifndef CONF_XOSC1_SWBEN -#define CONF_XOSC1_SWBEN 0 -#endif - -// Clock Failure Detector -// Indicates whether Clock Failure Detector is enabled or not -// xosc1_arch_cfden -#ifndef CONF_XOSC1_CFDEN -#define CONF_XOSC1_CFDEN 0 -#endif - -// Automatic Loop Control Enable -// Indicates whether Automatic Loop Control is enabled or not -// xosc1_arch_enalc -#ifndef CONF_XOSC1_ENALC -#define CONF_XOSC1_ENALC 0 -#endif - -// Low Buffer Gain Enable -// Indicates whether Low Buffer Gain is enabled or not -// xosc1_arch_lowbufgain -#ifndef CONF_XOSC1_LOWBUFGAIN -#define CONF_XOSC1_LOWBUFGAIN 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// xosc1_arch_ondemand -#ifndef CONF_XOSC1_ONDEMAND -#define CONF_XOSC1_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// xosc1_arch_runstdby -#ifndef CONF_XOSC1_RUNSTDBY -#define CONF_XOSC1_RUNSTDBY 0 -#endif - -// Crystal connected to XIN/XOUT Enable -// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not -// xosc1_arch_xtalen -#ifndef CONF_XOSC1_XTALEN -#define CONF_XOSC1_XTALEN 1 -#endif -// -// - -#if CONF_XOSC1_FREQUENCY >= 32000000 -#define CONF_XOSC1_CFDPRESC 0x0 -#define CONF_XOSC1_IMULT 0x7 -#define CONF_XOSC1_IPTAT 0x3 -#elif CONF_XOSC1_FREQUENCY >= 24000000 -#define CONF_XOSC1_CFDPRESC 0x1 -#define CONF_XOSC1_IMULT 0x6 -#define CONF_XOSC1_IPTAT 0x3 -#elif CONF_XOSC1_FREQUENCY >= 16000000 -#define CONF_XOSC1_CFDPRESC 0x2 -#define CONF_XOSC1_IMULT 0x5 -#define CONF_XOSC1_IPTAT 0x3 -#elif CONF_XOSC1_FREQUENCY >= 8000000 -#define CONF_XOSC1_CFDPRESC 0x3 -#define CONF_XOSC1_IMULT 0x4 -#define CONF_XOSC1_IPTAT 0x3 -#endif - -// DFLL Configuration -// Indicates whether configuration for DFLL is enabled or not -// enable_dfll -#ifndef CONF_DFLL_CONFIG -#define CONF_DFLL_CONFIG 0 -#endif - -// Reference Clock Source -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Generic clock generator 8 -// Generic clock generator 9 -// Generic clock generator 10 -// Generic clock generator 11 -// Select the clock source -// dfll_ref_clock -#ifndef CONF_DFLL_GCLK -#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -// Digital Frequency Locked Loop Control -// DFLL Enable -// Indicates whether DFLL is enabled or not -// dfll_arch_enable -#ifndef CONF_DFLL_ENABLE -#define CONF_DFLL_ENABLE 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// dfll_arch_ondemand -#ifndef CONF_DFLL_ONDEMAND -#define CONF_DFLL_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// dfll_arch_runstdby -#ifndef CONF_DFLL_RUNSTDBY -#define CONF_DFLL_RUNSTDBY 0 -#endif - -// USB Clock Recovery Mode -// Indicates whether USB Clock Recovery Mode is enabled or not -// dfll_arch_usbcrm -#ifndef CONF_DFLL_USBCRM -#define CONF_DFLL_USBCRM 0 -#endif - -// Wait Lock -// Indicates whether Wait Lock is enabled or not -// dfll_arch_waitlock -#ifndef CONF_DFLL_WAITLOCK -#define CONF_DFLL_WAITLOCK 1 -#endif - -// Bypass Coarse Lock -// Indicates whether Bypass Coarse Lock is enabled or not -// dfll_arch_bplckc -#ifndef CONF_DFLL_BPLCKC -#define CONF_DFLL_BPLCKC 0 -#endif - -// Quick Lock Disable -// Indicates whether Quick Lock Disable is enabled or not -// dfll_arch_qldis -#ifndef CONF_DFLL_QLDIS -#define CONF_DFLL_QLDIS 0 -#endif - -// Chill Cycle Disable -// Indicates whether Chill Cycle Disable is enabled or not -// dfll_arch_ccdis -#ifndef CONF_DFLL_CCDIS -#define CONF_DFLL_CCDIS 0 -#endif - -// Lose Lock After Wake -// Indicates whether Lose Lock After Wake is enabled or not -// dfll_arch_llaw -#ifndef CONF_DFLL_LLAW -#define CONF_DFLL_LLAW 0 -#endif - -// Stable DFLL Frequency -// Indicates whether Stable DFLL Frequency is enabled or not -// dfll_arch_stable -#ifndef CONF_DFLL_STABLE -#define CONF_DFLL_STABLE 0 -#endif - -// Operating Mode Selection -// <0=>Open Loop Mode -// <1=>Closed Loop Mode -// dfll_mode -#ifndef CONF_DFLL_MODE -#define CONF_DFLL_MODE 0x0 -#endif - -// Coarse Maximum Step <0x0-0x1F> -// dfll_arch_cstep -#ifndef CONF_DFLL_CSTEP -#define CONF_DFLL_CSTEP 0x1 -#endif - -// Fine Maximum Step <0x0-0xFF> -// dfll_arch_fstep -#ifndef CONF_DFLL_FSTEP -#define CONF_DFLL_FSTEP 0x1 -#endif - -// DFLL Multiply Factor <0x0-0xFFFF> -// dfll_mul -#ifndef CONF_DFLL_MUL -#define CONF_DFLL_MUL 0x0 -#endif - -// DFLL Calibration Overwrite -// Indicates whether Overwrite Calibration value of DFLL -// dfll_arch_calibration -#ifndef CONF_DFLL_OVERWRITE_CALIBRATION -#define CONF_DFLL_OVERWRITE_CALIBRATION 0 -#endif - -// Coarse Value <0x0-0x3F> -// dfll_arch_coarse -#ifndef CONF_DFLL_COARSE -#define CONF_DFLL_COARSE (0x1f / 4) -#endif - -// Fine Value <0x0-0xFF> -// dfll_arch_fine -#ifndef CONF_DFLL_FINE -#define CONF_DFLL_FINE (0x80) -#endif - -// - -// - -// - -// FDPLL0 Configuration -// Indicates whether configuration for FDPLL0 is enabled or not -// enable_fdpll0 -#ifndef CONF_FDPLL0_CONFIG -#define CONF_FDPLL0_CONFIG 0 -#endif - -// Reference Clock Source -// 32kHz External Crystal Oscillator (XOSC32K) -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Generic clock generator 8 -// Generic clock generator 9 -// Generic clock generator 10 -// Generic clock generator 11 -// Select the clock source. -// fdpll0_ref_clock -#ifndef CONF_FDPLL0_GCLK -#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K -#endif - -// Digital Phase Locked Loop Control -// Enable -// Indicates whether Digital Phase Locked Loop is enabled or not -// fdpll0_arch_enable -#ifndef CONF_FDPLL0_ENABLE -#define CONF_FDPLL0_ENABLE 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// fdpll0_arch_ondemand -#ifndef CONF_FDPLL0_ONDEMAND -#define CONF_FDPLL0_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// fdpll0_arch_runstdby -#ifndef CONF_FDPLL0_RUNSTDBY -#define CONF_FDPLL0_RUNSTDBY 0 -#endif - -// Loop Divider Ratio Fractional Part <0x0-0x1F> -// fdpll0_ldrfrac -#ifndef CONF_FDPLL0_LDRFRAC -#define CONF_FDPLL0_LDRFRAC 0xd -#endif - -// Loop Divider Ratio Integer Part <0x0-0x1FFF> -// fdpll0_ldr -#ifndef CONF_FDPLL0_LDR -#define CONF_FDPLL0_LDR 0x5b7 -#endif - -// Clock Divider <0x0-0x7FF> -// fdpll0_clock_div -#ifndef CONF_FDPLL0_DIV -#define CONF_FDPLL0_DIV 0x0 -#endif - -// DCO Filter Enable -// Indicates whether DCO Filter Enable is enabled or not -// fdpll0_arch_dcoen -#ifndef CONF_FDPLL0_DCOEN -#define CONF_FDPLL0_DCOEN 0 -#endif - -// Sigma-Delta DCO Filter Selection <0x0-0x7> -// fdpll0_clock_dcofilter -#ifndef CONF_FDPLL0_DCOFILTER -#define CONF_FDPLL0_DCOFILTER 0x0 -#endif - -// Lock Bypass -// Indicates whether Lock Bypass is enabled or not -// fdpll0_arch_lbypass -#ifndef CONF_FDPLL0_LBYPASS -#define CONF_FDPLL0_LBYPASS 0 -#endif - -// Lock Time -// <0x0=>No time-out, automatic lock -// <0x4=>The Time-out if no lock within 800 us -// <0x5=>The Time-out if no lock within 900 us -// <0x6=>The Time-out if no lock within 1 ms -// <0x7=>The Time-out if no lock within 11 ms -// fdpll0_arch_ltime -#ifndef CONF_FDPLL0_LTIME -#define CONF_FDPLL0_LTIME 0x0 -#endif - -// Reference Clock Selection -// <0x0=>GCLK clock reference -// <0x1=>XOSC32K clock reference -// <0x2=>XOSC0 clock reference -// <0x3=>XOSC1 clock reference -// fdpll0_arch_refclk -#ifndef CONF_FDPLL0_REFCLK -#define CONF_FDPLL0_REFCLK 0x1 -#endif - -// Wake Up Fast -// Indicates whether Wake Up Fast is enabled or not -// fdpll0_arch_wuf -#ifndef CONF_FDPLL0_WUF -#define CONF_FDPLL0_WUF 0 -#endif - -// Proportional Integral Filter Selection <0x0-0xF> -// fdpll0_arch_filter -#ifndef CONF_FDPLL0_FILTER -#define CONF_FDPLL0_FILTER 0x0 -#endif - -// -// -// FDPLL1 Configuration -// Indicates whether configuration for FDPLL1 is enabled or not -// enable_fdpll1 -#ifndef CONF_FDPLL1_CONFIG -#define CONF_FDPLL1_CONFIG 0 -#endif - -// Reference Clock Source -// 32kHz External Crystal Oscillator (XOSC32K) -// External Crystal Oscillator 8-48MHz (XOSC0) -// External Crystal Oscillator 8-48MHz (XOSC1) -// Generic clock generator 0 -// Generic clock generator 1 -// Generic clock generator 2 -// Generic clock generator 3 -// Generic clock generator 4 -// Generic clock generator 5 -// Generic clock generator 6 -// Generic clock generator 7 -// Generic clock generator 8 -// Generic clock generator 9 -// Generic clock generator 10 -// Generic clock generator 11 -// Select the clock source. -// fdpll1_ref_clock -#ifndef CONF_FDPLL1_GCLK -#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K -#endif - -// Digital Phase Locked Loop Control -// Enable -// Indicates whether Digital Phase Locked Loop is enabled or not -// fdpll1_arch_enable -#ifndef CONF_FDPLL1_ENABLE -#define CONF_FDPLL1_ENABLE 0 -#endif - -// On Demand Control -// Indicates whether On Demand Control is enabled or not -// fdpll1_arch_ondemand -#ifndef CONF_FDPLL1_ONDEMAND -#define CONF_FDPLL1_ONDEMAND 0 -#endif - -// Run in Standby -// Indicates whether Run in Standby is enabled or not -// fdpll1_arch_runstdby -#ifndef CONF_FDPLL1_RUNSTDBY -#define CONF_FDPLL1_RUNSTDBY 0 -#endif - -// Loop Divider Ratio Fractional Part <0x0-0x1F> -// fdpll1_ldrfrac -#ifndef CONF_FDPLL1_LDRFRAC -#define CONF_FDPLL1_LDRFRAC 0xd -#endif - -// Loop Divider Ratio Integer Part <0x0-0x1FFF> -// fdpll1_ldr -#ifndef CONF_FDPLL1_LDR -#define CONF_FDPLL1_LDR 0x5b7 -#endif - -// Clock Divider <0x0-0x7FF> -// fdpll1_clock_div -#ifndef CONF_FDPLL1_DIV -#define CONF_FDPLL1_DIV 0x0 -#endif - -// DCO Filter Enable -// Indicates whether DCO Filter Enable is enabled or not -// fdpll1_arch_dcoen -#ifndef CONF_FDPLL1_DCOEN -#define CONF_FDPLL1_DCOEN 0 -#endif - -// Sigma-Delta DCO Filter Selection <0x0-0x7> -// fdpll1_clock_dcofilter -#ifndef CONF_FDPLL1_DCOFILTER -#define CONF_FDPLL1_DCOFILTER 0x0 -#endif - -// Lock Bypass -// Indicates whether Lock Bypass is enabled or not -// fdpll1_arch_lbypass -#ifndef CONF_FDPLL1_LBYPASS -#define CONF_FDPLL1_LBYPASS 0 -#endif - -// Lock Time -// <0x0=>No time-out, automatic lock -// <0x4=>The Time-out if no lock within 800 us -// <0x5=>The Time-out if no lock within 900 us -// <0x6=>The Time-out if no lock within 1 ms -// <0x7=>The Time-out if no lock within 11 ms -// fdpll1_arch_ltime -#ifndef CONF_FDPLL1_LTIME -#define CONF_FDPLL1_LTIME 0x0 -#endif - -// Reference Clock Selection -// <0x0=>GCLK clock reference -// <0x1=>XOSC32K clock reference -// <0x2=>XOSC0 clock reference -// <0x3=>XOSC1 clock reference -// fdpll1_arch_refclk -#ifndef CONF_FDPLL1_REFCLK -#define CONF_FDPLL1_REFCLK 0x1 -#endif - -// Wake Up Fast -// Indicates whether Wake Up Fast is enabled or not -// fdpll1_arch_wuf -#ifndef CONF_FDPLL1_WUF -#define CONF_FDPLL1_WUF 0 -#endif - -// Proportional Integral Filter Selection <0x0-0xF> -// fdpll1_arch_filter -#ifndef CONF_FDPLL1_FILTER -#define CONF_FDPLL1_FILTER 0x0 -#endif - -// -// - -// <<< end of configuration section >>> - -#endif // HPL_OSCCTRL_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_rtc_config.h b/atmel-samd/asf4/samd51/config/hpl_rtc_config.h deleted file mode 100644 index b99821da5..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_rtc_config.h +++ /dev/null @@ -1,137 +0,0 @@ -/* Auto-generated config file hpl_rtc_config.h */ -#ifndef HPL_RTC_CONFIG_H -#define HPL_RTC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Basic settings - -#ifndef CONF_RTC_ENABLE -#define CONF_RTC_ENABLE 1 -#endif - -// Prescaler configuration -// <0x0=>OFF(Peripheral clock divided by 1) -// <0x1=>Peripheral clock divided by 1 -// <0x2=>Peripheral clock divided by 2 -// <0x3=>Peripheral clock divided by 4 -// <0x4=>Peripheral clock divided by 8 -// <0x5=>Peripheral clock divided by 16 -// <0x6=>Peripheral clock divided by 32 -// <0x7=>Peripheral clock divided by 64 -// <0x8=>Peripheral clock divided by 128 -// <0x9=>Peripheral clock divided by 256 -// <0xA=>Peripheral clock divided by 512 -// <0xB=>Peripheral clock divided by 1024 -// These bits define the RTC clock relative to the peripheral clock -// rtc_arch_prescaler -#ifndef CONF_RTC_PRESCALER -#define CONF_RTC_PRESCALER 0x0 - -#endif - -// Compare Value <1-4294967295> -// These bits define the RTC Compare value, the ticks period is equal to reciprocal of (rtc clock/prescaler/compare value), -// by default 1K clock input, 1 prescaler, 1 compare value, the ticks period equals to 1ms. -// rtc_arch_comp_val - -#ifndef CONF_RTC_COMP_VAL -#define CONF_RTC_COMP_VAL 1 - -#endif - -// Event control -// rtc_event_control -#ifndef CONF_RTC_EVENT_CONTROL_ENABLE -#define CONF_RTC_EVENT_CONTROL_ENABLE 0 -#endif - -// Periodic Interval 0 Event Output -// This bit indicates whether Periodic interval 0 event is enabled and will be generated -// rtc_pereo0 -#ifndef CONF_RTC_PEREO0 -#define CONF_RTC_PEREO0 0 -#endif -// Periodic Interval 1 Event Output -// This bit indicates whether Periodic interval 1 event is enabled and will be generated -// rtc_pereo1 -#ifndef CONF_RTC_PEREO1 -#define CONF_RTC_PEREO1 0 -#endif -// Periodic Interval 2 Event Output -// This bit indicates whether Periodic interval 2 event is enabled and will be generated -// rtc_pereo2 -#ifndef CONF_RTC_PEREO2 -#define CONF_RTC_PEREO2 0 -#endif -// Periodic Interval 3 Event Output -// This bit indicates whether Periodic interval 3 event is enabled and will be generated -// rtc_pereo3 -#ifndef CONF_RTC_PEREO3 -#define CONF_RTC_PEREO3 0 -#endif -// Periodic Interval 4 Event Output -// This bit indicates whether Periodic interval 4 event is enabled and will be generated -// rtc_pereo4 -#ifndef CONF_RTC_PEREO4 -#define CONF_RTC_PEREO4 0 -#endif -// Periodic Interval 5 Event Output -// This bit indicates whether Periodic interval 5 event is enabled and will be generated -// rtc_pereo5 -#ifndef CONF_RTC_PEREO5 -#define CONF_RTC_PEREO5 0 -#endif -// Periodic Interval 6 Event Output -// This bit indicates whether Periodic interval 6 event is enabled and will be generated -// rtc_pereo6 -#ifndef CONF_RTC_PEREO6 -#define CONF_RTC_PEREO6 0 -#endif -// Periodic Interval 7 Event Output -// This bit indicates whether Periodic interval 7 event is enabled and will be generated -// rtc_pereo7 -#ifndef CONF_RTC_PEREO7 -#define CONF_RTC_PEREO7 0 -#endif - -// Compare 0 Event Output -// This bit indicates whether Compare O event is enabled and will be generated -// rtc_cmpeo0 -#ifndef CONF_RTC_COMPE0 -#define CONF_RTC_COMPE0 0 -#endif - -// Compare 1 Event Output -// This bit indicates whether Compare 1 event is enabled and will be generated -// rtc_cmpeo1 -#ifndef CONF_RTC_COMPE1 -#define CONF_RTC_COMPE1 0 -#endif -// Overflow Event Output -// This bit indicates whether Overflow event is enabled and will be generated -// rtc_ovfeo -#ifndef CONF_RTC_OVFEO -#define CONF_RTC_OVFEO 0 -#endif - -// Tamper Event Output -// This bit indicates whether Tamper event output is enabled and will be generated -// rtc_tampereo -#ifndef CONF_RTC_TAMPEREO -#define CONF_RTC_TAMPEREO 0 -#endif - -// Tamper Event Input -// This bit indicates whether Tamper event input is enabled and will be generated -// rtc_tampevei -#ifndef CONF_RTC_TAMPEVEI -#define CONF_RTC_TAMPEVEI 0 -#endif -// - -// - -// <<< end of configuration section >>> - -#endif // HPL_RTC_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_sercom_config.h b/atmel-samd/asf4/samd51/config/hpl_sercom_config.h deleted file mode 100644 index 8458d9f5e..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_sercom_config.h +++ /dev/null @@ -1,553 +0,0 @@ -/* Auto-generated config file hpl_sercom_config.h */ -#ifndef HPL_SERCOM_CONFIG_H -#define HPL_SERCOM_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -// Enable configuration of module -#ifndef CONF_SERCOM_0_SPI_ENABLE -#define CONF_SERCOM_0_SPI_ENABLE 1 -#endif - -// Set module in SPI Master mode -#ifndef CONF_SERCOM_0_SPI_MODE -#define CONF_SERCOM_0_SPI_MODE 0x03 -#endif - -// Basic Configuration - -// Receive buffer enable -// Enable receive buffer to receive data from slave (RXEN) -// spi_master_rx_enable -#ifndef CONF_SERCOM_0_SPI_RXEN -#define CONF_SERCOM_0_SPI_RXEN 0x1 -#endif - -// Character Size -// Bit size for all characters sent over the SPI bus (CHSIZE) -// <0x0=>8 bits -// <0x1=>9 bits -// spi_master_character_size -#ifndef CONF_SERCOM_0_SPI_CHSIZE -#define CONF_SERCOM_0_SPI_CHSIZE 0x0 -#endif - -// Baud rate <1-12000000> -// The SPI data transfer rate -// spi_master_baud_rate -#ifndef CONF_SERCOM_0_SPI_BAUD -#define CONF_SERCOM_0_SPI_BAUD 50000 -#endif - -// - -// Advanced Configuration -// spi_master_advanced -#ifndef CONF_SERCOM_0_SPI_ADVANCED -#define CONF_SERCOM_0_SPI_ADVANCED 0 -#endif - -// Dummy byte <0x00-0x1ff> -// spi_master_dummybyte -// Dummy byte used when reading data from the slave without sending any data -#ifndef CONF_SERCOM_0_SPI_DUMMYBYTE -#define CONF_SERCOM_0_SPI_DUMMYBYTE 0x1ff -#endif - -// Data Order -// <0=>MSB first -// <1=>LSB first -// I least significant or most significant bit is shifted out first (DORD) -// spi_master_arch_dord -#ifndef CONF_SERCOM_0_SPI_DORD -#define CONF_SERCOM_0_SPI_DORD 0x0 -#endif - -// Clock Polarity -// <0=>SCK is low when idle -// <1=>SCK is high when idle -// Determines if the leading edge is rising or falling with a corresponding opposite edge at the trailing edge. (CPOL) -// spi_master_arch_cpol -#ifndef CONF_SERCOM_0_SPI_CPOL -#define CONF_SERCOM_0_SPI_CPOL 0x0 -#endif - -// Clock Phase -// <0x0=>Sample input on leading edge -// <0x1=>Sample input on trailing edge -// Determines if input data is sampled on leading or trailing SCK edge. (CPHA) -// spi_master_arch_cpha -#ifndef CONF_SERCOM_0_SPI_CPHA -#define CONF_SERCOM_0_SPI_CPHA 0x0 -#endif - -// Immediate Buffer Overflow Notification -// Controls when OVF is asserted (IBON) -// <0x0=>In data stream -// <0x1=>On buffer overflow -// spi_master_arch_ibon -#ifndef CONF_SERCOM_0_SPI_IBON -#define CONF_SERCOM_0_SPI_IBON 0x0 -#endif - -// Run in stand-by -// Module stays active in stand-by sleep mode. (RUNSTDBY) -// spi_master_arch_runstdby -#ifndef CONF_SERCOM_0_SPI_RUNSTDBY -#define CONF_SERCOM_0_SPI_RUNSTDBY 0x0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. (DBGSTOP) -// <0=>Keep running -// <1=>Halt -// spi_master_arch_dbgstop -#ifndef CONF_SERCOM_0_SPI_DBGSTOP -#define CONF_SERCOM_0_SPI_DBGSTOP 0 -#endif - -// - -// Address mode disabled in master mode -#ifndef CONF_SERCOM_0_SPI_AMODE_EN -#define CONF_SERCOM_0_SPI_AMODE_EN 0 -#endif - -#ifndef CONF_SERCOM_0_SPI_AMODE -#define CONF_SERCOM_0_SPI_AMODE 0 -#endif - -#ifndef CONF_SERCOM_0_SPI_ADDR -#define CONF_SERCOM_0_SPI_ADDR 0 -#endif - -#ifndef CONF_SERCOM_0_SPI_ADDRMASK -#define CONF_SERCOM_0_SPI_ADDRMASK 0 -#endif - -#ifndef CONF_SERCOM_0_SPI_SSDE -#define CONF_SERCOM_0_SPI_SSDE 0 -#endif - -#ifndef CONF_SERCOM_0_SPI_MSSEN -#define CONF_SERCOM_0_SPI_MSSEN 0x0 -#endif - -#ifndef CONF_SERCOM_0_SPI_PLOADEN -#define CONF_SERCOM_0_SPI_PLOADEN 0 -#endif - -// Receive Data Pinout -// <0x0=>PAD[0] -// <0x1=>PAD[1] -// <0x2=>PAD[2] -// <0x3=>PAD[3] -// spi_master_rxpo -#ifndef CONF_SERCOM_0_SPI_RXPO -#define CONF_SERCOM_0_SPI_RXPO 2 -#endif - -// Transmit Data Pinout -// <0x0=>PAD[0,1]_DO_SCK -// <0x1=>PAD[2,3]_DO_SCK -// <0x2=>PAD[3,1]_DO_SCK -// <0x3=>PAD[0,3]_DO_SCK -// spi_master_txpo -#ifndef CONF_SERCOM_0_SPI_TXPO -#define CONF_SERCOM_0_SPI_TXPO 0 -#endif - -// Calculate baud register value from requested baudrate value -#ifndef CONF_SERCOM_0_SPI_BAUD_RATE -#define CONF_SERCOM_0_SPI_BAUD_RATE ((float)CONF_GCLK_SERCOM0_CORE_FREQUENCY / (float)(2 * CONF_SERCOM_0_SPI_BAUD)) - 1 -#endif - -#include - -#ifndef CONF_SERCOM_1_USART_ENABLE -#define CONF_SERCOM_1_USART_ENABLE 1 -#endif - -// Basic Configuration - -// Receive buffer enable -// Enable input buffer in SERCOM module -// usart_rx_enable -#ifndef CONF_SERCOM_1_USART_RXEN -#define CONF_SERCOM_1_USART_RXEN 1 -#endif - -// Transmitt buffer enable -// Enable output buffer in SERCOM module -// usart_tx_enable -#ifndef CONF_SERCOM_1_USART_TXEN -#define CONF_SERCOM_1_USART_TXEN 1 -#endif - -// Frame parity -// <0x0=>No parity -// <0x1=>Even parity -// <0x2=>Odd parity -// Parity bit mode for USART frame -// usart_parity -#ifndef CONF_SERCOM_1_USART_PARITY -#define CONF_SERCOM_1_USART_PARITY 0x0 -#endif - -// Character Size -// <0x0=>8 bits -// <0x1=>9 bits -// <0x5=>5 bits -// <0x6=>6 bits -// <0x7=>7 bits -// Data character size in USART frame -// usart_character_size -#ifndef CONF_SERCOM_1_USART_CHSIZE -#define CONF_SERCOM_1_USART_CHSIZE 0x0 -#endif - -// Stop Bit -// <0=>One stop bit -// <1=>Two stop bits -// Number of stop bits in USART frame -// usart_stop_bit -#ifndef CONF_SERCOM_1_USART_SBMODE -#define CONF_SERCOM_1_USART_SBMODE 0 -#endif - -// Baud rate <1-3000000> -// USART baud rate setting -// usart_baud_rate -#ifndef CONF_SERCOM_1_USART_BAUD -#define CONF_SERCOM_1_USART_BAUD 9600 -#endif - -// - -// Advanced configuration -// usart_advanced -#ifndef CONF_SERCOM_1_USART_ADVANCED_CONFIG -#define CONF_SERCOM_1_USART_ADVANCED_CONFIG 0 -#endif - -// Run in stand-by -// Keep the module running in standby sleep mode -// usart_arch_runstdby -#ifndef CONF_SERCOM_1_USART_RUNSTDBY -#define CONF_SERCOM_1_USART_RUNSTDBY 0 -#endif - -// Immediate Buffer Overflow Notification -// Controls when the BUFOVF status bit is asserted -// usart_arch_ibon -#ifndef CONF_SERCOM_1_USART_IBON -#define CONF_SERCOM_1_USART_IBON 0 -#endif - -// Start of Frame Detection Enable -// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) -// usart_arch_sfde -#ifndef CONF_SERCOM_1_USART_SFDE -#define CONF_SERCOM_1_USART_SFDE 0 -#endif - -// Collision Detection Enable -// Collision detection enable -// usart_arch_cloden -#ifndef CONF_SERCOM_1_USART_CLODEN -#define CONF_SERCOM_1_USART_CLODEN 0 -#endif - -// Operating Mode -// <0x0=>USART with external clock -// <0x1=>USART with internal clock -// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. -// usart_arch_clock_mode -#ifndef CONF_SERCOM_1_USART_MODE -#define CONF_SERCOM_1_USART_MODE 0x1 -#endif - -// Sample Rate -// <0x0=>16x arithmetic -// <0x1=>16x fractional -// <0x2=>8x arithmetic -// <0x3=>8x fractional -// <0x3=>3x -// How many over-sampling bits used when samling data state -// usart_arch_sampr -#ifndef CONF_SERCOM_1_USART_SAMPR -#define CONF_SERCOM_1_USART_SAMPR 0x0 -#endif - -// Sample Adjustment -// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) -// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) -// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) -// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) -// Adjust which samples to use for data sampling in asynchronous mode -// usart_arch_sampa -#ifndef CONF_SERCOM_1_USART_SAMPA -#define CONF_SERCOM_1_USART_SAMPA 0x0 -#endif - -// Fractional Part <0-7> -// Fractional part of the baud rate if baud rate generator is in fractional mode -// usart_arch_fractional -#ifndef CONF_SERCOM_1_USART_FRACTIONAL -#define CONF_SERCOM_1_USART_FRACTIONAL 0x0 -#endif - -// Data Order -// <0=>MSB is transmitted first -// <1=>LSB is transmitted first -// Data order of the data bits in the frame -// usart_arch_dord -#ifndef CONF_SERCOM_1_USART_DORD -#define CONF_SERCOM_1_USART_DORD 1 -#endif - -// Does not do anything in UART mode -#define CONF_SERCOM_1_USART_CPOL 0 - -// Encoding Format -// <0=>No encoding -// <1=>IrDA encoded -// usart_arch_enc -#ifndef CONF_SERCOM_1_USART_ENC -#define CONF_SERCOM_1_USART_ENC 0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. -// <0=>Keep running -// <1=>Halt -// usart_arch_dbgstop -#ifndef CONF_SERCOM_1_USART_DEBUG_STOP_MODE -#define CONF_SERCOM_1_USART_DEBUG_STOP_MODE 0 -#endif - -// - -#ifndef CONF_SERCOM_1_USART_INACK -#define CONF_SERCOM_1_USART_INACK 0x0 -#endif - -#ifndef CONF_SERCOM_1_USART_DSNACK -#define CONF_SERCOM_1_USART_DSNACK 0x0 -#endif - -#ifndef CONF_SERCOM_1_USART_MAXITER -#define CONF_SERCOM_1_USART_MAXITER 0x7 -#endif - -#ifndef CONF_SERCOM_1_USART_GTIME -#define CONF_SERCOM_1_USART_GTIME 0x2 -#endif - -#define CONF_SERCOM_1_USART_RXINV 0x0 -#define CONF_SERCOM_1_USART_TXINV 0x0 - -#ifndef CONF_SERCOM_1_USART_CMODE -#define CONF_SERCOM_1_USART_CMODE 0 -#endif - -#ifndef CONF_SERCOM_1_USART_RXPO -#define CONF_SERCOM_1_USART_RXPO 1 /* RX is on PIN_PA01 */ -#endif - -#ifndef CONF_SERCOM_1_USART_TXPO -#define CONF_SERCOM_1_USART_TXPO 0 /* TX is on PIN_PA00 */ -#endif - -/* Set correct parity settings in register interface based on PARITY setting */ -#if CONF_SERCOM_1_USART_PARITY == 0 -#define CONF_SERCOM_1_USART_PMODE 0 -#define CONF_SERCOM_1_USART_FORM 0 -#else -#define CONF_SERCOM_1_USART_PMODE CONF_SERCOM_1_USART_PARITY - 1 -#define CONF_SERCOM_1_USART_FORM 1 -#endif - -// Calculate BAUD register value in UART mode -#if CONF_SERCOM_1_USART_SAMPR == 0 -#ifndef CONF_SERCOM_1_USART_BAUD_RATE -#define CONF_SERCOM_1_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_1_USART_SAMPR == 1 -#ifndef CONF_SERCOM_1_USART_BAUD_RATE -#define CONF_SERCOM_1_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 16)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8) -#endif -#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_1_USART_SAMPR == 2 -#ifndef CONF_SERCOM_1_USART_BAUD_RATE -#define CONF_SERCOM_1_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_1_USART_SAMPR == 3 -#ifndef CONF_SERCOM_1_USART_BAUD_RATE -#define CONF_SERCOM_1_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 8)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8) -#endif -#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#elif CONF_SERCOM_1_USART_SAMPR == 4 -#ifndef CONF_SERCOM_1_USART_BAUD_RATE -#define CONF_SERCOM_1_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY) -#endif -#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0 -#endif -#endif - -#include - -#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER -#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) -#endif - -#ifndef CONF_SERCOM_2_I2CM_ENABLE -#define CONF_SERCOM_2_I2CM_ENABLE 1 -#endif - -// Basic - -// I2C Bus clock speed (Hz) <1-400000> -// I2C Bus clock (SCL) speed measured in Hz -// i2c_master_baud_rate -#ifndef CONF_SERCOM_2_I2CM_BAUD -#define CONF_SERCOM_2_I2CM_BAUD 100000 -#endif - -// - -// Advanced -// i2c_master_advanced -#ifndef CONF_SERCOM_2_I2CM_ADVANCED_CONFIG -#define CONF_SERCOM_2_I2CM_ADVANCED_CONFIG 0 -#endif - -// TRise (ns) <0-300> -// Determined by the bus impedance, check electric characteristics in the datasheet -// Standard Fast Mode: typical 215ns, max 300ns -// Fast Mode +: typical 60ns, max 100ns -// High Speed Mode: typical 20ns, max 40ns -// i2c_master_arch_trise - -#ifndef CONF_SERCOM_2_I2CM_TRISE -#define CONF_SERCOM_2_I2CM_TRISE 215 -#endif - -// Master SCL Low Extended Time-Out (MEXTTOEN) -// This enables the master SCL low extend time-out -// i2c_master_arch_mexttoen -#ifndef CONF_SERCOM_2_I2CM_MEXTTOEN -#define CONF_SERCOM_2_I2CM_MEXTTOEN 0 -#endif - -// Slave SCL Low Extend Time-Out (SEXTTOEN) -// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine -// i2c_master_arch_sexttoen -#ifndef CONF_SERCOM_2_I2CM_SEXTTOEN -#define CONF_SERCOM_2_I2CM_SEXTTOEN 0 -#endif - -// SCL Low Time-Out (LOWTOUT) -// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold -// i2c_master_arch_lowtout -#ifndef CONF_SERCOM_2_I2CM_LOWTOUT -#define CONF_SERCOM_2_I2CM_LOWTOUT 0 -#endif - -// Inactive Time-Out (INACTOUT) -// <0x0=>Disabled -// <0x1=>5-6 SCL cycle time-out(50-60us) -// <0x2=>10-11 SCL cycle time-out(100-110us) -// <0x3=>20-21 SCL cycle time-out(200-210us) -// Defines if inactivity time-out should be enabled, and how long the time-out should be -// i2c_master_arch_inactout -#ifndef CONF_SERCOM_2_I2CM_INACTOUT -#define CONF_SERCOM_2_I2CM_INACTOUT 0x0 -#endif - -// SDA Hold Time (SDAHOLD) -// <0=>Disabled -// <1=>50-100ns hold time -// <2=>300-600ns hold time -// <3=>400-800ns hold time -// Defines the SDA hold time with respect to the negative edge of SCL -// i2c_master_arch_sdahold -#ifndef CONF_SERCOM_2_I2CM_SDAHOLD -#define CONF_SERCOM_2_I2CM_SDAHOLD 0x2 -#endif - -// Run in stand-by -// Determine if the module shall run in standby sleep mode -// i2c_master_arch_runstdby -#ifndef CONF_SERCOM_2_I2CM_RUNSTDBY -#define CONF_SERCOM_2_I2CM_RUNSTDBY 0 -#endif - -// Debug Stop Mode -// Behavior of the baud-rate generator when CPU is halted by external debugger. -// <0=>Keep running -// <1=>Halt -// i2c_master_arch_dbgstop -#ifndef CONF_SERCOM_2_I2CM_DEBUG_STOP_MODE -#define CONF_SERCOM_2_I2CM_DEBUG_STOP_MODE 0 -#endif - -// - -#ifndef CONF_SERCOM_2_I2CM_SPEED -#define CONF_SERCOM_2_I2CM_SPEED 0x00 // Speed: Standard/Fast mode -#endif -#if CONF_SERCOM_2_I2CM_TRISE < 215 || CONF_SERCOM_2_I2CM_TRISE > 300 -#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns -#undef CONF_SERCOM_2_I2CM_TRISE -#define CONF_SERCOM_2_I2CM_TRISE 215 -#endif - -// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) -// BAUD + BAUDLOW = -------------------------------------------------------------------- -// i2c_scl_freq -// BAUD: register value low [7:0] -// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW -#define CONF_SERCOM_2_I2CM_BAUD_BAUDLOW \ - (((CONF_GCLK_SERCOM2_CORE_FREQUENCY - (CONF_SERCOM_2_I2CM_BAUD * 10) \ - - (CONF_SERCOM_2_I2CM_TRISE * (CONF_SERCOM_2_I2CM_BAUD / 100) * (CONF_GCLK_SERCOM2_CORE_FREQUENCY / 10000) \ - / 1000)) \ - * 10 \ - + 5) \ - / (CONF_SERCOM_2_I2CM_BAUD * 10)) -#ifndef CONF_SERCOM_2_I2CM_BAUD_RATE -#if CONF_SERCOM_2_I2CM_BAUD_BAUDLOW > (0xFF * 2) -#warning Requested I2C baudrate too low, please check -#define CONF_SERCOM_2_I2CM_BAUD_RATE 0xFF -#elif CONF_SERCOM_2_I2CM_BAUD_BAUDLOW <= 1 -#warning Requested I2C baudrate too high, please check -#define CONF_SERCOM_2_I2CM_BAUD_RATE 1 -#else -#define CONF_SERCOM_2_I2CM_BAUD_RATE \ - ((CONF_SERCOM_2_I2CM_BAUD_BAUDLOW & 0x1) \ - ? (CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ - : (CONF_SERCOM_2_I2CM_BAUD_BAUDLOW / 2)) -#endif -#endif - -// <<< end of configuration section >>> - -#endif // HPL_SERCOM_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_systick_config.h b/atmel-samd/asf4/samd51/config/hpl_systick_config.h deleted file mode 100644 index a7f2f3620..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_systick_config.h +++ /dev/null @@ -1,18 +0,0 @@ -/* Auto-generated config file hpl_systick_config.h */ -#ifndef HPL_SYSTICK_CONFIG_H -#define HPL_SYSTICK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Advanced settings -// SysTick exception request -// Indicates whether the generation of SysTick exception is enabled or not -// systick_arch_tickint -#ifndef CONF_SYSTICK_TICKINT -#define CONF_SYSTICK_TICKINT 0 -#endif -// - -// <<< end of configuration section >>> - -#endif // HPL_SYSTICK_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_tc_config.h b/atmel-samd/asf4/samd51/config/hpl_tc_config.h deleted file mode 100644 index 38d48e9b6..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_tc_config.h +++ /dev/null @@ -1,209 +0,0 @@ -/* Auto-generated config file hpl_tc_config.h */ -#ifndef HPL_TC_CONFIG_H -#define HPL_TC_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#include - -#ifndef CONF_TC0_ENABLE -#define CONF_TC0_ENABLE 1 -#endif - -// Basic settings -// Prescaler -// <0=> No division -// <1=> Divide by 2 -// <2=> Divide by 4 -// <3=> Divide by 8 -// <4=> Divide by 16 -// <5=> Divide by 64 -// <6=> Divide by 256 -// <7=> Divide by 1024 -// This defines the prescaler value -// tc_prescaler -#ifndef CONF_TC0_PRESCALER -#define CONF_TC0_PRESCALER 0 -#endif -// - -// PWM Waveform Output settings -// Waveform Period Value (uS) <0x00-0xFFFFFFFF> -// The unit of this value is us. -// tc_arch_wave_per_val -#ifndef CONF_TC0_WAVE_PER_VAL -#define CONF_TC0_WAVE_PER_VAL 0x3e8 -#endif - -// Waveform Duty Value (0.1%) <0x00-0x03E8> -// The unit of this value is 1/1000. -// tc_arch_wave_duty_val -#ifndef CONF_TC0_WAVE_DUTY_VAL -#define CONF_TC0_WAVE_DUTY_VAL 0x1f4 -#endif - -/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */ -#if CONF_TC0_PRESCALER < TC_CTRLA_PRESCALER_DIV64_Val -#define CONF_TC0_CC0 \ - ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1000000 / (1 << CONF_TC0_PRESCALER) - 1)) -#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) - -#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV64_Val -#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 64000000 - 1)) -#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) - -#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV256_Val -#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 256000000 - 1)) -#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) - -#elif CONF_TC0_PRESCALER == TC_CTRLA_PRESCALER_DIV1024_Val -#define CONF_TC0_CC0 ((uint32_t)(((double)CONF_TC0_WAVE_PER_VAL * CONF_GCLK_TC0_FREQUENCY) / 1024000000 - 1)) -#define CONF_TC0_CC1 ((CONF_TC0_CC0 * CONF_TC0_WAVE_DUTY_VAL) / 1000) -#endif - -// - -// Advanced settings -// Mode -// Counter in 16-bit mode -// Counter in 32-bit mode -// These bits mode -// tc_mode -#ifndef CONF_TC0_MODE -#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT16_Val -#endif - -// Period Value <0x00000000-0xFFFFFFFF> -// tc_per -#ifndef CONF_TC0_PER -#define CONF_TC0_PER 0x32 -#endif -// - -// Advanced settings -// Prescaler and Counter Synchronization Selection -// Reload or reset counter on next GCLK -// Reload or reset counter on next prescaler clock -// Reload or reset counter on next GCLK and reset prescaler counter -// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. -// tc_arch_presync -#ifndef CONF_TC0_PRESCSYNC -#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val -#endif - -// Run in standby -// Indicates whether the will continue running in standby sleep mode or not -// tc_arch_runstdby -#ifndef CONF_TC0_RUNSTDBY -#define CONF_TC0_RUNSTDBY 0 -#endif - -// On-Demand -// Indicates whether the TC0's on-demand mode is on or not -// tc_arch_ondemand -#ifndef CONF_TC0_ONDEMAND -#define CONF_TC0_ONDEMAND 0 -#endif - -// Auto Lock -// <0x0=>The Lock Update bit is not affected on overflow/underflow and re-trigger event -// <0x1=>The Lock Update bit is set on each overflow/underflow or re-trigger event -// tc_arch_alock -#ifndef CONF_TC0_ALOCK -#define CONF_TC0_ALOCK 0 -#endif - -/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CAPTEN0 0 -//#define CONF_TC0_CAPTEN1 0 -//#define CONF_TC0_COPEN0 0 -//#define CONF_TC0_COPEN1 0 - -/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_DIR 0 -//#define CONF_TC0_ONESHOT 0 -//#define CONF_TC0_LUPD 0 - -// Debug Running Mode -// Indicates whether the Debug Running Mode is enabled or not -// tc_arch_dbgrun -#ifndef CONF_TC0_DBGRUN -#define CONF_TC0_DBGRUN 0 -#endif - -// Event control -// timer_event_control -#ifndef CONF_TC0_EVENT_CONTROL_ENABLE -#define CONF_TC0_EVENT_CONTROL_ENABLE 0 -#endif - -// Output Event On Match or Capture on Channel 0 -// Enable output of event on timer tick -// tc_arch_mceo0 -#ifndef CONF_TC0_MCEO0 -#define CONF_TC0_MCEO0 0 -#endif - -// Output Event On Match or Capture on Channel 1 -// Enable output of event on timer tick -// tc_arch_mceo1 -#ifndef CONF_TC0_MCEO1 -#define CONF_TC0_MCEO1 0 -#endif - -// Output Event On Timer Tick -// Enable output of event on timer tick -// tc_arch_ovfeo -#ifndef CONF_TC0_OVFEO -#define CONF_TC0_OVFEO 0 -#endif - -// Event Input -// Enable asynchronous input events -// tc_arch_tcei -#ifndef CONF_TC0_TCEI -#define CONF_TC0_TCEI 0 -#endif - -// Inverted Event Input -// Invert the asynchronous input events -// tc_arch_tcinv -#ifndef CONF_TC0_TCINV -#define CONF_TC0_TCINV 0 -#endif - -// Event action -// <0=> Event action disabled -// <1=> Start, restart or re-trigger TC on event -// <2=> Count on event -// <3=> Start on event -// <4=> Time stamp capture -// <5=> Period captured in CC0, pulse width in CC1 -// <6=> Period captured in CC1, pulse width in CC0 -// <7=> Pulse width capture -// Event which will be performed on an event -// tc_arch_evact -#ifndef CONF_TC0_EVACT -#define CONF_TC0_EVACT 0 -#endif -// - -/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_WAVEGEN TC_CTRLA_WAVEGEN_MFRQ_Val - -/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_INVEN0 0 -//#define CONF_TC0_INVEN1 0 - -/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_PERBUF 0 - -/* Commented intentionally. Timer uses fixed value. May be used by other abstractions based on TC. */ -//#define CONF_TC0_CCBUF0 0 -//#define CONF_TC0_CCBUF1 0 - -// - -// <<< end of configuration section >>> - -#endif // HPL_TC_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_trng_config.h b/atmel-samd/asf4/samd51/config/hpl_trng_config.h deleted file mode 100644 index ba9014989..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_trng_config.h +++ /dev/null @@ -1,27 +0,0 @@ -/* Auto-generated config file hpl_trng_config.h */ -#ifndef HPL_TRNG_CONFIG_H -#define HPL_TRNG_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Advanced configurations - -// Run In Standby -// Indicates whether the TRNG works in standby mode -// trng_runstdby -#ifndef CONF_TRNG_RUNSTDBY -#define CONF_TRNG_RUNSTDBY 0 -#endif - -// Data Ready Event Output Enable -// Indicates whether the TRNG generates event on Data Ready -// trng_datardyeo -#ifndef CONF_TRNG_DATARDYEO -#define CONF_TRNG_DATARDYEO 0 -#endif - -// - -// <<< end of configuration section >>> - -#endif // HPL_TRNG_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/hpl_usb_config.h b/atmel-samd/asf4/samd51/config/hpl_usb_config.h deleted file mode 100644 index 73a9fea44..000000000 --- a/atmel-samd/asf4/samd51/config/hpl_usb_config.h +++ /dev/null @@ -1,355 +0,0 @@ -/* Auto-generated config file hpl_usb_config.h */ -#ifndef HPL_USB_CONFIG_H -#define HPL_USB_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -#define CONF_USB_N_0 0 -#define CONF_USB_N_1 1 -#define CONF_USB_N_2 2 -#define CONF_USB_N_3 3 -#define CONF_USB_N_4 4 -#define CONF_USB_N_5 5 -#define CONF_USB_N_6 6 -#define CONF_USB_N_7 7 -#define CONF_USB_N_8 8 -#define CONF_USB_N_9 9 -#define CONF_USB_N_10 10 -#define CONF_USB_N_11 11 -#define CONF_USB_N_12 12 -#define CONF_USB_N_13 13 -#define CONF_USB_N_14 14 -#define CONF_USB_N_15 15 - -#define CONF_USB_D_EP_N_MAX (USB_EPT_NUM - 1) -#define CONF_USB_D_N_EP_MAX (CONF_USB_D_EP_N_MAX * 2 - 1) - -// USB Device HAL Configuration - -// Max number of endpoints supported -// Limits the number of endpoints (described by EP address) can be used in app. -// 1 (EP0 only) -// 2 (EP0 + 1 endpoint) -// 3 (EP0 + 2 endpoints) -// 4 (EP0 + 3 endpoints) -// 5 (EP0 + 4 endpoints) -// 6 (EP0 + 5 endpoints) -// 7 (EP0 + 6 endpoints) -// 8 (EP0 + 7 endpoints) -// Max possible (by "Max Endpoint Number" config) -// usbd_num_ep_sp -#ifndef CONF_USB_D_NUM_EP_SP -#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4 -#endif - -// - -// Max Endpoint Number supported -// Limits the max endpoint number. -// USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1. -// Reduce the value according to specific device design, to cut-off memory usage. -// 0 (only EP0) -// 1 (EP 0x81 or 0x01) -// 2 (EP 0x82 or 0x02) -// 3 (EP 0x83 or 0x03) -// 4 (EP 0x84 or 0x04) -// 5 (EP 0x85 or 0x05) -// 6 (EP 0x86 or 0x06) -// 7 (EP 0x87 or 0x07) -// Max possible (by HW) -// The number of physical endpoints - 1 -// usbd_arch_max_ep_n -#ifndef CONF_USB_D_MAX_EP_N -#define CONF_USB_D_MAX_EP_N CONF_USB_N_2 -#endif - -// USB Speed Limit -// Limits the working speed of the device. -// Full speed -// Low Speed -// usbd_arch_speed -#ifndef CONF_USB_D_SPEED -#define CONF_USB_D_SPEED USB_SPEED_FS -#endif - -// Cache buffer size for EP0 -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time. -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// usb_arch_ep0_cache -#ifndef CONF_USB_EP0_CACHE -#define CONF_USB_EP0_CACHE 64 -#endif - -// Cache configuration EP1 -// Cache buffer size for EP1 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep1_cache -#ifndef CONF_USB_EP1_CACHE -#define CONF_USB_EP1_CACHE 64 -#endif - -// Cache buffer size for EP1 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep1_I_CACHE -#ifndef CONF_USB_EP1_I_CACHE -#define CONF_USB_EP1_I_CACHE 0 -#endif -// - -// Cache configuration EP2 -// Cache buffer size for EP2 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep2_cache -#ifndef CONF_USB_EP2_CACHE -#define CONF_USB_EP2_CACHE 64 -#endif - -// Cache buffer size for EP2 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep2_I_CACHE -#ifndef CONF_USB_EP2_I_CACHE -#define CONF_USB_EP2_I_CACHE 0 -#endif -// - -// Cache configuration EP3 -// Cache buffer size for EP3 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep3_cache -#ifndef CONF_USB_EP3_CACHE -#define CONF_USB_EP3_CACHE 64 -#endif - -// Cache buffer size for EP3 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep3_I_CACHE -#ifndef CONF_USB_EP3_I_CACHE -#define CONF_USB_EP3_I_CACHE 0 -#endif -// - -// Cache configuration EP4 -// Cache buffer size for EP4 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep4_cache -#ifndef CONF_USB_EP4_CACHE -#define CONF_USB_EP4_CACHE 64 -#endif - -// Cache buffer size for EP4 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep4_I_CACHE -#ifndef CONF_USB_EP4_I_CACHE -#define CONF_USB_EP4_I_CACHE 0 -#endif -// - -// Cache configuration EP5 -// Cache buffer size for EP5 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep5_cache -#ifndef CONF_USB_EP5_CACHE -#define CONF_USB_EP5_CACHE 64 -#endif - -// Cache buffer size for EP5 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep5_I_CACHE -#ifndef CONF_USB_EP5_I_CACHE -#define CONF_USB_EP5_I_CACHE 0 -#endif -// - -// Cache configuration EP6 -// Cache buffer size for EP6 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep6_cache -#ifndef CONF_USB_EP6_CACHE -#define CONF_USB_EP6_CACHE 64 -#endif - -// Cache buffer size for EP6 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep6_I_CACHE -#ifndef CONF_USB_EP6_I_CACHE -#define CONF_USB_EP6_I_CACHE 0 -#endif -// - -// Cache configuration EP7 -// Cache buffer size for EP7 OUT -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_arch_ep7_cache -#ifndef CONF_USB_EP7_CACHE -#define CONF_USB_EP7_CACHE 64 -#endif - -// Cache buffer size for EP7 IN -// Cache is used because the USB hardware always uses DMA which requires specific memory feature. -// This cache must not be allocated if you plan to use the endpoint as control endpoint. -// No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size -// <0=> No cache -// <8=> Cached by 8 bytes buffer -// <16=> Cached by 16 bytes buffer -// <32=> Cached by 32 bytes buffer -// <64=> Cached by 64 bytes buffer -// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP) -// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP) -// usb_ep7_I_CACHE -#ifndef CONF_USB_EP7_I_CACHE -#define CONF_USB_EP7_I_CACHE 0 -#endif -// - -// <<< end of configuration section >>> - -#endif // HPL_USB_CONFIG_H diff --git a/atmel-samd/asf4/samd51/config/peripheral_clk_config.h b/atmel-samd/asf4/samd51/config/peripheral_clk_config.h deleted file mode 100644 index e68fad767..000000000 --- a/atmel-samd/asf4/samd51/config/peripheral_clk_config.h +++ /dev/null @@ -1,926 +0,0 @@ -/* Auto-generated config file peripheral_clk_config.h */ -#ifndef PERIPHERAL_CLK_CONFIG_H -#define PERIPHERAL_CLK_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// ADC Clock Source -// adc_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for ADC. -#ifndef CONF_GCLK_ADC0_SRC -#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_ADC0_FREQUENCY - * \brief ADC0's Clock frequency - */ -#ifndef CONF_GCLK_ADC0_FREQUENCY -#define CONF_GCLK_ADC0_FREQUENCY 12000000 -#endif - -// DAC Clock Source - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// dac_gclk_selection -// Select the clock source for DAC. -#ifndef CONF_GCLK_DAC_SRC -#define CONF_GCLK_DAC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_DAC_FREQUENCY - * \brief DAC's Clock frequency - */ -#ifndef CONF_GCLK_DAC_FREQUENCY -#define CONF_GCLK_DAC_FREQUENCY 12000000 -#endif - -// EVSYS Channel 0 Clock Source -// evsys_clk_selection_0 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 0. -#ifndef CONF_GCLK_EVSYS_CHANNEL_0_SRC -#define CONF_GCLK_EVSYS_CHANNEL_0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_0_FREQUENCY 12000000.0 -#endif - -// EVSYS Channel 1 Clock Source -// evsys_clk_selection_1 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 1. -#ifndef CONF_GCLK_EVSYS_CHANNEL_1_SRC -#define CONF_GCLK_EVSYS_CHANNEL_1_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_1_FREQUENCY 12000000.0 -#endif - -// EVSYS Channel 2 Clock Source -// evsys_clk_selection_2 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 2. -#ifndef CONF_GCLK_EVSYS_CHANNEL_2_SRC -#define CONF_GCLK_EVSYS_CHANNEL_2_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_2_FREQUENCY 12000000.0 -#endif - -// EVSYS Channel 3 Clock Source -// evsys_clk_selection_3 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 3. -#ifndef CONF_GCLK_EVSYS_CHANNEL_3_SRC -#define CONF_GCLK_EVSYS_CHANNEL_3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_3_FREQUENCY 12000000.0 -#endif - -// EVSYS Channel 4 Clock Source -// evsys_clk_selection_4 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 4. -#ifndef CONF_GCLK_EVSYS_CHANNEL_4_SRC -#define CONF_GCLK_EVSYS_CHANNEL_4_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_4_FREQUENCY 12000000.0 -#endif - -// EVSYS Channel 5 Clock Source -// evsys_clk_selection_5 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 5. -#ifndef CONF_GCLK_EVSYS_CHANNEL_5_SRC -#define CONF_GCLK_EVSYS_CHANNEL_5_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_5_FREQUENCY 12000000.0 -#endif - -// EVSYS Channel 6 Clock Source -// evsys_clk_selection_6 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 6. -#ifndef CONF_GCLK_EVSYS_CHANNEL_6_SRC -#define CONF_GCLK_EVSYS_CHANNEL_6_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_6_FREQUENCY 12000000.0 -#endif - -// EVSYS Channel 7 Clock Source -// evsys_clk_selection_7 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 7. -#ifndef CONF_GCLK_EVSYS_CHANNEL_7_SRC -#define CONF_GCLK_EVSYS_CHANNEL_7_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_7_FREQUENCY 12000000.0 -#endif - -// EVSYS Channel 8 Clock Source -// evsys_clk_selection_8 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 8. -#ifndef CONF_GCLK_EVSYS_CHANNEL_8_SRC -#define CONF_GCLK_EVSYS_CHANNEL_8_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_8_FREQUENCY 12000000.0 -#endif - -// EVSYS Channel 9 Clock Source -// evsys_clk_selection_9 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 9. -#ifndef CONF_GCLK_EVSYS_CHANNEL_9_SRC -#define CONF_GCLK_EVSYS_CHANNEL_9_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_9_FREQUENCY 12000000.0 -#endif - -// EVSYS Channel 10 Clock Source -// evsys_clk_selection_10 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 10. -#ifndef CONF_GCLK_EVSYS_CHANNEL_10_SRC -#define CONF_GCLK_EVSYS_CHANNEL_10_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_10_FREQUENCY 12000000.0 -#endif - -// EVSYS Channel 11 Clock Source -// evsys_clk_selection_11 - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for channel 11. -#ifndef CONF_GCLK_EVSYS_CHANNEL_11_SRC -#define CONF_GCLK_EVSYS_CHANNEL_11_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY - * \brief EVSYS's Clock frequency - */ - -#ifndef CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY -#define CONF_GCLK_EVSYS_CHANNEL_11_FREQUENCY 12000000.0 -#endif - -/** - * \def CONF_CPU_FREQUENCY - * \brief CPU's Clock frequency - */ -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 12000000 -#endif - -// RTC Clock Source -// rtc_clk_selection -// RTC source -// Select the clock source for RTC. -#ifndef CONF_GCLK_RTC_SRC -#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE -#endif - -/** - * \def CONF_GCLK_RTC_FREQUENCY - * \brief RTC's Clock frequency - */ -#ifndef CONF_GCLK_RTC_FREQUENCY -#define CONF_GCLK_RTC_FREQUENCY 1024 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM0_CORE_SRC -#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM0_SLOW_SRC -#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY - * \brief SERCOM0's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY -#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 12000000 -#endif - -/** - * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY - * \brief SERCOM0's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM1_CORE_SRC -#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM1_SLOW_SRC -#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY - * \brief SERCOM1's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY -#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 12000000 -#endif - -/** - * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY - * \brief SERCOM1's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768 -#endif - -// Core Clock Source -// core_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM2_CORE_SRC -#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -// Slow Clock Source -// slow_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the slow clock source. -#ifndef CONF_GCLK_SERCOM2_SLOW_SRC -#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val -#endif - -/** - * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY - * \brief SERCOM2's Core Clock frequency - */ -#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY -#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 12000000 -#endif - -/** - * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY - * \brief SERCOM2's Slow Clock frequency - */ -#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 -#endif - -// TC Clock Source -// tc_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for TC. -#ifndef CONF_GCLK_TC0_SRC -#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val -#endif - -/** - * \def CONF_GCLK_TC0_FREQUENCY - * \brief TC0's Clock frequency - */ -#ifndef CONF_GCLK_TC0_FREQUENCY -#define CONF_GCLK_TC0_FREQUENCY 12000000 -#endif - -// USB Clock Source -// usb_gclk_selection - -// Generic clock generator 0 - -// Generic clock generator 1 - -// Generic clock generator 2 - -// Generic clock generator 3 - -// Generic clock generator 4 - -// Generic clock generator 5 - -// Generic clock generator 6 - -// Generic clock generator 7 - -// Generic clock generator 8 - -// Generic clock generator 9 - -// Generic clock generator 10 - -// Generic clock generator 11 - -// Select the clock source for USB. -#ifndef CONF_GCLK_USB_SRC -#define CONF_GCLK_USB_SRC GCLK_PCHCTRL_GEN_GCLK0_Val - -#endif - -/** - * \def CONF_GCLK_USB_FREQUENCY - * \brief USB's Clock frequency - */ -#ifndef CONF_GCLK_USB_FREQUENCY -#define CONF_GCLK_USB_FREQUENCY 12000000 -#endif - -// <<< end of configuration section >>> - -#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/atmel-samd/asf4/samd51/documentation/usb_device_composite.rst b/atmel-samd/asf4/samd51/documentation/usb_device_composite.rst deleted file mode 100644 index 1d6151cc2..000000000 --- a/atmel-samd/asf4/samd51/documentation/usb_device_composite.rst +++ /dev/null @@ -1,32 +0,0 @@ -==================== -USB Device Composite -==================== - -USB Device Composite is a part of the USB Device Stack library. It provides the support for -combining different USB classes into one USB device application. For more detailed features -or use cases introduction, user can refer to the related class documents. - - -Features --------- -* Combination of different USB classes. - - -Applications ------------- - -* An USB device which is composed by CDC ACM, HID Keyboard,etc. - -Dependencies ------------- - -* USB Device Driver -* USB Device Stack Core -* USB Device CDC -* USB Device HID - - -Limitations ------------ - -N/A diff --git a/atmel-samd/asf4/samd51/documentation/usb_device_core.rst b/atmel-samd/asf4/samd51/documentation/usb_device_core.rst deleted file mode 100644 index fc7018625..000000000 --- a/atmel-samd/asf4/samd51/documentation/usb_device_core.rst +++ /dev/null @@ -1,41 +0,0 @@ -=============== -USB Device Core -=============== - -USB Device Core is a part of the USB Device Stack library. It handles all the requests -during USB Enumeration process and helps upper class driver to be installed successfully -if only the descriptor configuration is correct. For more detailed description about Bus -Enumeration, user can refer to Chapter 9 (USB Device Framework) in Universal Serial Bus -Specification. - -Features --------- -* Initialization/de-initialization -* Enabling/disabling USB device class components -* Data Transfer -* Attaching/detaching control -* Waking up by USB host -* Callbacks management on: - - * SOF event - * USB Device state change - * USB Device request handler - - -Applications ------------- - -N/A - -Dependencies ------------- - -* USB Device Driver -* USB Protocol Core - - -Limitations ------------ - -* It is recommended that at least one device class should run above the USB - device core. diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_cdc.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_cdc.rst deleted file mode 100644 index 3cf414b92..000000000 --- a/atmel-samd/asf4/samd51/documentation/usb_protocol_cdc.rst +++ /dev/null @@ -1,24 +0,0 @@ -================ -USB CDC Protocol -================ - -USB CDC Protocol is a part of the USB Device Stack library. It provides basic -macro definitions and data structures which are compliant with CDC(Communications -Device Class) Specification version 1.2. - - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_core.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_core.rst deleted file mode 100644 index 4d5e01bbf..000000000 --- a/atmel-samd/asf4/samd51/documentation/usb_protocol_core.rst +++ /dev/null @@ -1,40 +0,0 @@ -================= -USB Protocol Core -================= - -USB Protocol Core is a part of the USB Device Stack library. It provides basic -macro definitions, data structures and API functions which are compliant with -USB specification version 2.0.0/2.0.1 for user. - -In addition, it provides interfaces of USB descriptor searching for the upper -layer to use, which is especially helpful in the USB enumeration process. - -Features --------- -* Packaging USB device, configuration, interface, endpoint descriptors. -* Getting the descriptor length or type from an assigned USB descriptor. -* Getting VID, PID value from an assigned USB descriptor. -* Getting the total length of an USB configuration descriptor. -* Finding the next valid descriptor in a given USB descriptor. -* Finding an endpoint descriptor in a given USB descriptor. -* Finding a specific descriptor by an assigned descriptor type. -* Finding a configure descriptor by an assigned configure value. -* Finding a string descriptor by an assigned string index. - - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A - diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_hid.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_hid.rst deleted file mode 100644 index 613c22cec..000000000 --- a/atmel-samd/asf4/samd51/documentation/usb_protocol_hid.rst +++ /dev/null @@ -1,24 +0,0 @@ -================ -USB HID Protocol -================ - -USB HID Protocol is a part of the USB Device Stack library. It provides basic -macro definitions and data structures which are compliant with HID(Human Interface -Device) Specification version 1.11. - - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_hub.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_hub.rst deleted file mode 100644 index d60b0bbfd..000000000 --- a/atmel-samd/asf4/samd51/documentation/usb_protocol_hub.rst +++ /dev/null @@ -1,32 +0,0 @@ -====================== -USB Protocol Hub Class -====================== - -USB Protocol Hub Class is a part of the USB Device Stack library. It provides -basic macro definitions, data structures and API functions which are compliant -with Hub part of USB specification version 2.0.0/2.0.1 for user. - -In addition, it provides interfaces of USB requests filling and input data -analyzing for the upper layer to use. - -Features --------- -* Hub requests filling -* Hub change bitmap analyzing - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A - diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_msc.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_msc.rst deleted file mode 100644 index 6c7df5450..000000000 --- a/atmel-samd/asf4/samd51/documentation/usb_protocol_msc.rst +++ /dev/null @@ -1,25 +0,0 @@ -================ -USB MSC Protocol -================ - -USB MSC Protocol is a part of the USB Device Stack library. It provides basic -macro definitions and data structures which are compliant with Mass Storage -Control/Bulk/Interrupt (CBI) Specification 1.1 and Mass Storage UFI Command -Specification 1.0. - - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A diff --git a/atmel-samd/asf4/samd51/documentation/usb_protocol_vendor.rst b/atmel-samd/asf4/samd51/documentation/usb_protocol_vendor.rst deleted file mode 100644 index e244675a6..000000000 --- a/atmel-samd/asf4/samd51/documentation/usb_protocol_vendor.rst +++ /dev/null @@ -1,24 +0,0 @@ -=================== -USB Vendor Protocol -=================== - -USB Vendor Protocol is a part of the USB Device Stack library. It provides basic -macro definitions which are compliant with Universal Serial Bus Specification -Revision 2.0. - - -Applications ------------- - -N/A - -Dependencies ------------- - -N/A - - -Limitations ------------ - -N/A diff --git a/atmel-samd/asf4/samd51/driver_init.c b/atmel-samd/asf4/samd51/driver_init.c deleted file mode 100644 index cece74926..000000000 --- a/atmel-samd/asf4/samd51/driver_init.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ - -#include "driver_init.h" -#include -#include -#include -#include -#include - -struct timer_descriptor TIMER_0; -struct spi_m_sync_descriptor SPI_0; - -struct adc_sync_descriptor ADC_0; - -struct dac_sync_descriptor DAC_0; - -struct flash_descriptor FLASH_0; - -struct usart_sync_descriptor USART_0; - -struct i2c_m_sync_desc I2C_0; - -struct pwm_descriptor PWM_0; - -struct rand_sync_desc RAND_0; - -void ADC_0_PORT_init(void) -{ -} - -void ADC_0_CLOCK_init(void) -{ - hri_mclk_set_APBDMASK_ADC0_bit(MCLK); - hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); -} - -void ADC_0_init(void) -{ - ADC_0_CLOCK_init(); - ADC_0_PORT_init(); - adc_sync_init(&ADC_0, ADC0, (void *)NULL); -} - -void DAC_0_PORT_init(void) -{ -} - -void DAC_0_CLOCK_init(void) -{ - - hri_mclk_set_APBDMASK_DAC_bit(MCLK); - hri_gclk_write_PCHCTRL_reg(GCLK, DAC_GCLK_ID, CONF_GCLK_DAC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); -} - -void DAC_0_init(void) -{ - DAC_0_CLOCK_init(); - dac_sync_init(&DAC_0, DAC); - DAC_0_PORT_init(); -} - -void EVENT_SYSTEM_0_init(void) -{ - - hri_mclk_set_APBBMASK_EVSYS_bit(MCLK); - event_system_init(); -} - -void FLASH_0_CLOCK_init(void) -{ - - hri_mclk_set_AHBMASK_NVMCTRL_bit(MCLK); -} - -void FLASH_0_init(void) -{ - FLASH_0_CLOCK_init(); - flash_init(&FLASH_0, NVMCTRL); -} - -/** - * \brief Timer initialization function - * - * Enables Timer peripheral, clocks and initializes Timer driver - */ -static void TIMER_0_init(void) -{ - hri_mclk_set_APBAMASK_RTC_bit(MCLK); - timer_init(&TIMER_0, RTC, _rtc_get_timer()); -} - -void SPI_0_PORT_init(void) -{ - - // Set pin direction to output - gpio_set_pin_direction(PA04, GPIO_DIRECTION_OUT); - - gpio_set_pin_level(PA04, - // Initial level - // pad_initial_level - // Low - // High - false); - - gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0); - - // Set pin direction to output - gpio_set_pin_direction(PA05, GPIO_DIRECTION_OUT); - - gpio_set_pin_level(PA05, - // Initial level - // pad_initial_level - // Low - // High - false); - - gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1); - - // Set pin direction to input - gpio_set_pin_direction(PA06, GPIO_DIRECTION_IN); - - gpio_set_pin_pull_mode(PA06, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA06, PINMUX_PA06D_SERCOM0_PAD2); -} - -void SPI_0_CLOCK_init(void) -{ - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK); -} - -void SPI_0_init(void) -{ - SPI_0_CLOCK_init(); - spi_m_sync_init(&SPI_0, SERCOM0); - SPI_0_PORT_init(); -} - -void USART_0_PORT_init(void) -{ - - gpio_set_pin_function(PA00, PINMUX_PA00D_SERCOM1_PAD0); - - gpio_set_pin_function(PA01, PINMUX_PA01D_SERCOM1_PAD1); -} - -void USART_0_CLOCK_init(void) -{ - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK); -} - -void USART_0_init(void) -{ - USART_0_CLOCK_init(); - usart_sync_init(&USART_0, SERCOM1, (void *)NULL); - USART_0_PORT_init(); -} - -void I2C_0_PORT_init(void) -{ - - gpio_set_pin_pull_mode(PA09, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA09, PINMUX_PA09D_SERCOM2_PAD0); - - gpio_set_pin_pull_mode(PA08, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA08, PINMUX_PA08D_SERCOM2_PAD1); -} - -void I2C_0_CLOCK_init(void) -{ - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - - hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); -} - -void I2C_0_init(void) -{ - I2C_0_CLOCK_init(); - i2c_m_sync_init(&I2C_0, SERCOM2); - I2C_0_PORT_init(); -} - -void delay_driver_init(void) -{ - delay_init(SysTick); -} - -void PWM_0_PORT_init(void) -{ -} - -void PWM_0_CLOCK_init(void) -{ - hri_mclk_set_APBAMASK_TC0_bit(MCLK); - hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); -} - -void PWM_0_init(void) -{ - PWM_0_CLOCK_init(); - PWM_0_PORT_init(); - pwm_init(&PWM_0, TC0, _tc_get_pwm()); -} - -void RAND_0_CLOCK_init(void) -{ - hri_mclk_set_APBCMASK_TRNG_bit(MCLK); -} - -void RAND_0_init(void) -{ - RAND_0_CLOCK_init(); - rand_sync_init(&RAND_0, TRNG); -} - -void USB_DEVICE_INSTANCE_PORT_init(void) -{ - - gpio_set_pin_direction(PA24, - // Pin direction - // pad_direction - // Off - // In - // Out - GPIO_DIRECTION_OUT); - - gpio_set_pin_level(PA24, - // Initial level - // pad_initial_level - // Low - // High - false); - - gpio_set_pin_pull_mode(PA24, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA24, - // Pin function - // pad_function - // Auto : use driver pinmux if signal is imported by driver, else turn off function - // Auto - // Off - // A - // B - // C - // D - // E - // F - // G - // H - // I - // J - // K - // L - // M - // N - PINMUX_PA24H_USB_DM); - - gpio_set_pin_direction(PA25, - // Pin direction - // pad_direction - // Off - // In - // Out - GPIO_DIRECTION_OUT); - - gpio_set_pin_level(PA25, - // Initial level - // pad_initial_level - // Low - // High - false); - - gpio_set_pin_pull_mode(PA25, - // Pull configuration - // pad_pull_config - // Off - // Pull-up - // Pull-down - GPIO_PULL_OFF); - - gpio_set_pin_function(PA25, - // Pin function - // pad_function - // Auto : use driver pinmux if signal is imported by driver, else turn off function - // Auto - // Off - // A - // B - // C - // D - // E - // F - // G - // H - // I - // J - // K - // L - // M - // N - PINMUX_PA25H_USB_DP); -} - -/* The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock - * for low speed and full speed operation. */ -#if (CONF_GCLK_USB_FREQUENCY > (48000000 + 48000000 / 400)) || (CONF_GCLK_USB_FREQUENCY < (48000000 - 48000000 / 400)) -#warning USB clock should be 48MHz ~ 0.25% clock, check your configuration! -#endif - -void USB_DEVICE_INSTANCE_CLOCK_init(void) -{ - - hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, CONF_GCLK_USB_SRC | GCLK_PCHCTRL_CHEN); - hri_mclk_set_AHBMASK_USB_bit(MCLK); - hri_mclk_set_APBBMASK_USB_bit(MCLK); -} - -void USB_DEVICE_INSTANCE_init(void) -{ - USB_DEVICE_INSTANCE_CLOCK_init(); - usb_d_init(); - USB_DEVICE_INSTANCE_PORT_init(); -} - -void system_init(void) -{ - init_mcu(); - - ADC_0_init(); - - DAC_0_init(); - - EVENT_SYSTEM_0_init(); - - FLASH_0_init(); - - TIMER_0_init(); - - SPI_0_init(); - - USART_0_init(); - - I2C_0_init(); - - delay_driver_init(); - - PWM_0_init(); - - RAND_0_init(); - - USB_DEVICE_INSTANCE_init(); -} diff --git a/atmel-samd/asf4/samd51/driver_init.h b/atmel-samd/asf4/samd51/driver_init.h deleted file mode 100644 index d00f92388..000000000 --- a/atmel-samd/asf4/samd51/driver_init.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef DRIVER_INIT_INCLUDED -#define DRIVER_INIT_INCLUDED - -#include "atmel_start_pins.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include - -#include - -#include -#include - -#include - -#include - -#include -#include -#include - -#include - -#include "hal_usb_device.h" - -extern struct adc_sync_descriptor ADC_0; - -extern struct dac_sync_descriptor DAC_0; - -extern struct flash_descriptor FLASH_0; -extern struct timer_descriptor TIMER_0; -extern struct spi_m_sync_descriptor SPI_0; - -extern struct usart_sync_descriptor USART_0; - -extern struct i2c_m_sync_desc I2C_0; - -extern struct pwm_descriptor PWM_0; - -extern struct rand_sync_desc RAND_0; - -void ADC_0_PORT_init(void); -void ADC_0_CLOCK_init(void); -void ADC_0_init(void); - -void DAC_0_PORT_init(void); -void DAC_0_CLOCK_init(void); -void DAC_0_init(void); - -void FLASH_0_init(void); -void FLASH_0_CLOCK_init(void); - -void SPI_0_PORT_init(void); -void SPI_0_CLOCK_init(void); -void SPI_0_init(void); - -void USART_0_PORT_init(void); -void USART_0_CLOCK_init(void); -void USART_0_init(void); - -void I2C_0_CLOCK_init(void); -void I2C_0_init(void); -void I2C_0_PORT_init(void); - -void delay_driver_init(void); - -void PWM_0_PORT_init(void); -void PWM_0_CLOCK_init(void); -void PWM_0_init(void); - -void RAND_0_CLOCK_init(void); -void RAND_0_init(void); - -void USB_DEVICE_INSTANCE_CLOCK_init(void); -void USB_DEVICE_INSTANCE_init(void); - -/** - * \brief Perform system initialization, initialize pins and clocks for - * peripherals - */ -void system_init(void); - -#ifdef __cplusplus -} -#endif -#endif // DRIVER_INIT_INCLUDED diff --git a/atmel-samd/asf4/samd51/examples/driver_examples.c b/atmel-samd/asf4/samd51/examples/driver_examples.c deleted file mode 100644 index 91ae2887a..000000000 --- a/atmel-samd/asf4/samd51/examples/driver_examples.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ - -#include "driver_examples.h" -#include "driver_init.h" -#include "utils.h" - -/** - * Example of using ADC_0 to generate waveform. - */ -void ADC_0_example(void) -{ - uint8_t buffer[2]; - - adc_sync_enable_channel(&ADC_0, 0); - - while (1) { - adc_sync_read_channel(&ADC_0, 0, buffer, 2); - } -} - -/** - * Example of using DAC_0 to generate waveform. - */ -void DAC_0_example(void) -{ - uint16_t i = 0; - - dac_sync_enable_channel(&DAC_0, 0); - - for (;;) { - dac_sync_write(&DAC_0, 0, &i, 1); - i = (i + 1) % 1024; - } -} - -static uint8_t src_data[512]; -static uint8_t chk_data[512]; -/** - * Example of using FLASH_0 to read and write buffer. - */ -void FLASH_0_example(void) -{ - uint32_t page_size; - uint16_t i; - - /* Init source data */ - page_size = flash_get_page_size(&FLASH_0); - - for (i = 0; i < page_size; i++) { - src_data[i] = i; - } - - /* Write data to flash */ - flash_write(&FLASH_0, 0x3200, src_data, page_size); - - /* Read data from flash */ - flash_read(&FLASH_0, 0x3200, chk_data, page_size); -} - -static struct timer_task TIMER_0_task1, TIMER_0_task2; -/** - * Example of using TIMER_0. - */ -static void TIMER_0_task1_cb(const struct timer_task *const timer_task) -{ -} - -static void TIMER_0_task2_cb(const struct timer_task *const timer_task) -{ -} - -void TIMER_0_example(void) -{ - TIMER_0_task1.interval = 100; - TIMER_0_task1.cb = TIMER_0_task1_cb; - TIMER_0_task1.mode = TIMER_TASK_REPEAT; - TIMER_0_task2.interval = 200; - TIMER_0_task2.cb = TIMER_0_task2_cb; - TIMER_0_task2.mode = TIMER_TASK_REPEAT; - - timer_add_task(&TIMER_0, &TIMER_0_task1); - timer_add_task(&TIMER_0, &TIMER_0_task2); - timer_start(&TIMER_0); -} - -/** - * Example of using SPI_0 to write "Hello World" using the IO abstraction. - */ -static uint8_t example_SPI_0[12] = "Hello World!"; - -void SPI_0_example(void) -{ - struct io_descriptor *io; - spi_m_sync_get_io_descriptor(&SPI_0, &io); - - spi_m_sync_enable(&SPI_0); - io_write(io, example_SPI_0, 12); -} - -/** - * Example of using USART_0 to write "Hello World" using the IO abstraction. - */ -void USART_0_example(void) -{ - struct io_descriptor *io; - usart_sync_get_io_descriptor(&USART_0, &io); - usart_sync_enable(&USART_0); - - io_write(io, (uint8_t *)"Hello World!", 12); -} - -void I2C_0_example(void) -{ - struct io_descriptor *I2C_0_io; - - i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); - i2c_m_sync_enable(&I2C_0); - i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); - io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); -} - -void delay_example(void) -{ - delay_ms(5000); -} - -/** - * Example of using PWM_0. - */ -void PWM_0_example(void) -{ - pwm_set_parameters(&PWM_0, 10000, 5000); - pwm_enable(&PWM_0); -} - -/** - * Example of using RAND_0 to generate waveform. - */ -void RAND_0_example(void) -{ - uint32_t random_n[4]; - rand_sync_enable(&RAND_0); - random_n[0] = rand_sync_read32(&RAND_0); - random_n[1] = rand_sync_read32(&RAND_0); - rand_sync_read_buf32(&RAND_0, &random_n[2], 2); - if (random_n[0] == random_n[1]) { - /* halt */ - while (1) - ; - } - if (random_n[2] == random_n[3]) { - /* halt */ - while (1) - ; - } -} diff --git a/atmel-samd/asf4/samd51/examples/driver_examples.h b/atmel-samd/asf4/samd51/examples/driver_examples.h deleted file mode 100644 index 71fc42f74..000000000 --- a/atmel-samd/asf4/samd51/examples/driver_examples.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file - * to avoid losing it when reconfiguring. - */ -#ifndef DRIVER_EXAMPLES_H_INCLUDED -#define DRIVER_EXAMPLES_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -void ADC_0_example(void); - -void DAC_0_example(void); - -void FLASH_0_example(void); - -void USART_0_example(void); - -void I2C_0_example(void); - -void delay_example(void); - -void PWM_0_example(void); - -void RAND_0_example(void); - -#ifdef __cplusplus -} -#endif -#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/atmel-samd/asf4/samd51/gcc/Makefile b/atmel-samd/asf4/samd51/gcc/Makefile deleted file mode 100644 index 7f98ae0b6..000000000 --- a/atmel-samd/asf4/samd51/gcc/Makefile +++ /dev/null @@ -1,312 +0,0 @@ - -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -ifdef SystemRoot - SHELL = cmd.exe - MK_DIR = mkdir -else - ifeq ($(shell uname), Linux) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW32) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW64) - MK_DIR = mkdir -p - endif -endif - -# List the subdirectories for creating object files -SUB_DIRS += \ - \ -hpl/adc \ -usb/class/cdc/device \ -hpl/ramecc \ -hpl/evsys \ -examples \ -hpl/systick \ -hpl/oscctrl \ -hpl/tc \ -hpl/osc32kctrl \ -usb \ -hpl/dmac \ -hal/src \ -hal/utils/src \ -hpl/rtc \ -hpl/trng \ -usb/class/hid/device \ -hpl/usb \ -gcc \ -hpl/mclk \ -hpl/gclk \ -gcc/gcc \ -usb/device \ -hpl/pm \ -hpl/dac \ -hpl/sercom \ -hpl/nvmctrl \ -hpl/core \ -usb/class/msc/device - -# List the object files -OBJS += \ -hal/src/hal_io.o \ -hpl/systick/hpl_systick.o \ -usb/usb_protocol.o \ -usb/class/hid/device/hiddf_generic.o \ -hpl/evsys/hpl_evsys.o \ -hpl/core/hpl_core_m4.o \ -usb/class/cdc/device/cdcdf_acm.o \ -hal/utils/src/utils_syscalls.o \ -hpl/mclk/hpl_mclk.o \ -hpl/nvmctrl/hpl_nvmctrl.o \ -usb/class/msc/device/mscdf.o \ -hal/src/hal_spi_m_sync.o \ -hal/src/hal_timer.o \ -hal/src/hal_pwm.o \ -hpl/usb/hpl_usb.o \ -hal/src/hal_i2c_m_sync.o \ -hal/src/hal_delay.o \ -hpl/pm/hpl_pm.o \ -hpl/core/hpl_init.o \ -hpl/ramecc/hpl_ramecc.o \ -hal/utils/src/utils_list.o \ -usb/class/hid/device/hiddf_mouse.o \ -hal/utils/src/utils_assert.o \ -hpl/dmac/hpl_dmac.o \ -hpl/oscctrl/hpl_oscctrl.o \ -hal/src/hal_rand_sync.o \ -hpl/trng/hpl_trng.o \ -usb/class/hid/device/hiddf_keyboard.o \ -hal/src/hal_usart_sync.o \ -hpl/dac/hpl_dac.o \ -hpl/gclk/hpl_gclk.o \ -hal/src/hal_flash.o \ -hal/src/hal_init.o \ -gcc/system_samd51.o \ -gcc/gcc/startup_samd51.o \ -hal/src/hal_usb_device.o \ -main.o \ -hpl/osc32kctrl/hpl_osc32kctrl.o \ -hpl/rtc/hpl_rtc.o \ -examples/driver_examples.o \ -driver_init.o \ -hal/src/hal_adc_sync.o \ -hal/src/hal_dac_sync.o \ -hpl/sercom/hpl_sercom.o \ -hal/src/hal_gpio.o \ -hal/src/hal_evsys.o \ -hal/utils/src/utils_event.o \ -hal/src/hal_sleep.o \ -usb_start.o \ -atmel_start.o \ -usb/device/usbdc.o \ -hpl/tc/hpl_tc.o \ -hal/src/hal_atomic.o \ -hpl/adc/hpl_adc.o - -OBJS_AS_ARGS += \ -"hal/src/hal_io.o" \ -"hpl/systick/hpl_systick.o" \ -"usb/usb_protocol.o" \ -"usb/class/hid/device/hiddf_generic.o" \ -"hpl/evsys/hpl_evsys.o" \ -"hpl/core/hpl_core_m4.o" \ -"usb/class/cdc/device/cdcdf_acm.o" \ -"hal/utils/src/utils_syscalls.o" \ -"hpl/mclk/hpl_mclk.o" \ -"hpl/nvmctrl/hpl_nvmctrl.o" \ -"usb/class/msc/device/mscdf.o" \ -"hal/src/hal_spi_m_sync.o" \ -"hal/src/hal_timer.o" \ -"hal/src/hal_pwm.o" \ -"hpl/usb/hpl_usb.o" \ -"hal/src/hal_i2c_m_sync.o" \ -"hal/src/hal_delay.o" \ -"hpl/pm/hpl_pm.o" \ -"hpl/core/hpl_init.o" \ -"hpl/ramecc/hpl_ramecc.o" \ -"hal/utils/src/utils_list.o" \ -"usb/class/hid/device/hiddf_mouse.o" \ -"hal/utils/src/utils_assert.o" \ -"hpl/dmac/hpl_dmac.o" \ -"hpl/oscctrl/hpl_oscctrl.o" \ -"hal/src/hal_rand_sync.o" \ -"hpl/trng/hpl_trng.o" \ -"usb/class/hid/device/hiddf_keyboard.o" \ -"hal/src/hal_usart_sync.o" \ -"hpl/dac/hpl_dac.o" \ -"hpl/gclk/hpl_gclk.o" \ -"hal/src/hal_flash.o" \ -"hal/src/hal_init.o" \ -"gcc/system_samd51.o" \ -"gcc/gcc/startup_samd51.o" \ -"hal/src/hal_usb_device.o" \ -"main.o" \ -"hpl/osc32kctrl/hpl_osc32kctrl.o" \ -"hpl/rtc/hpl_rtc.o" \ -"examples/driver_examples.o" \ -"driver_init.o" \ -"hal/src/hal_adc_sync.o" \ -"hal/src/hal_dac_sync.o" \ -"hpl/sercom/hpl_sercom.o" \ -"hal/src/hal_gpio.o" \ -"hal/src/hal_evsys.o" \ -"hal/utils/src/utils_event.o" \ -"hal/src/hal_sleep.o" \ -"usb_start.o" \ -"atmel_start.o" \ -"usb/device/usbdc.o" \ -"hpl/tc/hpl_tc.o" \ -"hal/src/hal_atomic.o" \ -"hpl/adc/hpl_adc.o" - -# List the dependency files -DEPS := $(OBJS:%.o=%.d) - -DEPS_AS_ARGS += \ -"usb/usb_protocol.d" \ -"hal/utils/src/utils_event.d" \ -"hal/src/hal_io.d" \ -"hpl/ramecc/hpl_ramecc.d" \ -"hpl/systick/hpl_systick.d" \ -"hpl/core/hpl_core_m4.d" \ -"hpl/evsys/hpl_evsys.d" \ -"hal/utils/src/utils_syscalls.d" \ -"usb/class/cdc/device/cdcdf_acm.d" \ -"gcc/gcc/startup_samd51.d" \ -"hal/src/hal_i2c_m_sync.d" \ -"hpl/usb/hpl_usb.d" \ -"hal/src/hal_evsys.d" \ -"usb/class/msc/device/mscdf.d" \ -"hpl/nvmctrl/hpl_nvmctrl.d" \ -"hal/src/hal_pwm.d" \ -"hal/src/hal_timer.d" \ -"hal/src/hal_spi_m_sync.d" \ -"usb/class/hid/device/hiddf_mouse.d" \ -"hal/utils/src/utils_list.d" \ -"hpl/dmac/hpl_dmac.d" \ -"hal/utils/src/utils_assert.d" \ -"hpl/mclk/hpl_mclk.d" \ -"hal/src/hal_delay.d" \ -"hpl/core/hpl_init.d" \ -"hpl/pm/hpl_pm.d" \ -"hal/src/hal_flash.d" \ -"hpl/gclk/hpl_gclk.d" \ -"hal/src/hal_usb_device.d" \ -"usb_start.d" \ -"hal/src/hal_init.d" \ -"hal/src/hal_usart_sync.d" \ -"usb/class/hid/device/hiddf_keyboard.d" \ -"hpl/trng/hpl_trng.d" \ -"hal/src/hal_rand_sync.d" \ -"hpl/dac/hpl_dac.d" \ -"driver_init.d" \ -"hal/src/hal_adc_sync.d" \ -"hpl/osc32kctrl/hpl_osc32kctrl.d" \ -"main.d" \ -"examples/driver_examples.d" \ -"hpl/rtc/hpl_rtc.d" \ -"hal/src/hal_sleep.d" \ -"hpl/sercom/hpl_sercom.d" \ -"hal/src/hal_dac_sync.d" \ -"hal/src/hal_gpio.d" \ -"usb/class/hid/device/hiddf_generic.d" \ -"hal/src/hal_atomic.d" \ -"hpl/tc/hpl_tc.d" \ -"usb/device/usbdc.d" \ -"hpl/oscctrl/hpl_oscctrl.d" \ -"hpl/adc/hpl_adc.d" \ -"gcc/system_samd51.d" \ -"atmel_start.d" - -OUTPUT_FILE_NAME :=AtmelStart -QUOTE := " -OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf -OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf - -vpath %.c ../ -vpath %.s ../ -vpath %.S ../ - -# All Target -all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) - -# Linker target - - -$(OUTPUT_FILE_PATH): $(OBJS) - @echo Building target: $@ - @echo Invoking: ARM/GNU Linker - $(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \ --Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m4 \ - \ - \ --T"../gcc/gcc/samd51g19a_flash.ld" \ --L"../gcc/gcc" - @echo Finished building target: $@ - - "arm-none-eabi-objcopy" -O binary "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).bin" - "arm-none-eabi-objcopy" -O ihex -R .eeprom -R .fuse -R .lock -R .signature \ - "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).hex" - "arm-none-eabi-objcopy" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma \ - .eeprom=0 --no-change-warnings -O binary "$(OUTPUT_FILE_NAME).elf" \ - "$(OUTPUT_FILE_NAME).eep" || exit 0 - "arm-none-eabi-objdump" -h -S "$(OUTPUT_FILE_NAME).elf" > "$(OUTPUT_FILE_NAME).lss" - "arm-none-eabi-size" "$(OUTPUT_FILE_NAME).elf" - -# Compiler targets - - -%.o: %.c - @echo Building file: $< - @echo ARM/GNU C Compiler - $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAMD51G19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ --MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" - @echo Finished building: $< - -%.o: %.s - @echo Building file: $< - @echo ARM/GNU Assembler - $(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAMD51G19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ --MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" - @echo Finished building: $< - -%.o: %.S - @echo Building file: $< - @echo ARM/GNU Preprocessing Assembler - $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAMD51G19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ --I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dac" -I"../hpl/dmac" -I"../hpl/evsys" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/trng" -I"../hpl/usb" -I"../hri" -I"../" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/class/composite/device" -I"../usb/class/hid" -I"../usb/class/hid/device" -I"../usb/class/hub" -I"../usb/class/msc" -I"../usb/class/msc/device" -I"../usb/class/vendor" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ --MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" - @echo Finished building: $< - -# Detect changes in the dependent files and recompile the respective object files. -ifneq ($(MAKECMDGOALS),clean) -ifneq ($(strip $(DEPS)),) --include $(DEPS) -endif -endif - -$(SUB_DIRS): - $(MK_DIR) "$@" - -clean: - rm -f $(OBJS_AS_ARGS) - rm -f $(OUTPUT_FILE_PATH) - rm -f $(DEPS_AS_ARGS) - rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \ - $(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \ - $(OUTPUT_FILE_NAME).srec diff --git a/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_flash.ld b/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_flash.ld deleted file mode 100644 index c1a2dd39b..000000000 --- a/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_flash.ld +++ /dev/null @@ -1,163 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal FLASH on the SAMD51G19A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 - qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > rom - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > rom - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - .bkupram (NOLOAD): - { - . = ALIGN(8); - _sbkupram = .; - *(.bkupram .bkupram.*); - . = ALIGN(8); - _ebkupram = .; - } > bkupram - - .qspi (NOLOAD): - { - . = ALIGN(8); - _sqspi = .; - *(.qspi .qspi.*); - . = ALIGN(8); - _eqspi = .; - } > qspi - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_sram.ld b/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_sram.ld deleted file mode 100644 index cf8e5a314..000000000 --- a/atmel-samd/asf4/samd51/gcc/gcc/samd51g19a_sram.ld +++ /dev/null @@ -1,162 +0,0 @@ -/** - * \file - * - * \brief Linker script for running in internal SRAM on the SAMD51G19A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -SEARCH_DIR(.) - -/* Memory Spaces Definitions */ -MEMORY -{ - ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 - bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 - qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 -} - -/* The stack size used by the application. NOTE: you need to adjust according to your application. */ -STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; - -/* Section Definitions */ -SECTIONS -{ - .text : - { - . = ALIGN(4); - _sfixed = .; - KEEP(*(.vectors .vectors.*)) - *(.text .text.* .gnu.linkonce.t.*) - *(.glue_7t) *(.glue_7) - *(.rodata .rodata* .gnu.linkonce.r.*) - *(.ARM.extab* .gnu.linkonce.armextab.*) - - /* Support C constructors, and C destructors in both user code - and the C library. This also provides support for C++ code. */ - . = ALIGN(4); - KEEP(*(.init)) - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - - . = ALIGN(4); - _efixed = .; /* End of text section */ - } > ram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - PROVIDE_HIDDEN (__exidx_start = .); - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ram - PROVIDE_HIDDEN (__exidx_end = .); - - . = ALIGN(4); - _etext = .; - - .relocate : AT (_etext) - { - . = ALIGN(4); - _srelocate = .; - *(.ramfunc .ramfunc.*); - *(.data .data.*); - . = ALIGN(4); - _erelocate = .; - } > ram - - .bkupram (NOLOAD): - { - . = ALIGN(8); - _sbkupram = .; - *(.bkupram .bkupram.*); - . = ALIGN(8); - _ebkupram = .; - } > bkupram - - .qspi (NOLOAD): - { - . = ALIGN(8); - _sqspi = .; - *(.qspi .qspi.*); - . = ALIGN(8); - _eqspi = .; - } > qspi - - /* .bss section which is used for uninitialized data */ - .bss (NOLOAD) : - { - . = ALIGN(4); - _sbss = . ; - _szero = .; - *(.bss .bss.*) - *(COMMON) - . = ALIGN(4); - _ebss = . ; - _ezero = .; - } > ram - - /* stack section */ - .stack (NOLOAD): - { - . = ALIGN(8); - _sstack = .; - . = . + STACK_SIZE; - . = ALIGN(8); - _estack = .; - } > ram - - . = ALIGN(4); - _end = . ; -} diff --git a/atmel-samd/asf4/samd51/gcc/gcc/startup_samd51.c b/atmel-samd/asf4/samd51/gcc/gcc/startup_samd51.c deleted file mode 100644 index 2528e635f..000000000 --- a/atmel-samd/asf4/samd51/gcc/gcc/startup_samd51.c +++ /dev/null @@ -1,680 +0,0 @@ -/** - * \file - * - * \brief gcc starttup file for SAMD51 - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "samd51.h" - -/* Initialize segments */ -extern uint32_t _sfixed; -extern uint32_t _efixed; -extern uint32_t _etext; -extern uint32_t _srelocate; -extern uint32_t _erelocate; -extern uint32_t _szero; -extern uint32_t _ezero; -extern uint32_t _sstack; -extern uint32_t _estack; - -/** \cond DOXYGEN_SHOULD_SKIP_THIS */ -int main(void); -/** \endcond */ - -void __libc_init_array(void); - -/* Default empty handler */ -void Dummy_Handler(void); - -/* Cortex-M4 core handlers */ -void NMI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void MemManage_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void BusFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void UsageFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SVC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void DebugMon_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); - -/* Peripherals handlers */ -void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void MCLK_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void OSCCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ -void OSCCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ -void OSCCTRL_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, - OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, - OSCCTRL_DFLLRDY */ -void OSCCTRL_3_Handler(void) __attribute__(( - weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ -void OSCCTRL_4_Handler(void) __attribute__(( - weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ -void OSC32KCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SUPC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, - SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY - */ -void SUPC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */ -void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void EIC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */ -void EIC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */ -void EIC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */ -void EIC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */ -void EIC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */ -void EIC_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */ -void EIC_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */ -void EIC_7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */ -void EIC_8_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */ -void EIC_9_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */ -void EIC_10_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */ -void EIC_11_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */ -void EIC_12_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */ -void EIC_13_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */ -void EIC_14_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */ -void EIC_15_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */ -void FREQM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void NVMCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, - NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, - NVMCTRL_6, NVMCTRL_7 */ -void NVMCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ -void DMAC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ -void DMAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ -void DMAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ -void DMAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ -void DMAC_4_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, - DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, - DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, - DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, - DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, - DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, - DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, - DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, - DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, - DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, - DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, - DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, - DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, - DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, - DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, - DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, - DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, - DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ -void EVSYS_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */ -void EVSYS_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */ -void EVSYS_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */ -void EVSYS_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */ -void EVSYS_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, - EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, - EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, - EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, - EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, - EVSYS_OVR_9 */ -void PAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TAL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TAL_BRK */ -void TAL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TAL_IPS_0, TAL_IPS_1 */ -void RAMECC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void SERCOM0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */ -void SERCOM0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */ -void SERCOM0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */ -void SERCOM0_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ -void SERCOM1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */ -void SERCOM1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */ -void SERCOM1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */ -void SERCOM1_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ -void SERCOM2_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */ -void SERCOM2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */ -void SERCOM2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */ -void SERCOM2_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ -void SERCOM3_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */ -void SERCOM3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */ -void SERCOM3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */ -void SERCOM3_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ -#ifdef ID_SERCOM4 -void SERCOM4_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */ -void SERCOM4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */ -void SERCOM4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */ -void SERCOM4_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ -#endif -#ifdef ID_SERCOM5 -void SERCOM5_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */ -void SERCOM5_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */ -void SERCOM5_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */ -void SERCOM5_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ -#endif -#ifdef ID_SERCOM6 -void SERCOM6_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */ -void SERCOM6_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */ -void SERCOM6_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */ -void SERCOM6_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ -#endif -#ifdef ID_SERCOM7 -void SERCOM7_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */ -void SERCOM7_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */ -void SERCOM7_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */ -void SERCOM7_3_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ -#endif -#ifdef ID_CAN0 -void CAN0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_CAN1 -void CAN1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_USB -void USB_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, - USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, - USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, - USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, - USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, - USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, - USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, - USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, - USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, - USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, - USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, - USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, - USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, - USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ -void USB_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */ -void USB_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, - USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, - USB_TRCPT0_6, USB_TRCPT0_7 */ -void USB_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, - USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, - USB_TRCPT1_6, USB_TRCPT1_7 */ -#endif -#ifdef ID_GMAC -void GMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void TCC0_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, - TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ -void TCC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */ -void TCC0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */ -void TCC0_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */ -void TCC0_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */ -void TCC0_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */ -void TCC0_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */ -void TCC1_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, - TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ -void TCC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */ -void TCC1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */ -void TCC1_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */ -void TCC1_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */ -void TCC2_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, - TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ -void TCC2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */ -void TCC2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */ -void TCC2_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */ -#ifdef ID_TCC3 -void TCC3_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, - TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ -void TCC3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */ -void TCC3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */ -#endif -#ifdef ID_TCC4 -void TCC4_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, - TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ -void TCC4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */ -void TCC4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */ -#endif -void TC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_TC4 -void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC5 -void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC6 -void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_TC7 -void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void PDEC_0_Handler(void) - __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ -void PDEC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */ -void PDEC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */ -void ADC0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */ -void ADC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */ -void ADC1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */ -void ADC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */ -void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void DAC_0_Handler(void) - __attribute__((weak, - alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ -void DAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */ -void DAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */ -void DAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */ -void DAC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */ -#ifdef ID_I2S -void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void PCC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void AES_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -void TRNG_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_ICM -void ICM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_PUKCC -void PUKCC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -void QSPI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#ifdef ID_SDHC0 -void SDHC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif -#ifdef ID_SDHC1 -void SDHC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); -#endif - -/* Exception Table */ -__attribute__((section(".vectors"), used)) const DeviceVectors exception_table - = { - - /* Configure Initial Stack Pointer, using linker-generated symbols */ - .pvStack = (void *)(&_estack), - - .pfnReset_Handler = (void *)Reset_Handler, - .pfnNMI_Handler = (void *)NMI_Handler, - .pfnHardFault_Handler = (void *)HardFault_Handler, - .pfnMemManage_Handler = (void *)MemManage_Handler, - .pfnBusFault_Handler = (void *)BusFault_Handler, - .pfnUsageFault_Handler = (void *)UsageFault_Handler, - .pvReservedM9 = (void *)(0UL), /* Reserved */ - .pvReservedM8 = (void *)(0UL), /* Reserved */ - .pvReservedM7 = (void *)(0UL), /* Reserved */ - .pvReservedM6 = (void *)(0UL), /* Reserved */ - .pfnSVC_Handler = (void *)SVC_Handler, - .pfnDebugMon_Handler = (void *)DebugMon_Handler, - .pvReservedM3 = (void *)(0UL), /* Reserved */ - .pfnPendSV_Handler = (void *)PendSV_Handler, - .pfnSysTick_Handler = (void *)SysTick_Handler, - - /* Configurable interrupts */ - .pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */ - .pfnMCLK_Handler = (void *)MCLK_Handler, /* 1 Main Clock */ - .pfnOSCCTRL_0_Handler = (void *)OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - .pfnOSCCTRL_1_Handler = (void *)OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - .pfnOSCCTRL_2_Handler - = (void *)OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, - OSCCTRL_DFLLRDY */ - .pfnOSCCTRL_3_Handler = (void *) - OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - .pfnOSCCTRL_4_Handler = (void *) - OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - .pfnOSC32KCTRL_Handler = (void *)OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ - .pfnSUPC_0_Handler = (void *)SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, - SUPC_VCORERDY, SUPC_VREGRDY */ - .pfnSUPC_1_Handler = (void *)SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */ - .pfnWDT_Handler = (void *)WDT_Handler, /* 10 Watchdog Timer */ - .pfnRTC_Handler = (void *)RTC_Handler, /* 11 Real-Time Counter */ - .pfnEIC_0_Handler = (void *)EIC_0_Handler, /* 12 EIC_EXTINT_0 */ - .pfnEIC_1_Handler = (void *)EIC_1_Handler, /* 13 EIC_EXTINT_1 */ - .pfnEIC_2_Handler = (void *)EIC_2_Handler, /* 14 EIC_EXTINT_2 */ - .pfnEIC_3_Handler = (void *)EIC_3_Handler, /* 15 EIC_EXTINT_3 */ - .pfnEIC_4_Handler = (void *)EIC_4_Handler, /* 16 EIC_EXTINT_4 */ - .pfnEIC_5_Handler = (void *)EIC_5_Handler, /* 17 EIC_EXTINT_5 */ - .pfnEIC_6_Handler = (void *)EIC_6_Handler, /* 18 EIC_EXTINT_6 */ - .pfnEIC_7_Handler = (void *)EIC_7_Handler, /* 19 EIC_EXTINT_7 */ - .pfnEIC_8_Handler = (void *)EIC_8_Handler, /* 20 EIC_EXTINT_8 */ - .pfnEIC_9_Handler = (void *)EIC_9_Handler, /* 21 EIC_EXTINT_9 */ - .pfnEIC_10_Handler = (void *)EIC_10_Handler, /* 22 EIC_EXTINT_10 */ - .pfnEIC_11_Handler = (void *)EIC_11_Handler, /* 23 EIC_EXTINT_11 */ - .pfnEIC_12_Handler = (void *)EIC_12_Handler, /* 24 EIC_EXTINT_12 */ - .pfnEIC_13_Handler = (void *)EIC_13_Handler, /* 25 EIC_EXTINT_13 */ - .pfnEIC_14_Handler = (void *)EIC_14_Handler, /* 26 EIC_EXTINT_14 */ - .pfnEIC_15_Handler = (void *)EIC_15_Handler, /* 27 EIC_EXTINT_15 */ - .pfnFREQM_Handler = (void *)FREQM_Handler, /* 28 Frequency Meter */ - .pfnNVMCTRL_0_Handler = (void *) - NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, - NVMCTRL_7 */ - .pfnNVMCTRL_1_Handler = (void *)NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - .pfnDMAC_0_Handler = (void *)DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - .pfnDMAC_1_Handler = (void *)DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - .pfnDMAC_2_Handler = (void *)DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - .pfnDMAC_3_Handler = (void *)DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - .pfnDMAC_4_Handler = (void *)DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, - DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, - DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, - DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, - DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, - DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, - DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, - DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, - DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, - DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, - DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, - DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, - DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, - DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, - DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, - DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, - DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, - DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, - DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, - DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, - DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - .pfnEVSYS_0_Handler = (void *)EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */ - .pfnEVSYS_1_Handler = (void *)EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */ - .pfnEVSYS_2_Handler = (void *)EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */ - .pfnEVSYS_3_Handler = (void *)EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */ - .pfnEVSYS_4_Handler = (void *)EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, - EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, - EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, - EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - .pfnPAC_Handler = (void *)PAC_Handler, /* 41 Peripheral Access Controller */ - .pfnTAL_0_Handler = (void *)TAL_0_Handler, /* 42 TAL_BRK */ - .pfnTAL_1_Handler = (void *)TAL_1_Handler, /* 43 TAL_IPS_0, TAL_IPS_1 */ - .pvReserved44 = (void *)(0UL), /* 44 Reserved */ - .pfnRAMECC_Handler = (void *)RAMECC_Handler, /* 45 RAM ECC */ - .pfnSERCOM0_0_Handler = (void *)SERCOM0_0_Handler, /* 46 SERCOM0_0 */ - .pfnSERCOM0_1_Handler = (void *)SERCOM0_1_Handler, /* 47 SERCOM0_1 */ - .pfnSERCOM0_2_Handler = (void *)SERCOM0_2_Handler, /* 48 SERCOM0_2 */ - .pfnSERCOM0_3_Handler = (void *)SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - .pfnSERCOM1_0_Handler = (void *)SERCOM1_0_Handler, /* 50 SERCOM1_0 */ - .pfnSERCOM1_1_Handler = (void *)SERCOM1_1_Handler, /* 51 SERCOM1_1 */ - .pfnSERCOM1_2_Handler = (void *)SERCOM1_2_Handler, /* 52 SERCOM1_2 */ - .pfnSERCOM1_3_Handler = (void *)SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - .pfnSERCOM2_0_Handler = (void *)SERCOM2_0_Handler, /* 54 SERCOM2_0 */ - .pfnSERCOM2_1_Handler = (void *)SERCOM2_1_Handler, /* 55 SERCOM2_1 */ - .pfnSERCOM2_2_Handler = (void *)SERCOM2_2_Handler, /* 56 SERCOM2_2 */ - .pfnSERCOM2_3_Handler = (void *)SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - .pfnSERCOM3_0_Handler = (void *)SERCOM3_0_Handler, /* 58 SERCOM3_0 */ - .pfnSERCOM3_1_Handler = (void *)SERCOM3_1_Handler, /* 59 SERCOM3_1 */ - .pfnSERCOM3_2_Handler = (void *)SERCOM3_2_Handler, /* 60 SERCOM3_2 */ - .pfnSERCOM3_3_Handler = (void *)SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ -#ifdef ID_SERCOM4 - .pfnSERCOM4_0_Handler = (void *)SERCOM4_0_Handler, /* 62 SERCOM4_0 */ - .pfnSERCOM4_1_Handler = (void *)SERCOM4_1_Handler, /* 63 SERCOM4_1 */ - .pfnSERCOM4_2_Handler = (void *)SERCOM4_2_Handler, /* 64 SERCOM4_2 */ - .pfnSERCOM4_3_Handler = (void *)SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ -#else - .pvReserved62 = (void *)(0UL), /* 62 Reserved */ - .pvReserved63 = (void *)(0UL), /* 63 Reserved */ - .pvReserved64 = (void *)(0UL), /* 64 Reserved */ - .pvReserved65 = (void *)(0UL), /* 65 Reserved */ -#endif -#ifdef ID_SERCOM5 - .pfnSERCOM5_0_Handler = (void *)SERCOM5_0_Handler, /* 66 SERCOM5_0 */ - .pfnSERCOM5_1_Handler = (void *)SERCOM5_1_Handler, /* 67 SERCOM5_1 */ - .pfnSERCOM5_2_Handler = (void *)SERCOM5_2_Handler, /* 68 SERCOM5_2 */ - .pfnSERCOM5_3_Handler = (void *)SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ -#else - .pvReserved66 = (void *)(0UL), /* 66 Reserved */ - .pvReserved67 = (void *)(0UL), /* 67 Reserved */ - .pvReserved68 = (void *)(0UL), /* 68 Reserved */ - .pvReserved69 = (void *)(0UL), /* 69 Reserved */ -#endif -#ifdef ID_SERCOM6 - .pfnSERCOM6_0_Handler = (void *)SERCOM6_0_Handler, /* 70 SERCOM6_0 */ - .pfnSERCOM6_1_Handler = (void *)SERCOM6_1_Handler, /* 71 SERCOM6_1 */ - .pfnSERCOM6_2_Handler = (void *)SERCOM6_2_Handler, /* 72 SERCOM6_2 */ - .pfnSERCOM6_3_Handler = (void *)SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ -#else - .pvReserved70 = (void *)(0UL), /* 70 Reserved */ - .pvReserved71 = (void *)(0UL), /* 71 Reserved */ - .pvReserved72 = (void *)(0UL), /* 72 Reserved */ - .pvReserved73 = (void *)(0UL), /* 73 Reserved */ -#endif -#ifdef ID_SERCOM7 - .pfnSERCOM7_0_Handler = (void *)SERCOM7_0_Handler, /* 74 SERCOM7_0 */ - .pfnSERCOM7_1_Handler = (void *)SERCOM7_1_Handler, /* 75 SERCOM7_1 */ - .pfnSERCOM7_2_Handler = (void *)SERCOM7_2_Handler, /* 76 SERCOM7_2 */ - .pfnSERCOM7_3_Handler = (void *)SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ -#else - .pvReserved74 = (void *)(0UL), /* 74 Reserved */ - .pvReserved75 = (void *)(0UL), /* 75 Reserved */ - .pvReserved76 = (void *)(0UL), /* 76 Reserved */ - .pvReserved77 = (void *)(0UL), /* 77 Reserved */ -#endif -#ifdef ID_CAN0 - .pfnCAN0_Handler = (void *)CAN0_Handler, /* 78 Control Area Network 0 */ -#else - .pvReserved78 = (void *)(0UL), /* 78 Reserved */ -#endif -#ifdef ID_CAN1 - .pfnCAN1_Handler = (void *)CAN1_Handler, /* 79 Control Area Network 1 */ -#else - .pvReserved79 = (void *)(0UL), /* 79 Reserved */ -#endif -#ifdef ID_USB - .pfnUSB_0_Handler = (void *) - USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, - USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, - USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, - USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, - USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, - USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, - USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, - USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, - USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, - USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, - USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - .pfnUSB_1_Handler = (void *)USB_1_Handler, /* 81 USB_SOF_HSOF */ - .pfnUSB_2_Handler = (void *)USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, - USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - .pfnUSB_3_Handler = (void *)USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, - USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ -#else - .pvReserved80 = (void *)(0UL), /* 80 Reserved */ - .pvReserved81 = (void *)(0UL), /* 81 Reserved */ - .pvReserved82 = (void *)(0UL), /* 82 Reserved */ - .pvReserved83 = (void *)(0UL), /* 83 Reserved */ -#endif -#ifdef ID_GMAC - .pfnGMAC_Handler = (void *)GMAC_Handler, /* 84 Ethernet MAC */ -#else - .pvReserved84 = (void *)(0UL), /* 84 Reserved */ -#endif - .pfnTCC0_0_Handler = (void *) - TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, - TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - .pfnTCC0_1_Handler = (void *)TCC0_1_Handler, /* 86 TCC0_MC_0 */ - .pfnTCC0_2_Handler = (void *)TCC0_2_Handler, /* 87 TCC0_MC_1 */ - .pfnTCC0_3_Handler = (void *)TCC0_3_Handler, /* 88 TCC0_MC_2 */ - .pfnTCC0_4_Handler = (void *)TCC0_4_Handler, /* 89 TCC0_MC_3 */ - .pfnTCC0_5_Handler = (void *)TCC0_5_Handler, /* 90 TCC0_MC_4 */ - .pfnTCC0_6_Handler = (void *)TCC0_6_Handler, /* 91 TCC0_MC_5 */ - .pfnTCC1_0_Handler = (void *) - TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, - TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - .pfnTCC1_1_Handler = (void *)TCC1_1_Handler, /* 93 TCC1_MC_0 */ - .pfnTCC1_2_Handler = (void *)TCC1_2_Handler, /* 94 TCC1_MC_1 */ - .pfnTCC1_3_Handler = (void *)TCC1_3_Handler, /* 95 TCC1_MC_2 */ - .pfnTCC1_4_Handler = (void *)TCC1_4_Handler, /* 96 TCC1_MC_3 */ - .pfnTCC2_0_Handler = (void *) - TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, - TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - .pfnTCC2_1_Handler = (void *)TCC2_1_Handler, /* 98 TCC2_MC_0 */ - .pfnTCC2_2_Handler = (void *)TCC2_2_Handler, /* 99 TCC2_MC_1 */ - .pfnTCC2_3_Handler = (void *)TCC2_3_Handler, /* 100 TCC2_MC_2 */ -#ifdef ID_TCC3 - .pfnTCC3_0_Handler - = (void *)TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, - TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - .pfnTCC3_1_Handler = (void *)TCC3_1_Handler, /* 102 TCC3_MC_0 */ - .pfnTCC3_2_Handler = (void *)TCC3_2_Handler, /* 103 TCC3_MC_1 */ -#else - .pvReserved101 = (void *)(0UL), /* 101 Reserved */ - .pvReserved102 = (void *)(0UL), /* 102 Reserved */ - .pvReserved103 = (void *)(0UL), /* 103 Reserved */ -#endif -#ifdef ID_TCC4 - .pfnTCC4_0_Handler - = (void *)TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, - TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - .pfnTCC4_1_Handler = (void *)TCC4_1_Handler, /* 105 TCC4_MC_0 */ - .pfnTCC4_2_Handler = (void *)TCC4_2_Handler, /* 106 TCC4_MC_1 */ -#else - .pvReserved104 = (void *)(0UL), /* 104 Reserved */ - .pvReserved105 = (void *)(0UL), /* 105 Reserved */ - .pvReserved106 = (void *)(0UL), /* 106 Reserved */ -#endif - .pfnTC0_Handler = (void *)TC0_Handler, /* 107 Basic Timer Counter 0 */ - .pfnTC1_Handler = (void *)TC1_Handler, /* 108 Basic Timer Counter 1 */ - .pfnTC2_Handler = (void *)TC2_Handler, /* 109 Basic Timer Counter 2 */ - .pfnTC3_Handler = (void *)TC3_Handler, /* 110 Basic Timer Counter 3 */ -#ifdef ID_TC4 - .pfnTC4_Handler = (void *)TC4_Handler, /* 111 Basic Timer Counter 4 */ -#else - .pvReserved111 = (void *)(0UL), /* 111 Reserved */ -#endif -#ifdef ID_TC5 - .pfnTC5_Handler = (void *)TC5_Handler, /* 112 Basic Timer Counter 5 */ -#else - .pvReserved112 = (void *)(0UL), /* 112 Reserved */ -#endif -#ifdef ID_TC6 - .pfnTC6_Handler = (void *)TC6_Handler, /* 113 Basic Timer Counter 6 */ -#else - .pvReserved113 = (void *)(0UL), /* 113 Reserved */ -#endif -#ifdef ID_TC7 - .pfnTC7_Handler = (void *)TC7_Handler, /* 114 Basic Timer Counter 7 */ -#else - .pvReserved114 = (void *)(0UL), /* 114 Reserved */ -#endif - .pfnPDEC_0_Handler = (void *)PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - .pfnPDEC_1_Handler = (void *)PDEC_1_Handler, /* 116 PDEC_MC_0 */ - .pfnPDEC_2_Handler = (void *)PDEC_2_Handler, /* 117 PDEC_MC_1 */ - .pfnADC0_0_Handler = (void *)ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */ - .pfnADC0_1_Handler = (void *)ADC0_1_Handler, /* 119 ADC0_RESRDY */ - .pfnADC1_0_Handler = (void *)ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */ - .pfnADC1_1_Handler = (void *)ADC1_1_Handler, /* 121 ADC1_RESRDY */ - .pfnAC_Handler = (void *)AC_Handler, /* 122 Analog Comparators */ - .pfnDAC_0_Handler - = (void *)DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - .pfnDAC_1_Handler = (void *)DAC_1_Handler, /* 124 DAC_EMPTY_0 */ - .pfnDAC_2_Handler = (void *)DAC_2_Handler, /* 125 DAC_EMPTY_1 */ - .pfnDAC_3_Handler = (void *)DAC_3_Handler, /* 126 DAC_RESRDY_0 */ - .pfnDAC_4_Handler = (void *)DAC_4_Handler, /* 127 DAC_RESRDY_1 */ -#ifdef ID_I2S - .pfnI2S_Handler = (void *)I2S_Handler, /* 128 Inter-IC Sound Interface */ -#else - .pvReserved128 = (void *)(0UL), /* 128 Reserved */ -#endif - .pfnPCC_Handler = (void *)PCC_Handler, /* 129 Parallel Capture Controller */ - .pfnAES_Handler = (void *)AES_Handler, /* 130 Advanced Encryption Standard */ - .pfnTRNG_Handler = (void *)TRNG_Handler, /* 131 True Random Generator */ -#ifdef ID_ICM - .pfnICM_Handler = (void *)ICM_Handler, /* 132 Integrity Check Monitor */ -#else - .pvReserved132 = (void *)(0UL), /* 132 Reserved */ -#endif -#ifdef ID_PUKCC - .pfnPUKCC_Handler = (void *)PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ -#else - .pvReserved133 = (void *)(0UL), /* 133 Reserved */ -#endif - .pfnQSPI_Handler = (void *)QSPI_Handler, /* 134 Quad SPI interface */ -#ifdef ID_SDHC0 - .pfnSDHC0_Handler = (void *)SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */ -#else - .pvReserved135 = (void *)(0UL), /* 135 Reserved */ -#endif -#ifdef ID_SDHC1 - .pfnSDHC1_Handler = (void *)SDHC1_Handler /* 136 SD/MMC Host Controller 1 */ -#else - .pvReserved136 = (void *)(0UL) /* 136 Reserved */ -#endif -}; - -/** - * \brief This is the code that gets called on processor reset. - * To initialize the device, and call the main() routine. - */ -void Reset_Handler(void) -{ - uint32_t *pSrc, *pDest; - - /* Initialize the relocate segment */ - pSrc = &_etext; - pDest = &_srelocate; - - if (pSrc != pDest) { - for (; pDest < &_erelocate;) { - *pDest++ = *pSrc++; - } - } - - /* Clear the zero segment */ - for (pDest = &_szero; pDest < &_ezero;) { - *pDest++ = 0; - } - - /* Set the vector table base address */ - pSrc = (uint32_t *)&_sfixed; - SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); - -#if __FPU_USED - /* Enable FPU */ - SCB->CPACR |= (0xFu << 20); - __DSB(); - __ISB(); -#endif - - /* Initialize the C library */ - //__libc_init_array(); - - /* Branch to main function */ - main(); - - /* Infinite loop */ - while (1) - ; -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Dummy_Handler(void) -{ - while (1) { - } -} diff --git a/atmel-samd/asf4/samd51/gcc/system_samd51.c b/atmel-samd/asf4/samd51/gcc/system_samd51.c deleted file mode 100644 index 07ddede56..000000000 --- a/atmel-samd/asf4/samd51/gcc/system_samd51.c +++ /dev/null @@ -1,64 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup. - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "samd51.h" - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (48000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} diff --git a/atmel-samd/asf4/samd51/hal/documentation/adc_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/adc_sync.rst deleted file mode 100644 index d189565ad..000000000 --- a/atmel-samd/asf4/samd51/hal/documentation/adc_sync.rst +++ /dev/null @@ -1,74 +0,0 @@ -====================== -ADC Synchronous driver -====================== - -An ADC (Analog-to-Digital Converter) converts analog signals to digital values. -A reference signal with a known voltage level is quantified into equally -sized chunks, each representing a digital value from 0 to the highest number -possible with the bit resolution supported by the ADC. The input voltage -measured by the ADC is compared against these chunks and the chunk with the -closest voltage level defines the digital value that can be used to represent -the analog input voltage level. - -Usually an ADC can operate in either differential or single-ended mode. -In differential mode two signals (V+ and V-) are compared against each other -and the resulting digital value represents the relative voltage level between -V+ and V-. This means that if the input voltage level on V+ is lower than on -V- the digital value is negative, which also means that in differential -mode one bit is lost to the sign. In single-ended mode only V+ is compared -against the reference voltage, and the resulting digital value can only be -positive, but the full bit-range of the ADC can be used. - -Usually multiple resolutions are supported by the ADC, lower resolution can -reduce the conversion time, but lose accuracy. - -Some ADCs has a gain stage on the input lines which can be used to increase the -dynamic range. The default gain value is usually x1, which means that the -conversion range is from 0V to the reference voltage. -Applications can change the gain stage, to increase or reduce the conversion -range. - -The window mode allows the conversion result to be compared to a set of -predefined threshold values. Applications can use callback function to monitor -if the conversion result exceeds predefined threshold value. - -Usually multiple reference voltages are supported by the ADC, both internal and -external with difference voltage levels. The reference voltage have an impact -on the accuracy, and should be selected to cover the full range of the analog -input signal and never less than the expected maximum input voltage. - -There are two conversion modes supported by ADC, single shot and free running. -In single shot mode the ADC only make one conversion when triggered by the -application, in free running mode it continues to make conversion from it -is triggered until it is stopped by the application. When window monitoring, -the ADC should be set to free running mode. - -Features --------- -* Initialization and de-initialization -* Support multiple Conversion Mode, Single or Free run -* Start ADC Conversion -* Read Conversion Result - -Applications ------------- -* Measurement of internal sensor. E.g., MCU internal temperature sensor value. -* Measurement of external sensor. E.g., Temperature, humidity sensor value. -* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave. - -Dependencies ------------- -* ADC hardware - -Concurrency ------------ -N/A - -Limitations ------------ -N/A - -Knows issues and workarounds ----------------------------- -N/A - diff --git a/atmel-samd/asf4/samd51/hal/documentation/dac_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/dac_sync.rst deleted file mode 100644 index b3f322929..000000000 --- a/atmel-samd/asf4/samd51/hal/documentation/dac_sync.rst +++ /dev/null @@ -1,41 +0,0 @@ -====================== -DAC Synchronous driver -====================== - -A DAC (Digital-to-Analog Converter) converts digital value to an analog voltage. -The digital value from 0 to the highest represent the output voltage value. -The digital highest value possible with the bit resolution supported by the -DAC. For example a 10 bit resolution DAC hardware, the highest value is 1024. -The highest output voltage possible with the reference voltage. - -The driver can convert a serials digital value. The pre-defined data should -be an data array. Application can invoke dac_sync_write to start the conversation. - -Features --------- -* Initialization and de-initialization -* Enabling and disabling -* Support for DACs with channels -* Writing buffers with multiple samples to DAC - -Applications ------------- -* Generate audio signals by connecting the DAC output to a speaker -* Generate a reference voltage - -Dependencies ------------- -* DAC hardware - -Concurrency ------------ -N/A - -Limitations ------------ -N/A - -Knows issues and workarounds ----------------------------- -N/A - diff --git a/atmel-samd/asf4/samd51/hal/documentation/evsys.rst b/atmel-samd/asf4/samd51/hal/documentation/evsys.rst deleted file mode 100644 index 01d40bc56..000000000 --- a/atmel-samd/asf4/samd51/hal/documentation/evsys.rst +++ /dev/null @@ -1,24 +0,0 @@ -=================== -Event system driver -=================== - -Event system allows autonomous, low-latency and configurable communication between peripherals. - -Several peripherals can be configured to generate and/or respond to signals known as events. The exact condition -to generate an event, or the action taken upon receiving an event, is specific to each peripheral. Peripherals that -respond to events are event users, peripherals that generate events are called event generators. A peripheral can have -one or more event generators and can have one or more event users. - -Communication is made without CPU intervention and without consuming system resources such as bus or RAM bandwidth. This -reduces the load on the CPU and system resources, compared to a traditional interrupt-based system. - -The Event System consists of several channels which route the internal events from generators -to users. Each event generator can be selected as source for multiple channels, but a channel cannot -be set to use multiple event generators at the same time. - -Event system driver allows to configure event system of an MCU. - -Limitations ------------ - - - Event channel configuration is static diff --git a/atmel-samd/asf4/samd51/hal/documentation/flash.rst b/atmel-samd/asf4/samd51/hal/documentation/flash.rst deleted file mode 100644 index fcc86e63f..000000000 --- a/atmel-samd/asf4/samd51/hal/documentation/flash.rst +++ /dev/null @@ -1,52 +0,0 @@ -The Flash Driver -================ - -Flash is a re-programmable memory that retains program and data -storage even with power off. - -User can write or read several bytes from any valid address in a flash. - -As to the erase/lock/unlock command, the input parameter of address should -be a bytes address aligned with the page start, otherwise, the command will fail -to be executed. At the meantime, the number of pages that can be locked or unlocked -at once depends on region size of the flash. User can get the real number -from the function return value which could be different for the different devices. - -Features --------- - -* Initialization/de-initialization -* Writing/Reading bytes -* Locking/Unlocking/Erasing pages -* Notifications about errors or being ready for a new command - -Applications ------------- - -* Mini disk which can retain program and data storage -* Boot loader -* Non volatile storage - -Dependencies ------------- - -The peripheral which controls a re-programmable flash memory. - -Concurrency ------------ - -N/A - -Limitations ------------ - -User should pay attention to set a proper stack size in their application, -since the driver manages a temporary buffer in stack to cache unchanged data -when calling flash write and erase function. -Due to flash memory architecture of SAMD21/D20/L21/L22/C20/C21/D09/D10/D11/R21, -write operation erazes row content before each write. - -Known issues and workarounds ----------------------------- - -N/A diff --git a/atmel-samd/asf4/samd51/hal/documentation/i2c_master_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/i2c_master_sync.rst deleted file mode 100644 index 77b4f6e9c..000000000 --- a/atmel-samd/asf4/samd51/hal/documentation/i2c_master_sync.rst +++ /dev/null @@ -1,87 +0,0 @@ -============================= -I2C Master synchronous driver -============================= - -I2C (Inter-Integrated Circuit) is a two wire serial interface usually used -for on-board low-speed bi-directional communication between controllers and -peripherals. The master device is responsible for initiating and controlling -all transfers on the I2C bus. Only one master device can be active on the I2C -bus at the time, but the master role can be transferred between devices on the -same I2C bus. I2C uses only two bidirectional open-drain lines, usually -designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up -resistors. - -The stop condition is automatically controlled by the driver if the I/O write and -read functions are used, but can be manually controlled by using the -i2c_m_sync_transfer function. - -Often a master accesses different information in the slave by accessing -different registers in the slave. This is done by first sending a message to -the target slave containing the register address, followed by a repeated start -condition (no stop condition between) ending with transferring register data. -This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read -function, but limited to 8-bit register addresses. - -I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in -Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to -stick within the SCL clock frequency range supported by the selected mode. -The requested SCL clock frequency is not validated by the -i2c_m_sync_set_baudrate function against the selected I2C mode. - -Features --------- - - * I2C Master support - * Initialization and de-initialization - * Enabling and disabling - * Run-time bus speed configuration - * Write and read I2C messages - * Slave register access functions (limited to 8-bit address) - * Manual or automatic stop condition generation - * 10- and 7- bit addressing - * I2C Modes supported - +----------------------+-------------------+ - |* Standard/Fast mode | (SCL: 1 - 400kHz) | - +----------------------+-------------------+ - |* Fastmode+ | (SCL: 1 - 1000kHz)| - +----------------------+-------------------+ - |* Highspeed mode | (SCL: 1 - 3400kHz)| - +----------------------+-------------------+ - -Applications ------------- - -* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals -* Data communication between micro controllers -* Controlling displays - -Dependencies ------------- - -* I2C Master capable hardware - -Concurrency ------------ - -N/A - -Limitations ------------ - -General -^^^^^^^ - - * System Managmenet Bus (SMBus) not supported. - * Power Management Bus (PMBus) not supported. - -Clock considerations -^^^^^^^^^^^^^^^^^^^^ - -The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected. - -Known issues and workarounds ----------------------------- - -N/A - - diff --git a/atmel-samd/asf4/samd51/hal/documentation/pwm.rst b/atmel-samd/asf4/samd51/hal/documentation/pwm.rst deleted file mode 100644 index 71785c634..000000000 --- a/atmel-samd/asf4/samd51/hal/documentation/pwm.rst +++ /dev/null @@ -1,53 +0,0 @@ -The PWM Driver(bare-bone) -========================= - -Pulse-width modulation (PWM) is used to create an analog behavior -digitally by controlling the amount of power transferred to the -connected peripheral. This is achieved by controlling the high period -(duty-cycle) of a periodic signal. - -User can change the period or duty cycle whenever PWM is running. The -function pwm_set_parameters is used to configure these two parameters. -Note these are raw register values and the parameter duty_cycle means -the period of first half during one cycle, which should be not beyond -total period value. - -In addition, user can also get multi PWM channels output from different -peripherals at the same time, which is implemented more flexible by the -function pointers. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* Run-time control of PWM duty-cycle and period -* Notifications about errors and one PWM cycle is done - -Applications ------------- - -Motor control, ballast, LED, H-bridge, power converters, and -other types of power control applications. - -Dependencies ------------- - -The peripheral which can perform waveform generation like frequency -generation and pulse-width modulation, such as Timer/Counter. - -Concurrency ------------ - -N/A - -Limitations ------------ - -The current driver doesn't support the features like recoverable, -non-recoverable faults, dithering, dead-time insertion. - -Known issues and workarounds ----------------------------- - -N/A diff --git a/atmel-samd/asf4/samd51/hal/documentation/rand_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/rand_sync.rst deleted file mode 100644 index 19ec1d367..000000000 --- a/atmel-samd/asf4/samd51/hal/documentation/rand_sync.rst +++ /dev/null @@ -1,43 +0,0 @@ -========================================== -Random Number Generator Synchronous driver -========================================== - -Random Number Generator (RAND) generates a sequence of numbers that can not -be reasonably predicted better than by a random chance. - -In some implementation cases, seed is required for the Random Number Generator -to generate random numbers. rand_sync_set_seed is used to update the seed. -If it's actually not required by the generator implementation, the function just -returns ERR_UNSUPPORTED_OP. - -Features --------- - -* Initialization and de-initialization -* Enabling and Disabling -* Setting seed -* 8-bit and 32-bit random data/data array generation - -Applications ------------- - -* Generate random keys for data encryption - -Dependencies ------------- - -* Random number generation hardware/software - -Concurrency ------------ -N/A - -Limitations ------------ - -N/A - -Known issues and workarounds ----------------------------- -N/A - diff --git a/atmel-samd/asf4/samd51/hal/documentation/spi_master_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/spi_master_sync.rst deleted file mode 100644 index 4fbe45e29..000000000 --- a/atmel-samd/asf4/samd51/hal/documentation/spi_master_sync.rst +++ /dev/null @@ -1,51 +0,0 @@ -The SPI Master Synchronous Driver -================================= - -The serial peripheral interface (SPI) is a synchronous serial communication -interface. - -SPI devices communicate in full duplex mode using a master-slave -architecture with a single master. The master device originates the frame for -reading and writing. Multiple slave devices are supported through selection -with individual slave select (SS) lines. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* Control of the following settings: - - * Baudrate - * SPI mode - * Character size - * Data order -* Data transfer: transmission, reception and full-duplex - -Applications ------------- - -Send/receive/exchange data with a SPI slave device. E.g., serial flash, SD card, -LCD controller, etc. - -Dependencies ------------- - -SPI master capable hardware - -Concurrency ------------ - -N/A - -Limitations ------------ - -The slave select (SS) is not automatically inserted during read/write/transfer, -user must use I/O to control the devices' SS. - -Known issues and workarounds ----------------------------- - -N/A - diff --git a/atmel-samd/asf4/samd51/hal/documentation/timer.rst b/atmel-samd/asf4/samd51/hal/documentation/timer.rst deleted file mode 100644 index c5ca63d12..000000000 --- a/atmel-samd/asf4/samd51/hal/documentation/timer.rst +++ /dev/null @@ -1,52 +0,0 @@ -============================ -The Timer driver (bare-bone) -============================ - -The Timer driver provides means for delayed and periodical function invocation. - -A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has -been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a -configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically -changes execution delays and periods for all tasks in the timers task queue. - -A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue -and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on -the period set in the task configuration. -In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to -reuse the memory of expired task in the callback. - -Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available. - -Features --------- -* Initialization and de-initialization -* Starting and stopping -* Timer tasks - periodical invocation of functions -* Changing and obtaining of the period of a timer - -Applications ------------- -* Delayed and periodical function execution for middle-ware stacks and applications. - -Dependencies ------------- -* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt. - -Concurrency ------------ -The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during -the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed -until the task adding or removing is complete. - -The task queue is not protected from the access by interrupts not used by the driver. Due to this -it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes -the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver. - -Limitations ------------ -* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts. -* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task. - -Knows issues and workarounds ----------------------------- -Not applicable diff --git a/atmel-samd/asf4/samd51/hal/documentation/usart_sync.rst b/atmel-samd/asf4/samd51/hal/documentation/usart_sync.rst deleted file mode 100644 index 73f76b749..000000000 --- a/atmel-samd/asf4/samd51/hal/documentation/usart_sync.rst +++ /dev/null @@ -1,58 +0,0 @@ -The USART Synchronous Driver -============================ - -The universal synchronous and asynchronous receiver and transmitter -(USART) is usually used to transfer data from one device to the other. - -User can set action for flow control pins by function usart_set_flow_control, -if the flow control is enabled. All the available states are defined in union -usart_flow_control_state. - -Note that user can set state of flow control pins only if automatic support of -the flow control is not supported by the hardware. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* Control of the following settings: - - * Baudrate - * UART or USRT communication mode - * Character size - * Data order - * Flow control -* Data transfer: transmission, reception - -Applications ------------- - -They are commonly used in a terminal application or low-speed communication -between devices. - -Dependencies ------------- - -USART capable hardware. - -Concurrency ------------ - -Write buffer should not be changed while data is being sent. - - -Limitations ------------ - -* The driver does not support 9-bit character size. -* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. -And the SCK pin can't be set directly. Application can use a GCLK output PIN -to generate SCK. For example to communicate with a SMARTCARD with ISO7816 -(F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be -config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. - -Known issues and workarounds ----------------------------- - -N/A diff --git a/atmel-samd/asf4/samd51/hal/documentation/usb_device_async.rst b/atmel-samd/asf4/samd51/hal/documentation/usb_device_async.rst deleted file mode 100644 index 647eec071..000000000 --- a/atmel-samd/asf4/samd51/hal/documentation/usb_device_async.rst +++ /dev/null @@ -1,195 +0,0 @@ -The USB Device Asynchronous Driver -================================== - -Universal Serial Bus (USB) is an industry standard that defines the cables, -connectors and communication protocols used in a bus for connection, -communication, and power supply between computers and electronic devices. - -The USB device driver provides necessary APIs to support USB Device states and -USB data flow. So that the USB Device enumeration, class and vendor support can -be implemented base on it. The driver is asynchronous, which means that all USB -data processing is done in callbacks.. - -To be recognized by a host, a USB device must handle a subset of the USB events. -The USB device should build up control communication to report its descriptors -to the host and accept host's requests. An application or upper stack that uses -the USB device driver should have its descriptors prepared, catch the callbacks, -monitor the control requests and handle them correctly. -Usually, a USB device application that can be enumerated may use the following -sequence: - -* Initialize -* Register callback and handle Reset event, where: - - * Initialize endpoint 0 - * Register callbacks for endpoint 0, where some of the standard requests - defined in Chapter 9, USB specification - (see `USB 2.0 Documents `_) - are handled - - * Setup request handling callback - - * On *GetDeviceDescriptor* request, sends device descriptor - * On *GetConfigurationDescriptor* request, sends configuration descriptors - * On *SetAddress* request sends no data, just goes to status phase - * On *SetConfigure* request initialize and enable other endpoints, sends - no data, just goes to status phase - * Transfer done handling callback - - * On *SetAddress* request apply the new address - * On *SetConfigure* request a global variable can be set to indicates - that the host driver is loaded and device is ready to work - * Enable endpoint 0 -* Enable -* Attach device - -To support USB transfer on endpoints, endpoints information is stored -by the driver internally, including control request data, endpoint status, -callbacks and transfer data pointers. The number of endpoints that the driver -can support is defined through configuration. To optimize RAM usage, the -number of endpoints the driver needs to support should be minimized. - -Features --------- - -* Initialization/de-initialization -* Enabling/disabling -* USB device attachment/detachment -* USB device address control -* USB working speed status -* USB device frame number and micro frame number status -* Sending remote wakeup to host -* Callback management for following USB events: - - * Start of Frame (SOF) - * Other USB events: - - * VBus change - * Reset - * Wakeup - * Linked Power Management (LPM) Suspend - * Suspend - * Error -* Endpoints management: - - * Endpoint initialization/de-initialization - * Endpoint enabling/disabling - * Control endpoint setup request packet - * Data transfer and abort - * Endpoint halt state control - * Endpoint status, including: - - * Endpoint address - * Last transfer result status code - * Last error status code - * Current transfer state - * Transfer size and done count - * Endpoint callback management for endpoint and its transfer events: - - * In case a setup request received on control endpoint - * In case transfer finished with/without error - -Applications ------------- - -USB Device stack, to monitor USB events, handle control requests and process -data. - -Dependencies ------------- - -* USB device capable hardware -* 48MHz clock for low-speed and full-speed and 480MHz clock for high-speed - -Concurrency ------------ - -N/A - -Limitations ------------ - -* When a buffer is used by a USB endpoint to transfer data, it must be kept - unchanged while the transfer is in progress. -* After receiving a request that has no data expected, the transfer function - must be called with data length zero to complete control status phase. - -Known issues and workarounds ----------------------------- - -N/A - -Considerations for D21 USB --------------------------- - -Clocks -^^^^^^ - -DFLL must be used to generate 48MHz clock for USB device with either of the -following mode: - -* USB Clock Recovery Mode - - * Set "DFLL Enable", "Bypass Coarse Lock", "Chill Cycle Disable", - "USB Clock Recovery Mode", "Stable DFLL Frequency" - * Clear "Wait Lock" - * Leave "Operating Mode Selection" to "Closed Loop Mode" - -* Closed Loop Mode - - * Set "DFLL Enable" - * Clear "USB Clock Recovery Mode", "Stable DFLL Frequency" - * Select "Closed Loop Mode" of "Operating Mode Selection" - * Set "DFLL Multiply Factor" to 1464 or 1465 (48000000/32768) - * Select "Reference Clock Source" to use 32768Hz source, e.g., use GCLK1 and - for GCLK1 settings: - - * Set "Generic Clock Generator Enable" - * Select "XOSC32K" of "Generic clock generator 1 source", and for XOSC32K - settings: - - * Set "External 32K Oscillator Enable", "Enable 32KHz Output", - "Enable XTAL" - * Set a right value for "Startup time for the 32K Oscillator", e.g., - 1125092 us - -Endpoints -^^^^^^^^^ - -Each USB device endpoint number supports two endpoint addresses, corresponding -to IN and OUT endpoint. E.g., for endpoint 1, the endpoint IN has address 0x81 -and endpoint OUT has address 0x01. Thus, the possible supported endpoint -addresses are almost two times of max endpoint number (endpoint 0 must be used -as control endpoint instead of dedicated IN and OUT endpoints). - -Buffering and RAM usage optimization -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -When transferring data through USB device endpoints, buffer pointers can be -used to let endpoint get access to the buffer, but there are some limits: - -* For control endpoint there must always be a buffer available to put received - setup packet. -* For IN endpoint (transmit to host) the data must in RAM. -* For OUT endpoint (receive from host) the data pointer must be aligned, and - the data size must be aligned by max endpoint size and not zero. - -The driver has option for each endpoint to allocate internal static buffer as -cache to buffer input/output data, to remove upper limits. The configuration -affects the parameter check of transfer functions, and the RAM usage. - -* For control endpoints, cache buffer must be enabled to fill setup packet. - In addition, to support unaligned OUT packet and IN packet inside flash, the - buffer size must be equal to or larger than max endpoint size. -* For OUT endpoints, if the cache is allocated, it's possible to pass unaligned - buffer address and buffer size to transfer function. Else the transfer - function only accepts aligned buffer with it's size multiple of endpoint - packet size. -* For IN endpoints, if the cache is allocated, it's possible to pass buffer - pointer to internal flash or other memory part other than RAM to the transfer - function. - -To optimize the RAM usage, the configuration of max endpoint number, max number -of endpoints supported and the buffer usage of used input and/or output -endpoints can be adjusted. - diff --git a/atmel-samd/asf4/samd51/hal/include/hal_adc_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_adc_sync.h deleted file mode 100644 index fb4604aa5..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_adc_sync.h +++ /dev/null @@ -1,287 +0,0 @@ -/** - * \file - * - * \brief ADC functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_ADC_SYNC_H_INCLUDED -#define _HAL_ADC_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_adc_sync - * - * @{ - */ - -/** - * \brief ADC descriptor - * - * The ADC descriptor forward declaration. - */ -struct adc_sync_descriptor; - -/** - * \brief ADC descriptor - */ -struct adc_sync_descriptor { - /** ADC device */ - struct _adc_sync_device device; -}; - -/** - * \brief Initialize ADC - * - * This function initializes the given ADC descriptor. - * It checks if the given hardware is not initialized and if the given hardware - * is permitted to be initialized. - * - * \param[out] descr An ADC descriptor to initialize - * \param[in] hw The pointer to hardware instance - * \param[in] func The pointer to a set of functions pointers - * - * \return Initialization status. - */ -int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func); - -/** - * \brief Deinitialize ADC - * - * This function deinitializes the given ADC descriptor. - * It checks if the given hardware is initialized and if the given hardware is - * permitted to be deinitialized. - * - * \param[in] descr An ADC descriptor to deinitialize - * - * \return De-initialization status. - */ -int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr); - -/** - * \brief Enable ADC - * - * Use this function to set the ADC peripheral to enabled state. - * - * \param[in] descr Pointer to the ADC descriptor - * \param[in] channel Channel number - * - * \return Operation status - * - */ -int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel); - -/** - * \brief Disable ADC - * - * Use this function to set the ADC peripheral to disabled state. - * - * \param[in] descr Pointer to the ADC descriptor - * \param[in] channel Channel number - * - * \return Operation status - * - */ -int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel); - -/** - * \brief Read data from ADC - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] channel Channel number - * \param[in] buf A buffer to read data to - * \param[in] length The size of a buffer - * - * \return The number of bytes read. - */ -int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, - const uint16_t length); - -/** - * \brief Set ADC reference source - * - * This function sets ADC reference source. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] reference A reference source to set - * - * \return Status of the ADC reference source setting. - */ -int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference); - -/** - * \brief Set ADC resolution - * - * This function sets ADC resolution. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] resolution A resolution to set - * - * \return Status of the ADC resolution setting. - */ -int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution); - -/** - * \brief Set ADC input source of a channel - * - * This function sets ADC positive and negative input sources. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] pos_input A positive input source to set - * \param[in] neg_input A negative input source to set - * \param[in] channel Channel number - * - * \return Status of the ADC channels setting. - */ -int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel); - -/** - * \brief Set ADC conversion mode - * - * This function sets ADC conversion mode. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] mode A conversion mode to set - * - * \return Status of the ADC conversion mode setting. - */ -int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode); - -/** - * \brief Set ADC differential mode - * - * This function sets ADC differential mode. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] channel Channel number - * \param[in] mode A differential mode to set - * - * \return Status of the ADC differential mode setting. - */ -int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel, - const enum adc_differential_mode mode); - -/** - * \brief Set ADC channel gain - * - * This function sets ADC channel gain. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] channel Channel number - * \param[in] gain A gain to set - * - * \return Status of the ADC gain setting. - */ -int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, - const adc_gain_t gain); - -/** - * \brief Set ADC window mode - * - * This function sets ADC window mode. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] mode A window mode to set - * - * \return Status of the ADC window mode setting. - */ -int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode); - -/** - * \brief Set ADC thresholds - * - * This function sets ADC positive and negative thresholds. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] low_threshold A lower thresholds to set - * \param[in] up_threshold An upper thresholds to set - * - * \return Status of the ADC thresholds setting. - */ -int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold); - -/** - * \brief Retrieve threshold state - * - * This function retrieves ADC threshold state. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[out] state The threshold state - * - * \return The state of ADC thresholds state retrieving. - */ -int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, - adc_threshold_status_t *const state); - -/** - * \brief Check if conversion is complete - * - * This function checks if the ADC has finished the conversion. - * - * \param[in] descr The pointer to the ADC descriptor - * \param[in] channel Channel number - * - * \return The status of ADC conversion completion checking. - * \retval 1 The conversion is complete - * \retval 0 The conversion is not complete - */ -int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t adc_sync_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#include - -#endif /* _HAL_ADC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_atomic.h b/atmel-samd/asf4/samd51/hal/include/hal_atomic.h deleted file mode 100644 index 8a51b2a96..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_atomic.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * \file - * - * \brief Critical sections related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_ATOMIC_H_INCLUDED -#define _HAL_ATOMIC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_atomic - * - *@{ - */ - -/** - * \brief Type for the register holding global interrupt enable flag - */ -typedef uint32_t hal_atomic_t; - -/** - * \brief Helper macro for entering critical sections - * - * This macro is recommended to be used instead of a direct call - * hal_enterCritical() function to enter critical - * sections. No semicolon is required after the macro. - * - * \section atomic_usage Usage Example - * \code - * CRITICAL_SECTION_ENTER() - * Critical code - * CRITICAL_SECTION_LEAVE() - * \endcode - */ -#define CRITICAL_SECTION_ENTER() \ - { \ - volatile hal_atomic_t __atomic; \ - atomic_enter_critical(&__atomic); - -/** - * \brief Helper macro for leaving critical sections - * - * This macro is recommended to be used instead of a direct call - * hal_leaveCritical() function to leave critical - * sections. No semicolon is required after the macro. - * - * \section atomic_usage Usage Example - * \code - * CRITICAL_SECTION_ENTER() - * Some critical code - * CRITICAL_SECTION_LEAVE() - * \endcode - */ -#define CRITICAL_SECTION_LEAVE() \ - atomic_leave_critical(&__atomic); \ - } - -/** - * \brief Disable interrupts, enter critical section - * - * Disables global interrupts. Supports nested critical sections, - * so that global interrupts are only re-enabled - * upon leaving the outermost nested critical section. - * - * \param[out] atomic The pointer to a variable to store the value of global - * interrupt enable flag - */ -void atomic_enter_critical(hal_atomic_t volatile *atomic); - -/** - * \brief Exit atomic section - * - * Enables global interrupts. Supports nested critical sections, - * so that global interrupts are only re-enabled - * upon leaving the outermost nested critical section. - * - * \param[in] atomic The pointer to a variable, which stores the latest stored - * value of the global interrupt enable flag - */ -void atomic_leave_critical(hal_atomic_t volatile *atomic); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t atomic_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_dac_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_dac_sync.h deleted file mode 100644 index 79c68b2cb..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_dac_sync.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - * \file - * - * \brief DAC functionality declaration. - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef HAL_SYNC_DAC_H_INCLUDED -#define HAL_SYNC_DAC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_dac_sync - * - *@{ - */ - -/** - * \brief DAC synchronous descriptor. - * - * The DAC descriptor forward declaration. - */ -struct dac_sync_descriptor; - -/** - * \brief DAC synchronous channel descriptor. - * - */ -struct dac_sync_channel { - /** Pointer to buffer what to be converted */ - uint16_t *buffer; - /** The length of buffer */ - uint32_t length; -}; - -/** - * \brief DAC synchronous descriptor - */ -struct dac_sync_descriptor { - /** DAC device */ - struct _dac_sync_device device; - /** DAC selected channel */ - struct dac_sync_channel sel_ch[CHANNEL_NUM]; -}; - -/** \brief Initialize the DAC HAL instance and hardware. - * \param[out] descr A DAC descriptor to initialize - * \param[in] hw The pointer to hardware instance - * \return Operation status. - */ -int32_t dac_sync_init(struct dac_sync_descriptor *const descr, void *const hw); - -/** \brief Deinitialize the DAC HAL instance and hardware. - * \param[in] descr Pointer to the HAL DAC descriptor - * \return Operation status. - */ -int32_t dac_sync_deinit(struct dac_sync_descriptor *const descr); - -/** \brief Enable DAC channel. - * \param[in] descr Pointer to the HAL DAC descriptor - * \param[in] ch Channel number - * \return Operation status. - */ -int32_t dac_sync_enable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch); - -/** \brief Disable DAC channel. - * \param[in] descr Pointer to the HAL DAC descriptor - * \param[in] ch Channel number - * \return Operation status. - */ -int32_t dac_sync_disable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch); - -/** \brief DAC converts digital data to analog output. - * \param[in] descr Pointer to the HAL DAC descriptor - * \param[in] ch the Channel selected to output - * \param[in] buffer Pointer to digital data or buffer - * \param[in] length The number of elements in the buffer - * \return Operation status. - */ -int32_t dac_sync_write(struct dac_sync_descriptor *const descr, const uint8_t ch, uint16_t *buffer, uint32_t length); - -/** \brief Get DAC driver version - * - * \return Current driver version. - */ -uint32_t dac_sync_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_DAC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_delay.h b/atmel-samd/asf4/samd51/hal/include/hal_delay.h deleted file mode 100644 index 48fee826f..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_delay.h +++ /dev/null @@ -1,99 +0,0 @@ -/** - * \file - * - * \brief HAL delay related functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -#ifndef _HAL_DELAY_H_INCLUDED -#define _HAL_DELAY_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_delay Delay Driver - * - *@{ - */ - -/** - * \brief Initialize Delay driver - * - * \param[in] hw The pointer to hardware instance - */ -void delay_init(void *const hw); - -/** - * \brief Perform delay in us - * - * This function performs delay for the given amount of microseconds. - * - * \param[in] us The amount delay in us - */ -void delay_us(const uint16_t us); - -/** - * \brief Perform delay in ms - * - * This function performs delay for the given amount of milliseconds. - * - * \param[in] ms The amount delay in ms - */ -void delay_ms(const uint16_t ms); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t delay_get_version(void); - -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_evsys.h b/atmel-samd/asf4/samd51/hal/include/hal_evsys.h deleted file mode 100644 index f24fa4c66..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_evsys.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief HAL event system related functionality declaration. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include - -#ifndef _HAL_EVSYS_H_INCLUDED -#define _HAL_EVSYS_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_evsys - * - * @{ - */ - -/** - * \brief Initialize event system. - * - * \return Initialization status. - */ -int32_t event_system_init(void); - -/** - * \brief Deinitialize event system. - * - * \return De-initialization status. - */ -int32_t event_system_deinit(void); - -/** - * \brief Enable event reception by the given user from the given channel - * - * \param[in] user A user to enable - * \param[in] channel A channel the user is assigned to - * - * \return Status of operation. - */ -int32_t event_system_enable_user(const uint16_t user, const uint16_t channel); - -/** - * \brief Disable event reception by the given user from the given channel - * - * \param[in] user A user to disable - * \param[in] channel A channel the user is assigned to - * - * \return Status of operation. - */ -int32_t event_system_disable_user(const uint16_t user, const uint16_t channel); - -/** - * \brief Enable event generation by the given generator for the given channel - * - * \param[in] generator A generator to disable - * \param[in] channel A channel the generator is assigned to - * - * \return Status of operation. - */ -int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel); - -/** - * \brief Disable event generation by the given generator for the given channel - * - * \param[in] generator A generator to disable - * \param[in] channel A channel the generator is assigned to - * - * \return Status of operation. - */ -int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t event_system_get_version(void); - -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_EVSYS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_flash.h b/atmel-samd/asf4/samd51/hal/include/hal_flash.h deleted file mode 100644 index ffba519de..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_flash.h +++ /dev/null @@ -1,219 +0,0 @@ -/** - * \file - * - * \brief Flash related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_FLASH_H_INCLUDED -#define _HAL_FLASH_H_INCLUDED - -#include - -/** - * \addtogroup doc_driver_hal_flash - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Forward declaration of flash_descriptor. */ -struct flash_descriptor; - -/** The callback types */ -enum flash_cb_type { - /** Callback type for ready to accept a new command */ - FLASH_CB_READY, - /** Callback type for error */ - FLASH_CB_ERROR, - FLASH_CB_N -}; - -/** \brief Prototype of callback on FLASH - * - */ -typedef void (*flash_cb_t)(struct flash_descriptor *const descr); - -/** \brief FLASH HAL callbacks - * - */ -struct flash_callbacks { - /** Callback invoked when ready to accept a new command */ - flash_cb_t cb_ready; - /** Callback invoked when error occurs */ - flash_cb_t cb_error; -}; - -/** \brief FLASH HAL driver struct for asynchronous access - */ -struct flash_descriptor { - /** Pointer to FLASH device instance */ - struct _flash_device dev; - /** Callbacks for asynchronous transfer */ - struct flash_callbacks callbacks; -}; - -/** \brief Initialize the FLASH HAL instance and hardware for callback mode - * - * Initialize FLASH HAL with interrupt mode (uses callbacks). - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] hw Pointer to the hardware base. - * \return Initialize status. - */ -int32_t flash_init(struct flash_descriptor *flash, void *const hw); - -/** \brief Deinitialize the FLASH HAL instance - * - * Abort transfer, disable and reset FLASH, and deinitialize software. - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \return Deinitialze status. - */ -int32_t flash_deinit(struct flash_descriptor *flash); - -/** \brief Writes a number of bytes to a page in the internal Flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address to write into flash - * \param[in] buffer Pointer to a buffer where the content - * will be written to the flash - * \param[in] length Number of bytes to write - * \return Write status. - */ -int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length); - -/** \brief Appends a number of bytes to a page in the internal Flash - * - * This functions never erases the flash before writing. - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address to write to flash - * \param[in] buffer Pointer to a buffer with data to write to flash - * \param[in] length Number of bytes to append - * \return Append status. - */ -int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - -/** \brief Reads a number of bytes to a page in the internal Flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] src_addr Source bytes address to read from flash - * \param[out] buffer Pointer to a buffer where the content - * of the read pages will be stored - * \param[in] length Number of bytes to read - * \return Read status. - */ -int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length); - -/** \brief Register a function as FLASH transfer completion callback - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] type Callback type (\ref flash_cb_type). - * \param[in] func Pointer to callback function. - * \retval 0 Success - * \retval -1 Error - */ -int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func); - -/** \brief Execute lock in the internal flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address aligned with page - * start to be locked - * \param[in] page_nums Number of pages to be locked - * - * \return Real locked numbers of pages. - */ -int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); - -/** \brief Execute unlock in the internal flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address aligned with page - * start to be unlocked - * \param[in] page_nums Number of pages to be unlocked - * - * \return Real unlocked numbers of pages. - */ -int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); - -/** \brief Execute erase in the internal flash - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] dst_addr Destination bytes address aligned with page - * start to be erased - * \param[in] page_nums Number of pages to be erased - * \retval 0 Success - * \retval -1 Error - */ -int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums); - -/** - * \brief Get the flash page size - * - * \param[in, out] flash Pointer to the HAL FLASH instance - * - * \return The flash page size - */ -uint32_t flash_get_page_size(struct flash_descriptor *flash); - -/** - * \brief Get the number of flash page - * - * \param[in, out] flash Pointer to the HAL FLASH instance. - * - * \return The flash total page numbers - */ -uint32_t flash_get_total_pages(struct flash_descriptor *flash); - -/** \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t flash_get_version(void); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* ifndef _HAL_FLASH_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_gpio.h b/atmel-samd/asf4/samd51/hal/include/hal_gpio.h deleted file mode 100644 index f0e8af8d7..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_gpio.h +++ /dev/null @@ -1,212 +0,0 @@ -/** - * \file - * - * \brief Port - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ -#ifndef _HAL_GPIO_INCLUDED_ -#define _HAL_GPIO_INCLUDED_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Set gpio pull mode - * - * Set pin pull mode, non existing pull modes throws an fatal assert - * - * \param[in] pin The pin number for device - * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin high with internal - * resistor - * GPIO_PULL_UP = Pull pin low with internal resistor - * GPIO_PULL_OFF = Disable pin pull mode - */ -static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) -{ - _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); -} - -/** - * \brief Set pin function - * - * Select which function a pin will be used for - * - * \param[in] pin The pin number for device - * \param[in] function The pin function is given by a 32-bit wide bitfield - * found in the header files for the device - * - */ -static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) -{ - _gpio_set_pin_function(pin, function); -} - -/** - * \brief Set port data direction - * - * Select if the pin data direction is input, output or disabled. - * If disabled state is not possible, this function throws an assert. - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to the - * corresponding pin - * \param[in] direction GPIO_DIRECTION_IN = Data direction in - * GPIO_DIRECTION_OUT = Data direction out - * GPIO_DIRECTION_OFF = Disables the pin - * (low power state) - */ -static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction) -{ - _gpio_set_direction(port, mask, direction); -} - -/** - * \brief Set gpio data direction - * - * Select if the pin data direction is input, output or disabled. - * If disabled state is not possible, this function throws an assert. - * - * \param[in] pin The pin number for device - * \param[in] direction GPIO_DIRECTION_IN = Data direction in - * GPIO_DIRECTION_OUT = Data direction out - * GPIO_DIRECTION_OFF = Disables the pin - * (low power state) - */ -static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) -{ - _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); -} - -/** - * \brief Set port level - * - * Sets output level on the pins defined by the bit mask - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply port level to the corresponding - * pin - * \param[in] level true = Pin levels set to "high" state - * false = Pin levels set to "low" state - */ -static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) -{ - _gpio_set_level(port, mask, level); -} - -/** - * \brief Set gpio level - * - * Sets output level on a pin - * - * \param[in] pin The pin number for device - * \param[in] level true = Pin level set to "high" state - * false = Pin level set to "low" state - */ -static inline void gpio_set_pin_level(const uint8_t pin, const bool level) -{ - _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); -} - -/** - * \brief Toggle out level on pins - * - * Toggle the pin levels on pins defined by bit mask - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding - * pin - */ -static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) -{ - _gpio_toggle_level(port, mask); -} - -/** - * \brief Toggle output level on pin - * - * Toggle the pin levels on pins defined by bit mask - * - * \param[in] pin The pin number for device - */ -static inline void gpio_toggle_pin_level(const uint8_t pin) -{ - _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); -} - -/** - * \brief Get input level on pins - * - * Read the input level on pins connected to a port - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - */ -static inline uint32_t gpio_get_port_level(const enum gpio_port port) -{ - return _gpio_get_level(port); -} - -/** - * \brief Get level on pin - * - * Reads the level on pins connected to a port - * - * \param[in] pin The pin number for device - */ -static inline bool gpio_get_pin_level(const uint8_t pin) -{ - return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); -} -/** - * \brief Get current driver version - */ -uint32_t gpio_get_version(void); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/atmel-samd/asf4/samd51/hal/include/hal_i2c_m_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_i2c_m_sync.h deleted file mode 100644 index 65741831a..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_i2c_m_sync.h +++ /dev/null @@ -1,254 +0,0 @@ -/** - * \file - * - * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_I2C_M_SYNC_H_INCLUDED -#define _HAL_I2C_M_SYNC_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_i2c_master_sync - * - * @{ - */ - -#define I2C_M_MAX_RETRY 1 - -/** - * \brief I2C descriptor structure, embed i2c_device & i2c_interface - */ -struct i2c_m_sync_desc { - struct _i2c_m_sync_device device; - struct io_descriptor io; - uint16_t slave_addr; -}; - -/** - * \brief Initialize synchronous I2C interface - * - * This function initializes the given I/O descriptor to be used as a - * synchronous I2C interface descriptor. - * It checks if the given hardware is not initialized and if the given hardware - * is permitted to be initialized. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - * \retval -1 The passed parameters were invalid or the interface is already initialized - * \retval 0 The initialization is completed successfully - */ -int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw); - -/** - * \brief Deinitialize I2C interface - * - * This function deinitializes the given I/O descriptor. - * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Uninitialization status. - * \retval -1 The passed parameters were invalid or the interface is already deinitialized - * \retval 0 The de-initialization is completed successfully - */ -int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c); - -/** - * \brief Set the slave device address - * - * This function sets the next transfer target slave I2C device address. - * It takes no effect to any already started access. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] addr The slave address to access - * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN - * - * \return Masked slave address. The mask is a maximum 10-bit address, and 10th - * bit is set if a 10-bit address is used - */ -int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len); - -/** - * \brief Set baudrate - * - * This function sets the I2C device to the specified baudrate. - * It only takes effect when the hardware is disabled. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] clkrate Unused parameter. Should always be 0 - * \param[in] baudrate The baudrate value set to master - * - * \return Whether successfully set the baudrate - * \retval -1 The passed parameters were invalid or the device is already enabled - * \retval 0 The baudrate set is completed successfully - */ -int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Sync version of enable hardware - * - * This function enables the I2C device, and then waits for this enabling operation to be done - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Whether successfully enable the device - * \retval -1 The passed parameters were invalid or the device enable failed - * \retval 0 The hardware enabling is completed successfully - */ -int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c); - -/** - * \brief Sync version of disable hardware - * - * This function disables the I2C device and then waits for this disabling operation to be done - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return Whether successfully disable the device - * \retval -1 The passed parameters were invalid or the device disable failed - * \retval 0 The hardware disabling is completed successfully - */ -int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c); - -/** - * \brief Sync version of write command to I2C slave - * - * This function will write the value to a specified register in the I2C slave device and - * then wait for this operation to be done. - * - * The sequence of this routine is - * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] reg The internal address/register of the I2C slave device - * \param[in] buffer The buffer holding data to write to the I2C slave device - * \param[in] length The length (in bytes) to write to the I2C slave device - * - * \return Whether successfully write to the device - * \retval <0 The passed parameters were invalid or write fail - * \retval 0 Writing to register is completed successfully - */ -int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); - -/** - * \brief Sync version of read register value from I2C slave - * - * This function will read a byte value from a specified register in the I2C slave device and - * then wait for this operation to be done. - * - * The sequence of this routine is - * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] reg The internal address/register of the I2C slave device - * \param[in] buffer The buffer to hold the read data from the I2C slave device - * \param[in] length The length (in bytes) to read from the I2C slave device - * - * \return Whether successfully read from the device - * \retval <0 The passed parameters were invalid or read fail - * \retval 0 Reading from register is completed successfully - */ -int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); - -/** - * \brief Sync version of transfer message to/from the I2C slave - * - * This function will transfer a message between the I2C slave and the master. This function will wait for the operation - * to be done. - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * \param[in] msg An i2c_m_msg struct - * - * \return The status of the operation - * \retval 0 Operation completed successfully - * \retval <0 Operation failed - */ -int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg); - -/** - * \brief Sync version of send stop condition on the i2c bus - * - * This function will create a stop condition on the i2c bus to release the bus - * - * \param[in] i2c An I2C descriptor, which is used to communicate through I2C - * - * \return The status of the operation - * \retval 0 Operation completed successfully - * \retval <0 Operation failed - */ -int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c); - -/** - * \brief Return I/O descriptor for this I2C instance - * - * This function will return a I/O instance for this I2C driver instance - * - * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C - * \param[in] io_descriptor A pointer to an I/O descriptor pointer type - * - * \return Error code - * \retval 0 No error detected - * \retval <0 Error code - */ -int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t i2c_m_sync_get_version(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/atmel-samd/asf4/samd51/hal/include/hal_init.h b/atmel-samd/asf4/samd51/hal/include/hal_init.h deleted file mode 100644 index a970943eb..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_init.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * \file - * - * \brief HAL initialization related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_INIT_H_INCLUDED -#define _HAL_INIT_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_init Init Driver - * - *@{ - */ - -/** - * \brief Initialize the hardware abstraction layer - * - * This function calls the various initialization functions. - * Currently the following initialization functions are supported: - * - System clock initialization - */ -static inline void init_mcu(void) -{ - _init_chip(); -} - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t init_get_version(void); - -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_io.h b/atmel-samd/asf4/samd51/hal/include/hal_io.h deleted file mode 100644 index e8005e3db..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_io.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - * \file - * - * \brief I/O related functionality declaration. - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_IO_INCLUDED -#define _HAL_IO_INCLUDED - -/** - * \addtogroup doc_driver_hal_helper_io I/O Driver - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief I/O descriptor - * - * The I/O descriptor forward declaration. - */ -struct io_descriptor; - -/** - * \brief I/O write function pointer type - */ -typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O read function pointer type - */ -typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O descriptor - */ -struct io_descriptor { - io_write_t write; /*! The write function pointer. */ - io_read_t read; /*! The read function pointer. */ -}; - -/** - * \brief I/O write interface - * - * This function writes up to \p length of bytes to a given I/O descriptor. - * It returns the number of bytes actually write. - * - * \param[in] descr An I/O descriptor to write - * \param[in] buf The buffer pointer to story the write data - * \param[in] length The number of bytes to write - * - * \return The number of bytes written - */ -int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); - -/** - * \brief I/O read interface - * - * This function reads up to \p length bytes from a given I/O descriptor, and - * stores it in the buffer pointed to by \p buf. It returns the number of bytes - * actually read. - * - * \param[in] descr An I/O descriptor to read - * \param[in] buf The buffer pointer to story the read data - * \param[in] length The number of bytes to read - * - * \return The number of bytes actually read. This number can be less than the - * requested length. E.g., in a driver that uses ring buffer for - * reception, it may depend on the availability of data in the - * ring buffer. - */ -int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HAL_IO_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_pwm.h b/atmel-samd/asf4/samd51/hal/include/hal_pwm.h deleted file mode 100644 index 29efc4bc4..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_pwm.h +++ /dev/null @@ -1,161 +0,0 @@ -/** - * \file - * - * \brief PWM functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef HAL_PWM_H_INCLUDED -#define HAL_PWM_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_pwm_async - * - *@{ - */ - -/** - * \brief PWM descriptor - * - * The PWM descriptor forward declaration. - */ -struct pwm_descriptor; - -/** - * \brief PWM callback type - */ -typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr); - -/** - * \brief PWM callback types - */ -enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB }; - -/** - * \brief PWM callbacks - */ -struct pwm_callbacks { - pwm_cb_t period; - pwm_cb_t error; -}; - -/** \brief PWM descriptor - */ -struct pwm_descriptor { - /** PWM device */ - struct _pwm_device device; - /** PWM callback structure */ - struct pwm_callbacks pwm_cb; -}; - -/** \brief Initialize the PWM HAL instance and hardware - * - * \param[in] descr Pointer to the HAL PWM descriptor - * \param[in] hw The pointer to hardware instance - * \param[in] func The pointer to a set of functions pointers - * - * \return Operation status. - */ -int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func); - -/** \brief Deinitialize the PWM HAL instance and hardware - * - * \param[in] descr Pointer to the HAL PWM descriptor - * - * \return Operation status. - */ -int32_t pwm_deinit(struct pwm_descriptor *const descr); - -/** \brief PWM output start - * - * \param[in] descr Pointer to the HAL PWM descriptor - * - * \return Operation status. - */ -int32_t pwm_enable(struct pwm_descriptor *const descr); - -/** \brief PWM output stop - * - * \param[in] descr Pointer to the HAL PWM descriptor - * - * \return Operation status. - */ -int32_t pwm_disable(struct pwm_descriptor *const descr); - -/** \brief Register PWM callback - * - * \param[in] descr Pointer to the HAL PWM descriptor - * \param[in] type Callback type - * \param[in] cb A callback function, passing NULL de-registers callback - * - * \return Operation status. - * \retval 0 Success - * \retval -1 Error - */ -int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb); - -/** \brief Change PWM parameter - * - * \param[in] descr Pointer to the HAL PWM descriptor - * \param[in] period Total period of one PWM cycle - * \param[in] duty_cycle Period of PWM first half during one cycle - * - * \return Operation status. - */ -int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, - const pwm_period_t duty_cycle); - -/** \brief Get PWM driver version - * - * \return Current driver version. - */ -uint32_t pwm_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_PWM;_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_rand_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_rand_sync.h deleted file mode 100644 index 481f48ca1..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_rand_sync.h +++ /dev/null @@ -1,144 +0,0 @@ -/** - * \file - * - * \brief Generic Random Number Generator (RAND) functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_RAND_SYNC_H_INCLUDED -#define _HAL_RAND_SYNC_H_INCLUDED - -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_rand_sync - * - *@{ - */ - -/** Random Number Generator polling device. */ -struct rand_sync_desc { - struct _rand_sync_dev dev; -}; - -/** - * \brief Initialize the Random Number Generator Driver - * \param[out] desc Pointer to the device descriptor instance struct - * \param[in, out] hw Pointer to the hardware for device instance - * \return Initialization operation result status, ERR_NONE (0) for OK. - */ -int32_t rand_sync_init(struct rand_sync_desc *const desc, void *const hw); - -/** - * \brief Deinitialize the Random Number Generator Driver - * \param[out] desc Pointer to the device descriptor instance struct - */ -void rand_sync_deinit(struct rand_sync_desc *const desc); - -/** - * \brief Enable the Random Number Generator Driver - * \param[out] desc Pointer to the device descriptor instance struct - * \return Enable operation result status, ERR_NONE (0) for OK. - */ -int32_t rand_sync_enable(struct rand_sync_desc *const desc); - -/** - * \brief Disable the Random Number Generator Driver - * \param[out] desc Pointer to the device descriptor instance struct - */ -void rand_sync_disable(struct rand_sync_desc *const desc); - -/** - * \brief Set seed for the Random Number Generator Driver - * \param[out] desc Pointer to the device descriptor instance struct - */ -int32_t rand_sync_set_seed(struct rand_sync_desc *const desc, const uint32_t seed); - -/** - * \brief Read the 8-bit Random Number - * \param[in] desc Pointer to the device descriptor instance struct - * \return The random number generated - */ -uint8_t rand_sync_read8(const struct rand_sync_desc *const desc); - -/** - * \brief Read the 32-bit Random Number - * \param[in] desc Pointer to the device descriptor instance struct - * \return The random number generated - */ -uint32_t rand_sync_read32(const struct rand_sync_desc *const desc); - -/** - * \brief Read the 8-bit Random Number Sequence into a buffer - * \param[in] desc Pointer to the device descriptor instance struct - * \param[out] buf Pointer to the buffer to fill an array of generated numbers - * \param[in] len Number of random numbers to read - */ -void rand_sync_read_buf8(const struct rand_sync_desc *const desc, uint8_t *buf, uint32_t len); - -/** - * \brief Read the 32-bit Random Number Sequence into a buffer - * \param[in] desc Pointer to the device descriptor instance struct - * \param[out] buf Pointer to the buffer to fill an array of generated numbers - * \param[in] len Number of random numbers to read - */ -void rand_sync_read_buf32(const struct rand_sync_desc *const desc, uint32_t *buf, uint32_t len); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t rand_sync_get_version(void); - -/* I/O read will be used to get random data. */ - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_RAND_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_sleep.h b/atmel-samd/asf4/samd51/hal/include/hal_sleep.h deleted file mode 100644 index 0a11856b1..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_sleep.h +++ /dev/null @@ -1,84 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SLEEP_H_INCLUDED -#define _HAL_SLEEP_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_helper_sleep - * - *@{ - */ - -/** - * \brief Set the sleep mode of the device and put the MCU to sleep - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see the data sheet. - * - * \param[in] mode Sleep mode to use - * - * \return The status of a sleep request - * \retval -1 The requested sleep mode was invalid or not available - * \retval 0 The operation completed successfully, returned after leaving the - * sleep - */ -int sleep(const uint8_t mode); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t sleep_get_version(void); -/**@}*/ -#ifdef __cplusplus -} -#endif -#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_spi_m_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_spi_m_sync.h deleted file mode 100644 index 2c630ff09..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_spi_m_sync.h +++ /dev/null @@ -1,220 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SPI_M_SYNC_H_INCLUDED -#define _HAL_SPI_M_SYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup doc_driver_hal_spi_master_sync - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** \brief SPI HAL driver struct for polling mode - * - */ -struct spi_m_sync_descriptor { - /** SPI device instance */ - struct _spi_sync_dev dev; - /** I/O read/write */ - struct io_descriptor io; - /** Flags for HAL driver */ - uint16_t flags; -}; - -/** \brief Initialize SPI HAL instance and hardware for polling mode - * - * Initialize SPI HAL with polling mode. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] hw Pointer to the hardware base. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_INVALID_DATA Error, initialized. - */ -int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw); - -/** \brief Deinitialize the SPI HAL instance and hardware - * - * Abort transfer, disable and reset SPI, deinit software. - * - * \param[in] spi Pointer to the HAL SPI instance. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval <0 Error code. - */ -void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi); - -/** \brief Enable SPI - * - * \param[in] spi Pointer to the HAL SPI instance. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval <0 Error code. - */ -void spi_m_sync_enable(struct spi_m_sync_descriptor *spi); - -/** \brief Disable SPI - * - * \param[in] spi Pointer to the HAL SPI instance. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval <0 Error code. - */ -void spi_m_sync_disable(struct spi_m_sync_descriptor *spi); - -/** \brief Set SPI baudrate - * - * Works if SPI is initialized as master, it sets the baudrate. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] baud_val The target baudrate value - * (see "baudrate calculation" for calculating the value). - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The baudrate is not supported. - */ -int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val); - -/** \brief Set SPI mode - * - * Set the SPI transfer mode (\ref spi_transfer_mode), - * which controls the clock polarity and clock phase: - * - Mode 0: leading edge is rising edge, data sample on leading edge. - * - Mode 1: leading edge is rising edge, data sample on trailing edge. - * - Mode 2: leading edge is falling edge, data sample on leading edge. - * - Mode 3: leading edge is falling edge, data sample on trailing edge. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] mode The mode (0~3). - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The mode is not supported. - */ -int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode); - -/** \brief Set SPI transfer character size in number of bits - * - * The character size (\ref spi_char_size) influence the way the data is - * sent/received. - * For char size <= 8-bit, data is stored byte by byte. - * For char size between 9-bit ~ 16-bit, data is stored in 2-byte length. - * Note that the default and recommended char size is 8-bit since it's - * supported by all system. - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] char_size The char size (~16, recommended 8). - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The char size is not supported. - */ -int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size); - -/** \brief Set SPI transfer data order - * - * \param[in] spi Pointer to the HAL SPI instance. - * \param[in] dord The data order: send LSB/MSB first. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy - * \retval ERR_INVALID_ARG The data order is not supported. - */ -int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord); - -/** \brief Perform the SPI data transfer (TX and RX) in polling way - * - * Activate CS, do TX and RX and deactivate CS. It blocks. - * - * \param[in, out] spi Pointer to the HAL SPI instance. - * \param[in] xfer Pointer to the transfer information (\ref spi_xfer). - * - * \retval size Success. - * \retval >=0 Timeout, with number of characters transferred. - * \retval ERR_BUSY SPI is busy - */ -int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *xfer); - -/** - * \brief Return the I/O descriptor for this SPI instance - * - * This function will return an I/O instance for this SPI driver instance. - * - * \param[in] spi An SPI master descriptor, which is used to communicate through - * SPI - * \param[in, out] io A pointer to an I/O descriptor pointer type - * - * \retval ERR_NONE - */ -int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io); - -/** \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t spi_m_sync_get_version(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* ifndef _HAL_SPI_M_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_timer.h b/atmel-samd/asf4/samd51/hal/include/hal_timer.h deleted file mode 100644 index b5c8f6082..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_timer.h +++ /dev/null @@ -1,216 +0,0 @@ -/** - * \file - * - * \brief Timer task functionality declaration. - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_TIMER_H_INCLUDED -#define _HAL_TIMER_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_timer - * - * @{ - */ - -/** - * \brief Timer mode type - */ -enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT }; - -/** - * \brief Timer task descriptor - * - * The timer task descriptor forward declaration. - */ -struct timer_task; - -/** - * \brief Timer task callback function type - */ -typedef void (*timer_cb_t)(const struct timer_task *const timer_task); - -/** - * \brief Timer task structure - */ -struct timer_task { - struct list_element elem; /*! List element. */ - uint32_t time_label; /*! Absolute timer start time. */ - - uint32_t interval; /*! Number of timer ticks before calling the task. */ - timer_cb_t cb; /*! Function pointer to the task. */ - enum timer_task_mode mode; /*! Task mode: one shot or repeat. */ -}; - -/** - * \brief Timer structure - */ -struct timer_descriptor { - struct _timer_device device; - uint32_t time; - struct list_descriptor tasks; /*! Timer tasks list. */ - volatile uint8_t flags; -}; - -/** - * \brief Initialize timer - * - * This function initializes the given timer. - * It checks if the given hardware is not initialized and if the given hardware - * is permitted to be initialized. - * - * \param[out] descr A timer descriptor to initialize - * \param[in] hw The pointer to the hardware instance - * \param[in] func The pointer to a set of function pointers - * - * \return Initialization status. - */ -int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func); - -/** - * \brief Deinitialize timer - * - * This function deinitializes the given timer. - * It checks if the given hardware is initialized and if the given hardware is - * permitted to be deinitialized. - * - * \param[in] descr A timer descriptor to deinitialize - * - * \return De-initialization status. - */ -int32_t timer_deinit(struct timer_descriptor *const descr); - -/** - * \brief Start timer - * - * This function starts the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to start - * - * \return Timer starting status. - */ -int32_t timer_start(struct timer_descriptor *const descr); - -/** - * \brief Stop timer - * - * This function stops the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to stop - * - * \return Timer stopping status. - */ -int32_t timer_stop(struct timer_descriptor *const descr); - -/** - * \brief Set amount of clock cycles per timer tick - * - * This function sets the amount of clock cycles per timer tick for the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to stop - * \param[in] clock_cycles The amount of clock cycles per tick to set - * - * \return Setting clock cycles amount status. - */ -int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles); - -/** - * \brief Retrieve the amount of clock cycles in a tick - * - * This function retrieves how many clock cycles there are in a single timer tick. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to convert ticks to - * clock cycles - * \param[out] cycles The amount of clock cycles - * - * \return The status of clock cycles retrieving. - */ -int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles); - -/** - * \brief Add timer task - * - * This function adds the given timer task to the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to add task to - * \param[in] task A task to add - * - * \return Timer's task adding status. - */ -int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task); - -/** - * \brief Remove timer task - * - * This function removes the given timer task from the given timer. - * It checks if the given hardware is initialized. - * - * \param[in] descr The timer descriptor of a timer to remove task from - * \param[in] task A task to remove - * - * \return Timer's task removing status. - */ -int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t timer_get_version(void); -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_TIMER_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_usart_sync.h b/atmel-samd/asf4/samd51/hal/include/hal_usart_sync.h deleted file mode 100644 index e2aef748d..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_usart_sync.h +++ /dev/null @@ -1,257 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_SYNC_USART_H_INCLUDED -#define _HAL_SYNC_USART_H_INCLUDED - -#include "hal_io.h" -#include - -/** - * \addtogroup doc_driver_hal_usart_sync - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Synchronous USART descriptor - */ -struct usart_sync_descriptor { - struct io_descriptor io; - struct _usart_sync_device device; -}; - -/** - * \brief Initialize USART interface - * - * This function initializes the given I/O descriptor to be used - * as USART interface descriptor. - * It checks if the given hardware is not initialized and - * if the given hardware is permitted to be initialized. - * - * \param[out] descr A USART descriptor which is used to communicate via USART - * \param[in] hw The pointer to hardware instance - * \param[in] func The pointer to as set of functions pointers - * - * \return Initialization status. - */ -int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func); - -/** - * \brief Deinitialize USART interface - * - * This function deinitializes the given I/O descriptor. - * It checks if the given hardware is initialized and - * if the given hardware is permitted to be deinitialized. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return De-initialization status. - */ -int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr); - -/** - * \brief Enable USART interface - * - * Enables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Enabling status. - */ -int32_t usart_sync_enable(struct usart_sync_descriptor *const descr); - -/** - * \brief Disable USART interface - * - * Disables the USART interface - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return Disabling status. - */ -int32_t usart_sync_disable(struct usart_sync_descriptor *const descr); - -/** - * \brief Retrieve I/O descriptor - * - * This function retrieves the I/O descriptor of the given USART descriptor. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] io An I/O descriptor to retrieve - * - * \return The status of the I/O descriptor retrieving. - */ -int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io); - -/** - * \brief Specify action for flow control pins - * - * This function sets the action (or state) for the flow control pins - * if the flow control is enabled. - * It sets the state of flow control pins only if the automatic support of - * the flow control is not supported by the hardware. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] state A state to set the flow control pins - * - * \return The status of flow control action setup. - */ -int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, - const union usart_flow_control_state state); - -/** - * \brief Set USART baud rate - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] baud_rate A baud rate to set - * - * \return The status of baud rate setting. - */ -int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate); - -/** - * \brief Set USART data order - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] data_order A data order to set - * - * \return The status of data order setting. - */ -int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order); - -/** - * \brief Set USART mode - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] mode A mode to set - * - * \return The status of mode setting. - */ -int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode); - -/** - * \brief Set USART parity - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] parity A parity to set - * - * \return The status of parity setting. - */ -int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity); - -/** - * \brief Set USART stop bits - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] stop_bits Stop bits to set - * - * \return The status of stop bits setting. - */ -int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits); - -/** - * \brief Set USART character size - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[in] size A character size to set - * - * \return The status of character size setting. - */ -int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins - * if the flow control is enabled. - * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case - * if the flow control is done by the hardware - * and the pins state cannot be read out. - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * \param[out] state The state of flow control pins - * - * \return The status of flow control state reading. - */ -int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, - union usart_flow_control_state *const state); - -/** - * \brief Check if the USART transmitter is empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of USART TX empty checking. - * \retval 0 The USART transmitter is not empty - * \retval 1 The USART transmitter is empty - */ -int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr); - -/** - * \brief Check if the USART receiver is not empty - * - * \param[in] descr A USART descriptor which is used to communicate via USART - * - * \return The status of USART RX empty checking. - * \retval 1 The USART receiver is not empty - * \retval 0 The USART receiver is empty - */ -int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr); - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t usart_sync_get_version(void); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HAL_SYNC_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hal_usb_device.h b/atmel-samd/asf4/samd51/hal/include/hal_usb_device.h deleted file mode 100644 index 8b7bd5ec7..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hal_usb_device.h +++ /dev/null @@ -1,305 +0,0 @@ -/** - * \file - * - * \brief SAM USB device HAL - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HAL_USB_DEVICE_H_INCLUDED -#define _HAL_USB_DEVICE_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_usb_device - * - * @{ - */ - -/** USB device endpoint status structure. */ -struct usb_d_ep_status { - /** Endpoint address, including direction. */ - uint8_t ep; - /** Endpoint transfer status code that triggers the callback. - * \ref usb_xfer_code. */ - uint8_t code; - /** Endpoint error, if \c code is \ref USB_TRANS_ERROR. */ - uint8_t error; - /** Transfer state, \ref usb_ep_state. */ - uint8_t state; - /** Transfer count. */ - uint32_t count; - /** Transfer size. */ - uint32_t size; -}; - -/** Prototype function for callback that is invoked on USB device SOF. */ -typedef void (*usb_d_sof_cb_t)(void); - -/** Prototype function for callback that is invoked on USB device events. */ -typedef void (*usb_d_event_cb_t)(const enum usb_event event, const uint32_t param); - -/** USB device callbacks. */ -struct usb_d_callbacks { - /** Callback that is invoked on SOF. */ - usb_d_sof_cb_t sof; - /** Callback that is invoked on USB RESET/WAKEUP/RESUME/SUSPEND. */ - usb_d_event_cb_t event; -}; - -/** Callback that is invoked when setup packet is received. - * Return \c true if request has been handled, or control endpoint will - * stall IN/OUT transactions. - */ -typedef bool (*usb_d_ep_cb_setup_t)(const uint8_t ep, const uint8_t *req); - -/** Callback that is invoked when buffer is done without error, but last packet - * is full size packet without ZLP. - * Return \c true if more data has been requested. - */ -typedef bool (*usb_d_ep_cb_more_t)(const uint8_t ep, const uint32_t count); - -/** Callback that is invoked when all data is finished, including background - * transfer, or error happens. - * In control transfer data stage, return value is checked, - * return \c false if no error happens. - */ -typedef bool (*usb_d_ep_cb_xfer_t)(const uint8_t ep, const enum usb_xfer_code code, void *param); - -/** - * \brief Initialize the USB device driver - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_init(void); - -/** - * \brief Deinitialize the USB device driver - */ -void usb_d_deinit(void); - -/** - * \brief Register the USB device callback - * \param[in] type The callback type to register. - * \param[in] func The callback function, NULL to disable callback. - */ -void usb_d_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func); - -/** - * \brief Enable the USB device driver - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_enable(void); - -/** - * \brief Disable the USB device driver - */ -void usb_d_disable(void); - -/** - * \brief Attach the USB device - */ -void usb_d_attach(void); - -/** - * \brief Detach the USB device - */ -void usb_d_detach(void); - -/** - * \brief Retrieve current USB working speed. - * \return USB Speed. See \ref usb_speed. - */ -enum usb_speed usb_d_get_speed(void); - -/** - * \brief Retrieve current USB frame number. - * \return Frame number. - */ -uint16_t usb_d_get_frame_num(void); - -/** - * \brief Retrieve current USB micro frame number. - * \return Micro frame number inside a frame (0~7). - * 0 if not available (not HS). - */ -uint8_t usb_d_get_uframe_num(void); - -/** - * \brief Set the USB address that is used. - * \param[in] addr The address to set. - */ -void usb_d_set_address(const uint8_t addr); - -/** - * \brief Send remote wakeup to host - * \return Operation status. - */ -void usb_d_send_remotewakeup(void); - -/** - * \brief Initialize the endpoint 0. - * - * Note that endpoint 0 must be initialized as control endpoint. - * - * \param[in] max_pkt_size Max. packet size of EP0. - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_ep0_init(const uint8_t max_pkt_size); - -/** - * \brief Initialize the endpoint. - * - * \param[in] ep The endpoint address. - * \param[in] attr The endpoint attributes. - * \param[in] max_pkt_size Max. packet size of EP0. - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_size); - -/** - * \brief Disable and deinitialize the endpoint. - * \param[in] ep The endpoint address to deinitialize. - */ -void usb_d_ep_deinit(const uint8_t ep); - -/** - * \brief Register the USB device endpoint callback on initialized endpoint. - * - * \param[in] ep The endpoint address. - * \param[in] type The callback type to register. - * \param[in] func The callback function, NULL to disable callback. - */ -void usb_d_ep_register_callback(const uint8_t ep, const enum usb_d_ep_cb_type type, const FUNC_PTR func); - -/** - * \brief Enabled the initialized endpoint. - * - * Setup request will be monitored after enabling a control endpoint. - * - * \param[in] ep The endpoint address. - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_ep_enable(const uint8_t ep); - -/** - * \brief Disable the initialized endpoint. - * \param[in] ep The endpoint address. - */ -void usb_d_ep_disable(const uint8_t ep); - -/** - * \brief Get request data pointer to access received setup request packet - * \param[in] ep The endpoint address. - * \return Pointer to the request data. - * \retval NULL The endpoint is not a control endpoint. - */ -uint8_t *usb_d_ep_get_req(const uint8_t ep); - -/** - * \brief Endpoint transfer. - * - * For control endpoints, start the transfer according to the direction in the bmRequest - * type, and finish with STATUS stage. - * For non-control endpoints, the transfer will be unique direction. Defined by - * bit 8 of the endpoint address. - * - * \param[in] xfer Pointer to the transfer description. - * \return Operation status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer); - -/** - * \brief Abort an on-going transfer on a specific endpoint. - * - * \param[in] ep The endpoint address. - */ -void usb_d_ep_abort(const uint8_t ep); - -/** - * \brief Retrieve the endpoint status. - * - * \param[in] ep The endpoint address. - * \param[out] stat Pointer to the buffer to fill the status description. - * - * \return Endpoint status. - * \retval 1 Busy. - * \retval 0 Idle. - * \retval <0 Error code. - */ -int32_t usb_d_ep_get_status(const uint8_t ep, struct usb_d_ep_status *stat); - -/** - * \brief Endpoint halt control. - * - * \param[in] ep The endpoint address. - * \param[in] ctrl Control code (SET/CLEAR/GET). - * - * \return Operation status or HALT state (if \c ctrl is \ref USB_EP_HALT_GET). - */ -int32_t usb_d_ep_halt(const uint8_t ep, const enum usb_ep_halt_ctrl ctrl); - -/** \brief Retrieve the current driver version - * - * \return Current driver version. - */ -uint32_t usb_d_get_version(void); - -/**@}*/ - -#ifdef __cplusplus -} -#endif - -#endif /* _HAL_USB_DEVICE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_adc_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_adc_async.h deleted file mode 100644 index 31612be00..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_adc_async.h +++ /dev/null @@ -1,274 +0,0 @@ -/** - * \file - * - * \brief ADC related functionality declaration. - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_ADC_ASYNC_H_INCLUDED -#define _HPL_ADC_ASYNC_H_INCLUDED - -/** - * \addtogroup HPL ADC - * - * \section hpl_async_adc_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_adc_sync.h" -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief ADC device structure - * - * The ADC device structure forward declaration. - */ -struct _adc_async_device; - -/** - * \brief ADC callback types - */ -enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB }; - -/** - * \brief ADC interrupt callbacks - */ -struct _adc_async_callbacks { - void (*window_cb)(struct _adc_async_device *device, const uint8_t channel); - void (*error_cb)(struct _adc_async_device *device, const uint8_t channel); -}; - -/** - * \brief ADC channel interrupt callbacks - */ -struct _adc_async_ch_callbacks { - void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data); -}; - -/** - * \brief ADC descriptor device structure - */ -struct _adc_async_device { - struct _adc_async_callbacks adc_async_cb; - struct _adc_async_ch_callbacks adc_async_ch_cb; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize synchronous ADC - * - * This function does low level ADC configuration. - * - * param[in] device The pointer to ADC device instance - * param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw); - -/** - * \brief Deinitialize ADC - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_async_deinit(struct _adc_async_device *const device); - -/** - * \brief Enable ADC peripheral - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel); - -/** - * \brief Disable ADC peripheral - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel); - -/** - * \brief Retrieve ADC conversion data size - * - * \param[in] device The pointer to ADC device instance - * - * \return The data size in bytes - */ -uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device); - -/** - * \brief Check if conversion is done - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * - * \return The status of conversion - * \retval true The conversion is done - * \retval false The conversion is not done - */ -bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel); - -/** - * \brief Make conversion - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_async_convert(struct _adc_async_device *const device); - -/** - * \brief Retrieve the conversion result - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * - * The result value - */ -uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel); - -/** - * \brief Set reference source - * - * \param[in] device The pointer to ADC device instance - * \param[in] reference A reference source to set - */ -void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference); - -/** - * \brief Set resolution - * - * \param[in] device The pointer to ADC device instance - * \param[in] resolution A resolution to set - */ -void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution); - -/** - * \brief Set ADC input source of a channel - * - * \param[in] device The pointer to ADC device instance - * \param[in] pos_input A positive input source to set - * \param[in] neg_input A negative input source to set - * \param[in] channel Channel number - */ -void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel); - -/** - * \brief Set conversion mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A conversion mode to set - */ -void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode); - -/** - * \brief Set differential mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] mode A differential mode to set - */ -void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel, - const enum adc_differential_mode mode); - -/** - * \brief Set gain - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] gain A gain to set - */ -void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain); - -/** - * \brief Set window mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A mode to set - */ -void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode); - -/** - * \brief Set lower threshold - * - * \param[in] device The pointer to ADC device instance - * \param[in] low_threshold A lower threshold to set - * \param[in] up_threshold An upper thresholds to set - */ -void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold); - -/** - * \brief Retrieve threshold state - * - * \param[in] device The pointer to ADC device instance - * \param[out] state The threshold state - */ -void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state); - -/** - * \brief Enable/disable ADC channel interrupt - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] type The type of interrupt to disable/enable if applicable - * \param[in] state Enable or disable - */ -void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel, - const enum _adc_async_callback_type type, const bool state); - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_ADC_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_adc_dma.h b/atmel-samd/asf4/samd51/hal/include/hpl_adc_dma.h deleted file mode 100644 index 40ff158d2..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_adc_dma.h +++ /dev/null @@ -1,253 +0,0 @@ -/** - * \file - * - * \brief ADC related functionality declaration. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_ADC_DMA_H_INCLUDED -#define _HPL_ADC_DMA_H_INCLUDED - -/** - * \addtogroup HPL ADC - * - * \section hpl_dma_adc_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief ADC device structure - * - * The ADC device structure forward declaration. - */ -struct _adc_dma_device; - -/** - * \brief ADC callback types - */ -enum _adc_dma_callback_type { ADC_DMA_DEVICE_COMPLETE_CB, ADC_DMA_DEVICE_ERROR_CB }; - -/** - * \brief ADC interrupt callbacks - */ -struct _adc_dma_callbacks { - void (*complete)(struct _adc_dma_device *device, const uint16_t data); - void (*error)(struct _adc_dma_device *device); -}; - -/** - * \brief ADC descriptor device structure - */ -struct _adc_dma_device { - struct _adc_dma_callbacks adc_dma_cb; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize synchronous ADC - * - * This function does low level ADC configuration. - * - * param[in] device The pointer to ADC device instance - * param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw); - -/** - * \brief Deinitialize ADC - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_dma_deinit(struct _adc_dma_device *const device); - -/** - * \brief Enable ADC peripheral - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel); - -/** - * \brief Disable ADC peripheral - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel); - -/** - * \brief Return address of ADC DMA source - * - * \param[in] device The pointer to ADC device instance - * - * \return ADC DMA source address - */ -uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device); - -/** - * \brief Retrieve ADC conversion data size - * - * \param[in] device The pointer to ADC device instance - * - * \return The data size in bytes - */ -uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device); - -/** - * \brief Check if conversion is done - * - * \param[in] device The pointer to ADC device instance - * - * \return The status of conversion - * \retval true The conversion is done - * \retval false The conversion is not done - */ -bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device); - -/** - * \brief Make conversion - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_dma_convert(struct _adc_dma_device *const device); - -/** - * \brief Set reference source - * - * \param[in] device The pointer to ADC device instance - * \param[in] reference A reference source to set - */ -void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference); - -/** - * \brief Set resolution - * - * \param[in] device The pointer to ADC device instance - * \param[in] resolution A resolution to set - */ -void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution); - -/** - * \brief Set ADC input source of a channel - * - * \param[in] device The pointer to ADC device instance - * \param[in] pos_input A positive input source to set - * \param[in] neg_input A negative input source to set - * \param[in] channel Channel number - */ -void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel); - -/** - * \brief Set conversion mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A conversion mode to set - */ -void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode); - -/** - * \brief Set differential mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] mode A differential mode to set - */ -void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel, - const enum adc_differential_mode mode); - -/** - * \brief Set gain - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] gain A gain to set - */ -void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain); - -/** - * \brief Set window mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A mode to set - */ -void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode); - -/** - * \brief Set thresholds - * - * \param[in] device The pointer to ADC device instance - * \param[in] low_threshold A lower thresholds to set - * \param[in] up_threshold An upper thresholds to set - */ -void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold); - -/** - * \brief Retrieve threshold state - * - * \param[in] device The pointer to ADC device instance - * \param[out] state The threshold state - */ -void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state); - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_ADC_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_adc_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_adc_sync.h deleted file mode 100644 index 84ab01ab3..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_adc_sync.h +++ /dev/null @@ -1,281 +0,0 @@ -/** - * \file - * - * \brief ADC related functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_ADC_SYNC_H_INCLUDED -#define _HPL_ADC_SYNC_H_INCLUDED - -/** - * \addtogroup HPL ADC - * - * \section hpl_adc_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "compiler.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief ADC reference source - */ -typedef uint8_t adc_reference_t; - -/** - * \brief ADC resolution - */ -typedef uint8_t adc_resolution_t; - -/** - * \brief ADC positive input for channel - */ -typedef uint8_t adc_pos_input_t; - -/** - * \brief ADC negative input for channel - */ -typedef uint8_t adc_neg_input_t; - -/** - * \brief ADC threshold - */ -typedef uint16_t adc_threshold_t; - -/** - * \brief ADC gain - */ -typedef uint8_t adc_gain_t; - -/** - * \brief ADC conversion mode - */ -enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN }; - -/** - * \brief ADC differential mode - */ -enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL }; - -/** - * \brief ADC window mode - */ -typedef uint8_t adc_window_mode_t; - -/** - * \brief ADC threshold status - */ -typedef bool adc_threshold_status_t; - -/** - * \brief ADC sync descriptor device structure - */ -struct _adc_sync_device { - void *hw; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize synchronous ADC - * - * This function does low level ADC configuration. - * - * param[in] device The pointer to ADC device instance - * param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize ADC - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_sync_deinit(struct _adc_sync_device *const device); - -/** - * \brief Enable ADC - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel); - -/** - * \brief Disable ADC - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - */ -void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel); - -/** - * \brief Retrieve ADC conversion data size - * - * \param[in] device The pointer to ADC device instance - * - * \return The data size in bytes - */ -uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device); - -/** - * \brief Check if conversion is done - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * - * \return The status of conversion - * \retval true The conversion is done - * \retval false The conversion is not done - */ -bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel); - -/** - * \brief Make conversion - * - * \param[in] device The pointer to ADC device instance - */ -void _adc_sync_convert(struct _adc_sync_device *const device); - -/** - * \brief Retrieve the conversion result - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * - * \return The result value of channel - */ -uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel); - -/** - * \brief Set reference source - * - * \param[in] device The pointer to ADC device instance - * \param[in] reference A reference source to set - */ -void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference); - -/** - * \brief Set resolution - * - * \param[in] device The pointer to ADC device instance - * \param[in] resolution A resolution to set - */ -void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution); - -/** - * \brief Set ADC input source of a channel - * - * \param[in] device The pointer to ADC device instance - * \param[in] pos_input A positive input source to set - * \param[in] neg_input A negative input source to set - * \param[in] channel Channel number - */ -void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel); - -/** - * \brief Set conversion mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A conversion mode to set - */ -void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode); - -/** - * \brief Set differential mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] mode A differential mode to set - */ -void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel, - const enum adc_differential_mode mode); - -/** - * \brief Set gain - * - * \param[in] device The pointer to ADC device instance - * \param[in] channel Channel number - * \param[in] gain A gain to set - */ -void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain); - -/** - * \brief Set window mode - * - * \param[in] device The pointer to ADC device instance - * \param[in] mode A mode to set - */ -void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode); - -/** - * \brief Set threshold - * - * \param[in] device The pointer to ADC device instance - * \param[in] low_threshold A lower threshold to set - * \param[in] up_threshold An upper thresholds to set - */ -void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold); - -/** - * \brief Retrieve threshold state - * - * \param[in] device The pointer to ADC device instance - * \param[out] state The threshold state - */ -void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_ADC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_calendar.h b/atmel-samd/asf4/samd51/hal/include/hpl_calendar.h deleted file mode 100644 index 9b9002c25..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_calendar.h +++ /dev/null @@ -1,252 +0,0 @@ -/** - * \file - * - * \brief Generic CALENDAR functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_CALENDER_H_INCLUDED -#define _HPL_CALENDER_H_INCLUDED - -#include -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Calendar structure - * - * The Calendar structure forward declaration. - */ -struct calendar_dev; - -/** - * \brief Available mask options for alarms. - * - * Available mask options for alarms. - */ -enum calendar_alarm_option { - /** Alarm disabled. */ - CALENDAR_ALARM_MATCH_DISABLED = 0, - /** Alarm match on second. */ - CALENDAR_ALARM_MATCH_SEC, - /** Alarm match on second and minute. */ - CALENDAR_ALARM_MATCH_MIN, - /** Alarm match on second, minute, and hour. */ - CALENDAR_ALARM_MATCH_HOUR, - /** Alarm match on second, minute, hour, and day. */ - CALENDAR_ALARM_MATCH_DAY, - /** Alarm match on second, minute, hour, day, and month. */ - CALENDAR_ALARM_MATCH_MONTH, - /** Alarm match on second, minute, hour, day, month and year. */ - CALENDAR_ALARM_MATCH_YEAR -}; - -/** - * \brief Available mode for alarms. - */ -enum calendar_alarm_mode { ONESHOT = 1, REPEAT }; -/** - * \brief Prototype of callback on alarm match - */ -typedef void (*calendar_drv_cb_alarm_t)(struct calendar_dev *const dev); - -/** - * \brief Structure of Calendar instance - */ -struct calendar_dev { - /** Pointer to the hardware base */ - void *hw; - /** Alarm match callback */ - calendar_drv_cb_alarm_t callback; - /** IRQ struct */ - struct _irq_descriptor irq; -}; - -/** - * \brief Time struct for calendar - */ -struct calendar_time { - /*range from 0 to 59*/ - uint8_t sec; - /*range from 0 to 59*/ - uint8_t min; - /*range from 0 to 23*/ - uint8_t hour; -}; - -/** - * \brief Time struct for calendar - */ -struct calendar_date { - /*range from 1 to 28/29/30/31*/ - uint8_t day; - /*range from 1 to 12*/ - uint8_t month; - /*absolute year>= 1970(such as 2000)*/ - uint16_t year; -}; - -/** \brief Calendar driver struct - * - */ -struct calendar_descriptor { - struct calendar_dev device; - struct list_descriptor alarms; - /*base date/time = base_year/1/1/0/0/0(year/month/day/hour/min/sec)*/ - uint32_t base_year; - uint8_t flags; -}; - -/** \brief Date&Time struct for calendar - */ -struct calendar_date_time { - struct calendar_time time; - struct calendar_date date; -}; - -/** \brief struct for alarm time - */ -struct _calendar_alarm { - struct calendar_date_time datetime; - uint32_t timestamp; - enum calendar_alarm_option option; - enum calendar_alarm_mode mode; -}; - -/** - * \brief Initialize Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_init(struct calendar_dev *const dev); - -/** - * \brief Deinitialize Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_deinit(struct calendar_dev *const dev); - -/** - * \brief Enable Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_enable(struct calendar_dev *const dev); - -/** - * \brief Disable Calendar instance - * - * \param[in] dev The pointer to calendar device struct - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_disable(struct calendar_dev *const dev); -/** - * \brief Set time for calendar - * - * \param[in] dev The pointer to calendar device struct - * \param[in] p_calendar_time Pointer to the time configuration - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_set_time(struct calendar_dev *const dev, struct calendar_time *const p_calendar_time); - -/** - * \brief Set date for calendar - * - * \param[in] dev The pointer to calendar device struct - * \param[in] p_calendar_date Pointer to the date configuration - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_set_date(struct calendar_dev *const dev, struct calendar_date *const p_calendar_date); - -/** - * \brief Get the time for calendar HAL instance and hardware - * Retrieve the time from calendar instance. - * - * \param[in] dev The pointer to calendar device struct - * \param[in] date_time Pointer to value that will be filled with current time - * - * \return Return current counter value - */ -uint32_t _calendar_get_date_time(struct calendar_dev *const dev, struct calendar_date_time *const date_time); - -/** - * \brief Set compare value for calendar - * - * \param[in] dev The pointer to calendar device struct - * \param[in] alarm Pointer to the configuration - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_set_alarm(struct calendar_dev *const dev, struct _calendar_alarm *const alarm); - -/** - * \brief Register callback for calendar alarm - * - * \param[in] dev The pointer to calendar device struct - * \param[in] callback The pointer to callback function - * - * \return ERR_NONE on success, or an error code on failure. - */ -int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback); - -/** - * \brief Set calendar IRQ - * - * \param[in] dev The pointer to calendar device struct - */ -void _calendar_set_irq(struct calendar_dev *const dev); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_RTC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_core.h b/atmel-samd/asf4/samd51/hal/include/hpl_core.h deleted file mode 100644 index db448a16a..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_core.h +++ /dev/null @@ -1,66 +0,0 @@ -/** - * \file - * - * \brief CPU core related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_CORE_H_INCLUDED -#define _HPL_CORE_H_INCLUDED - -/** - * \addtogroup HPL Core - * - * \section hpl_core_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_core_port.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_dac_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_dac_async.h deleted file mode 100644 index 5d7d81303..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_dac_async.h +++ /dev/null @@ -1,181 +0,0 @@ -/** - * \file - * - * \brief DAC related functionality declaration. - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_DAC_H_INCLUDED -#define _HPL_DAC_H_INCLUDED - -/** - * \addtogroup hpl__dac__group DAC HPL APIs - * See interface description here: \ref hpl__dac__doc - * - */ - -/**@{*/ - -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DAC hardware Channel Number - */ -#ifndef CHANNEL_NUM -#define CHANNEL_NUM 2 -#endif - -/** - * \brief DAC callback types - */ -enum _dac_callback_type { DAC_DEVICE_CONVERSION_DONE_CB, DAC_DEVICE_ERROR_CB }; - -/** - * \brief DAC device structure - * - * The DAC device structure forward declaration. - */ -struct _dac_async_device; - -/** - * \brief DAC interrupt handlers structure - */ -struct _dac_callback { - /** Transmit ready(Data Buffer empty) handler */ - void (*tx_ready_cb)(struct _dac_async_device *device, const uint8_t ch); - /** Error handler */ - void (*tx_error_cb)(struct _dac_async_device *device, const uint8_t ch); -}; - -/** - * \brief DAC descriptor device structure. - */ -struct _dac_async_device { - struct _dac_callback dac_cb; /*!< Interrupt handers */ - struct _irq_descriptor irq; /*!< Interrupt descriptor */ - void * hw; /*!< Hardware module instance handler */ -}; - -/** - * \brief Initialize asynchronous DAC. - * - * This function does low level DAC configuration. - * - * \param[in] device The pointer to DAC device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _dac_async_init(struct _dac_async_device *const device, void *const hw); - -/** - * \brief Deinitialize DAC. - * - * \param[in] device The pointer to DAC device instance - */ -void _dac_async_deinit(struct _dac_async_device *const device); - -/** - * \brief Enable DAC Channel. - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - */ -void _dac_async_enable_channel(struct _dac_async_device *const device, const uint8_t ch); - -/** - * \brief Disable DAC Channel. - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - */ -void _dac_async_disable_channel(struct _dac_async_device *const device, const uint8_t ch); - -/** - * \brief Checks if DAC channel is enabled - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - * - * \return true channel is enabled, false otherwise - */ -bool _dac_async_is_channel_enable(struct _dac_async_device *const device, const uint8_t ch); - -/** - * \brief Write DAC data for output. - * - * \param[in] device The pointer to DAC device instance - * \param[in] data Digital data which to be converted - * \param[in] ch The channel selected to output - */ -void _dac_async_write_data(struct _dac_async_device *const device, const uint16_t data, const uint8_t ch); - -/** - * \brief Enable/disable DAC interrupt - * - * param[in] device The pointer to DAC device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _dac_async_set_irq_state(struct _dac_async_device *const device, const enum _dac_callback_type type, - const bool state); - -#ifdef __cplusplus -} -#endif - -/**@}*/ - -/** - * \page hpl__dac__doc DAC HPL Interface Driver - * - * \section hpl__dac__desc DAC HPL Description - * - * The following device can use this HPL driver - * - Atmel | SMART SAM D21 - * - * \section hpl__dac__imple DAC HPL Implements - * - \subpage hpl__dac__hw_module1__doc - */ - -#endif /* _HPL_DAC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_dac_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_dac_sync.h deleted file mode 100644 index f59f2d73b..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_dac_sync.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - * \file - * - * \brief DAC related functionality declaration. - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_DAC_SYNC_H_INCLUDED -#define _HPL_DAC_SYNC_H_INCLUDED - -/** - * \addtogroup hpl__dac__group DAC HPL APIs - * See interface description here: \ref hpl__dac__doc - * - */ - -/**@{*/ - -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * DAC hardware Channel Number - */ -#ifndef CHANNEL_NUM -#define CHANNEL_NUM 2 -#endif - -/** - * \brief DAC sync descriptor device structure. - */ -struct _dac_sync_device { - void *hw; /*!< Hardware module instance handler */ -}; - -/** - * \brief Initialize synchronous DAC. - * - * This function does low level DAC configuration. - * - * \param[in] device The pointer to DAC device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _dac_sync_init(struct _dac_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize DAC. - * - * \param[in] device The pointer to DAC device instance - */ -void _dac_sync_deinit(struct _dac_sync_device *const device); - -/** - * \brief Enable DAC Channel. - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - */ -void _dac_sync_enable_channel(struct _dac_sync_device *const device, const uint8_t ch); - -/** - * \brief Disable DAC Channel. - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - */ -void _dac_sync_disable_channel(struct _dac_sync_device *const device, const uint8_t ch); - -/** - * \brief Checks if DAC channel is enabled - * - * \param[in] device The pointer to DAC device instance - * \param[in] ch channel number - * - * \return true channel is enabled, false otherwise - */ -bool _dac_sync_is_channel_enable(struct _dac_sync_device *const device, const uint8_t ch); - -/** - * \brief Write synchronous DAC data for output. - * - * \param[in] device The pointer to DAC device instance - * \param[in] data Digital data which to be converted - * \param[in] ch The channel selected to output - */ -void _dac_sync_write_data(struct _dac_sync_device *const device, const uint16_t data, const uint8_t ch); - -#ifdef __cplusplus -} -#endif - -/**@}*/ - -/** - * \page hpl__dac__doc DAC HPL Interface Driver - * - * \section hpl__dac__desc DAC HPL Description - * - * The following device can use this HPL driver - * - Atmel | SMART SAM D21 - * - * \section hpl__dac__imple DAC HPL Implements - * - \subpage hpl__dac__hw_module1__doc - */ - -#endif /* _HPL_DAC_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_delay.h b/atmel-samd/asf4/samd51/hal/include/hpl_delay.h deleted file mode 100644 index 7d2a6f90b..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_delay.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * \file - * - * \brief Delay related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_DELAY_H_INCLUDED -#define _HPL_DELAY_H_INCLUDED - -/** - * \addtogroup HPL Delay - * - * \section hpl_delay_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ - -/** - * \brief Initialize delay functionality - * - * \param[in] hw The pointer to hardware instance - */ -void _delay_init(void *const hw); - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - * - * \param[in] us The amount of us to delay for - * - * \return The amount of cycles - */ -uint32_t _get_cycles_for_us(const uint16_t us); - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - * - * \param[in] ms The amount of ms to delay for - * - * \return The amount of cycles - */ -uint32_t _get_cycles_for_ms(const uint16_t ms); - -/** - * \brief Delay loop to delay n number of cycles - * - * \param[in] hw The pointer to hardware instance - * \param[in] cycles The amount of cycles to delay for - */ -void _delay_cycles(void *const hw, uint32_t cycles); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_dma.h b/atmel-samd/asf4/samd51/hal/include/hpl_dma.h deleted file mode 100644 index f8c8cce42..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_dma.h +++ /dev/null @@ -1,167 +0,0 @@ -/** - * \file - * - * \brief DMA related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_DMA_H_INCLUDED -#define _HPL_DMA_H_INCLUDED - -/** - * \addtogroup HPL DMA - * - * \section hpl_dma_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct _dma_resource; - -/** - * \brief DMA callback types - */ -enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; - -/** - * \brief DMA interrupt callbacks - */ -struct _dma_callbacks { - void (*transfer_done)(struct _dma_resource *resource); - void (*error)(struct _dma_resource *resource); -}; - -/** - * \brief DMA resource structure - */ -struct _dma_resource { - struct _dma_callbacks dma_cb; - void * back; -}; - -/** - * \brief Initialize DMA - * - * This function does low level DMA configuration. - * - * \return initialize status - */ -int32_t _dma_init(void); - -/** - * \brief Set destination address - * - * \param[in] channel DMA channel to set destination address for - * \param[in] dst Destination address - * - * \return setting status - */ -int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); - -/** - * \brief Set source address - * - * \param[in] channel DMA channel to set source address for - * \param[in] src Source address - * - * \return setting status - */ -int32_t _dma_set_source_address(const uint8_t channel, const void *const src); - -/** - * \brief Enable/disable source address incrementation during DMA transaction - * - * \param[in] channel DMA channel to set source address for - * \param[in] enable True to enable, false to disable - * - * \return status of operation - */ -int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); - -/** - * \brief Set the amount of data to be transfered per transaction - * - * \param[in] channel DMA channel to set data amount for - * \param[in] amount Data amount - * - * \return status of operation - */ -int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); - -/** - * \brief Trigger DMA transaction on the given channel - * - * \param[in] channel DMA channel to trigger transaction on - * - * \return status of operation - */ -int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); - -/** - * \brief Retrieves DMA resource structure - * - * \param[out] resource The resource to be retrieved - * \param[in] channel DMA channel to retrieve structure for - * - * \return status of operation - */ -int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); - -/** - * \brief Enable/disable DMA interrupt - * - * \param[in] channel DMA channel to enable/disable interrupt for - * \param[in] type The type of interrupt to disable/enable if applicable - * \param[in] state Enable or disable - */ -void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); - -#ifdef __cplusplus -} -#endif - -#endif /* HPL_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_evsys.h b/atmel-samd/asf4/samd51/hal/include/hpl_evsys.h deleted file mode 100644 index 43baf4353..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_evsys.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - * \file - * - * \brief Event system related functionality declaration. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_EVSYS_H_INCLUDED -#define _HPL_EVSYS_H_INCLUDED - -/** - * \addtogroup HPL EVSYS - * - * \section hpl_eveys_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Initialize event system. - * - * \return Status of operation. - */ -int32_t _event_system_init(void); - -/** - * \brief Deinitialize event system. - * - * \return Status of operation. - */ -int32_t _event_system_deinit(void); - -/** - * \brief Enable/disable event reception by the given user from the given - * channel - * - * \param[in] user A user to enable - * \param[in] channel A channel the user is assigned to - * \param[in] on true to enable, false to disable - * - * \return Status of operation. - */ -int32_t _event_system_enable_user(const uint16_t user, const uint16_t channel, const bool on); - -/** - * \brief Enable/disable event generation by the given generator for the given - * channel - * - * \param[in] generator A generator to enable - * \param[in] channel A channel the user is assigned to - * \param[in] on true to enable, false to disable - * - * \return Status of operation. - */ -int32_t _event_system_enable_generator(const uint16_t generator, const uint16_t channel, const bool on); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_EVSYS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_flash.h b/atmel-samd/asf4/samd51/hal/include/hpl_flash.h deleted file mode 100644 index 6a59f757c..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_flash.h +++ /dev/null @@ -1,228 +0,0 @@ -/** - * \file - * - * \brief FLASH related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_FLASH_H_INCLUDED -#define _HPL_FLASH_H_INCLUDED - -/** - * \addtogroup hpl__flash__group FLASH HPL APIs - * - */ - -/**@{*/ - -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief FLASH device structure - * - * The FLASH device structure forward declaration. - */ -struct _flash_device; - -/** The callback types */ -enum _flash_cb_type { FLASH_DEVICE_CB_READY, FLASH_DEVICE_CB_ERROR, FLASH_DEVICE_CB_N }; - -/** - * \brief FLASH interrupt handlers structure - */ -struct _flash_callback { - /** Ready to accept new command handler */ - void (*ready_cb)(struct _flash_device *device); - /** Error handler */ - void (*error_cb)(struct _flash_device *device); -}; - -/** - * \brief FLASH descriptor device structure. - */ -struct _flash_device { - struct _flash_callback flash_cb; /*!< Interrupt handers */ - struct _irq_descriptor irq; /*!< Interrupt descriptor */ - void * hw; /*!< Hardware module instance handler */ -}; - -/** - * \brief Initialize FLASH. - * - * This function does low level FLASH configuration. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialize status. - */ -int32_t _flash_init(struct _flash_device *const device, void *const hw); - -/** - * \brief Deinitialize FLASH. - * - * \param[in] device The pointer to FLASH device instance - */ -void _flash_deinit(struct _flash_device *const device); - -/** - * \brief Reads a number of bytes in the internal Flash. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] src_addr Source bytes address to read from flash - * \param[out] buffer Pointer to a buffer where the content - * of the read page will be stored - * \param[in] length Number of bytes to read - */ -void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length); - -/** - * \brief Writes a number of bytes in the internal Flash. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address to write into flash - * \param[in] buffer Pointer to buffer where the data to - * write is stored - * \param[in] length Number of bytes to write - */ -void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - -/** - * \brief Appends a number of bytes in the internal Flash. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address to write into flash - * \param[in] buffer Pointer to buffer with data to write to flash - * \param[in] length Number of bytes to write - */ -void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length); - -/** \brief Execute lock in the internal flash - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address aligned with page - * start to be locked - * \param[in] page_nums Number of pages to be locked - * - * \return Real locked numbers of pages. - */ -int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); - -/** \brief Execute unlock in the internal flash - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address aligned with page - * start to be unlocked - * \param[in] page_nums Number of pages to be unlocked - * - * \return Real unlocked numbers of pages. - */ -int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); - -/** \brief check whether the region which is pointed by address - * is locked - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address to check - * - * \return The lock status of assigned address. - */ -bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr); - -/** \brief Execute erase in the internal flash - * \param[in] device The pointer to FLASH device instance - * \param[in] dst_addr Destination bytes address aligned with page - * start to be erased - * \param[in] page_nums Number of pages to be erased - */ -void _flash_erase(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums); - -/** - * \brief Get the flash page size. - * - * \param[in] device The pointer to FLASH device instance - * - * \return The flash page size - */ -uint32_t _flash_get_page_size(struct _flash_device *const device); - -/** - * \brief Get the numbers of flash page. - * - * \param[in] device The pointer to FLASH device instance - * - * \return The flash total page numbers - */ -uint32_t _flash_get_total_pages(struct _flash_device *const device); - -/** - * \brief Get the number of wait states for read and write operations. - * - * \param[in] device The pointer to FLASH device instance - * - * \return The number of wait states for read and write operations - */ -uint8_t _flash_get_wait_state(struct _flash_device *const device); - -/** - * \brief Set the number of wait states for read and write operations. - * - * \param[in] device The pointer to FLASH device instance - * \param[in] state The number of wait states - * - */ -void _flash_set_wait_state(struct _flash_device *const device, uint8_t state); - -/** - * \brief Enable/disable Flash interrupt - * - * param[in] device The pointer to Flash device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state); - -#ifdef __cplusplus -} -#endif - -/**@}*/ - -#endif /* _HPL_FLASH_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_gpio.h b/atmel-samd/asf4/samd51/hal/include/hpl_gpio.h deleted file mode 100644 index e1de9c58e..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_gpio.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - * \file - * - * \brief Port related functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_GPIO_H_INCLUDED -#define _HPL_GPIO_H_INCLUDED - -/** - * \addtogroup HPL Port - * - * \section hpl_port_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif -/** - * \brief Macros for the pin and port group, lower 5 - * bits stands for pin number in the group, higher 3 - * bits stands for port group - */ -#define GPIO_PIN(n) (((n)&0x1Fu) << 0) -#define GPIO_PORT(n) ((n) >> 5) -#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) -#define GPIO_PIN_FUNCTION_OFF 0xffffffff - -/** - * \brief PORT pull mode settings - */ -enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; - -/** - * \brief PORT direction settins - */ -enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; - -/** - * \brief PORT group abstraction - */ - -enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Port initialization function - * - * Port initialization function should setup the port module based - * on a static configuration file, this function should normally - * not be called directly, but is a part of hal_init() - */ -void _gpio_init(void); - -/** - * \brief Set direction on port with mask - * - * Set data direction for each pin, or disable the pin - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to the - * corresponding pin - * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input - * and disable input buffer to disable the pin - * GPIO_DIRECTION_IN = set pin direction to input - * and enable input buffer to enable the pin - * GPIO_DIRECTION_OUT = set pin direction to output - * and disable input buffer - */ -static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction); - -/** - * \brief Set output level on port with mask - * - * Sets output state on pin to high or low with pin masking - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to - * the corresponding pin - * \param[in] level true = pin level is set to 1 - * false = pin level is set to 0 - */ -static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); - -/** - * \brief Change output level to the opposite with mask - * - * Change pin output level to the opposite with pin masking - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] mask Bit mask where 1 means apply direction setting to - * the corresponding pin - */ -static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); - -/** - * \brief Get input levels on all port pins - * - * Get input level on all port pins, will read IN register if configured to - * input and OUT register if configured as output - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - */ -static inline uint32_t _gpio_get_level(const enum gpio_port port); - -/** - * \brief Set pin pull mode - * - * Set pull mode on a single pin - * - * \notice This function will automatically change pin direction to input - * - * \param[in] port Ports are grouped into groups of maximum 32 pins, - * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc - * \param[in] pin The pin in the group that pull mode should be selected - * for - * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled - * GPIO_PULL_DOWN = pull resistor on pin will pull pin - * level to ground level - * GPIO_PULL_UP = pull resistor on pin will pull pin - * level to VCC - */ -static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, - const enum gpio_pull_mode pull_mode); - -/** - * \brief Set gpio function - * - * Select which function a gpio is used for - * - * \param[in] gpio The gpio to set function for - * \param[in] function The gpio function is given by a 32-bit wide bitfield - * found in the header files for the device - * - */ -static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); - -#include -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_async.h deleted file mode 100644 index c00d7e733..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_async.h +++ /dev/null @@ -1,215 +0,0 @@ -/** - * \file - * - * \brief I2C Master Hardware Proxy Layer(HPL) declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED -#define _HPL_I2C_M_ASYNC_H_INCLUDED - -#include "hpl_i2c_m_sync.h" -#include "hpl_irq.h" -#include "utils.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c master callback names - */ -enum _i2c_m_async_callback_type { - I2C_M_ASYNC_DEVICE_ERROR, - I2C_M_ASYNC_DEVICE_TX_COMPLETE, - I2C_M_ASYNC_DEVICE_RX_COMPLETE -}; - -struct _i2c_m_async_device; - -typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); -typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); - -/** - * \brief i2c callback pointers structure - */ -struct _i2c_m_async_callback { - _i2c_error_cb_t error; - _i2c_complete_cb_t tx_complete; - _i2c_complete_cb_t rx_complete; -}; - -/** - * \brief i2c device structure - */ -struct _i2c_m_async_device { - struct _i2c_m_service service; - void * hw; - struct _i2c_m_async_callback cb; - struct _irq_descriptor irq; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize I2C in interrupt mode - * - * This function does low level I2C configuration. - * - * \param[in] i2c_dev The pointer to i2c interrupt device structure - * \param[in] hw The pointer to hardware instance - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); - -/** - * \brief Deinitialize I2C in interrupt mode - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Transfer data by I2C - * - * This function does low level I2C data transfer. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] msg The pointer to i2c msg structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); - -/** - * \brief Set baud rate of I2C - * - * This function does low level I2C set baud rate. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] clkrate The clock rate(KHz) input to i2c module - * \param[in] baudrate The demand baud rate(KHz) of i2c module - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Register callback to I2C - * - * This function does low level I2C callback register. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] cb_type The callback type request - * \param[in] func The callback function pointer - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, - FUNC_PTR func); - -/** - * \brief Generate stop condition on the I2C bus - * - * This function will generate a stop condition on the I2C bus - * - * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C - * - * \return Operation status - * \retval 0 Operation executed successfully - * \retval <0 Operation failed - */ -int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Returns the number of bytes left or not used in the I2C message buffer - * - * This function will return the number of bytes left (not written to the bus) or still free - * (not received from the bus) in the message buffer, depending on direction of transmission. - * - * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C - * - * \return Number of bytes or error code - * \retval >0 Positive number indicating bytes left - * \retval 0 Buffer is full/empty depending on direction - * \retval <0 Error code - */ -int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); - -/** - * \brief Enable/disable I2C master interrupt - * - * param[in] device The pointer to I2C master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, - const bool state); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_sync.h deleted file mode 100644 index 4a643ee65..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_m_sync.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - * \file - * - * \brief I2C Master Hardware Proxy Layer(HPL) declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_M_SYNC_H_INCLUDED -#define _HPL_I2C_M_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c flags - */ -#define I2C_M_RD 0x0001 /* read data, from slave to master */ -#define I2C_M_BUSY 0x0100 -#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ -#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ -#define I2C_M_FAIL 0x1000 -#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ - -/** - * \brief i2c Return codes - */ -#define I2C_OK 0 /* Operation successful */ -#define I2C_ACK -1 /* Received ACK from device on I2C bus */ -#define I2C_NACK -2 /* Received NACK from device on I2C bus */ -#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ -#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ -#define I2C_ERR_BUS -5 /* Bus error */ -#define I2C_ERR_BUSY -6 /* Device busy */ -#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ - -/** - * \brief i2c I2C Modes - */ -#define I2C_STANDARD_MODE 0x00 -#define I2C_FASTMODE 0x01 -#define I2C_HIGHSPEED_MODE 0x02 - -/** - * \brief i2c master message structure - */ -struct _i2c_m_msg { - uint16_t addr; - volatile uint16_t flags; - int32_t len; - uint8_t * buffer; -}; - -/** - * \brief i2c master service - */ -struct _i2c_m_service { - struct _i2c_m_msg msg; - uint16_t mode; - uint16_t trise; -}; - -/** - * \brief i2c sync master device structure - */ -struct _i2c_m_sync_device { - struct _i2c_m_service service; - void * hw; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize I2C - * - * This function does low level I2C configuration. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] hw The pointer to hardware instance - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); - -/** - * \brief Deinitialize I2C - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] i2c_dev The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); - -/** - * \brief Transfer data by I2C - * - * This function does low level I2C data transfer. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] msg The pointer to i2c msg structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); - -/** - * \brief Set baud rate of I2C - * - * This function does low level I2C set baud rate. - * - * \param[in] i2c_dev The pointer to i2c device structure - * \param[in] clkrate The clock rate(KHz) input to i2c module - * \param[in] baudrate The demand baud rate(KHz) of i2c module - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); - -/** - * \brief Send send condition on the I2C bus - * - * This function will generate a stop condition on the I2C bus - * - * \param[in] i2c_dev The pointer to i2c device struct - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_async.h deleted file mode 100644 index b240478f7..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_async.h +++ /dev/null @@ -1,194 +0,0 @@ -/** - * \file - * - * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED -#define _HPL_I2C_S_ASYNC_H_INCLUDED - -#include "hpl_i2c_s_sync.h" -#include "hpl_irq.h" -#include "utils.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief i2c callback types - */ -enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; - -/** - * \brief Forward declaration of I2C Slave device - */ -struct _i2c_s_async_device; - -/** - * \brief i2c slave callback function type - */ -typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); - -/** - * \brief i2c slave callback pointers structure - */ -struct _i2c_s_async_callback { - void (*error)(struct _i2c_s_async_device *const device); - void (*tx)(struct _i2c_s_async_device *const device); - void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); -}; - -/** - * \brief i2c slave device structure - */ -struct _i2c_s_async_device { - void * hw; - struct _i2c_s_async_callback cb; - struct _irq_descriptor irq; -}; - -/** - * \name HPL functions - */ - -/** - * \brief Initialize asynchronous I2C slave - * - * This function does low level I2C configuration. - * - * \param[in] device The pointer to i2c interrupt device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); - -/** - * \brief Deinitialize asynchronous I2C in interrupt mode - * - * \param[in] device The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); - -/** - * \brief Check if 10-bit addressing mode is on - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Cheking status - * \retval 1 10-bit addressing mode is on - * \retval 0 10-bit addressing mode is off - */ -int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); - -/** - * \brief Set I2C slave address - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] address Address to set - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); - -/** - * \brief Write a byte to the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] data Data to write - */ -void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); - -/** - * \brief Retrieve I2C slave status - * - * \param[in] device The pointer to i2c slave device structure - * - *\return I2C slave status - */ -i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); - -/** - * \brief Abort data transmission - * - * \param[in] device The pointer to i2c device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); - -/** - * \brief Enable/disable I2C slave interrupt - * - * param[in] device The pointer to I2C slave device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] disable Enable or disable - */ -int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, - const bool disable); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_sync.h deleted file mode 100644 index a0f4fa465..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_i2c_s_sync.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - * \file - * - * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_I2C_S_SYNC_H_INCLUDED -#define _HPL_I2C_S_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief I2C Slave status type - */ -typedef uint32_t i2c_s_status_t; - -/** - * \brief i2c slave device structure - */ -struct _i2c_s_sync_device { - void *hw; -}; - -#include - -/** - * \name HPL functions - */ - -/** - * \brief Initialize synchronous I2C slave - * - * This function does low level I2C configuration. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize synchronous I2C slave - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); - -/** - * \brief Enable I2C module - * - * This function does low level I2C enable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); - -/** - * \brief Disable I2C module - * - * This function does low level I2C disable. - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); - -/** - * \brief Check if 10-bit addressing mode is on - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Cheking status - * \retval 1 10-bit addressing mode is on - * \retval 0 10-bit addressing mode is off - */ -int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); - -/** - * \brief Set I2C slave address - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] address Address to set - * - * \return Return 0 for success and negative value for error - */ -int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); - -/** - * \brief Write a byte to the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * \param[in] data Data to write - */ -void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); - -/** - * \brief Retrieve I2C slave status - * - * \param[in] device The pointer to i2c slave device structure - * - *\return I2C slave status - */ -i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); - -/** - * \brief Read a byte from the given I2C instance - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Data received via I2C interface. - */ -uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); - -/** - * \brief Check if I2C is ready to send next byte - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Status of the ready check. - * \retval true if the I2C is ready to send next byte - * \retval false if the I2C is not ready to send next byte - */ -bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); - -/** - * \brief Check if there is data received by I2C - * - * \param[in] device The pointer to i2c slave device structure - * - * \return Status of the data received check. - * \retval true if the I2C has received a byte - * \retval false if the I2C has not received a byte - */ -bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_init.h b/atmel-samd/asf4/samd51/hal/include/hpl_init.h deleted file mode 100644 index be54600c0..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_init.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - * \file - * - * \brief Init related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_INIT_H_INCLUDED -#define _HPL_INIT_H_INCLUDED - -/** - * \addtogroup HPL Init - * - * \section hpl_init_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initializes clock sources - */ -void _sysctrl_init_sources(void); - -/** - * \brief Initializes Power Manager - */ -void _pm_init(void); - -/** - * \brief Initialize generators - */ -void _gclk_init_generators(void); - -/** - * \brief Initialize 32 kHz clock sources - */ -void _osc32kctrl_init_sources(void); - -/** - * \brief Initialize clock sources - */ -void _oscctrl_init_sources(void); - -/** - * \brief Initialize clock sources that need input reference clocks - */ -void _sysctrl_init_referenced_generators(void); - -/** - * \brief Initialize clock sources that need input reference clocks - */ -void _oscctrl_init_referenced_generators(void); - -/** - * \brief Initialize master clock generator - */ -void _mclk_init(void); - -/** - * \brief Initialize clock generator - */ -void _lpmcu_misc_regs_init(void); - -/** - * \brief Initialize clock generator - */ -void _pmc_init(void); - -/** - * \brief Set performance level - * - * \param[in] level The performance level to set - */ -void _set_performance_level(const uint8_t level); - -/** - * \brief Initialize the chip - */ -void _init_chip(void); - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_irq.h b/atmel-samd/asf4/samd51/hal/include/hpl_irq.h deleted file mode 100644 index 7325b5711..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_irq.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - * \file - * - * \brief IRQ related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_IRQ_H_INCLUDED -#define _HPL_IRQ_H_INCLUDED - -/** - * \addtogroup HPL IRQ - * - * \section hpl_irq_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief IRQ descriptor - */ -struct _irq_descriptor { - void (*handler)(void *parameter); - void *parameter; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Retrieve current IRQ number - * - * \return The current IRQ number - */ -uint8_t _irq_get_current(void); - -/** - * \brief Disable the given IRQ - * - * \param[in] n The number of IRQ to disable - */ -void _irq_disable(uint8_t n); - -/** - * \brief Set the given IRQ - * - * \param[in] n The number of IRQ to set - */ -void _irq_set(uint8_t n); - -/** - * \brief Clear the given IRQ - * - * \param[in] n The number of IRQ to clear - */ -void _irq_clear(uint8_t n); - -/** - * \brief Enable the given IRQ - * - * \param[in] n The number of IRQ to enable - */ -void _irq_enable(uint8_t n); - -/** - * \brief Register IRQ handler - * - * \param[in] number The number registered IRQ - * \param[in] irq The pointer to irq handler to register - * - * \return The status of IRQ handler registering - * \retval -1 Passed parameters were invalid - * \retval 0 The registering is completed successfully - */ -void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_missing_features.h b/atmel-samd/asf4/samd51/hal/include/hpl_missing_features.h deleted file mode 100644 index 90fa16be4..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_missing_features.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * \file - * - * \brief Family-dependent missing features expected by HAL - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_MISSING_FEATURES -#define _HPL_MISSING_FEATURES - -#endif /* _HPL_MISSING_FEATURES */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_pwm.h b/atmel-samd/asf4/samd51/hal/include/hpl_pwm.h deleted file mode 100644 index 8deb54cc0..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_pwm.h +++ /dev/null @@ -1,203 +0,0 @@ -/** - * \file - * - * \brief PWM related functionality declaration. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _HPL_PWM_H_INCLUDED -#define _HPL_PWM_H_INCLUDED - -/** - * \addtogroup HPL PWM - * - * \section hpl_pwm_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief PWM callback types - */ -enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB }; - -/** - * \brief PWM pulse-width period - */ -typedef uint32_t pwm_period_t; - -/** - * \brief PWM device structure - * - * The PWM device structure forward declaration. - */ -struct _pwm_device; - -/** - * \brief PWM interrupt callbacks - */ -struct _pwm_callback { - void (*pwm_period_cb)(struct _pwm_device *device); - void (*pwm_error_cb)(struct _pwm_device *device); -}; - -/** - * \brief PWM descriptor device structure - */ -struct _pwm_device { - struct _pwm_callback callback; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \brief PWM functions, pointers to low-level functions - */ -struct _pwm_hpl_interface { - int32_t (*init)(struct _pwm_device *const device, void *const hw); - void (*deinit)(struct _pwm_device *const device); - void (*start_pwm)(struct _pwm_device *const device); - void (*stop_pwm)(struct _pwm_device *const device); - void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); - bool (*is_pwm_enabled)(const struct _pwm_device *const device); - pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device); - uint32_t (*pwm_get_duty)(const struct _pwm_device *const device); - void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); -}; -/** - * \brief Initialize TC - * - * This function does low level TC configuration. - * - * \param[in] device The pointer to PWM device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - */ -int32_t _pwm_init(struct _pwm_device *const device, void *const hw); - -/** - * \brief Deinitialize TC - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_deinit(struct _pwm_device *const device); - -/** - * \brief Retrieve offset of the given tc hardware instance - * - * \param[in] device The pointer to PWM device instance - * - * \return The offset of the given tc hardware instance - */ -uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device); - -/** - * \brief Start hardware pwm - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_enable(struct _pwm_device *const device); - -/** - * \brief Stop hardware pwm - * - * \param[in] device The pointer to PWM device instance - */ -void _pwm_disable(struct _pwm_device *const device); - -/** - * \brief Set pwm parameter - * - * \param[in] device The pointer to PWM device instance - * \param[in] period Total period of one PWM cycle. - * \param[in] duty_cycle Period of PWM first half during one cycle. - */ -void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); - -/** - * \brief Check if pwm is working - * - * \param[in] device The pointer to PWM device instance - * - * \return Check status. - * \retval true The given pwm is working - * \retval false The given pwm is not working - */ -bool _pwm_is_enabled(const struct _pwm_device *const device); - -/** - * \brief Get pwm waveform period value - * - * \param[in] device The pointer to PWM device instance - * - * \return Period value. - */ -pwm_period_t _pwm_get_period(const struct _pwm_device *const device); - -/** - * \brief Get pwm waveform duty cycle value - * - * \param[in] device The pointer to PWM device instance - * - * \return Duty cycle value - */ -uint32_t _pwm_get_duty(const struct _pwm_device *const device); - -/** - * \brief Enable/disable PWM interrupt - * - * param[in] device The pointer to PWM device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] disable Enable or disable - */ -void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_PWM_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_ramecc.h b/atmel-samd/asf4/samd51/hal/include/hpl_ramecc.h deleted file mode 100644 index 014d815ec..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_ramecc.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - * \file - * - * \brief RAMECC related functionality declaration. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_RAMECC_H_INCLUDED -#define _HPL_RAMECC_H_INCLUDED - -/** - * \addtogroup HPL RAMECC - * - * \section hpl_ramecc_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief RAMECC callback type - */ -typedef void (*ramecc_cb_t)(const uint32_t data); - -/** - * \brief RAMECC callback types - */ -enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB }; - -/** - * \brief RAMECC interrupt callbacks - */ -struct _ramecc_callbacks { - ramecc_cb_t dual_bit_err; - ramecc_cb_t single_bit_err; -}; - -/** - * \brief RAMECC device structure - */ -struct _ramecc_device { - struct _ramecc_callbacks ramecc_cb; - struct _irq_descriptor irq; -}; - -/** - * \brief Initialize RAMECC - * - * This function does low level RAMECC configuration. - * - * \return initialize status - */ -int32_t _ramecc_init(void); - -/** - * \brief Register RAMECC callback - * - * \param[in] type The type of callback - * \param[in] cb A callback function - */ -void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_RAMECC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_rand_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_rand_sync.h deleted file mode 100644 index 3155b718e..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_rand_sync.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - * \file - * - * \brief Random Number Generator (RAND) related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_RAND_SYNC_H_INCLUDED -#define _HPL_RAND_SYNC_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** Random Number Generator polling device. */ -struct _rand_sync_dev { - /** Pointer to private data or hardware base */ - void *prvt; - /** Number of bits generated for each read operation */ - uint8_t n_bits; -}; - -/** - * \brief Initialize the Random Number Generator Driver - * \param[out] dev Pointer to the device instance struct - * \param[in, out] hw Pointer to the hardware for device instance - * \return Initialization operation result status, 0 for OK. - */ -int32_t _rand_sync_init(struct _rand_sync_dev *const dev, void *const hw); - -/** - * \brief Deinitialize the Random Number Generator Driver - * \param[in, out] dev Pointer to the device instance struct - */ -void _rand_sync_deinit(struct _rand_sync_dev *const dev); - -/** - * \brief Enable the Random Number Generator Driver - * \param[out] dev Pointer to the device instance struct - * \return Enable operation result status, 0 for OK. - */ -int32_t _rand_sync_enable(struct _rand_sync_dev *const dev); - -/** - * \brief Disable the Random Number Generator Driver - * \param[out] dev Pointer to the device instance struct - */ -void _rand_sync_disable(struct _rand_sync_dev *const dev); - -/** - * \brief Set seed for the Random Number Generator Driver - * \param[out] dev Pointer to the device instance struct - * \param[in] seed The seed to set - * \return Operation result - * \retval ERR_NONE Operation complete success - * \retval ERR_UNSUPPORTED_OP Seed not supported - */ -int32_t _rand_sync_set_seed(struct _rand_sync_dev *const dev, const uint32_t seed); - -/** - * \brief Polling random number until it's read back - * \param[in] dev Pointer to the device instance struct - * \return The random number value - */ -uint32_t _rand_sync_read_one(const struct _rand_sync_dev *const dev); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_RAND_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_reset.h b/atmel-samd/asf4/samd51/hal/include/hpl_reset.h deleted file mode 100644 index c9861cdcf..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_reset.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * \file - * - * \brief Reset related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_RESET_H_INCLUDED -#define _HPL_RESET_H_INCLUDED - -/** - * \addtogroup HPL Reset - * - * \section hpl_reset_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Reset reason enumeration - * - * The list of possible reset reasons. - */ -enum reset_reason { - RESET_REASON_POR = 1, - RESET_REASON_BOD12 = 2, - RESET_REASON_BOD33 = 4, - RESET_REASON_NVM = 8, - RESET_REASON_EXT = 16, - RESET_REASON_WDT = 32, - RESET_REASON_SYST = 64, - RESET_REASON_BACKUP = 128 -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Retrieve the reset reason - * - * Retrieves the reset reason of the last MCU reset. - * - *\return An enum value indicating the reason of the last reset. - */ -enum reset_reason _get_reset_reason(void); - -/** - * \brief Reset MCU - */ -void _reset_mcu(void); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_sleep.h b/atmel-samd/asf4/samd51/hal/include/hpl_sleep.h deleted file mode 100644 index 3bd6a1cb2..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_sleep.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SLEEP_H_INCLUDED -#define _HPL_SLEEP_H_INCLUDED - -/** - * \addtogroup HPL Sleep - * - * \section hpl_sleep_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifndef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Set the sleep mode for the device - * - * This function sets the sleep mode for the device. - * For an overview of which systems are disabled in sleep for the different - * sleep modes see datasheet. - * - * \param[in] mode Sleep mode to use - * - * \return the status of a sleep request - * \retval -1 The requested sleep mode was invalid - * \retval 0 The operation completed successfully, sleep mode is set - */ -int32_t _set_sleep_mode(const uint8_t mode); - -/** - * \brief Reset MCU - */ -void _reset_mcu(void); - -/** - * \brief Put MCU to sleep - */ -void _go_to_sleep(void); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi.h deleted file mode 100644 index 14177642f..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_spi.h +++ /dev/null @@ -1,173 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (C) 2014 - 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_H_INCLUDED -#define _HPL_SPI_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief SPI Dummy char is used when reading data from the SPI slave - */ -#define SPI_DUMMY_CHAR 0x1ff - -/** - * \brief SPI message to let driver to process - */ -//@{ -struct spi_msg { - /** Pointer to the output data buffer */ - uint8_t *txbuf; - /** Pointer to the input data buffer */ - uint8_t *rxbuf; - /** Size of the message data in SPI characters */ - uint32_t size; -}; -//@} - -/** - * \brief SPI transfer modes - * SPI transfer mode controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - */ -enum spi_transfer_mode { - /** Leading edge is rising edge, data sample on leading edge. */ - SPI_MODE_0, - /** Leading edge is rising edge, data sample on trailing edge. */ - SPI_MODE_1, - /** Leading edge is falling edge, data sample on leading edge. */ - SPI_MODE_2, - /** Leading edge is falling edge, data sample on trailing edge. */ - SPI_MODE_3 -}; - -/** - * \brief SPI character sizes - * The character size influence the way the data is sent/received. - * For char size <= 8 data is stored byte by byte. - * For char size between 9 ~ 16 data is stored in 2-byte length. - * Note that the default and recommended char size is 8 bit since it's - * supported by all system. - */ -enum spi_char_size { - /** Character size is 8 bit. */ - SPI_CHAR_SIZE_8 = 0, - /** Character size is 9 bit. */ - SPI_CHAR_SIZE_9 = 1, - /** Character size is 10 bit. */ - SPI_CHAR_SIZE_10 = 2, - /** Character size is 11 bit. */ - SPI_CHAR_SIZE_11 = 3, - /** Character size is 12 bit. */ - SPI_CHAR_SIZE_12 = 4, - /** Character size is 13 bit. */ - SPI_CHAR_SIZE_13 = 5, - /** Character size is 14 bit. */ - SPI_CHAR_SIZE_14 = 6, - /** Character size is 15 bit. */ - SPI_CHAR_SIZE_15 = 7, - /** Character size is 16 bit. */ - SPI_CHAR_SIZE_16 = 8 -}; - -/** - * \brief SPI data order - */ -enum spi_data_order { - /** MSB goes first. */ - SPI_DATA_ORDER_MSB_1ST = 0, - /** LSB goes first. */ - SPI_DATA_ORDER_LSB_1ST = 1 -}; - -/** \brief Transfer descriptor for SPI - * Transfer descriptor holds TX and RX buffers - */ -struct spi_xfer { - /** Pointer to data buffer to TX */ - uint8_t *txbuf; - /** Pointer to data buffer to RX */ - uint8_t *rxbuf; - /** Size of data characters to TX & RX */ - uint32_t size; -}; - -/** SPI generic driver. */ -struct spi_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Reference start of sync/async variables */ - uint32_t sync_async_misc[1]; -}; - -/** - * \brief Calculate the baudrate value for hardware to use to set baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] clk Clock frequency (Hz) for baudrate generation. - * \param[in] baud Target baudrate (bps). - * \return Error or baudrate value. - * \retval >0 Baudrate value. - * \retval ERR_INVALID_ARG Calculation fail. - */ -int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_async.h deleted file mode 100644 index b81ef12af..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_spi_async.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * \file - * - * \brief Common SPI related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_ASYNC_H_INCLUDED -#define _HPL_SPI_ASYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Callbacks the SPI driver must offer in async mode - */ -//@{ -/** The callback types */ -enum _spi_async_dev_cb_type { - /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ - SPI_DEV_CB_TX, - /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ - SPI_DEV_CB_RX, - /** Callback type for \ref _spi_async_dev_cb_complete_t. */ - SPI_DEV_CB_COMPLETE, - /** Number of callbacks. */ - SPI_DEV_CB_N -}; - -struct _spi_async_dev; - -/** \brief The prototype for callback on SPI transfer complete. - * If status code is zero, it indicates the normal completion, that is, - * SS deactivation. - * If status code belows zero, it indicates complete. - */ -typedef void (*_spi_async_dev_cb_complete_t)(struct _spi_async_dev *dev, int32_t status); - -/** \brief The prototype for callback on SPI transmit/receive event - * For TX, the callback is invoked when transmit is done or ready to start - * transmit. - * For RX, the callback is invoked when receive is done or ready to read data, - * see \ref _spi_async_dev_read_one_t on data reading. - * Without DMA enabled, the callback is invoked on each character event. - * With DMA enabled, the callback is invoked on DMA buffer done. - */ -typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); - -/** - * \brief The callbacks offered by SPI driver - */ -struct _spi_async_dev_callbacks { - /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ - _spi_async_dev_cb_xfer_t tx; - /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ - _spi_async_dev_cb_xfer_t rx; - /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ - _spi_async_dev_cb_complete_t complete; -}; -//@} - -/** - * \brief SPI async driver - */ -//@{ - -/** SPI driver to support async HAL */ -struct _spi_async_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Data size, number of bytes for each character */ - uint8_t char_size; - /** Dummy byte used in master mode when reading the slave */ - uint16_t dummy_byte; - - /** \brief Pointer to callback functions, ignored for polling mode - * Pointer to the callback functions so that initialize the driver to - * handle interrupts. - */ - struct _spi_async_dev_callbacks callbacks; - /** IRQ instance for SPI device. */ - struct _irq_descriptor irq; -}; -//@} - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_dma.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_dma.h deleted file mode 100644 index 3f2088c05..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_spi_dma.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * \file - * - * \brief Common SPI DMA related functionality declaration. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_DMA_H_INCLUDED -#define _HPL_SPI_DMA_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** The callback types */ -enum _spi_dma_dev_cb_type { - /** Callback type for DMA transmit. */ - SPI_DEV_CB_DMA_TX, - /** Callback type for DMA receive. */ - SPI_DEV_CB_DMA_RX, - /** Callback type for DMA error. */ - SPI_DEV_CB_DMA_ERROR, - /** Number of callbacks. */ - SPI_DEV_CB_DMA_N -}; - -struct _spi_dma_dev; - -/** - * \brief The prototype for callback on SPI DMA. - */ -typedef void (*_spi_dma_cb_t)(struct _dma_resource *resource); - -/** - * \brief The callbacks offered by SPI driver - */ -struct _spi_dma_dev_callbacks { - _spi_dma_cb_t tx; - _spi_dma_cb_t rx; - _spi_dma_cb_t error; -}; - -/** SPI driver to support DMA HAL */ -struct _spi_dma_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Pointer to callback functions */ - struct _spi_dma_dev_callbacks callbacks; - /** IRQ instance for SPI device. */ - struct _irq_descriptor irq; - /** DMA resource */ - struct _dma_resource *resource; -}; - -#ifdef __cplusplus -} -#endif - -#endif /* ifndef _HPL_SPI_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_async.h deleted file mode 100644 index f2d330495..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_async.h +++ /dev/null @@ -1,248 +0,0 @@ -/** - * \file - * - * \brief SPI Slave Async related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED -#define _HPL_SPI_M_ASYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_m_async_dev _spi_async_dev - -#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type - -/** Uses common SPI async device driver complete callback type. */ -#define _spi_m_async_dev_cb_complete_t _spi_async_dev_cb_complete_t - -/** Uses common SPI async device driver transfer callback type. */ -#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t - -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on Slave Select (SS) rising - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_m_async_enable_ss_detect(struct _spi_m_async_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); - -/** - * \brief Register the SPI device callback - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, - const FUNC_PTR func); - -/** - * \brief Enable/disable SPI master interrupt - * - * param[in] device The pointer to SPI master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, - const bool state); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_dma.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_dma.h deleted file mode 100644 index 5e676fdc5..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_dma.h +++ /dev/null @@ -1,187 +0,0 @@ -/** - * \file - * - * \brief SPI Master DMA related functionality declaration. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_DMA_H_INCLUDED -#define _HPL_SPI_M_DMA_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI dma device driver. */ -#define _spi_m_dma_dev _spi_dma_dev - -#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type - -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 ERR_NONE is operation done successfully. - */ -int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); - -/** - * \brief Register the SPI device callback - * \param[in] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); - -/** \brief Do SPI data transfer (TX & RX) with DMA - * Log the TX & RX buffers and transfer them in background. It never blocks. - * - * \param[in] dev Pointer to the SPI device instance. - * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). - * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). - * \param[in] length spi transfer data length. - * - * \return Operation status. - * \retval ERR_NONE Success. - * \retval ERR_BUSY Busy. - */ -int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, - const uint16_t length); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_sync.h deleted file mode 100644 index fff1db4f2..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_spi_m_sync.h +++ /dev/null @@ -1,171 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_M_SYNC_H_INCLUDED -#define _HPL_SPI_M_SYNC_H_INCLUDED - -#include -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_m_sync_dev _spi_sync_dev - -/** - * \brief Initialize SPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); - -/** - * \brief Deinitialize SPI - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); - -/** - * \brief Enable SPI for access without interrupts - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on - * how it's generated. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); - -/** - * \brief Transfer the whole message without interrupt - * Transfer the message, it will keep waiting until the message finish or - * error. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] msg Pointer to the message instance to process. - * \return Error or number of characters transferred. - * \retval ERR_BUSY SPI hardware is not ready to start transfer (not - * enabled, busy applying settings, ...). - * \retval SPI_ERR_OVERFLOW Overflow error. - * \retval >=0 Number of characters transferred. - */ -int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_async.h deleted file mode 100644 index aec3c0a6f..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_async.h +++ /dev/null @@ -1,227 +0,0 @@ -/** - * \file - * - * \brief SPI Slave Async related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED -#define _HPL_SPI_S_ASYNC_H_INCLUDED - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_s_async_dev _spi_async_dev - -#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type - -/** Uses common SPI async device driver complete callback type. */ -#define _spi_s_async_dev_cb_complete_t _spi_async_dev_cb_complete_t - -/** Uses common SPI async device driver transfer callback type. */ -#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t - -/** - * \brief Initialize SPI for access with interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); - -/** - * \brief Enable SPI for access with interrupts - * Enable the SPI and enable callback generation of receive and error - * interrupts. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI and interrupts. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Enable interrupt on Slave Select (SS) rising - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retvat 0 OK Status - */ -int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); - -/** - * \brief Register the SPI device callback - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] cb_type The callback type. - * \param[in] func The callback function to register. NULL to disable callback. - * \return Always 0. - */ -int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, - const FUNC_PTR func); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_sync.h deleted file mode 100644 index d42368697..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_spi_s_sync.h +++ /dev/null @@ -1,237 +0,0 @@ -/** - * \file - * - * \brief SPI related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_S_SYNC_H_INCLUDED -#define _HPL_SPI_S_SYNC_H_INCLUDED - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** Uses common SPI async device driver. */ -#define _spi_s_sync_dev _spi_sync_dev - -/** - * \brief Initialize SPI for access without interrupts - * It will load default hardware configuration and software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] hw Pointer to the hardware base. - * \return Operation status. - * \retval ERR_INVALID_ARG Input parameter problem. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval ERR_DENIED SPI has been enabled. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); - -/** - * \brief Initialize SPI for access with interrupts - * Disable, reset the hardware and the software struct. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); - -/** - * \brief Enable SPI for access without interrupts - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval ERR_BUSY SPI hardware not ready (resetting). - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); - -/** - * \brief Disable SPI for access without interrupts - * Disable SPI. Deactivate all CS pins if works as master. - * \param[in, out] dev Pointer to the SPI device instance. - * \return Operation status. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); - -/** - * \brief Set SPI transfer mode - * Set SPI transfer mode (\ref spi_transfer_mode), - * which controls clock polarity and clock phase. - * Mode 0: leading edge is rising edge, data sample on leading edge. - * Mode 1: leading edge is rising edge, data sample on trailing edge. - * Mode 2: leading edge is falling edge, data sample on leading edge. - * Mode 3: leading edge is falling edge, data sample on trailing edge. - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] mode The SPI transfer mode. - * \return Operation status. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); - -/** - * \brief Set SPI baudrate - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] char_size The character size, see \ref spi_char_size. - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); - -/** - * \brief Set SPI data order - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] dord SPI data order (LSB/MSB first). - * \return Operation status. - * \retval ERR_INVALID_ARG The character size is not supported. - * \retval ERR_BUSY SPI is not ready to accept new setting. - * \retval 0 Operation done successfully. - */ -int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); - -/** - * \brief Enable interrupt on character output - * - * Enable interrupt when a new character can be written - * to the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable output interrupt - * false = disable output interrupt - * - * \return Status code - * \retval 0 Ok status - */ -int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); - -/** - * \brief Enable interrupt on character input - * - * Enable interrupt when a new character is ready to be - * read from the SPI device. - * - * \param[in] dev Pointer to the SPI device instance - * \param[in] state true = enable input interrupts - * false = disable input interrupt - * - * \return Status code - * \retval 0 OK Status - */ -int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); - -/** - * \brief Read one character to SPI device instance - * \param[in, out] dev Pointer to the SPI device instance. - * - * \return Character read from SPI module - */ -uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); - -/** - * \brief Write one character to assigned buffer - * \param[in, out] dev Pointer to the SPI device instance. - * \param[in] data - * - * \return Status code of write operation - * \retval 0 Write operation OK - */ -int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); - -/** - * \brief Check if TX ready - * - * \param[in] dev Pointer to the SPI device instance - * - * \return TX ready state - * \retval true TX ready - * \retval false TX not ready - */ -bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if RX character ready - * - * \param[in] dev Pointer to the SPI device instance - * - * \return RX character ready state - * \retval true RX character ready - * \retval false RX character not ready - */ -bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if SS deactiviation detected - * - * \param[in] dev Pointer to the SPI device instance - * - * \return SS deactiviation state - * \retval true SS deactiviation detected - * \retval false SS deactiviation not detected - */ -bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); - -/** - * \brief Check if error is detected - * - * \param[in] dev Pointer to the SPI device instance - * - * \return Error detection state - * \retval true Error detected - * \retval false Error not detected - */ -bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_spi_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_spi_sync.h deleted file mode 100644 index a231a0bb5..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_spi_sync.h +++ /dev/null @@ -1,80 +0,0 @@ -/** - * \file - * - * \brief Common SPI related functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SPI_SYNC_H_INCLUDED -#define _HPL_SPI_SYNC_H_INCLUDED - -#include -#include - -#include - -/** - * \addtogroup hpl_spi HPL SPI - * - * \section hpl_spi_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** SPI driver to support sync HAL */ -struct _spi_sync_dev { - /** Pointer to the hardware base or private data for special device. */ - void *prvt; - /** Data size, number of bytes for each character */ - uint8_t char_size; - /** Dummy byte used in master mode when reading the slave */ - uint16_t dummy_byte; -}; - -#ifdef __cplusplus -} -#endif - -/**@}*/ -#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_time_measure.h b/atmel-samd/asf4/samd51/hal/include/hpl_time_measure.h deleted file mode 100644 index 7502a5910..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_time_measure.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - * \file - * - * \brief Time measure related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_TIME_MEASURE_H_INCLUDED -#define _HPL_TIME_MEASURE_H_INCLUDED - -/** - * \addtogroup HPL Time measure - * - * \section hpl_time_measure_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief System time type - */ -typedef uint32_t system_time_t; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize system time module - * - * \param[in] hw The pointer to hardware instance to initialize - */ -void _system_time_init(void *const hw); - -/** - * \brief Deinitialize system time module - * - * \param[in] hw The pointer to hardware instance to initialize - */ -void _system_time_deinit(void *const hw); - -/** - * \brief Get system time - * - * \param[in] hw The pointer to hardware instance to initialize - */ -system_time_t _system_time_get(const void *const hw); - -/** - * \brief Get maximum possible system time - * - * \param[in] hw The pointer to hardware instance to initialize - */ -system_time_t _system_time_get_max_time_value(const void *const hw); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_TIME_MEASURE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_timer.h b/atmel-samd/asf4/samd51/hal/include/hpl_timer.h deleted file mode 100644 index d2434e8c4..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_timer.h +++ /dev/null @@ -1,170 +0,0 @@ -/** - * \file - * - * \brief Timer related functionality declaration. - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_TIMER_H_INCLUDED -#define _HPL_TIMER_H_INCLUDED - -/** - * \addtogroup HPL Timer - * - * \section hpl_timer_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Timer device structure - * - * The Timer device structure forward declaration. - */ -struct _timer_device; - -/** - * \brief Timer interrupt callbacks - */ -struct _timer_callbacks { - void (*period_expired)(struct _timer_device *device); -}; - -/** - * \brief Timer device structure - */ -struct _timer_device { - struct _timer_callbacks timer_cb; - struct _irq_descriptor irq; - void * hw; -}; - -/** - * \brief Timer functions, pointers to low-level functions - */ -struct _timer_hpl_interface { - int32_t (*init)(struct _timer_device *const device, void *const hw); - void (*deinit)(struct _timer_device *const device); - void (*start_timer)(struct _timer_device *const device); - void (*stop_timer)(struct _timer_device *const device); - void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); - uint32_t (*get_period)(const struct _timer_device *const device); - bool (*is_timer_started)(const struct _timer_device *const device); - void (*set_timer_irq)(struct _timer_device *const device); -}; -/** - * \brief Initialize TCC - * - * This function does low level TCC configuration. - * - * \param[in] device The pointer to timer device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status. - */ -int32_t _timer_init(struct _timer_device *const device, void *const hw); - -/** - * \brief Deinitialize TCC - * - * \param[in] device The pointer to timer device instance - */ -void _timer_deinit(struct _timer_device *const device); - -/** - * \brief Start hardware timer - * - * \param[in] device The pointer to timer device instance - */ -void _timer_start(struct _timer_device *const device); - -/** - * \brief Stop hardware timer - * - * \param[in] device The pointer to timer device instance - */ -void _timer_stop(struct _timer_device *const device); - -/** - * \brief Set timer period - * - * \param[in] device The pointer to timer device instance - */ -void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); - -/** - * \brief Retrieve timer period - * - * \param[in] device The pointer to timer device instance - * - * \return Timer period - */ -uint32_t _timer_get_period(const struct _timer_device *const device); - -/** - * \brief Check if timer is running - * - * \param[in] device The pointer to timer device instance - * - * \return Check status. - * \retval true The given timer is running - * \retval false The given timer is not running - */ -bool _timer_is_started(const struct _timer_device *const device); - -/** - * \brief Set timer IRQ - * - * \param[in] device The pointer to timer device instance - */ -void _timer_set_irq(struct _timer_device *const device); - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usart.h b/atmel-samd/asf4/samd51/hal/include/hpl_usart.h deleted file mode 100644 index f6235de93..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_usart.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USART_H_INCLUDED -#define _HPL_USART_H_INCLUDED - -/** - * \addtogroup HPL USART SYNC - * - * \section hpl_usart_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART flow control state - */ -union usart_flow_control_state { - struct { - uint8_t cts : 1; - uint8_t rts : 1; - uint8_t unavailable : 1; - uint8_t reserved : 5; - } bit; - uint8_t value; -}; - -/** - * \brief USART baud rate mode - */ -enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; - -/** - * \brief USART data order - */ -enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; - -/** - * \brief USART mode - */ -enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; - -/** - * \brief USART parity - */ -enum usart_parity { - USART_PARITY_EVEN = 0, - USART_PARITY_ODD = 1, - USART_PARITY_NONE = 2, - USART_PARITY_SPACE = 3, - USART_PARITY_MARK = 4 -}; - -/** - * \brief USART stop bits mode - */ -enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; - -/** - * \brief USART character size - */ -enum usart_character_size { - USART_CHARACTER_SIZE_8BITS = 0, - USART_CHARACTER_SIZE_9BITS = 1, - USART_CHARACTER_SIZE_5BITS = 5, - USART_CHARACTER_SIZE_6BITS = 6, - USART_CHARACTER_SIZE_7BITS = 7 -}; - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usart_async.h b/atmel-samd/asf4/samd51/hal/include/hpl_usart_async.h deleted file mode 100644 index 1bcb3da44..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_usart_async.h +++ /dev/null @@ -1,280 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USART_ASYNC_H_INCLUDED -#define _HPL_USART_ASYNC_H_INCLUDED - -/** - * \addtogroup HPL USART - * - * \section hpl_usart_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include "hpl_usart.h" -#include "hpl_irq.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART callback types - */ -enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; - -/** - * \brief USART device structure - * - * The USART device structure forward declaration. - */ -struct _usart_async_device; - -/** - * \brief USART interrupt callbacks - */ -struct _usart_async_callbacks { - void (*tx_byte_sent)(struct _usart_async_device *device); - void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); - void (*tx_done_cb)(struct _usart_async_device *device); - void (*error_cb)(struct _usart_async_device *device); -}; - -/** - * \brief USART descriptor device structure - */ -struct _usart_async_device { - struct _usart_async_callbacks usart_cb; - struct _irq_descriptor irq; - void * hw; -}; -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize asynchronous USART - * - * This function does low level USART configuration. - * - * \param[in] device The pointer to USART device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); - -/** - * \brief Deinitialize USART - * - * This function closes the given USART by disabling its clock. - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_deinit(struct _usart_async_device *const device); - -/** - * \brief Enable usart module - * - * This function will enable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable(struct _usart_async_device *const device); - -/** - * \brief Disable usart module - * - * This function will disable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_disable(struct _usart_async_device *const device); - -/** - * \brief Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); - -/** - * \brief Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); - -/** - * \brief Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); - -/** - * \brief Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); - -/** - * \brief Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); - -/** - * \brief Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); - -/** - * \brief Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); - -/** - * \brief Retrieve usart status - * - * \param[in] device The pointer to USART device instance - */ -uint32_t _usart_async_get_status(const struct _usart_async_device *const device); - -/** - * \brief Write a byte to the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - */ -void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); - -/** - * \brief Check if USART is ready to send next byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART is ready to send next byte - * \retval false if the USART is not ready to send next byte - */ -bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); - -/** - * \brief Set the state of flow control pins - * - * \param[in] device The pointer to USART device instance - * \param[in] state - A state of flow control pins to set - */ -void _usart_async_set_flow_control_state(struct _usart_async_device *const device, - const union usart_flow_control_state state); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins. - * - * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. - */ -union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); - -/** - * \brief Enable data register empty interrupt - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); - -/** - * \brief Enable transmission complete interrupt - * - * \param[in] device The pointer to USART device instance - */ -void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); - -/** - * \brief Retrieve ordinal number of the given USART hardware instance - * - * \param[in] device The pointer to USART device instance - * - * \return The ordinal number of the given USART hardware instance - */ -uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); - -/** - * \brief Enable/disable USART interrupt - * - * param[in] device The pointer to USART device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, - const bool state); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usart_sync.h b/atmel-samd/asf4/samd51/hal/include/hpl_usart_sync.h deleted file mode 100644 index c7881583c..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_usart_sync.h +++ /dev/null @@ -1,253 +0,0 @@ -/** - * \file - * - * \brief USART related functionality declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_SYNC_USART_H_INCLUDED -#define _HPL_SYNC_USART_H_INCLUDED - -/** - * \addtogroup HPL USART SYNC - * - * \section hpl_usart_sync_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief USART descriptor device structure - */ -struct _usart_sync_device { - void *hw; -}; - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Initialize synchronous USART - * - * This function does low level USART configuration. - * - * \param[in] device The pointer to USART device instance - * \param[in] hw The pointer to hardware instance - * - * \return Initialization status - */ -int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); - -/** - * \brief Deinitialize USART - * - * This function closes the given USART by disabling its clock. - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_deinit(struct _usart_sync_device *const device); - -/** - * \brief Enable usart module - * - * This function will enable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_enable(struct _usart_sync_device *const device); - -/** - * \brief Disable usart module - * - * This function will disable the usart module - * - * \param[in] device The pointer to USART device instance - */ -void _usart_sync_disable(struct _usart_sync_device *const device); - -/** - * \brief Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); - -/** - * \brief Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); - -/** - * \brief Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); - -/** - * \brief Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); - -/** - * \brief Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); - -/** - * \brief Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); - -/** - * \brief Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); - -/** - * \brief Retrieve usart status - * - * \param[in] device The pointer to USART device instance - */ -uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); - -/** - * \brief Write a byte to the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - */ -void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); - -/** - * \brief Read a byte from the given USART instance - * - * \param[in] device The pointer to USART device instance - * \param[in] data Data to write - * - * \return Data received via USART interface. - */ -uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); - -/** - * \brief Check if USART is ready to send next byte - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the ready check. - * \retval true if the USART is ready to send next byte - * \retval false if the USART is not ready to send next byte - */ -bool _usart_sync_is_byte_sent(const struct _usart_sync_device *const device); - -/** - * \brief Check if there is data received by USART - * - * \param[in] device The pointer to USART device instance - * - * \return Status of the data received check. - * \retval true if the USART has received a byte - * \retval false if the USART has not received a byte - */ -bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); - -/** - * \brief Set the state of flow control pins - * - * \param[in] device The pointer to USART device instance - * \param[in] state - A state of flow control pins to set - */ -void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, - const union usart_flow_control_state state); - -/** - * \brief Retrieve the state of flow control pins - * - * This function retrieves the of flow control pins. - * - * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. - */ -union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); - -/** - * \brief Retrieve ordinal number of the given USART hardware instance - * - * \param[in] device The pointer to USART device instance - * - * \return The ordinal number of the given USART hardware instance - */ -uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usb.h b/atmel-samd/asf4/samd51/hal/include/hpl_usb.h deleted file mode 100644 index d31bd9785..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_usb.h +++ /dev/null @@ -1,281 +0,0 @@ -/** - * \file - * - * \brief SAM USB HPL - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USB_H_INCLUDED -#define _HPL_USB_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** \name USB Spec definitions */ -/*@{*/ - -/** Return 8-bit unsigned USB data. */ -#define USB_GET_U8(addr, offset) (((uint8_t *)(addr))[(offset)]) - -/** Return 16-bit unsigned USB data. */ -#define USB_GET_U16(addr, offset) ((((uint8_t *)(addr))[(offset) + 0] << 0) + (((uint8_t *)(addr))[(offset) + 1] << 8)) - -/** Return 32-bit unsigned USB data. */ -#define USB_GET_U32(addr, offset) \ - ((((uint8_t *)(addr))[(offset) + 0] << 0) + (((uint8_t *)(addr))[(offset) + 1] << 8) \ - + (((uint8_t *)(addr))[(offset) + 2] << 16) \ - + (((uint8_t *)(addr))[(offset) + 3] << 32)) - -/** Offset of bmRequestType in USB request buffer. */ -#define USB_bmRequestType_Offset 0 - -/** Offset of bRequest in USB request buffer. */ -#define USB_bRequest_Offset 1 - -/** Offset of wValue in USB request buffer. */ -#define USB_wValue_Offset 2 - -/** Offset of wIndex in USB request buffer. */ -#define USB_wIndex_Offset 4 - -/** Offset of wLength in USB request buffer. */ -#define USB_wLength_Offset 6 - -/** Get value of bmRequestType from USB request. */ -#define USB_GET_bmRequestType(req) USB_GET_U8((req), USB_bmRequestType_Offset) - -/** Get value of bRequest from USB request. */ -#define USB_GET_bRequest(req) USB_GET_U8((req), USB_bRequest_Offset) - -/** Get value of wValue from USB request. */ -#define USB_GET_wValue(req) USB_GET_U16((req), USB_wValue_Offset) - -/** Get value of wIndex from USB request. */ -#define USB_GET_wIndex(req) USB_GET_U16((req), USB_wIndex_Offset) - -/** Get value of wLength from USB request. */ -#define USB_GET_wLength(req) USB_GET_U16((req), USB_wLength_Offset) - -/** USB request IN indication of bmRequestType. */ -#define USB_REQ_TYPE_IN 0x80u - -/** USB endpoint number mask of bEndpointAddress. */ -#define USB_EP_N_MASK 0x0Fu - -/** USB endpoint direction bit of bEndpointAddress. */ -#define USB_EP_DIR 0x80u - -/** Get USB endpoint direction from endpoint address. */ -#define USB_EP_GET_DIR(ep_addr) ((ep_addr)&USB_EP_DIR) - -/** Get USB endpoint number from endpoint address. */ -#define USB_EP_GET_N(ep_addr) ((ep_addr)&USB_EP_N_MASK) - -/** Transfer type in EP descriptor bmAttributes: Control. */ -#define USB_EP_XTYPE_CTRL 0x0 - -/** Transfer type in EP descriptor bmAttributes: Isochronous. */ -#define USB_EP_XTYPE_ISOCH 0x1 - -/** Transfer type in EP descriptor bmAttributes: Bulk. */ -#define USB_EP_XTYPE_BULK 0x2 - -/** Transfer type in EP descriptor bmAttributes: Interrupt. */ -#define USB_EP_XTYPE_INTERRUPT 0x3 - -/** Transfer type mask in EP descriptor bmAttributes. */ -#define USB_EP_XTYPE_MASK 0x3u - -/*@}*/ - -/** \name USB status codes - *@{ - */ -/** USB operation is done successfully. */ -#define USB_OK 0 -/** USB (endpoint) is busy. */ -#define USB_BUSY 1 -/** USB (endpoint) is halted. */ -#define USB_HALTED 2 - -/** General error. */ -#define USB_ERROR 0x10 -/** Operation is denied by hardware (e.g., syncing). */ -#define USB_ERR_DENIED 0x11 -/** Input parameter error. */ -#define USB_ERR_PARAM 0x12 -/** Functionality is not supported (e.g., initialize endpoint without cache to be control). */ -#define USB_ERR_FUNC 0x13 -/** Re-initialize, re-enable ... */ -#define USB_ERR_REDO 0x14 -/** Not enough resource (memory, endpoints ...). */ -#define USB_ERR_ALLOC_FAIL 0x15 -/*@}*/ - -/** USB speed. */ -enum usb_speed { - /** USB Low Speed. */ - USB_SPEED_LS, - /** USB Full Speed. */ - USB_SPEED_FS, - /** USB High Speed. */ - USB_SPEED_HS, - /** USB Super Speed. */ - USB_SPEED_SS -}; - -/** USB transaction type. */ -enum usb_trans_type { - /** USB SETUP transaction. */ - USB_TRANS_SETUP, - /** USB IN transaction. */ - USB_TRANS_IN, - /** USB OUT transaction. */ - USB_TRANS_OUT -}; - -/** USB events that generates the device callbacks. */ -enum usb_event { - /** USB VBus changed, with parameter as present/not present. */ - USB_EV_VBUS, - /** USB RESET detected on bus. */ - USB_EV_RESET, - /** USB wakeup. */ - USB_EV_WAKEUP, - /** USB LPM suspend, with parameter as \ref usb_lpm_attributes. */ - USB_EV_LPM_SUSPEND, - /** USB suspend. */ - USB_EV_SUSPEND, - /** USB error, with parameter as error code. */ - USB_EV_ERROR, - /** Number of USB event types. */ - USB_EV_N -}; - -/** Control action for USB device endpoint stall. */ -enum usb_ep_stall_ctrl { - /** Clear stall of the endpoint. */ - USB_EP_STALL_CLR, - /** Stall the endpoint. */ - USB_EP_STALL_SET, - /** Return the stall status. */ - USB_EP_STALL_GET -}; - -/** Control action for USB device endpoint halt. */ -enum usb_ep_halt_ctrl { - /** Clear halt of the endpoint. */ - USB_EP_HALT_CLR = USB_EP_STALL_CLR, - /** Stall the endpoint. */ - USB_EP_HALT_SET = USB_EP_STALL_SET, - /** Return the halt status. */ - USB_EP_HALT_GET = USB_EP_STALL_GET -}; - -/** USB transactions status codes. */ -enum usb_trans_code { - /** TX or RX has been done without error. */ - USB_TRANS_DONE, - /** The endpoint is stalled. */ - USB_TRANS_STALL, - /** The endpoint transactions are aborted (cancel, control setup/status). */ - USB_TRANS_ABORT, - /** The endpoint transactions are aborted by reset/disable. */ - USB_TRANS_RESET, - /** Error is reported on the endpoint. */ - USB_TRANS_ERROR -}; - -/** Transfer status codes. */ -enum usb_xfer_code { - /** Transfer is done without error, for ctrl it means status packet done. */ - USB_XFER_DONE, - /** For control transfer only, data stage is done without error. */ - USB_XFER_DATA, - /** Endpoint stall is set. */ - USB_XFER_HALT, - /** Endpoint stall is cleared. */ - USB_XFER_UNHALT, - /** Transfer is aborted. */ - USB_XFER_ABORT, - /** Transfer is aborted because endpoint reset/disable. */ - USB_XFER_RESET, - /** There was an error. */ - USB_XFER_ERROR -}; - -/** USB endpoint errors. */ -enum usb_ep_error { - /** No error. */ - USB_EP_NO_ERROR, - /** CRC error. */ - USB_EP_ERR_CRC, - /** Endpoint transfer overflow. */ - USB_EP_ERR_OVERFLOW, - /** Other endpoint errors. */ - USB_EP_ERR_GENERAL -}; - -/** Endpoint transfer state. */ -enum usb_ep_state { - /** Endpoint is disabled. */ - USB_EP_S_DISABLED, - /** Endpoint is not busy. */ - USB_EP_S_IDLE, - /** Control transfer only, endpoint is transferring setup packet. */ - USB_EP_S_X_SETUP, - /** Endpoint is transferring data. */ - USB_EP_S_X_DATA, - /** Control transfer only, endpoint is in status stage. */ - USB_EP_S_X_STATUS, - /** Endpoint is halted. */ - USB_EP_S_HALTED, - /** Endpoint error. */ - USB_EP_S_ERROR -}; - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_USB_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usb_device.h b/atmel-samd/asf4/samd51/hal/include/hpl_usb_device.h deleted file mode 100644 index 640833f45..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_usb_device.h +++ /dev/null @@ -1,387 +0,0 @@ -/** - * \file - * - * \brief SAM USB HPL - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USB_DEVICE_H_INCLUDED -#define _HPL_USB_DEVICE_H_INCLUDED - -#include -#include "hpl_usb_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** USB Device callback type. */ -enum usb_d_cb_type { - /** USB device SOF callback. */ - USB_D_CB_SOF, - /** USB device events callbacks. */ - USB_D_CB_EVENT, - /** Number of types of USB device callback types. */ - USB_D_CB_N -}; - -/** USB Device endpoint callback type. */ -enum usb_d_ep_cb_type { - /** USB device endpoint setup callback. */ - USB_D_EP_CB_SETUP, - /** USB device endpoint more data callback. */ - USB_D_EP_CB_MORE, - /** USB device endpoint transaction done or error callback. */ - USB_D_EP_CB_XFER, - /** Number of types of USB device endpoint callback types. */ - USB_D_EP_CB_N -}; - -/** Control action for USB device LPM handshake. */ -enum usb_d_lpm_ctrl { - /** No LPM handshake, not supported. */ - USB_D_LPM_DISABLE, - /** ACK the LPM transaction. */ - USB_D_LPM_ACK, - /** NYET the LPM transaction. */ - USB_D_LPM_NYET -}; - -/** - * USB device transfer descriptor. - */ -struct usb_d_transfer { - /** Pointer to data buffer to transfer. - * Note that it's recommended that the buffer is 32-bit aligned since - * some of USB peripheral require this. - */ - uint8_t *buf; - /** Transfer size, in number of bytes. - * Note that it's recommended that the buffer size is 32-bit aligned - * (modeled by 4) since some of USB peripheral require this. - */ - uint32_t size; - /** Endpoint address. */ - uint8_t ep; - /** Append ZLP for IN transfer, wait ZLP for OUT transfer. */ - uint8_t zlp; -}; - -/** USB device transactions status structure. */ -struct usb_d_trans_status { - /** Total data size. */ - uint32_t size; - /** Total transfered data count. */ - uint32_t count; - /** Endpoint address. */ - uint8_t ep; - /** Endpoint type - CTRL/ISO/INT/BULK. */ - uint8_t xtype : 2; - /** Transactions state, busy or not. */ - uint8_t busy : 1; - /** Transactions state, setup received or not. */ - uint8_t setup : 1; - /** Transactions state, stall or not. */ - uint8_t stall : 1; - /** Transactions direction. */ - uint8_t dir : 1; -}; - -/** Prototype function for callback that is invoked on USB device SOF. */ -typedef void (*_usb_d_dev_sof_cb_t)(void); - -/** Prototype function for callback that is invoked on USB device events. */ -typedef void (*_usb_d_dev_event_cb_t)(const enum usb_event, const uint32_t param); - -/** HPL USB device callbacks. */ -struct _usb_d_dev_callbacks { - /** Callback that is invoked on SOF. */ - _usb_d_dev_sof_cb_t sof; - /** Callback that is invoked on USB RESET/WAKEUP/RESUME/SUSPEND. */ - _usb_d_dev_event_cb_t event; -}; - -/** USB device endpoint callbacks. */ -enum usb_d_dev_ep_cb_type { - /** Setup packet is received. */ - USB_D_DEV_EP_CB_SETUP, - /** Try to require more data. */ - USB_D_DEV_EP_CB_MORE, - /** Transaction done OK/ERROR. */ - USB_D_DEV_EP_CB_DONE, - /** Number of device endpoint callbacks. */ - USB_D_DEV_EP_CB_N -}; - -/** - * Callback that is invoked when control SETUP packet has bee received. - * \ref _usb_d_dev_ep_read_req() must be invoked to read setup data, and allow - * IN/OUT transactions on control endpoint. - */ -typedef void (*_usb_d_dev_ep_cb_setup_t)(const uint8_t ep); - -/** Callback that is invoked when buffer is done, but last packet is full size - * packet without ZLP. Return \c true if more data has been requested. */ -typedef bool (*_usb_d_dev_ep_cb_more_t)(const uint8_t ep, const uint32_t transfered); - -/** Callback that is invoked when all data is finished, including background - * transfer, or error happens. */ -typedef void (*_usb_d_dev_ep_cb_done_t)(const uint8_t ep, const int32_t code, const uint32_t transfered); - -/** Callbacks for HPL USB device endpoint. */ -struct _usb_d_dev_ep_callbacks { - /** Callback that is invoked when SETUP packet is received. - * \ref _usb_d_dev_ep_read_req() must be invoked to read setup data, and - * allow IN/OUT transactions on control endpoint. - */ - _usb_d_dev_ep_cb_setup_t setup; - /** Callback that is invoked to check if buffer is NULL and more data is - * required. - * It's called when last packet is full size packet, without - * auto ZLP enabled. - * It could be called when background transfer is still in progress. - */ - _usb_d_dev_ep_cb_more_t more; - /** Callback that is invoked when transaction is done, including background - * transfer, or error occurs. - */ - _usb_d_dev_ep_cb_done_t done; -}; - -/** - * \brief Initialize the USB device instance - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_init(void); - -/** - * \brief Deinitialize the USB device instance - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -void _usb_d_dev_deinit(void); - -/** - * \brief Register callback to handle USB device events - * \param[in] type Callback type. See \ref usb_d_cb_type. - * \param[in] func Pointer to callback function. - * Refer to \ref _usb_d_dev_callbacks for the prototypes. - */ -void _usb_d_dev_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func); - -/** - * \brief Register callback to handle USB device endpoint events - * \param[in] type Callback type. See \ref usb_d_dev_ep_cb_type. - * \param[in] func Pointer to callback function. - * Refer to \ref _usb_d_dev_ep_callbacks for the prototypes. - */ -void _usb_d_dev_register_ep_callback(const enum usb_d_dev_ep_cb_type type, const FUNC_PTR func); - -/** - * \brief Enable the USB device - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_enable(void); - -/** - * \brief Disable the USB device - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_disable(void); - -/** - * \brief Attach the USB device - */ -void _usb_d_dev_attach(void); - -/** - * \brief Detach the USB device - */ -void _usb_d_dev_detach(void); - -/** - * \brief Send the USB device remote wakeup to host - */ -void _usb_d_dev_send_remotewakeup(void); - -/** - * \brief Get the USB device working speed - * \return USB speed. See \ref usb_speed. - */ -enum usb_speed _usb_d_dev_get_speed(void); - -/** - * \brief Set the USB device address - * \param[in] addr Address to be used. - */ -void _usb_d_dev_set_address(const uint8_t addr); - -/** - * \brief Get the USB device address - * \return Address that is used. - */ -uint8_t _usb_d_dev_get_address(void); - -/** - * \brief Get the USB device frame number - * \return The frame number. - */ -uint16_t _usb_d_dev_get_frame_n(void); - -/** - * \brief Get the USB device micro frame number - * \return The micro frame number inside one frame (0~7). - */ -uint8_t _usb_d_dev_get_uframe_n(void); - -/** - * \brief Initialize and enable the USB device default endpoint 0 - * \param[in] max_pkt_siz Max endpoint size. - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_ep0_init(const uint8_t max_pkt_siz); - -/** - * \brief Initialize and enable the USB device endpoint - * \param[in] ep Endpoint address, - * see endpoint descriptor details in USB spec. - * \param[in] attr Endpoint attributes, - * see endpoint descriptor details in USB spec. - * \param[in] max_pkt_siz Endpoint size, - * see endpoint descriptor details in USB spec. - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_ep_init(const uint8_t ep, const uint8_t attr, uint16_t max_pkt_siz); - -/** - * \brief Disable and deinitialize the USB device endpoint - - * \param[in] ep The endpoint to deinitialize. - */ -void _usb_d_dev_ep_deinit(const uint8_t ep); - -/** - * \brief Enable the endpoint - * \param[in] ep The endpoint to enable. - * \return Operation result status. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_ep_enable(const uint8_t ep); - -/** - * \brief Disable the endpoint - * \param[in] ep The endpoint to disable. - */ -void _usb_d_dev_ep_disable(const uint8_t ep); - -/** - * \brief Set/Clear/Get USB device endpoint stall status - * \param[in] ep Endpoint address. - * \param[in] ctrl Operation selector. See \ref usb_ep_stall_ctrl. - * \return Operation result or stall status. - * \retval 0 Success or not stall. - * \retval 1 Endpoint is stalled. - * \retval -1 error. - */ -int32_t _usb_d_dev_ep_stall(const uint8_t ep, const enum usb_ep_stall_ctrl ctrl); - -/** - * \brief Read setup request data from specific endpoint - * \param[in] ep Endpoint address. - * \param[out] req_buf Pointer to buffer to locate the setup packet. - * \return Number of bytes or error code. - * \retval <0 error code. - * \retval 0 No setup packet ready for read. - * \retval >0 Size of bytes read, and ready to start IN/OUT. Note that if - * this number is over 8, only first 8 bytes will be copied. - */ -int32_t _usb_d_dev_ep_read_req(const uint8_t ep, uint8_t *req_buf); - -/** - * \brief Start USB device transfer - * - * On different USB peripheral hardware the transaction buffer address and size - * may have different constraints. E.g., some hardware may require input address - * 32-bit aligned, and input size 32-bit aligned. Refer to the corresponding - * hardware usage reference documents. - * The constraints are checked in implementation, with error code returned. - * - * \param[in] trans Pointer to the transaction description. - * \return Operation result status. - * \retval 1 Busy. - * \retval 0 Success. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_ep_trans(const struct usb_d_transfer *trans); - -/** - * \brief Abort pending USB device transaction on specific endpoint - * \param[in] ep Endpoint address to abort. - */ -void _usb_d_dev_ep_abort(const uint8_t ep); - -/** - * \brief Retrieve endpoint status. - * \param[in] ep Endpoint address. - * \param[out] stat Pointer to buffer to fill status description. - * \return Status. - * \retval 2 Packet writing. - * \retval 1 Busy. - * \retval 0 Ready. - * \retval <0 Error code. - */ -int32_t _usb_d_dev_ep_get_status(const uint8_t ep, struct usb_d_trans_status *stat); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_USB_DEVICE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_usb_host.h b/atmel-samd/asf4/samd51/hal/include/hpl_usb_host.h deleted file mode 100644 index ee48ecc3a..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_usb_host.h +++ /dev/null @@ -1,628 +0,0 @@ -/** - * \file - * - * \brief SAM USB host HPL - * - * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USB_HOST_H_INCLUDED -#define _HPL_USB_HOST_H_INCLUDED - -#include -#include -#include "hpl_usb_config.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** Driver version */ -#define USB_H_VERSION 0x00000001 - -/** - * @brief USB HCD callback types - */ -enum usb_h_cb_type { - /** SOF generated */ - USB_H_CB_SOF, - /** Root Hub change detected */ - USB_H_CB_ROOTHUB_CHANGE, - /** Number of USB HCD callback types */ - USB_H_CB_N -}; - -/** - * @brief USB HCD resource strategy - */ -enum usb_h_rsc_strategy { - /** Normal resource allocation, e.g., - * 1 bank for interrupt endpoint, - * 2 bank for bulk endpoint and normal iso endpoint, - * 3 bank for iso high bandwidth endpoint. - */ - USB_H_RSC_NORMAL = false, - /** Minimal resource allocation, e.g., only 1 bank for bulk endpoints */ - USB_H_RSC_MINIMAL = true -}; - -/** - * @brief USB HCD pipe states - */ -enum usb_h_pipe_state { - /** Pipe is free to allocate */ - USB_H_PIPE_S_FREE = 0x00, - /** Pipe is in configuration */ - USB_H_PIPE_S_CFG = 0x01, - /** Pipe is allocated and idle */ - USB_H_PIPE_S_IDLE = 0x02, - /** Pipe in control setup stage */ - USB_H_PIPE_S_SETUP = 0x03, - /** Pipe in data IN stage */ - USB_H_PIPE_S_DATI = 0x05, - /** Pipe in data OUT stage */ - USB_H_PIPE_S_DATO = 0x06, - /** Pipe in data IN ZLP stage */ - USB_H_PIPE_S_ZLPI = 0x07, - /** Pipe in data OUT ZLP stage */ - USB_H_PIPE_S_ZLPO = 0x08, - /** Pipe in control status IN stage */ - USB_H_PIPE_S_STATI = 0x09, - /** Pipe in control status OUT stage */ - USB_H_PIPE_S_STATO = 0x0A, - /** Taken by physical pipe (in process) */ - USB_H_PIPE_S_TAKEN = 0x10 -}; - -/** - * @brief USB HCD status code - */ -enum usb_h_status { - /** OK */ - USB_H_OK = ERR_NONE, - /** Busy */ - USB_H_BUSY = ERR_BUSY, - /** Denied */ - USB_H_DENIED = ERR_DENIED, - /** Timeout */ - USB_H_TIMEOUT = ERR_TIMEOUT, - /** Abort */ - USB_H_ABORT = ERR_ABORTED, - /** Stall protocol */ - USB_H_STALL = ERR_PROTOCOL, - /** Transfer reset by pipe re-configure */ - USB_H_RESET = ERR_REQ_FLUSHED, - /** Argument error */ - USB_H_ERR_ARG = ERR_INVALID_ARG, - /** Operation not supported */ - USB_H_ERR_UNSP_OP = ERR_UNSUPPORTED_OP, - /** No resource */ - USB_H_ERR_NO_RSC = ERR_NO_RESOURCE, - /** Not initialized */ - USB_H_ERR_NOT_INIT = ERR_NOT_INITIALIZED, - /** Some general error */ - USB_H_ERR = ERR_IO -}; - -/** Forward declare for pipe structure */ -struct usb_h_pipe; - -/** Forward declare for driver descriptor structure */ -struct usb_h_desc; - -/** - * \brief Prototyping USB HCD callback of SOF - */ -typedef void (*usb_h_cb_sof_t)(struct usb_h_desc *drv); - -/** - * \brief Prototyping USB HCD callback of root hub changing. - * According to the bitmap size, max port number is 31. - */ -typedef void (*usb_h_cb_roothub_t)(struct usb_h_desc *drv, uint8_t port, uint8_t ftr); - -/** - * Prototyping USB HCD callback of pipe transfer done. - * For control pipe, it's forced to call even if there is no transfer - * in progress, since the pipe size could be changed at run time. - */ -typedef void (*usb_h_pipe_cb_xfer_t)(struct usb_h_pipe *pipe); - -/** Access to max packet size of a pipe */ -#define usb_h_pipe_max_pkt_size(p) (p->max_pkt_size) - -/** Access to device address of a pipe */ -#define usb_h_pipe_dev_addr(p) (p->dev) - -/** Access to endpoint address of a pipe */ -#define usb_h_pipe_ep_addr(p) (p->ep) - -/** Access to state of a pipe */ -#define usb_h_pipe_state(p) (p->x.general.state) - -/** Access to status of a pipe */ -#define usb_h_pipe_status(p) (p->x.general.status) - -/** - * @brief USB Host Controller device structure - */ -struct usb_h_desc { - /** Pointer to hardware base */ - void *hw; - /** Pointer to private data for Host Controller driver */ - void *prvt; - /** Interrupt handling descriptor */ - struct _irq_descriptor irq; - /** Callback of SOF */ - usb_h_cb_sof_t sof_cb; - /** Callback of root hub change */ - usb_h_cb_roothub_t rh_cb; -#if CONF_USB_H_INST_OWNER_SP - /** Extension for the driver owner (upper layer user) */ - void *owner; -#endif -}; - -/** - * @brief Transfer descriptor for control transfer - * - * Timing in USB 2.0 spec.: - * - 9.2.6.1 : USB sets an upper limit of 5 seconds as the upper limit for any - * command to be processed. - * - 9.2.6.3 : if a device receives a SetAddress() request, the device must be - * able to complete processing of the request and be able to - * successfully complete the Status stage of the request within - * 50 ms. - * After successful completion of the Status stage, the device is - * allowed a SetAddress() recovery interval of 2 ms. At the end of - * this interval, the device must be able to accept Setup packets - * addressed to the new address. - * - 9.2.6.4 : For standard device requests that require no Data stage, a device - * must be able to complete the request and be able to successfully - * complete the Status stage of the request within 50 ms of receipt - * of the request. This limitation applies to requests to the - * device, interface, or endpoint. - * For standard device requests that require data stage transfer to - * the host, the device must be able to return the first data packet - * to the host within 500 ms of receipt of the request. For - * subsequent data packets, if any, the device must be able to - * return them within 500 ms of successful completion of the - * transmission of the previous packet. The device must then be - * able to successfully complete the status stage within 50 ms after - * returning the last data packet. - * For standard device requests that require a data stage transfer - * to the device, the 5-second limit applies. - * - 9.2.6.5 : Unless specifically exempted in the class document, all - * class-specific requests must meet the timing limitations for - * standard device requests. - * - * Conclusion: - * 1. Whole request with data: 5 seconds - * 2. Whole request without data: 50 ms - * 3. Data packets: 500 ms - */ -struct usb_h_ctrl_xfer { - /** Pointer to transfer data */ - uint8_t *data; - /** Pointer to setup packet */ - uint8_t *setup; - /** Expected transfer size */ - uint16_t size; - /** Transfer count */ - uint16_t count; - /** Timeout for request, -1 if disable timeout */ - int16_t req_timeout; - /** Timeout between packets - * (500ms for data and 50ms for status), -1 if disabled */ - int16_t pkt_timeout; - /** Packet size during transfer (<= allocate max packet size) */ - uint16_t pkt_size; - - /** Transfer state */ - uint8_t state; - /** Last transfer status */ - int8_t status; -}; - -/** - * @brief Transfer descriptor for bulk / interrupt / iso transfer - */ -struct usb_h_bulk_int_iso_xfer { - /** Expected transfer size */ - uint32_t size; - /** Transfer count */ - uint32_t count; - /** Pointer to transfer data */ - uint8_t *data; - /** Reserved */ - uint16_t reserved[3]; - - /** Transfer state */ - uint8_t state; - /** Last transfer status */ - int8_t status; -}; - -/** - * @brief Transfer descriptor for periodic high bandwidth transfer - */ -struct usb_h_high_bw_xfer { - /** Expected transfer size */ - uint32_t size; - /** Transfer count */ - uint32_t count; - /** Pointer to transfer data */ - uint8_t *data; - /** Micro frame packet sizes */ - uint16_t pkt_size[3]; - - /** Transfer state */ - uint8_t state; - /** Last transfer status */ - int8_t status; -}; - -/** - * @brief General transfer descriptor - */ -struct usb_h_xfer { - /** Reserved for different transfer */ - union { - uint16_t u16[9]; - uint8_t u8[18]; - } reserved; - /** Transfer state */ - uint8_t state; - /** Last transfer status */ - int8_t status; -}; - -/** - * @brief USB Host Controller Driver Pipe structure - */ -struct usb_h_pipe { - /** Pointer to the USB Host Controller Driver */ - struct usb_h_desc *hcd; - /** Pointer to the callback for transfer done */ - usb_h_pipe_cb_xfer_t done; -#if CONF_USB_H_INST_OWNER_SP - /** Pointer to the pipe owner */ - void *owner; -#endif - - /** Endpoint max packet size (bits 10..0) */ - uint16_t max_pkt_size; - /** Device address */ - uint8_t dev; - /** Endpoint address */ - uint8_t ep; - - /** Endpoint interval */ - uint8_t interval; - /** Endpoint type: Control, Isochronous, Bulk or Interrupt */ - uint8_t type; - /** Current toggle (driver dependent) */ - uint8_t toggle; - /** Endpoint number of banks (HW dependent) */ - uint8_t bank : 2; - /** Transfer speed (HW dependent) */ - uint8_t speed : 2; - /** High bandwidth periodic out */ - uint8_t high_bw_out : 1; - /** Uses DMA (on transfer) */ - uint8_t dma : 1; - /** Transfer ZLP support */ - uint8_t zlp : 1; - /** Transfer periodic */ - uint8_t periodic_start : 1; - - /** Transfer status */ - union { - /** General transfer info */ - struct usb_h_xfer general; - /** Control transfer status */ - struct usb_h_ctrl_xfer ctrl; - /** Bulk interrupt iso transfer status */ - struct usb_h_bulk_int_iso_xfer bii; - /** Periodic high bandwidth transfer status */ - struct usb_h_high_bw_xfer hbw; - } x; -}; - -/** - * @brief USB HCD Initialization - * - * @param drv Pointer to the HCD driver instance - * @param[in] hw Pointer to hardware base - * @param[in] prvt The private driver data (implement specific) - * - * @return Operation result status - * @retval ERR_DENIED Hardware has been enabled - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_init(struct usb_h_desc *drv, void *hw, void *prvt); - -/** - * @brief USB HCD de-initialization - * - * @param drv The driver - */ -void _usb_h_deinit(struct usb_h_desc *drv); - -/** - * @brief USB HCD enable - * - * @param drv The driver - */ -void _usb_h_enable(struct usb_h_desc *drv); - -/** - * @brief USB HCD disable - * - * @param drv The driver - */ -void _usb_h_disable(struct usb_h_desc *drv); - -/** - * @brief Register callbacks for USB HCD - * - * @param drv The driver - * @param[in] type The callback type - * @param[in] cb The callback function entry - * - * @return Operation result status - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_register_callback(struct usb_h_desc *drv, enum usb_h_cb_type type, FUNC_PTR cb); - -/** - * @brief Return current frame number - * - * @param drv The driver - * - * @return current frame number - */ -uint16_t _usb_h_get_frame_n(struct usb_h_desc *drv); - -/** - * @brief Return current micro frame number - * - * @param drv The driver - * - * @return current micro frame number - */ -uint8_t _usb_h_get_microframe_n(struct usb_h_desc *drv); - -/** - * @brief Suspend the USB bus - * - * @param drv The driver - */ -void _usb_h_suspend(struct usb_h_desc *drv); - -/** - * @brief Resume the USB bus - * - * @param drv The driver - */ -void _usb_h_resume(struct usb_h_desc *drv); - -/* Root hub related APIs */ - -/** - * \brief Reset the root hub port - * - * \param[in,out] drv Pointer to the USB HCD driver - * \param[in] port Root hub port, ignored if there is only one port - */ -void _usb_h_rh_reset(struct usb_h_desc *drv, uint8_t port); - -/** - * \brief Suspend the root hub port - * - * \param[in,out] drv Pointer to the USB HCD driver - * \param[in] port Root hub port, ignored if there is only one port - */ -void _usb_h_rh_suspend(struct usb_h_desc *drv, uint8_t port); - -/** - * \brief Resume the root hub port - * - * \param[in,out] drv Pointer to the USB HCD driver - * \param[in] port Root hub port, ignored if there is only one port - */ -void _usb_h_rh_resume(struct usb_h_desc *drv, uint8_t port); - -/** - * \brief Root hub or port feature status check - * - * Check USB Spec. for hub status and feature selectors. - * - * \param[in] drv Pointer to the USB HCD driver - * \param[in] port Set to 0 to get hub status, otherwise to get port status - * \param[in] ftr Hub feature/status selector - * (0: connection, 2: suspend, 4: reset, 9: LS, 10: HS) - * - * \return \c true if the status bit is 1 - */ -bool _usb_h_rh_check_status(struct usb_h_desc *drv, uint8_t port, uint8_t ftr); - -/* Pipe transfer functions */ - -/** - * @brief Allocate a pipe for USB host communication - * - * @param drv The USB HCD driver - * @param[in] dev The device address - * @param[in] ep The endpoint address - * @param[in] max_pkt_size The endpoint maximum packet size - * @param[in] attr The endpoint attribute - * @param[in] interval The endpoint interval - * (bInterval of USB Endpoint Descriptor) - * @param[in] speed The transfer speed of the endpoint - * @param[in] minimum_rsc Minimum the resource usage, \sa usb_h_rsc_strategy - * - * @return Pointer to allocated pipe structure instance - * @retval NULL allocation fail - */ -struct usb_h_pipe *_usb_h_pipe_allocate(struct usb_h_desc *drv, uint8_t dev, uint8_t ep, uint16_t max_pkt_size, - uint8_t attr, uint8_t interval, uint8_t speed, bool minimum_rsc); - -/** - * @brief Free an allocated pipe - * - * @param pipe The pipe - * - * @return Operation result status - * @retval ERR_BUSY Pipe is busy, use \ref _usb_h_pipe_abort to abort - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_pipe_free(struct usb_h_pipe *pipe); - -/** - * @brief Modify parameters of an allocated control pipe - * - * @param pipe The pipe - * @param[in] dev The device address - * @param[in] ep The endpoint address - * @param[in] max_pkt_size The maximum packet size, must be equal or - * less than allocated size - * @param[in] speed The working speed - * - * @return Operation result status - * @retval ERR_NOT_INITIALIZED Pipe is not allocated - * @retval ERR_BUSY Pipe is busy transferring - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_UNSUPPORTED_OP Pipe is not control pipe - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_pipe_set_control_param(struct usb_h_pipe *pipe, uint8_t dev, uint8_t ep, uint16_t max_pkt_size, - uint8_t speed); - -/** - * @brief Register transfer callback on a pipe - * - * @param pipe The pipe - * @param[in] cb Transfer callback function - * - * @return Operation result status - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_pipe_register_callback(struct usb_h_pipe *pipe, usb_h_pipe_cb_xfer_t cb); - -/** - * @brief Issue a control transfer (request) on a pipe - * - * \note When there is data stage, timeout between data packets is 500ms, the - * timeout between last data packet and the status packet is 50ms. - * - * @param pipe The pipe - * @param[in] setup Pointer to the setup packet - * @param[in,out] data Pointer to the data buffer - * @param[in] length The data length - * @param[in] timeout Timeout for whole request in ms - * - * @return Operation result status - * @retval ERR_NOT_INITIALIZED Pipe is not allocated - * @retval ERR_BUSY Pipe is busy transferring - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_UNSUPPORTED_OP Pipe is not control pipe - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_control_xfer(struct usb_h_pipe *pipe, uint8_t *setup, uint8_t *data, uint16_t length, int16_t timeout); - -/** - * @brief Issue a bulk / interrupt / iso transfer on a pipe - * - * @param pipe The pipe - * @param[in,out] data Pointer to the data buffer - * @param[in] length The data length - * @param[in] auto_zlp Auto append ZLP for OUT - * - * @return Operation result status - * @retval ERR_NOT_INITIALIZED Pipe is not allocated - * @retval ERR_BUSY Pipe is busy transferring - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_UNSUPPORTED_OP Pipe is control pipe - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_bulk_int_iso_xfer(struct usb_h_pipe *pipe, uint8_t *data, uint32_t length, bool auto_zlp); - -/** - * @brief Issue a periodic high bandwidth output on a pipe - * - * @param pipe The pipe - * @param[in,out] data Pointer to the data buffer - * @param[in] length The data length - * @param[in] trans_pkt_size The transaction packet sizes in a micro frame, - * 0 to use endpoint max packet size - * - * @return Operation result status - * @retval ERR_NOT_INITIALIZED Pipe is not allocated - * @retval ERR_BUSY Pipe is busy transferring - * @retval ERR_INVALID_ARG Argument error - * @retval ERR_UNSUPPORTED_OP Pipe is not high bandwidth periodic pipe, or - * DMA feature not enabled, or - * high bandwidth not enabled - * @retval ERR_NONE Operation done successfully - */ -int32_t _usb_h_high_bw_out(struct usb_h_pipe *pipe, uint8_t *data, uint32_t length, uint16_t trans_pkt_size[3]); - -/** - * @brief Check if pipe is busy transferring - * - * @param pipe The pipe - * - * @return \c true if pipe is busy - */ -bool _usb_h_pipe_is_busy(struct usb_h_pipe *pipe); - -/** - * @brief Abort pending transfer on a pipe - * - * @param pipe The pipe - */ -void _usb_h_pipe_abort(struct usb_h_pipe *pipe); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_USB_HOST_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/include/hpl_user_area.h b/atmel-samd/asf4/samd51/hal/include/hpl_user_area.h deleted file mode 100644 index b5c419bff..000000000 --- a/atmel-samd/asf4/samd51/hal/include/hpl_user_area.h +++ /dev/null @@ -1,133 +0,0 @@ -/** - * \file - * - * \brief Special user data area access - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_USER_DATA_H_INCLUDED -#define _HPL_USER_DATA_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Read data from user data area - * - * The user data area could be the area that stores user data that is not erased - * with the flash contents, e.g., - * - NVM Software Calibration Area of SAM D/L/C family - * - User Signature of SAM E/S/V 70 - * - * \param[in] base The base address of the user area - * \param[in] offset The byte offset of the data to be read inside the area - * \param[out] buf Pointer to buffer to place the read data - * \param[in] size Size of data in number of bytes - * - * \return Operation status or bytes read. - * \retval ERR_NONE Data read successfully - * \retval ERR_UNSUPPORTED_OP base address not in any supported user area - * \retval ERR_BAD_ADDRESS offset not in right area - * \retval ERR_INVALID_ARG offset and size exceeds the right area - */ -int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, const uint32_t size); - -/** - * \brief Read no more than 32 bits data from user data area - * - * When reading bits, the bitfield can cross 32-bis boundaries. - * - * \param[in] base The base address of the user area - * \param[in] bit_offset Offset in number of bits - * \param[in] n_bits Number of bits to read - * \return data read, assert if anything wrong (address not in user area - * offset, size error, etc.). - */ -uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits); - -/** - * \brief Write data to user data area - * - * The user data area could be the area that stores user data that is not erased - * with the flash contents, e.g., - * - NVM Software Calibration Area of SAM D/L/C family - * - User Signature of SAM E/S/V 70 - * - * When assigned offset and size exceeds the data area, error is reported. - * - * \param[out] base The base address of the user area - * \param[in] offset The offset of the data to be written inside the area - * \param[in] buf Pointer to buffer to place the written data - * \param[in] size Size of data in number of bytes - * - * \return Operation status or bytes writting. - * \retval ERR_NONE Data written successfully - * \retval ERR_UNSUPPORTED_OP base address not in any supported user area - * \retval ERR_DENIED Security bit is set - * \retval ERR_BAD_ADDRESS offset not in right area - * \retval ERR_INVALID_ARG offset and size exceeds the right area - */ -int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size); - -/** - * \brief Write no more than 32 bits data to user data area - * - * When writting bits, the bitfield can cross 32-bis boundaries. - * - * \param[out] base The base address of the user area - * \param[in] bit_offset Offset in number of bits - * \param[in] bits The data content - * \param[in] n_bits Number of bits to write - * \return Operation result - * \retval ERR_NONE Data written successfully - * \retval ERR_UNSUPPORTED_OP base address not in any supported user area - * \retval ERR_DENIED Security bit is set - * \retval ERR_BAD_ADDRESS offset not in right area - * \retval ERR_INVALID_ARG offset and size exceeds the right area - */ -int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits); - -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_USER_DATA_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/src/hal_adc_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_adc_sync.c deleted file mode 100644 index 9c7c3ab52..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_adc_sync.c +++ /dev/null @@ -1,254 +0,0 @@ -/** - * \file - * - * \brief ADC functionality implementation. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -/** - * \brief Indicates HAL being compiled. Must be defined before including. - */ -#define _COMPILING_HAL - -#include "hal_adc_sync.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Maximum amount of ADC interface instances - */ -#define MAX_ADC_AMOUNT ADC_INST_NUM - -/** - * \brief Initialize ADC - */ -int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func) -{ - ASSERT(descr && hw); - - return _adc_sync_init(&descr->device, hw); -} - -/** - * \brief Deinitialize ADC - */ -int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr) -{ - ASSERT(descr); - _adc_sync_deinit(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Enable ADC - */ -int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel) -{ - ASSERT(descr); - _adc_sync_enable_channel(&descr->device, channel); - - return ERR_NONE; -} - -/** - * \brief Disable ADC - */ -int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel) -{ - ASSERT(descr); - _adc_sync_disable_channel(&descr->device, channel); - return ERR_NONE; -} - -/* - * \brief Read data from ADC - */ -int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer, - const uint16_t length) -{ - uint8_t data_size; - uint16_t offset = 0; - - ASSERT(descr && buffer && length); - data_size = _adc_sync_get_data_size(&descr->device); - ASSERT(!(length % data_size)); - - do { - uint16_t result; - _adc_sync_convert(&descr->device); - - while (!_adc_sync_is_channel_conversion_done(&descr->device, channel)) - ; - - result = _adc_sync_read_channel_data(&descr->device, channel); - buffer[offset] = result; - if (1 < data_size) { - buffer[offset + 1] = result >> 8; - } - offset += data_size; - } while (offset < length); - - return offset; -} - -/** - * \brief Set ADC reference source - */ -int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference) -{ - ASSERT(descr); - _adc_sync_set_reference_source(&descr->device, reference); - - return ERR_NONE; -} - -/** - * \brief Set ADC resolution - */ -int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution) -{ - ASSERT(descr); - _adc_sync_set_resolution(&descr->device, resolution); - - return ERR_NONE; -} - -/** - * \brief Set ADC input source of a channel - */ -int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel) -{ - ASSERT(descr); - _adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel); - - return ERR_NONE; -} - -/** - * \brief Set ADC thresholds - */ -int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold) -{ - ASSERT(descr); - _adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold); - - return ERR_NONE; -} - -/** - * \brief Set ADC gain - */ -int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain) -{ - ASSERT(descr); - _adc_sync_set_channel_gain(&descr->device, channel, gain); - - return ERR_NONE; -} - -/** - * \brief Set ADC conversion mode - */ -int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode) -{ - ASSERT(descr); - _adc_sync_set_conversion_mode(&descr->device, mode); - - return ERR_NONE; -} - -/** - * \brief Set ADC differential mode - */ -int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel, - const enum adc_differential_mode mode) -{ - ASSERT(descr); - _adc_sync_set_channel_differential_mode(&descr->device, channel, mode); - - return ERR_NONE; -} - -/** - * \brief Set ADC window mode - */ -int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode) -{ - ASSERT(descr); - _adc_sync_set_window_mode(&descr->device, mode); - - return ERR_NONE; -} - -/** - * \brief Retrieve threshold state - */ -int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state) -{ - ASSERT(descr && state); - _adc_sync_get_threshold_state(&descr->device, state); - - return ERR_NONE; -} - -/** - * \brief Check if conversion is complete - */ -int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel) -{ - ASSERT(descr); - return _adc_sync_is_channel_conversion_done(&descr->device, channel); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t adc_sync_get_version(void) -{ - return DRIVER_VERSION; -} - -//@} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_atomic.c b/atmel-samd/asf4/samd51/hal/src/hal_atomic.c deleted file mode 100644 index 82a11e2bd..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_atomic.c +++ /dev/null @@ -1,76 +0,0 @@ -/** - * \file - * - * \brief Critical sections related functionality implementation. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_atomic.h" - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Disable interrupts, enter critical section - */ -void atomic_enter_critical(hal_atomic_t volatile *atomic) -{ - *atomic = __get_PRIMASK(); - __disable_irq(); - __DMB(); -} - -/** - * \brief Exit atomic section - */ -void atomic_leave_critical(hal_atomic_t volatile *atomic) -{ - __DMB(); - __set_PRIMASK(*atomic); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t atomic_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_dac_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_dac_sync.c deleted file mode 100644 index a56e6aef7..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_dac_sync.c +++ /dev/null @@ -1,141 +0,0 @@ -/** - * \file - * - * \brief DAC functionality implementation. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_dac_sync.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Initialize the DAC HAL instance and hardware. - */ -int32_t dac_sync_init(struct dac_sync_descriptor *const descr, void *const hw) -{ - uint8_t i; - int32_t rc; - - ASSERT(descr && hw); - - rc = _dac_sync_init(&descr->device, hw); - if (rc) { - return rc; - } - - for (i = 0; i < CHANNEL_NUM; i++) { - descr->sel_ch[i].buffer = NULL; - descr->sel_ch[i].length = 0; - } - - return ERR_NONE; -} - -/** - * \brief Deinitialize the DAC HAL instance and hardware - */ -int32_t dac_sync_deinit(struct dac_sync_descriptor *const descr) -{ - ASSERT(descr); - - _dac_sync_deinit(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Enable DAC channel - */ -int32_t dac_sync_enable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch) -{ - ASSERT(descr && (ch < CHANNEL_NUM)); - - _dac_sync_enable_channel(&descr->device, ch); - - return ERR_NONE; -} - -/** - * \brief Disable DAC channel - */ -int32_t dac_sync_disable_channel(struct dac_sync_descriptor *const descr, const uint8_t ch) -{ - ASSERT(descr && (ch < CHANNEL_NUM)); - - _dac_sync_disable_channel(&descr->device, ch); - - return ERR_NONE; -} - -/** - * \brief DAC convert digital data to analog output - */ -int32_t dac_sync_write(struct dac_sync_descriptor *descr, const uint8_t ch, uint16_t *buffer, uint32_t length) -{ - ASSERT(descr && (ch < CHANNEL_NUM) && buffer && length); - - /* check whether channel is enable */ - if (!_dac_sync_is_channel_enable(&descr->device, ch)) { - return ERR_NOT_READY; - } - - descr->sel_ch[ch].buffer = buffer; - descr->sel_ch[ch].length = length; - - while (descr->sel_ch[ch].length) { - _dac_sync_write_data(&descr->device, *(descr->sel_ch[ch].buffer), ch); - descr->sel_ch[ch].buffer++; - descr->sel_ch[ch].length--; - } - - return ERR_NONE; -} - -/** - * \brief Get DAC driver version - */ -uint32_t dac_sync_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_delay.c b/atmel-samd/asf4/samd51/hal/src/hal_delay.c deleted file mode 100644 index ce963db00..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_delay.c +++ /dev/null @@ -1,90 +0,0 @@ -/** - * \file - * - * \brief HAL delay related functionality implementation. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include "hal_delay.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief The pointer to a hardware instance used by the driver. - */ -static void *hardware; - -/** - * \brief Initialize Delay driver - */ -void delay_init(void *const hw) -{ - _delay_init(hardware = hw); -} - -/** - * \brief Perform delay in us - */ -void delay_us(const uint16_t us) -{ - _delay_cycles(hardware, _get_cycles_for_us(us)); -} - -/** - * \brief Perform delay in ms - */ -void delay_ms(const uint16_t ms) -{ - _delay_cycles(hardware, _get_cycles_for_ms(ms)); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t delay_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_evsys.c b/atmel-samd/asf4/samd51/hal/src/hal_evsys.c deleted file mode 100644 index 9001d7239..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_evsys.c +++ /dev/null @@ -1,108 +0,0 @@ -/** - * \file - * - * \brief HAL event system related functionality implementation. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_evsys.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Initialize event system. - */ -int32_t event_system_init(void) -{ - return _event_system_init(); -} - -/** - * \brief Deinitialize event system. - */ -int32_t event_system_deinit(void) -{ - return _event_system_deinit(); -} - -/** - * \brief Enable event reception by the given user from the given channel - */ -int32_t event_system_enable_user(const uint16_t user, const uint16_t channel) -{ - return _event_system_enable_user(user, channel, true); -} - -/** - * \brief Enable event reception by the given user from the given channel - */ -int32_t event_system_disable_user(const uint16_t user, const uint16_t channel) -{ - return _event_system_enable_user(user, channel, false); -} - -/** - * \brief Enable event generation by the given generator for the given channel - */ -int32_t event_system_enable_generator(const uint16_t generator, const uint16_t channel) -{ - return _event_system_enable_generator(generator, channel, true); -} - -/** - * \brief Enable event generation by the given generator for the given channel - */ -int32_t event_system_disable_generator(const uint16_t generator, const uint16_t channel) -{ - return _event_system_enable_generator(generator, channel, false); -} - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version - */ -uint32_t event_system_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_flash.c b/atmel-samd/asf4/samd51/hal/src/hal_flash.c deleted file mode 100644 index 165d46d89..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_flash.c +++ /dev/null @@ -1,330 +0,0 @@ -/** - * \file - * - * \brief Flash functionality implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_flash.h" -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -static void flash_ready(struct _flash_device *device); -static void flash_error(struct _flash_device *device); - -static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr); - -/** - * \brief Initialize the FLASH HAL instance and hardware for callback mode. - */ -int32_t flash_init(struct flash_descriptor *flash, void *const hw) -{ - int32_t rc; - - ASSERT(flash && hw); - - rc = _flash_init(&flash->dev, hw); - if (rc) { - return rc; - } - - flash->dev.flash_cb.ready_cb = flash_ready; - flash->dev.flash_cb.error_cb = flash_error; - - return ERR_NONE; -} - -/** - * \brief Deinitialize the FLASH HAL instance. - */ -int32_t flash_deinit(struct flash_descriptor *flash) -{ - ASSERT(flash); - - _flash_deinit(&flash->dev); - - return ERR_NONE; -} - -/** - * \brief Reads a number of bytes to a page in the internal Flash - */ -int32_t flash_read(struct flash_descriptor *flash, uint32_t src_addr, uint8_t *buffer, uint32_t length) -{ - ASSERT(flash && buffer && length); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - - /* Check if the address is valid */ - if ((src_addr > page_size * total_pages) || (src_addr + length > page_size * total_pages)) { - return ERR_BAD_ADDRESS; - } - - _flash_read(&flash->dev, src_addr, buffer, length); - - return ERR_NONE; -} - -/** - * \brief Updates several bytes to the internal Flash - */ -int32_t flash_write(struct flash_descriptor *flash, uint32_t dst_addr, uint8_t *buffer, uint32_t length) -{ - ASSERT(flash && buffer && length); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - - /* Check if the address is valid */ - if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { - return ERR_BAD_ADDRESS; - } - - if (_flash_is_locked(&flash->dev, dst_addr)) { - return ERR_DENIED; - } - - _flash_write(&flash->dev, dst_addr, buffer, length); - - return ERR_NONE; -} - -/** - * \brief Appends a number of bytes to a page in the internal Flash - */ -int32_t flash_append(struct flash_descriptor *flash, uint32_t dst_addr, const uint8_t *buffer, uint32_t length) -{ - ASSERT(flash && buffer && length); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - - /* Check if the address is valid */ - if ((dst_addr > page_size * total_pages) || (dst_addr + length > page_size * total_pages)) { - return ERR_BAD_ADDRESS; - } - - if (_flash_is_locked(&flash->dev, dst_addr)) { - return ERR_DENIED; - } - - _flash_append(&flash->dev, dst_addr, buffer, length); - - return ERR_NONE; -} - -/** - * \brief Execute erase in the internal flash - */ -int32_t flash_erase(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) -{ - ASSERT(flash && page_nums); - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - int32_t rc; - - rc = flash_is_address_aligned(flash, dst_addr); - if (rc) { - return rc; - } - - if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { - return ERR_INVALID_ARG; - } - - _flash_erase(&flash->dev, dst_addr, page_nums); - - return ERR_NONE; -} - -/** - * \brief Register a function as FLASH transfer completion callback - */ -int32_t flash_register_callback(struct flash_descriptor *flash, const enum flash_cb_type type, flash_cb_t func) -{ - ASSERT(flash); - - switch (type) { - case FLASH_CB_READY: - flash->callbacks.cb_ready = func; - break; - - case FLASH_CB_ERROR: - flash->callbacks.cb_error = func; - break; - - default: - return ERR_INVALID_ARG; - } - - _flash_set_irq_state(&flash->dev, (enum _flash_cb_type)type, NULL != func); - - return ERR_NONE; -} - -/** - * \brief Execute lock in the internal flash - */ -int32_t flash_lock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) -{ - ASSERT(flash && page_nums); - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - int32_t rc; - - rc = flash_is_address_aligned(flash, dst_addr); - if (rc) { - return rc; - } - - if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { - return ERR_INVALID_ARG; - } - - return _flash_lock(&flash->dev, dst_addr, page_nums); -} - -/** - * \brief Execute unlock in the internal flash - */ -int32_t flash_unlock(struct flash_descriptor *flash, const uint32_t dst_addr, const uint32_t page_nums) -{ - ASSERT(flash && page_nums); - uint32_t page_size = _flash_get_page_size(&flash->dev); - uint32_t total_pages = _flash_get_total_pages(&flash->dev); - int32_t rc; - - rc = flash_is_address_aligned(flash, dst_addr); - if (rc) { - return rc; - } - - if ((page_nums > total_pages) || (dst_addr / page_size + page_nums > total_pages)) { - return ERR_INVALID_ARG; - } - - return _flash_unlock(&flash->dev, dst_addr, page_nums); -} - -/** - * \brief Get the flash page size. - */ -uint32_t flash_get_page_size(struct flash_descriptor *flash) -{ - ASSERT(flash); - return _flash_get_page_size(&flash->dev); -} - -/** - * \brief Get the numbers of flash page. - */ -uint32_t flash_get_total_pages(struct flash_descriptor *flash) -{ - ASSERT(flash); - return _flash_get_total_pages(&flash->dev); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t flash_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \internal check the address whether it is aligned - * \param[in, out] flash Pointer to the HAL FLASH instance. - * \param[in] flash_addr address to be check in flash - * - * \return whether it is valid - * \retval 0 Valid. - * \retval -1 Error, invalid. - */ -static int32_t flash_is_address_aligned(struct flash_descriptor *flash, const uint32_t flash_addr) -{ - ASSERT(flash); - - uint32_t page_size = _flash_get_page_size(&flash->dev); - - /* Check if the read address not aligned to the start of a page */ - if (flash_addr & (page_size - 1)) { - return ERR_BAD_ADDRESS; - } - return ERR_NONE; -} - -/** - * \internal Ready for a new flash command - * - * \param[in] device The pointer to flash device structure - */ -static void flash_ready(struct _flash_device *device) -{ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wcast-align" - struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); - #pragma GCC diagnostic pop - if (descr->callbacks.cb_ready) { - descr->callbacks.cb_ready(descr); - } -} - -/** - * \internal Error occurs in flash command - * - * \param[in] device The pointer to flash device structure - */ -static void flash_error(struct _flash_device *device) -{ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wcast-align" - struct flash_descriptor *const descr = CONTAINER_OF(device, struct flash_descriptor, dev); - #pragma GCC diagnostic pop - if (descr->callbacks.cb_error) { - descr->callbacks.cb_error(descr); - } -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_gpio.c b/atmel-samd/asf4/samd51/hal/src/hal_gpio.c deleted file mode 100644 index 319726290..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_gpio.c +++ /dev/null @@ -1,54 +0,0 @@ -/** - * \file - * - * \brief Port - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_gpio.h" - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -uint32_t gpio_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_i2c_m_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_i2c_m_sync.c deleted file mode 100644 index 7fa26ac7f..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_i2c_m_sync.c +++ /dev/null @@ -1,268 +0,0 @@ -/** - * \file - * - * \brief I/O I2C related functionality implementation. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Sync version of I2C I/O read - */ -static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n) -{ - struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = n; - msg.flags = I2C_M_STOP | I2C_M_RD; - msg.buffer = buf; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret) { - return ret; - } - - return n; -} - -/** - * \brief Sync version of I2C I/O write - */ -static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) -{ - struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = n; - msg.flags = I2C_M_STOP; - msg.buffer = (uint8_t *)buf; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret) { - return ret; - } - - return n; -} - -/** - * \brief Sync version of i2c initialize - */ -int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) -{ - int32_t init_status; - ASSERT(i2c); - - init_status = _i2c_m_sync_init(&i2c->device, hw); - if (init_status) { - return init_status; - } - - /* Init I/O */ - i2c->io.read = i2c_m_sync_read; - i2c->io.write = i2c_m_sync_write; - - return ERR_NONE; -} - -/** - * \brief deinitialize - */ -int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c) -{ - int32_t status; - ASSERT(i2c); - - status = _i2c_m_sync_deinit(&i2c->device); - if (status) { - return status; - } - - i2c->io.read = NULL; - i2c->io.write = NULL; - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c enable - */ -int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c) -{ - return _i2c_m_sync_enable(&i2c->device); -} - -/** - * \brief Sync version of i2c disable - */ -int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c) -{ - return _i2c_m_sync_disable(&i2c->device); -} - -/** - * \brief Sync version of i2c set slave address - */ -int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len) -{ - return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN); -} - -/** - * \brief Sync version of i2c set baudrate - */ -int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate) -{ - return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate); -} - -/** - * \brief Sync version of i2c write command - */ -int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) -{ - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = 1; - msg.flags = 0; - msg.buffer = ® - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - msg.flags = I2C_M_STOP; - msg.buffer = buffer; - msg.len = length; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c read command - */ -int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) -{ - struct _i2c_m_msg msg; - int32_t ret; - - msg.addr = i2c->slave_addr; - msg.len = 1; - msg.flags = 0; - msg.buffer = ® - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - msg.flags = I2C_M_STOP | I2C_M_RD; - msg.buffer = buffer; - msg.len = length; - - ret = _i2c_m_sync_transfer(&i2c->device, &msg); - - if (ret != 0) { - /* error occurred */ - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Sync version of i2c transfer command - */ -int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg) -{ - return _i2c_m_sync_transfer(&i2c->device, msg); -} - -/** - * \brief Sync version of i2c send stop condition command - */ -int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c) -{ - return _i2c_m_sync_send_stop(&i2c->device); -} - -/** - * \brief Retrieve I/O descriptor - */ -int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io) -{ - *io = &i2c->io; - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t i2c_m_sync_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_init.c b/atmel-samd/asf4/samd51/hal/src/hal_init.c deleted file mode 100644 index bdcf2a409..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_init.c +++ /dev/null @@ -1,57 +0,0 @@ -/** - * \file - * - * \brief HAL initialization related functionality implementation. - * - * Copyright (C) 2014-2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_init.h" - -/** - * \brief Driver version - */ -#define HAL_INIT_VERSION 0x00000001u - -/** - * \brief Retrieve the current driver version - */ -uint32_t init_get_version(void) -{ - return HAL_INIT_VERSION; -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_io.c b/atmel-samd/asf4/samd51/hal/src/hal_io.c deleted file mode 100644 index 52638d9b0..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_io.c +++ /dev/null @@ -1,73 +0,0 @@ -/** - * \file - * - * \brief I/O functionality implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -uint32_t io_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \brief I/O write interface - */ -int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) -{ - ASSERT(io_descr && buf); - return io_descr->write(io_descr, buf, length); -} - -/** - * \brief I/O read interface - */ -int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) -{ - ASSERT(io_descr && buf); - return io_descr->read(io_descr, buf, length); -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_pwm.c b/atmel-samd/asf4/samd51/hal/src/hal_pwm.c deleted file mode 100644 index 2b9d2606f..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_pwm.c +++ /dev/null @@ -1,169 +0,0 @@ -/** - * \file - * - * \brief PWM functionality implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_pwm.h" -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -static void pwm_period_expired(struct _pwm_device *device); -static void pwm_detect_fault(struct _pwm_device *device); - -/** - * \brief Initialize pwm - */ -int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func) -{ - ASSERT(descr && hw); - _pwm_init(&descr->device, hw); - descr->device.callback.pwm_period_cb = pwm_period_expired; - descr->device.callback.pwm_error_cb = pwm_detect_fault; - return ERR_NONE; -} - -/** - * \brief Deinitialize pwm - */ -int32_t pwm_deinit(struct pwm_descriptor *const descr) -{ - ASSERT(descr); - _pwm_deinit(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Start pwm - */ -int32_t pwm_enable(struct pwm_descriptor *const descr) -{ - ASSERT(descr); - if (_pwm_is_enabled(&descr->device)) { - return ERR_DENIED; - } - _pwm_enable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Stop pwm - */ -int32_t pwm_disable(struct pwm_descriptor *const descr) -{ - ASSERT(descr); - if (!_pwm_is_enabled(&descr->device)) { - return ERR_DENIED; - } - _pwm_disable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Register PWM callback - */ -int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb) -{ - switch (type) { - case PWM_PERIOD_CB: - descr->pwm_cb.period = cb; - break; - - case PWM_ERROR_CB: - descr->pwm_cb.error = cb; - break; - - default: - return ERR_INVALID_ARG; - } - ASSERT(descr); - _pwm_set_irq_state(&descr->device, (enum _pwm_callback_type)type, NULL != cb); - return ERR_NONE; -} - -/** - * \brief Change PWM parameter - */ -int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, const pwm_period_t duty_cycle) -{ - ASSERT(descr); - _pwm_set_param(&descr->device, period, duty_cycle); - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t pwm_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \internal Process interrupts caused by period experied - */ -static void pwm_period_expired(struct _pwm_device *device) -{ - struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device); - - if (descr->pwm_cb.period) { - descr->pwm_cb.period(descr); - } -} - -/** - * \internal Process interrupts caused by pwm fault - */ -static void pwm_detect_fault(struct _pwm_device *device) -{ - struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device); - - if (descr->pwm_cb.error) { - descr->pwm_cb.error(descr); - } -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_rand_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_rand_sync.c deleted file mode 100644 index 927bdbeba..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_rand_sync.c +++ /dev/null @@ -1,132 +0,0 @@ -/** - * \file - * - * \brief Generic Random Number Generator (RNG) functionality declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include "hal_rand_sync.h" - -#define HAL_RNG_SYNC_VERSION 0x00000001u - -int32_t rand_sync_init(struct rand_sync_desc *const desc, void *const hw) -{ - ASSERT(desc); - - return _rand_sync_init(&desc->dev, hw); -} - -void rand_sync_deinit(struct rand_sync_desc *const desc) -{ - ASSERT(desc); - _rand_sync_deinit(&desc->dev); -} - -int32_t rand_sync_enable(struct rand_sync_desc *const desc) -{ - ASSERT(desc); - return _rand_sync_enable(&desc->dev); -} - -void rand_sync_disable(struct rand_sync_desc *const desc) -{ - ASSERT(desc); - _rand_sync_disable(&desc->dev); -} - -int32_t rand_sync_set_seed(struct rand_sync_desc *const desc, const uint32_t seed) -{ - ASSERT(desc); - return _rand_sync_set_seed(&desc->dev, seed); -} - -/** - * \brief Read data bits - */ -static uint32_t _rand_sync_read_data(const struct _rand_sync_dev *dev, const uint8_t n_bits) -{ - uint8_t r_bits = (dev->n_bits < 1) ? 32 : dev->n_bits; - if (r_bits < n_bits) { - uint8_t i; - uint32_t d = 0; - /* Join read bits */ - for (i = 0; i < n_bits; i += r_bits) { - d |= (uint32_t)(_rand_sync_read_one(dev) << i); - } - return d; - } else { - return _rand_sync_read_one(dev); - } -} - -uint8_t rand_sync_read8(const struct rand_sync_desc *const desc) -{ - ASSERT(desc); - return (uint8_t)_rand_sync_read_data(&desc->dev, 8); -} - -uint32_t rand_sync_read32(const struct rand_sync_desc *const desc) -{ - ASSERT(desc); - return (uint32_t)_rand_sync_read_data(&desc->dev, 32); -} - -void rand_sync_read_buf8(const struct rand_sync_desc *const desc, uint8_t *buf, uint32_t len) -{ - uint32_t i; - ASSERT(desc && (buf && len)); - for (i = 0; i < len; i++) { - buf[i] = (uint8_t)_rand_sync_read_data(&desc->dev, 8); - } -} - -void rand_sync_read_buf32(const struct rand_sync_desc *const desc, uint32_t *buf, uint32_t len) -{ - uint32_t i; - ASSERT(desc && (buf && len)); - for (i = 0; i < len; i++) { - buf[i] = (uint32_t)_rand_sync_read_data(&desc->dev, 32); - } -} - -uint32_t rand_sync_get_version(void) -{ - return HAL_RNG_SYNC_VERSION; -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_sleep.c b/atmel-samd/asf4/samd51/hal/src/hal_sleep.c deleted file mode 100644 index 2d1aadd67..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_sleep.c +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file - * - * \brief Sleep related functionality implementation. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_sleep.h" -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Set the sleep mode of the device and put the MCU to sleep - * - * For an overview of which systems are disabled in sleep for the different - * sleep modes, see the data sheet. - * - * \param[in] mode Sleep mode to use - * - * \return The status of a sleep request - * \retval -1 The requested sleep mode was invalid or not available - * \retval 0 The operation completed successfully, returned after leaving the - * sleep - */ -int sleep(const uint8_t mode) -{ - if (ERR_NONE != _set_sleep_mode(mode)) - return ERR_INVALID_ARG; - - _go_to_sleep(); - - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - * - * \return Current driver version - */ -uint32_t sleep_get_version(void) -{ - return DRIVER_VERSION; -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_spi_m_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_spi_m_sync.c deleted file mode 100644 index 8ceaa9a4a..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_spi_m_sync.c +++ /dev/null @@ -1,212 +0,0 @@ -/** - * \file - * - * \brief I/O SPI related functionality implementation. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_spi_m_sync.h" -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Driver version - */ -#define SPI_M_SYNC_DRIVER_VERSION 0x00000001u - -#define SPI_DEACTIVATE_NEXT 0x8000 - -static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length); -static int32_t _spi_m_sync_io_read(struct io_descriptor *const io, uint8_t *const buf, const uint16_t length); - -int32_t spi_m_sync_init(struct spi_m_sync_descriptor *spi, void *const hw) -{ - int32_t rc = 0; - - ASSERT(spi && hw); - - spi->dev.prvt = (void *)hw; - - rc = _spi_m_sync_init(&spi->dev, hw); - if (rc < 0) { - return rc; - } - - spi->flags = SPI_DEACTIVATE_NEXT; - spi->io.read = _spi_m_sync_io_read; - spi->io.write = _spi_m_sync_io_write; - - return ERR_NONE; -} - -void spi_m_sync_deinit(struct spi_m_sync_descriptor *spi) -{ - ASSERT(spi); - - _spi_m_sync_deinit(&spi->dev); -} - -void spi_m_sync_enable(struct spi_m_sync_descriptor *spi) -{ - ASSERT(spi); - - _spi_m_sync_enable(&spi->dev); -} - -void spi_m_sync_disable(struct spi_m_sync_descriptor *spi) -{ - ASSERT(spi); - - _spi_m_sync_disable(&spi->dev); -} - -int32_t spi_m_sync_set_baudrate(struct spi_m_sync_descriptor *spi, const uint32_t baud_val) -{ - ASSERT(spi); - - return _spi_m_sync_set_baudrate(&spi->dev, baud_val); -} - -int32_t spi_m_sync_set_mode(struct spi_m_sync_descriptor *spi, const enum spi_transfer_mode mode) -{ - ASSERT(spi); - - return _spi_m_sync_set_mode(&spi->dev, mode); -} - -int32_t spi_m_sync_set_char_size(struct spi_m_sync_descriptor *spi, const enum spi_char_size char_size) -{ - ASSERT(spi); - - return _spi_m_sync_set_char_size(&spi->dev, char_size); -} - -int32_t spi_m_sync_set_data_order(struct spi_m_sync_descriptor *spi, const enum spi_data_order dord) -{ - ASSERT(spi); - - return _spi_m_sync_set_data_order(&spi->dev, dord); -} - -/** \brief Do SPI read in polling way - * For SPI master, activate CS, do send 0xFFs and read data, deactivate CS. - * - * It blocks until all data read or error. - * - * \param[in, out] spi Pointer to the HAL SPI instance. - * \param[out] buf Pointer to the buffer to store read data. - * \param[in] size Size of the data in number of characters. - * \return Operation status. - * \retval size Success. - * \retval >=0 Time out, with number of characters read. - */ -static int32_t _spi_m_sync_io_read(struct io_descriptor *io, uint8_t *buf, const uint16_t length) -{ - ASSERT(io); - - struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); - struct spi_xfer xfer; - - xfer.rxbuf = buf; - xfer.txbuf = 0; - xfer.size = length; - - return spi_m_sync_transfer(spi, &xfer); -} - -/** \brief Do SPI data write in polling way - * For SPI master, activate CS, do buffer send and deactivate CS. The data back - * is discarded. - * - * The data read back is discarded. - * - * It blocks until all data sent or error. - * - * \param[in, out] spi Pointer to the HAL SPI instance. - * \param[in] p_xfer Pointer to the transfer information (\ref spi_transfer). - * \return Operation status. - * \retval size Success. - * \retval >=0 Timeout, with number of characters transferred. - */ -static int32_t _spi_m_sync_io_write(struct io_descriptor *const io, const uint8_t *const buf, const uint16_t length) -{ - ASSERT(io); - - struct spi_m_sync_descriptor *spi = CONTAINER_OF(io, struct spi_m_sync_descriptor, io); - struct spi_xfer xfer; - - xfer.rxbuf = 0; - xfer.txbuf = (uint8_t *)buf; - xfer.size = length; - - return spi_m_sync_transfer(spi, &xfer); -} - -int32_t spi_m_sync_transfer(struct spi_m_sync_descriptor *spi, const struct spi_xfer *p_xfer) -{ - struct spi_msg msg; - - ASSERT(spi && p_xfer); - - msg.txbuf = p_xfer->txbuf; - msg.rxbuf = p_xfer->rxbuf; - msg.size = p_xfer->size; - - return _spi_m_sync_trans(&spi->dev, &msg); -} - -int32_t spi_m_sync_get_io_descriptor(struct spi_m_sync_descriptor *const spi, struct io_descriptor **io) -{ - ASSERT(spi && io); - *io = &spi->io; - return 0; -} - -uint32_t spi_m_sync_get_version(void) -{ - return SPI_M_SYNC_DRIVER_VERSION; -} - -#ifdef __cplusplus -} -#endif diff --git a/atmel-samd/asf4/samd51/hal/src/hal_timer.c b/atmel-samd/asf4/samd51/hal/src/hal_timer.c deleted file mode 100644 index db0bbb8da..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_timer.c +++ /dev/null @@ -1,263 +0,0 @@ -/** - * \file - * - * \brief Timer functionality implementation. - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_timer.h" -#include -#include -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -/** - * \brief Timer flags - */ -#define TIMER_FLAG_QUEUE_IS_TAKEN 1 -#define TIMER_FLAG_INTERRUPT_TRIGERRED 2 - -static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time); -static void timer_process_counted(struct _timer_device *device); - -/** - * \brief Initialize timer - */ -int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func) -{ - ASSERT(descr && hw); - _timer_init(&descr->device, hw); - descr->time = 0; - descr->device.timer_cb.period_expired = timer_process_counted; - - return ERR_NONE; -} - -/** - * \brief Deinitialize timer - */ -int32_t timer_deinit(struct timer_descriptor *const descr) -{ - ASSERT(descr); - _timer_deinit(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Start timer - */ -int32_t timer_start(struct timer_descriptor *const descr) -{ - ASSERT(descr); - if (_timer_is_started(&descr->device)) { - return ERR_DENIED; - } - _timer_start(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Stop timer - */ -int32_t timer_stop(struct timer_descriptor *const descr) -{ - ASSERT(descr); - if (!_timer_is_started(&descr->device)) { - return ERR_DENIED; - } - _timer_stop(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Set amount of clock cycler per timer tick - */ -int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles) -{ - ASSERT(descr); - _timer_set_period(&descr->device, clock_cycles); - - return ERR_NONE; -} - -/** - * \brief Add timer task - */ -int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task) -{ - ASSERT(descr && task); - - descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; - if (is_list_element(&descr->tasks, task)) { - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - ASSERT(false); - return ERR_ALREADY_INITIALIZED; - } - task->time_label = descr->time; - timer_add_timer_task(&descr->tasks, task, descr->time); - - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { - CRITICAL_SECTION_ENTER() - descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; - _timer_set_irq(&descr->device); - CRITICAL_SECTION_LEAVE() - } - - return ERR_NONE; -} - -/** - * \brief Remove timer task - */ -int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task) -{ - ASSERT(descr && task); - - descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; - if (!is_list_element(&descr->tasks, task)) { - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - ASSERT(false); - return ERR_NOT_FOUND; - } - list_delete_element(&descr->tasks, task); - - descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; - if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { - CRITICAL_SECTION_ENTER() - descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; - _timer_set_irq(&descr->device); - CRITICAL_SECTION_LEAVE() - } - - return ERR_NONE; -} - -/** - * \brief Retrieve the amount of clock cycles in a tick - */ -int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles) -{ - ASSERT(descr && cycles); - *cycles = _timer_get_period(&descr->device); - return ERR_NONE; -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t timer_get_version(void) -{ - return DRIVER_VERSION; -} - -/** - * \internal Insert a timer task into sorted timer's list - * - * \param[in] head The pointer to the head of timer task list - * \param[in] task The pointer to task to add - * \param[in] time Current timer time - */ -static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) -{ - struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); - - if (!head) { - list_insert_as_head(list, new_task); - return; - } - - for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { - uint32_t time_left; - - if (it->time_label <= time) { - time_left = it->interval - (time - it->time_label); - } else { - time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; - } - if (time_left >= new_task->interval) - break; - prev = it; - } - - if (it == head) { - list_insert_as_head(list, new_task); - } else { - list_insert_after(prev, new_task); - } -} - -/** - * \internal Process interrupts - */ -static void timer_process_counted(struct _timer_device *device) -{ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wcast-align" - struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); - #pragma GCC diagnostic pop - struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); - uint32_t time = ++timer->time; - - if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { - timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; - return; - } - - while (it && ((time - it->time_label) >= it->interval)) { - struct timer_task *tmp = it; - - list_remove_head(&timer->tasks); - if (TIMER_TASK_REPEAT == tmp->mode) { - tmp->time_label = time; - timer_add_timer_task(&timer->tasks, tmp, time); - } - it = (struct timer_task *)list_get_head(&timer->tasks); - - tmp->cb(tmp); - } -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_usart_sync.c b/atmel-samd/asf4/samd51/hal/src/hal_usart_sync.c deleted file mode 100644 index ccc832db8..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_usart_sync.c +++ /dev/null @@ -1,285 +0,0 @@ -/** - * \file - * - * \brief I/O USART related functionality implementation. - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_usart_sync.h" -#include -#include - -/** - * \brief Driver version - */ -#define DRIVER_VERSION 0x00000001u - -static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); -static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); - -/** - * \brief Initialize usart interface - */ -int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func) -{ - int32_t init_status; - ASSERT(descr && hw); - init_status = _usart_sync_init(&descr->device, hw); - if (init_status) { - return init_status; - } - - descr->io.read = usart_sync_read; - descr->io.write = usart_sync_write; - - return ERR_NONE; -} - -/** - * \brief Uninitialize usart interface - */ -int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_deinit(&descr->device); - - descr->io.read = NULL; - descr->io.write = NULL; - - return ERR_NONE; -} - -/** - * \brief Enable usart interface - */ -int32_t usart_sync_enable(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_enable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Disable usart interface - */ -int32_t usart_sync_disable(struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - _usart_sync_disable(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Retrieve I/O descriptor - */ -int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io) -{ - ASSERT(descr && io); - - *io = &descr->io; - return ERR_NONE; -} - -/** - * \brief Specify action for flow control pins - */ -int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const descr, - const union usart_flow_control_state state) -{ - ASSERT(descr); - _usart_sync_set_flow_control_state(&descr->device, state); - - return ERR_NONE; -} - -/** - * \brief Set usart baud rate - */ -int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate) -{ - ASSERT(descr); - _usart_sync_set_baud_rate(&descr->device, baud_rate); - - return ERR_NONE; -} - -/** - * \brief Set usart data order - */ -int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order) -{ - ASSERT(descr); - _usart_sync_set_data_order(&descr->device, data_order); - - return ERR_NONE; -} - -/** - * \brief Set usart mode - */ -int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode) -{ - ASSERT(descr); - _usart_sync_set_mode(&descr->device, mode); - - return ERR_NONE; -} - -/** - * \brief Set usart parity - */ -int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity) -{ - ASSERT(descr); - _usart_sync_set_parity(&descr->device, parity); - - return ERR_NONE; -} - -/** - * \brief Set usart stop bits - */ -int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits) -{ - ASSERT(descr); - _usart_sync_set_stop_bits(&descr->device, stop_bits); - - return ERR_NONE; -} - -/** - * \brief Set usart character size - */ -int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size) -{ - ASSERT(descr); - _usart_sync_set_character_size(&descr->device, size); - - return ERR_NONE; -} - -/** - * \brief Retrieve the state of flow control pins - */ -int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr, - union usart_flow_control_state *const state) -{ - ASSERT(descr && state); - *state = _usart_sync_get_flow_control_state(&descr->device); - - return ERR_NONE; -} - -/** - * \brief Check if the usart transmitter is empty - */ -int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - return _usart_sync_is_byte_sent(&descr->device); -} - -/** - * \brief Check if the usart receiver is not empty - */ -int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr) -{ - ASSERT(descr); - return _usart_sync_is_byte_received(&descr->device); -} - -/** - * \brief Retrieve the current driver version - */ -uint32_t usart_sync_get_version(void) -{ - return DRIVER_VERSION; -} - -/* - * \internal Write the given data to usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf Data to write to usart - * \param[in] length The number of bytes to write - * - * \return The number of bytes written. - */ -static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) -{ - uint32_t offset = 0; - struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); - - ASSERT(io_descr && buf && length); - while (!_usart_sync_is_byte_sent(&descr->device)) - ; - do { - _usart_sync_write_byte(&descr->device, buf[offset]); - while (!_usart_sync_is_byte_sent(&descr->device)) - ; - } while (++offset < length); - - return (int32_t)offset; -} - -/* - * \internal Read data from usart interface - * - * \param[in] descr The pointer to an io descriptor - * \param[in] buf A buffer to read data to - * \param[in] length The size of a buffer - * - * \return The number of bytes read. - */ -static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) -{ - uint32_t offset = 0; - struct usart_sync_descriptor *descr = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io); - - ASSERT(io_descr && buf && length); - do { - while (!_usart_sync_is_byte_received(&descr->device)) - ; - buf[offset] = _usart_sync_read_byte(&descr->device); - } while (++offset < length); - - return (int32_t)offset; -} diff --git a/atmel-samd/asf4/samd51/hal/src/hal_usb_device.c b/atmel-samd/asf4/samd51/hal/src/hal_usb_device.c deleted file mode 100644 index 08ad12a30..000000000 --- a/atmel-samd/asf4/samd51/hal/src/hal_usb_device.c +++ /dev/null @@ -1,602 +0,0 @@ -/** - * \file - * - * \brief SAM USB device HAL - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hal_usb_device.h" -#include "hal_atomic.h" - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** USB device HAL driver version. */ -#define USB_D_VERSION 0x00000001u - -/** - * Endpoint callbacks for data transfer. - */ -struct usb_d_ep_callbacks { - /** Callback that is invoked when setup packet is received. */ - usb_d_ep_cb_setup_t req; - /** Callback invoked when buffer is done, but last packet is full size - * packet without ZLP. Return \c true if new transfer has been submitted. - */ - usb_d_ep_cb_more_t more; - /** Callback invoked when transfer is finished/halted/aborted or error - * occurs. - */ - usb_d_ep_cb_xfer_t xfer; -}; - -/** - * Endpoint transfer descriptor header. - */ -struct usb_ep_xfer_hdr { - /** Transfer type, reuse \ref usb_ep_type. */ - uint8_t type; - /** Endpoint address. */ - uint8_t ep; - /** Endpoint state. */ - uint8_t state; - /** Last status code. */ - uint8_t status; -}; - -/** - * Transfer descriptor. - */ -struct usb_ep_xfer { - /** General transfer descriptor. */ - struct usb_ep_xfer_hdr hdr; - /** Pointer to data buffer. */ - uint8_t *buf; - /** Transfer size. */ - uint32_t size; - /** Control request packet. */ - uint8_t req[8]; -}; - -/** - * USB device endpoint descriptor. - */ -struct usb_d_ep { - /** On-going transfer on the endpoint. */ - struct usb_ep_xfer xfer; - /** Endpoint callbacks. */ - struct usb_d_ep_callbacks callbacks; -}; - -/** - * USB device HAL driver descriptor. - */ -struct usb_d_descriptor { - /** USB device endpoints. */ - struct usb_d_ep ep[CONF_USB_D_NUM_EP_SP]; -}; - -/** The USB HAL driver descriptor instance. */ -static struct usb_d_descriptor usb_d_inst; - -/** \brief Find the endpoint. - * \param[in] ep Endpoint address. - * \return Index of endpoint descriptor. - * \retval >=0 The index. - * \retval <0 Not found (endpoint is not initialized). - */ -static int8_t _usb_d_find_ep(const uint8_t ep) -{ - int8_t i; - for (i = 0; i < CONF_USB_D_NUM_EP_SP; i++) { - if (usb_d_inst.ep[i].xfer.hdr.ep == ep) { - return i; - } - if (usb_d_inst.ep[i].xfer.hdr.type == USB_EP_XTYPE_CTRL - && (ep & USB_EP_N_MASK) == usb_d_inst.ep[i].xfer.hdr.ep) { - return i; - } - } - return -1; -} - -/** - * \brief Start transactions - * \param[in] ep Endpoint address. - * \param[in] dir Endpoint transfer direction. - * \param[in] buf Pointer to transfer buffer. - * \param[in] size Transfer size. - * \param[in] zlp Auto append ZLP for IN, or wait ZLP for OUT. - */ -static inline int32_t _usb_d_trans(const uint8_t ep, const bool dir, const uint8_t *buf, const uint32_t size, - const uint8_t zlp) -{ - struct usb_d_transfer trans - = {(uint8_t *)buf, size, dir ? (uint8_t)(ep | USB_EP_DIR) : (uint8_t)(ep & USB_EP_N_MASK), zlp}; - - return _usb_d_dev_ep_trans(&trans); -} - -/** - * \brief Dummy callback that returns false - * \param[in] unused0 Unused parameter. - * \param[in] unused1 Unused parameter. - * \param[in] unused2 Unused parameter. - * \return Always \c false. - */ -static bool usb_d_dummy_cb_false(uint32_t unused0, uint32_t unused1, uint32_t unused2) -{ - (void)unused0; - (void)unused1; - (void)unused2; - return false; -} - -/** - * \brief Callback invoked when SETUP packet is ready - * \param[in] ep Endpoint number with transfer direction on bit 8. - */ -static void usb_d_cb_trans_setup(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - uint8_t * req = ept->xfer.req; - - uint8_t n = _usb_d_dev_ep_read_req(ep, req); - if (n != 8) { - _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); - _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_SET); - return; - } - - _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); - _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_CLR); - ept->xfer.hdr.state = USB_EP_S_IDLE; - if (!ept->callbacks.req(ep, req)) { - ept->xfer.hdr.state = USB_EP_S_HALTED; - _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); - _usb_d_dev_ep_stall(ep | USB_EP_DIR, USB_EP_STALL_SET); - } -} - -/** - * \brief Callback invoked when request more data - * \param[in] ep Endpoint number with transfer direction on bit 8. - * \param[in] transfered Number of bytes transfered. - */ -static bool usb_d_cb_trans_more(const uint8_t ep, const uint32_t transfered) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - if (ept->xfer.hdr.state == USB_EP_S_X_DATA) { - return ept->callbacks.more(ep, transfered); - } - return false; -} - -/** - * \brief Handles the case that control endpoint transactions are done - * \param[in,out] ept Pointer to endpoint information. - */ -static inline void usb_d_ctrl_trans_done(struct usb_d_ep *ept) -{ - uint8_t state = ept->xfer.hdr.state; - bool req_dir = USB_GET_bmRequestType(ept->xfer.req) & USB_REQ_TYPE_IN; - - if (state == USB_EP_S_X_DATA) { - /* Data stage -> Status stage */ - bool err = ept->callbacks.xfer(ept->xfer.hdr.ep, USB_XFER_DATA, ept->xfer.req); - if (err) { - ept->xfer.hdr.state = USB_EP_S_HALTED; - ept->xfer.hdr.status = USB_XFER_HALT; - _usb_d_dev_ep_stall(req_dir ? ept->xfer.hdr.ep : (ept->xfer.hdr.ep | USB_EP_DIR), USB_EP_STALL_SET); - } else { - ept->xfer.hdr.state = USB_EP_S_X_STATUS; - _usb_d_trans(ept->xfer.hdr.ep, !req_dir, NULL, 0, 1); - } - } else { - /* Status stage done */ - ept->callbacks.xfer(ept->xfer.hdr.ep, USB_XFER_DONE, ept->xfer.req); - ept->xfer.hdr.state = USB_EP_S_X_SETUP; - } -} - -/** - * Callback when USB transactions are finished. - */ -static void _usb_d_cb_trans_done(const uint8_t ep, const int32_t code, const uint32_t transferred) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - - if (code == USB_TRANS_DONE) { - ept->xfer.hdr.status = USB_XFER_DONE; - if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { - usb_d_ctrl_trans_done(ept); - return; - } - ept->xfer.hdr.state = USB_EP_S_IDLE; - } else if (code == USB_TRANS_STALL) { - ept->xfer.hdr.status = USB_XFER_HALT; - if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { - ept->xfer.hdr.state = USB_EP_S_X_SETUP; - _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); - } else { - ept->xfer.hdr.state = USB_EP_S_HALTED; - } - } else if (code == USB_TRANS_ABORT) { - ept->xfer.hdr.status = USB_XFER_ABORT; - if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { - ept->xfer.hdr.state = USB_EP_S_X_SETUP; - return; - } - ept->xfer.hdr.state = USB_EP_S_IDLE; - } else if (code == USB_TRANS_RESET) { - ept->xfer.hdr.state = USB_EP_S_DISABLED; - ept->xfer.hdr.status = USB_XFER_RESET; - } else { - ept->xfer.hdr.state = USB_EP_S_ERROR; - ept->xfer.hdr.status = USB_XFER_ERROR; - } - - ept->callbacks.xfer(ep, (enum usb_xfer_code)ept->xfer.hdr.status, (void *)transferred); -} - -int32_t usb_d_init(void) -{ - int32_t rc = _usb_d_dev_init(); - uint8_t i; - if (rc < 0) { - return rc; - } - memset(usb_d_inst.ep, 0x00, sizeof(struct usb_d_ep) * CONF_USB_D_NUM_EP_SP); - for (i = 0; i < CONF_USB_D_NUM_EP_SP; i++) { - usb_d_inst.ep[i].xfer.hdr.ep = 0xFF; - usb_d_inst.ep[i].callbacks.req = (usb_d_ep_cb_setup_t)usb_d_dummy_cb_false; - usb_d_inst.ep[i].callbacks.more = (usb_d_ep_cb_more_t)usb_d_dummy_cb_false; - usb_d_inst.ep[i].callbacks.xfer = (usb_d_ep_cb_xfer_t)usb_d_dummy_cb_false; - } - /* Handles device driver endpoint callbacks to build transfer. */ - _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_SETUP, (FUNC_PTR)usb_d_cb_trans_setup); - _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_MORE, (FUNC_PTR)usb_d_cb_trans_more); - _usb_d_dev_register_ep_callback(USB_D_DEV_EP_CB_DONE, (FUNC_PTR)_usb_d_cb_trans_done); - return ERR_NONE; -} - -void usb_d_deinit(void) -{ - _usb_d_dev_deinit(); -} - -void usb_d_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func) -{ - /* Directly uses device driver callback. */ - _usb_d_dev_register_callback(type, func); -} - -int32_t usb_d_enable(void) -{ - return _usb_d_dev_enable(); -} - -void usb_d_disable(void) -{ - _usb_d_dev_disable(); -} - -void usb_d_attach(void) -{ - _usb_d_dev_attach(); -} - -void usb_d_detach(void) -{ - _usb_d_dev_detach(); -} - -enum usb_speed usb_d_get_speed(void) -{ - return _usb_d_dev_get_speed(); -} - -uint16_t usb_d_get_frame_num(void) -{ - return _usb_d_dev_get_frame_n(); -} - -uint8_t usb_d_get_uframe_num(void) -{ - return _usb_d_dev_get_uframe_n(); -} - -void usb_d_set_address(const uint8_t addr) -{ - _usb_d_dev_set_address(addr); -} - -void usb_d_send_remotewakeup(void) -{ - _usb_d_dev_send_remotewakeup(); -} - -int32_t usb_d_ep0_init(const uint8_t max_pkt_size) -{ - return usb_d_ep_init(0, USB_EP_XTYPE_CTRL, max_pkt_size); -} - -int32_t usb_d_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_size) -{ - int32_t rc; - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - if (ep_index >= 0) { - return -USB_ERR_REDO; - } else { - ep_index = _usb_d_find_ep(0xFF); - if (ep_index < 0) { - return -USB_ERR_ALLOC_FAIL; - } - ept = &usb_d_inst.ep[ep_index]; - } - rc = _usb_d_dev_ep_init(ep, attr, max_pkt_size); - if (rc < 0) { - return rc; - } - ept->xfer.hdr.ep = ep; - ept->xfer.hdr.type = attr & USB_EP_XTYPE_MASK; - return ERR_NONE; -} - -void usb_d_ep_deinit(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - if (ep_index < 0) { - return; - } - _usb_d_dev_ep_deinit(ep); - ept->xfer.hdr.ep = 0xFF; -} - -int32_t usb_d_ep_enable(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - int32_t rc; - if (ep_index < 0) { - return -USB_ERR_PARAM; - } - ept->xfer.hdr.state = (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) ? USB_EP_S_X_SETUP : USB_EP_S_IDLE; - rc = _usb_d_dev_ep_enable(ep); - if (rc < 0) { - ept->xfer.hdr.state = USB_EP_S_DISABLED; - } - return rc; -} - -void usb_d_ep_disable(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - if (ep_index < 0) { - return; - } - _usb_d_dev_ep_disable(ep); - ept->xfer.hdr.state = USB_EP_S_DISABLED; -} - -uint8_t *usb_d_ep_get_req(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - if (ep_index < 0) { - return NULL; - } - return usb_d_inst.ep[ep_index].xfer.req; -} - -int32_t usb_d_ep_transfer(const struct usb_d_transfer *xfer) -{ - int8_t ep_index = _usb_d_find_ep(xfer->ep); - struct usb_d_ep * ept = &usb_d_inst.ep[ep_index]; - bool dir = USB_EP_GET_DIR(xfer->ep), zlp = xfer->zlp; - uint32_t len = xfer->size; - int32_t rc; - volatile uint8_t state; - volatile hal_atomic_t flags; - - if (ep_index < 0) { - return -USB_ERR_PARAM; - } - - atomic_enter_critical(&flags); - state = ept->xfer.hdr.state; - if (state == USB_EP_S_IDLE) { - ept->xfer.hdr.state = USB_EP_S_X_DATA; - atomic_leave_critical(&flags); - } else { - atomic_leave_critical(&flags); - switch (state) { - case USB_EP_S_HALTED: - return USB_HALTED; - case USB_EP_S_ERROR: - return -USB_ERROR; - case USB_EP_S_DISABLED: - return -USB_ERR_FUNC; - default: /* USB_EP_S_X_xxxx */ - return USB_BUSY; - } - } - - if (ept->xfer.hdr.type == USB_EP_XTYPE_CTRL) { - uint16_t req_len = USB_GET_wLength(ept->xfer.req); - /* SETUP without data: ZLP IN as status. */ - if (req_len == 0) { - dir = true; - len = 0; - zlp = true; - ept->xfer.hdr.state = USB_EP_S_X_STATUS; - } else { - dir = (USB_GET_bmRequestType(ept->xfer.req) & USB_REQ_TYPE_IN); - /* Data length not exceed requested. */ - if (len > req_len) { - len = req_len; - } - if (dir) { - /* Setup -> In */ - zlp = (req_len > len); - } else { - zlp = false; - } - } - } - - rc = _usb_d_trans(xfer->ep, dir, xfer->buf, len, zlp); - return rc; -} - -void usb_d_ep_abort(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - if (ep_index < 0) { - return; - } - _usb_d_dev_ep_abort(ep); - ept->xfer.hdr.state = USB_EP_S_IDLE; - ept->xfer.hdr.status = USB_XFER_ABORT; -} - -int32_t usb_d_ep_get_status(const uint8_t ep, struct usb_d_ep_status *stat) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep * ept = &usb_d_inst.ep[ep_index]; - struct usb_d_trans_status tmp; - uint8_t state = ept->xfer.hdr.state; - if (ep_index < 0) { - return -USB_ERR_PARAM; - } - if (stat) { - /* Check transaction status if transferring data. */ - _usb_d_dev_ep_get_status(ep, &tmp); - stat->ep = ep; - stat->state = state; - stat->code = ept->xfer.hdr.status; - stat->count = tmp.count; - stat->size = tmp.size; - } - switch (state) { - case USB_EP_S_IDLE: - return USB_OK; - case USB_EP_S_HALTED: - return USB_HALTED; - case USB_EP_S_ERROR: - return -USB_ERROR; - case USB_EP_S_DISABLED: - return -USB_ERR_FUNC; - default: - /* Busy */ - return USB_BUSY; - } -} - -static inline int32_t _usb_d_ep_halt_clr(const uint8_t ep) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - int32_t rc; - if (ep_index < 0) { - return -USB_ERR_PARAM; - } - if (_usb_d_dev_ep_stall(ep, USB_EP_STALL_GET)) { - rc = _usb_d_dev_ep_stall(ep, USB_EP_STALL_CLR); - if (rc < 0) { - return rc; - } - ept->xfer.hdr.state = USB_EP_S_IDLE; - ept->xfer.hdr.status = USB_XFER_UNHALT; - ept->callbacks.xfer(ep, USB_XFER_UNHALT, NULL); - } - return ERR_NONE; -} - -int32_t usb_d_ep_halt(const uint8_t ep, const enum usb_ep_halt_ctrl ctrl) -{ - if (ctrl == USB_EP_HALT_CLR) { - return _usb_d_ep_halt_clr(ep); - } else if (ctrl == USB_EP_HALT_SET) { - return _usb_d_dev_ep_stall(ep, USB_EP_STALL_SET); - } else { - return _usb_d_dev_ep_stall(ep, USB_EP_STALL_GET); - } -} - -void usb_d_ep_register_callback(const uint8_t ep, const enum usb_d_ep_cb_type type, const FUNC_PTR func) -{ - int8_t ep_index = _usb_d_find_ep(ep); - struct usb_d_ep *ept = &usb_d_inst.ep[ep_index]; - FUNC_PTR f = func ? (FUNC_PTR)func : (FUNC_PTR)usb_d_dummy_cb_false; - if (ep_index < 0) { - return; - } - switch (type) { - case USB_D_EP_CB_SETUP: - ept->callbacks.req = (usb_d_ep_cb_setup_t)f; - break; - case USB_D_EP_CB_MORE: - ept->callbacks.more = (usb_d_ep_cb_more_t)f; - break; - case USB_D_EP_CB_XFER: - ept->callbacks.xfer = (usb_d_ep_cb_xfer_t)f; - break; - default: - break; - } -} - -uint32_t usb_d_get_version(void) -{ - return USB_D_VERSION; -} - -#ifdef __cplusplus -} -#endif diff --git a/atmel-samd/asf4/samd51/hal/utils/include/compiler.h b/atmel-samd/asf4/samd51/hal/utils/include/compiler.h deleted file mode 100644 index 3cd654f53..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/compiler.h +++ /dev/null @@ -1,28 +0,0 @@ -/****************************************************************************** - * compiler.h - * - * Created: 05.05.2014 - * Author: N. Fomin -******************************************************************************/ - -#ifndef _COMPILER_H -#define _COMPILER_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -#ifndef _UNIT_TEST_ -#include "parts.h" -#endif -#include "err_codes.h" - -#ifdef __cplusplus -} -#endif - -#endif /* _COMPILER_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/err_codes.h b/atmel-samd/asf4/samd51/hal/utils/include/err_codes.h deleted file mode 100644 index ebc80e58b..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/err_codes.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - * \file - * - * \brief Error code definitions. - * - * This file defines various status codes returned by functions, - * indicating success or failure as well as what kind of failure. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef ERROR_CODES_H_INCLUDED -#define ERROR_CODES_H_INCLUDED - -#define ERR_NONE 0 -#define ERR_INVALID_DATA -1 -#define ERR_NO_CHANGE -2 -#define ERR_ABORTED -3 -#define ERR_BUSY -4 -#define ERR_SUSPEND -5 -#define ERR_IO -6 -#define ERR_REQ_FLUSHED -7 -#define ERR_TIMEOUT -8 -#define ERR_BAD_DATA -9 -#define ERR_NOT_FOUND -10 -#define ERR_UNSUPPORTED_DEV -11 -#define ERR_NO_MEMORY -12 -#define ERR_INVALID_ARG -13 -#define ERR_BAD_ADDRESS -14 -#define ERR_BAD_FORMAT -15 -#define ERR_BAD_FRQ -16 -#define ERR_DENIED -17 -#define ERR_ALREADY_INITIALIZED -18 -#define ERR_OVERFLOW -19 -#define ERR_NOT_INITIALIZED -20 -#define ERR_SAMPLERATE_UNAVAILABLE -21 -#define ERR_RESOLUTION_UNAVAILABLE -22 -#define ERR_BAUDRATE_UNAVAILABLE -23 -#define ERR_PACKET_COLLISION -24 -#define ERR_PROTOCOL -25 -#define ERR_PIN_MUX_INVALID -26 -#define ERR_UNSUPPORTED_OP -27 -#define ERR_NO_RESOURCE -28 -#define ERR_NOT_READY -29 -#define ERR_FAILURE -30 -#define ERR_WRONG_LENGTH -31 - -#endif diff --git a/atmel-samd/asf4/samd51/hal/utils/include/events.h b/atmel-samd/asf4/samd51/hal/utils/include/events.h deleted file mode 100644 index 13c1d62db..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/events.h +++ /dev/null @@ -1,64 +0,0 @@ -/** -* \file -* -* \brief Events declaration. -* -* Copyright (C) 2015 Atmel Corporation. All rights reserved. -* -* \asf_license_start -* -* \page License -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of Atmel may not be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* 4. This software may only be redistributed and used in connection with an -* Atmel microcontroller product. -* -* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -* HOWEVER CAUSEsD AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -* \asf_license_stop -* -*/ - -#ifndef _EVENTS_H_INCLUDED -#define _EVENTS_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * \brief List of events. Must start with 0, be unique and follow numerical order. - */ -#define EVENT_IS_READY_TO_SLEEP_ID 0 -#define EVENT_PREPARE_TO_SLEEP_ID 1 -#define EVENT_WOKEN_UP_ID 2 - -#ifdef __cplusplus -} -#endif - -#endif /* _EVENTS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/parts.h b/atmel-samd/asf4/samd51/hal/utils/include/parts.h deleted file mode 100644 index 051336ed1..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/parts.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * \file - * - * \brief Atmel part identification macros - * - * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef ATMEL_PARTS_H -#define ATMEL_PARTS_H - -#include "samd51.h" - -#include "hri_d51.h" - -#endif /* ATMEL_PARTS_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils.h b/atmel-samd/asf4/samd51/hal/utils/include/utils.h deleted file mode 100644 index 1cc588ad7..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/utils.h +++ /dev/null @@ -1,364 +0,0 @@ -/** - * \file - * - * \brief Different macros. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef UTILS_H_INCLUDED -#define UTILS_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_utils_macro - * - * @{ - */ - -/** - * \brief Retrieve pointer to parent structure - */ -#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) - -/** - * \brief Retrieve array size - */ -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) - -/** - * \brief Emit the compiler pragma \a arg. - * - * \param[in] arg The pragma directive as it would appear after \e \#pragma - * (i.e. not stringified). - */ -#define COMPILER_PRAGMA(arg) _Pragma(#arg) - -/** - * \def COMPILER_PACK_SET(alignment) - * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. - */ -#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) - -/** - * \def COMPILER_PACK_RESET() - * \brief Set default alignment for subsequent struct and union definitions. - */ -#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) - -/** - * \brief Set aligned boundary. - */ -#if defined __GNUC__ -#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#elif defined __ICCARM__ -#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) -#elif defined __CC_ARM -#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) -#endif - -/** - * \brief Flash located data macros - */ -#if defined __GNUC__ -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#elif defined __ICCARM__ -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#elif defined __CC_ARM -#define PROGMEM_DECLARE(type, name) const type name -#define PROGMEM_T const -#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) -#define PROGMEM_PTR_T const * -#define PROGMEM_STRING_T const uint8_t * -#endif - -/** - * \brief Optimization - */ -#if defined __GNUC__ -#define OPTIMIZE_HIGH __attribute__((optimize(s))) -#elif defined __CC_ARM -#define OPTIMIZE_HIGH _Pragma("O3") -#elif defined __ICCARM__ -#define OPTIMIZE_HIGH _Pragma("optimize=high") -#endif - -/** - * \brief RAM located function attribute - */ -#if defined(__CC_ARM) /* Keil ?Vision 4 */ -#define RAMFUNC __attribute__((section(".ramfunc"))) -#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ -#define RAMFUNC __ramfunc -#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ -#define RAMFUNC __attribute__((section(".ramfunc"))) -#endif - -/** - * \brief No-init section. - * Place a data object or a function in a no-init section. - */ -#if defined(__CC_ARM) -#define NO_INIT(a) __attribute__((zero_init)) -#elif defined(__ICCARM__) -#define NO_INIT(a) __no_init -#elif defined(__GNUC__) -#define NO_INIT(a) __attribute__((section(".no_init"))) -#endif - -/** - * \brief Set user-defined section. - * Place a data object or a function in a user-defined section. - */ -#if defined(__CC_ARM) -#define COMPILER_SECTION(a) __attribute__((__section__(a))) -#elif defined(__ICCARM__) -#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) -#elif defined(__GNUC__) -#define COMPILER_SECTION(a) __attribute__((__section__(a))) -#endif - -/** - * \brief Define WEAK attribute. - */ -#if defined(__CC_ARM) /* Keil ?Vision 4 */ -#define WEAK __attribute__((weak)) -#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ -#define WEAK __weak -#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ -#define WEAK __attribute__((weak)) -#endif - -/** - * \brief Pointer to function - */ -typedef void (*FUNC_PTR)(void); - -#define LE_BYTE0(a) ((uint8_t)(a)) -#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) -#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) -#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) - -#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) -#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) - -/** \name Zero-Bit Counting - * - * Under GCC, __builtin_clz and __builtin_ctz behave like macros when - * applied to constant expressions (values known at compile time), so they are - * more optimized than the use of the corresponding assembly instructions and - * they can be used as constant expressions e.g. to initialize objects having - * static storage duration, and like the corresponding assembly instructions - * when applied to non-constant expressions (values unknown at compile time), so - * they are more optimized than an assembly periphrasis. Hence, clz and ctz - * ensure a possible and optimized behavior for both constant and non-constant - * expressions. - * - * @{ */ - -/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the leading zero bits. - * - * \return The count of leading zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -#define clz(u) __builtin_clz(u) -#else -#define clz(u) \ - (((u) == 0) \ - ? 32 \ - : ((u) & (1ul << 31)) ? 0 : ((u) & (1ul << 30)) ? 1 : ((u) & (1ul << 29)) \ - ? 2 \ - : ((u) & (1ul << 28)) \ - ? 3 \ - : ((u) & (1ul << 27)) \ - ? 4 \ - : ((u) & (1ul << 26)) \ - ? 5 \ - : ((u) & (1ul << 25)) ? 6 \ - : ((u) & (1ul << 24)) ? 7 : ((u) & (1ul << 23)) ? 8 : ((u) & (1ul << 22)) ? 9 : ((u) & (1ul << 21)) ? 10 : ((u) & (1ul << 20)) ? 11 : (( \ - u) \ - & (1ul \ - << 19)) \ - ? 12 \ - : ((u) \ - & (1ul \ - << 18)) \ - ? 13 \ - : ( \ - (u) \ - & (1ul \ - << 17)) \ - ? 14 \ - : ((u) & (1ul << 16)) ? 15 \ - : ((u) \ - & (1ul \ - << 15)) \ - ? 16 \ - : ((u) & (1ul << 14)) ? 17 \ - : ((u) & (1ul << 13)) ? 18 : ((u) & (1ul << 12)) ? 19 : ((u) & (1ul << 11)) ? 20 \ - : ((u) \ - & (1ul \ - << 10)) \ - ? 21 \ - : ((u) & (1ul << 9)) ? 22 \ - : ((u) & (1ul << 8)) ? 23 : ((u) \ - & (1ul \ - << 7)) \ - ? 24 \ - : ((u) & (1ul << 6)) ? 25 : ((u) & (1ul << 5)) ? 26 : ((u) & (1ul << 4)) ? 27 : ((u) & (1ul << 3)) ? 28 : ((u) \ - & (1ul \ - << 2)) \ - ? 29 \ - : ((u) & (1ul << 1)) ? 30 \ - : 31) -#endif - -/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. - * - * \param[in] u Value of which to count the trailing zero bits. - * - * \return The count of trailing zero bits in \a u. - */ -#if (defined __GNUC__) || (defined __CC_ARM) -#define ctz(u) __builtin_ctz(u) -#else -#define ctz(u) \ - ( \ - (u) & (1ul << 0) \ - ? 0 \ - : (u) & (1ul << 1) \ - ? 1 \ - : (u) & (1ul << 2) \ - ? 2 \ - : (u) & (1ul << 3) \ - ? 3 \ - : (u) & (1ul << 4) \ - ? 4 \ - : (u) & (1ul << 5) \ - ? 5 \ - : (u) & (1ul << 6) \ - ? 6 \ - : (u) & (1ul << 7) \ - ? 7 \ - : (u) & (1ul << 8) \ - ? 8 \ - : (u) & (1ul << 9) ? 9 \ - : (u) & (1ul << 10) \ - ? 10 \ - : (u) & (1ul << 11) \ - ? 11 \ - : (u) & (1ul << 12) \ - ? 12 \ - : (u) & (1ul << 13) \ - ? 13 \ - : (u) & (1ul \ - << 14) \ - ? 14 \ - : (u) & (1ul \ - << 15) \ - ? 15 \ - : (u) & (1ul << 16) ? 16 : (u) & (1ul << 17) ? 17 : (u) & (1ul << 18) ? 18 : (u) & (1ul << 19) ? 19 : (u) & (1ul << 20) ? 20 : (u) \ - & (1ul \ - << 21) \ - ? 21 \ - : (u) & (1ul << 22) ? 22 : (u) \ - & (1ul << 23) \ - ? 23 \ - : (u) & (1ul << 24) ? 24 \ - : (u) & (1ul << 25) ? 25 \ - : (u) & (1ul << 26) ? 26 : (u) & (1ul \ - << 27) \ - ? 27 \ - : (u) & (1ul \ - << 28) \ - ? 28 \ - : (u) & (1ul << 29) ? 29 \ - : (u) & (1ul << 30) ? 30 : ( \ - u) & (1ul << 31) \ - ? 31 \ - : 32) -#endif -/** @} */ - -/** - * \brief Counts the number of bits in a mask (no more than 32 bits) - * \param[in] mask Mask of which to count the bits. - */ -#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) - -/** - * \brief Retrieve the start position of bits mask (no more than 32 bits) - * \param[in] mask Mask of which to retrieve the start position. - */ -#define pos_of_mask(mask) ctz(mask) - -/** - * \brief Return division result of a/b and round up the result to the closest - * number divisible by "b" - */ -#define round_up(a, b) (((a)-1) / (b) + 1) - -/** - * \brief Get the minimum of x and y - */ -#define min(x, y) ((x) > (y) ? (y) : (x)) - -/** - * \brief Get the maximum of x and y - */ -#define max(x, y) ((x) > (y) ? (x) : (y)) - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* UTILS_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_assert.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_assert.h deleted file mode 100644 index ae679e7a3..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/utils_assert.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * \file - * - * \brief Asserts related functionality. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _ASSERT_H_INCLUDED -#define _ASSERT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#ifndef USE_SIMPLE_ASSERT -//# define USE_SIMPLE_ASSERT -#endif - -/** - * \brief Assert macro - * - * This macro is used to throw asserts. It can be mapped to different function - * based on debug level. - * - * \param[in] condition A condition to be checked; - * assert is thrown if the given condition is false - */ -#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) - -#ifdef DEBUG - -#ifdef USE_SIMPLE_ASSERT -#define ASSERT_IMPL(condition, file, line) \ - if (!(condition)) \ - __asm("BKPT #0"); -#else -#define ASSERT_IMPL(condition, file, line) asf_assert((condition), file, line) -#endif - -#else /* DEBUG */ - -#ifdef USE_SIMPLE_ASSERT -#define ASSERT_IMPL(condition, file, line) ((void)0) -#else -#define ASSERT_IMPL(condition, file, line) ((void)0) -#endif - -#endif /* DEBUG */ - -/** - * \brief Assert function - * - * This function is used to throw asserts. - * - * \param[in] condition A condition to be checked; assert is thrown if the given - * condition is false - * \param[in] file File name - * \param[in] line Line number - */ -void asf_assert(const bool condition, const char *const file, const int line); - -#ifdef __cplusplus -} -#endif -#endif /* _ASSERT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_decrement_macro.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_decrement_macro.h deleted file mode 100644 index b53c5da8c..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/utils_decrement_macro.h +++ /dev/null @@ -1,319 +0,0 @@ -/** - * \file - * - * \brief Decrement macro. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_DECREMENT_MACRO_H -#define _UTILS_DECREMENT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Compile time decrement, result value is entire integer literal - * - * \param[in] val - value to be decremented - */ -#define DEC_VALUE(val) DEC_##val - -// Preprocessor increment implementation -#define DEC_256 255 -#define DEC_255 254 -#define DEC_254 253 -#define DEC_253 252 -#define DEC_252 251 -#define DEC_251 250 -#define DEC_250 249 -#define DEC_249 248 -#define DEC_248 247 -#define DEC_247 246 -#define DEC_246 245 -#define DEC_245 244 -#define DEC_244 243 -#define DEC_243 242 -#define DEC_242 241 -#define DEC_241 240 -#define DEC_240 239 -#define DEC_239 238 -#define DEC_238 237 -#define DEC_237 236 -#define DEC_236 235 -#define DEC_235 234 -#define DEC_234 233 -#define DEC_233 232 -#define DEC_232 231 -#define DEC_231 230 -#define DEC_230 229 -#define DEC_229 228 -#define DEC_228 227 -#define DEC_227 226 -#define DEC_226 225 -#define DEC_225 224 -#define DEC_224 223 -#define DEC_223 222 -#define DEC_222 221 -#define DEC_221 220 -#define DEC_220 219 -#define DEC_219 218 -#define DEC_218 217 -#define DEC_217 216 -#define DEC_216 215 -#define DEC_215 214 -#define DEC_214 213 -#define DEC_213 212 -#define DEC_212 211 -#define DEC_211 210 -#define DEC_210 209 -#define DEC_209 208 -#define DEC_208 207 -#define DEC_207 206 -#define DEC_206 205 -#define DEC_205 204 -#define DEC_204 203 -#define DEC_203 202 -#define DEC_202 201 -#define DEC_201 200 -#define DEC_200 199 -#define DEC_199 198 -#define DEC_198 197 -#define DEC_197 196 -#define DEC_196 195 -#define DEC_195 194 -#define DEC_194 193 -#define DEC_193 192 -#define DEC_192 191 -#define DEC_191 190 -#define DEC_190 189 -#define DEC_189 188 -#define DEC_188 187 -#define DEC_187 186 -#define DEC_186 185 -#define DEC_185 184 -#define DEC_184 183 -#define DEC_183 182 -#define DEC_182 181 -#define DEC_181 180 -#define DEC_180 179 -#define DEC_179 178 -#define DEC_178 177 -#define DEC_177 176 -#define DEC_176 175 -#define DEC_175 174 -#define DEC_174 173 -#define DEC_173 172 -#define DEC_172 171 -#define DEC_171 170 -#define DEC_170 169 -#define DEC_169 168 -#define DEC_168 167 -#define DEC_167 166 -#define DEC_166 165 -#define DEC_165 164 -#define DEC_164 163 -#define DEC_163 162 -#define DEC_162 161 -#define DEC_161 160 -#define DEC_160 159 -#define DEC_159 158 -#define DEC_158 157 -#define DEC_157 156 -#define DEC_156 155 -#define DEC_155 154 -#define DEC_154 153 -#define DEC_153 152 -#define DEC_152 151 -#define DEC_151 150 -#define DEC_150 149 -#define DEC_149 148 -#define DEC_148 147 -#define DEC_147 146 -#define DEC_146 145 -#define DEC_145 144 -#define DEC_144 143 -#define DEC_143 142 -#define DEC_142 141 -#define DEC_141 140 -#define DEC_140 139 -#define DEC_139 138 -#define DEC_138 137 -#define DEC_137 136 -#define DEC_136 135 -#define DEC_135 134 -#define DEC_134 133 -#define DEC_133 132 -#define DEC_132 131 -#define DEC_131 130 -#define DEC_130 129 -#define DEC_129 128 -#define DEC_128 127 -#define DEC_127 126 -#define DEC_126 125 -#define DEC_125 124 -#define DEC_124 123 -#define DEC_123 122 -#define DEC_122 121 -#define DEC_121 120 -#define DEC_120 119 -#define DEC_119 118 -#define DEC_118 117 -#define DEC_117 116 -#define DEC_116 115 -#define DEC_115 114 -#define DEC_114 113 -#define DEC_113 112 -#define DEC_112 111 -#define DEC_111 110 -#define DEC_110 109 -#define DEC_109 108 -#define DEC_108 107 -#define DEC_107 106 -#define DEC_106 105 -#define DEC_105 104 -#define DEC_104 103 -#define DEC_103 102 -#define DEC_102 101 -#define DEC_101 100 -#define DEC_100 99 -#define DEC_99 98 -#define DEC_98 97 -#define DEC_97 96 -#define DEC_96 95 -#define DEC_95 94 -#define DEC_94 93 -#define DEC_93 92 -#define DEC_92 91 -#define DEC_91 90 -#define DEC_90 89 -#define DEC_89 88 -#define DEC_88 87 -#define DEC_87 86 -#define DEC_86 85 -#define DEC_85 84 -#define DEC_84 83 -#define DEC_83 82 -#define DEC_82 81 -#define DEC_81 80 -#define DEC_80 79 -#define DEC_79 78 -#define DEC_78 77 -#define DEC_77 76 -#define DEC_76 75 -#define DEC_75 74 -#define DEC_74 73 -#define DEC_73 72 -#define DEC_72 71 -#define DEC_71 70 -#define DEC_70 69 -#define DEC_69 68 -#define DEC_68 67 -#define DEC_67 66 -#define DEC_66 65 -#define DEC_65 64 -#define DEC_64 63 -#define DEC_63 62 -#define DEC_62 61 -#define DEC_61 60 -#define DEC_60 59 -#define DEC_59 58 -#define DEC_58 57 -#define DEC_57 56 -#define DEC_56 55 -#define DEC_55 54 -#define DEC_54 53 -#define DEC_53 52 -#define DEC_52 51 -#define DEC_51 50 -#define DEC_50 49 -#define DEC_49 48 -#define DEC_48 47 -#define DEC_47 46 -#define DEC_46 45 -#define DEC_45 44 -#define DEC_44 43 -#define DEC_43 42 -#define DEC_42 41 -#define DEC_41 40 -#define DEC_40 39 -#define DEC_39 38 -#define DEC_38 37 -#define DEC_37 36 -#define DEC_36 35 -#define DEC_35 34 -#define DEC_34 33 -#define DEC_33 32 -#define DEC_32 31 -#define DEC_31 30 -#define DEC_30 29 -#define DEC_29 28 -#define DEC_28 27 -#define DEC_27 26 -#define DEC_26 25 -#define DEC_25 24 -#define DEC_24 23 -#define DEC_23 22 -#define DEC_22 21 -#define DEC_21 20 -#define DEC_20 19 -#define DEC_19 18 -#define DEC_18 17 -#define DEC_17 16 -#define DEC_16 15 -#define DEC_15 14 -#define DEC_14 13 -#define DEC_13 12 -#define DEC_12 11 -#define DEC_11 10 -#define DEC_10 9 -#define DEC_9 8 -#define DEC_8 7 -#define DEC_7 6 -#define DEC_6 5 -#define DEC_5 4 -#define DEC_4 3 -#define DEC_3 2 -#define DEC_2 1 -#define DEC_1 0 - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_DECREMENT_MACRO_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_event.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_event.h deleted file mode 100644 index 48d9c88d5..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/utils_event.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - * \file - * - * \brief Events declaration. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_EVENT_H_INCLUDED -#define _UTILS_EVENT_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * \brief The maximum amount of events - */ -#define EVENT_MAX_AMOUNT 8 - -/** - * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the - * closest number divisible by 8. - */ -#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) - -/** - * \brief The type of event ID. IDs should start with 0 and be in numerical order. - */ -typedef uint8_t event_id_t; - -/** - * \brief The type of returned parameter. This type is big enough to contain - * pointer to data on any platform. - */ -typedef uintptr_t event_data_t; - -/** - * \brief The type of returned parameter. This type is big enough to contain - * pointer to data on any platform. - */ -typedef void (*event_cb_t)(event_id_t id, event_data_t data); - -/** - * \brief Event structure - */ -struct event { - struct list_element elem; /*! The pointer to next event */ - uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ - event_cb_t cb; /*! Callback to be called when an event occurs */ -}; - -/** - * \brief Subscribe to event - * - * \param[in] event The pointer to event structure - * \param[in] id The event ID to subscribe to - * \param[in] cb The callback function to call when the given event occurs - * - * \return The status of subscription - */ -int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); - -/** - * \brief Remove event from subscription - * - * \param[in] event The pointer to event structure - * \param[in] id The event ID to remove subscription from - * - * \return The status of subscription removing - */ -int32_t event_unsubscribe(struct event *const event, const event_id_t id); - -/** - * \brief Post event - * - * \param[in] id The event ID to post - * \param[in] data The event data to be passed to event subscribers - */ -void event_post(const event_id_t id, const event_data_t data); - -#ifdef __cplusplus -} -#endif - -#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_increment_macro.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_increment_macro.h deleted file mode 100644 index 9bbc63ff3..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/utils_increment_macro.h +++ /dev/null @@ -1,318 +0,0 @@ -/** - * \file - * - * \brief Increment macro. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_INCREMENT_MACRO_H -#define _UTILS_INCREMENT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Compile time increment, result value is entire integer literal - * - * \param[in] val - value to be incremented (254 max) - */ -#define INC_VALUE(val) SP_INC_##val - -// Preprocessor increment implementation -#define SP_INC_0 1 -#define SP_INC_1 2 -#define SP_INC_2 3 -#define SP_INC_3 4 -#define SP_INC_4 5 -#define SP_INC_5 6 -#define SP_INC_6 7 -#define SP_INC_7 8 -#define SP_INC_8 9 -#define SP_INC_9 10 -#define SP_INC_10 11 -#define SP_INC_11 12 -#define SP_INC_12 13 -#define SP_INC_13 14 -#define SP_INC_14 15 -#define SP_INC_15 16 -#define SP_INC_16 17 -#define SP_INC_17 18 -#define SP_INC_18 19 -#define SP_INC_19 20 -#define SP_INC_20 21 -#define SP_INC_21 22 -#define SP_INC_22 23 -#define SP_INC_23 24 -#define SP_INC_24 25 -#define SP_INC_25 26 -#define SP_INC_26 27 -#define SP_INC_27 28 -#define SP_INC_28 29 -#define SP_INC_29 30 -#define SP_INC_30 31 -#define SP_INC_31 32 -#define SP_INC_32 33 -#define SP_INC_33 34 -#define SP_INC_34 35 -#define SP_INC_35 36 -#define SP_INC_36 37 -#define SP_INC_37 38 -#define SP_INC_38 39 -#define SP_INC_39 40 -#define SP_INC_40 41 -#define SP_INC_41 42 -#define SP_INC_42 43 -#define SP_INC_43 44 -#define SP_INC_44 45 -#define SP_INC_45 46 -#define SP_INC_46 47 -#define SP_INC_47 48 -#define SP_INC_48 49 -#define SP_INC_49 50 -#define SP_INC_50 51 -#define SP_INC_51 52 -#define SP_INC_52 53 -#define SP_INC_53 54 -#define SP_INC_54 55 -#define SP_INC_55 56 -#define SP_INC_56 57 -#define SP_INC_57 58 -#define SP_INC_58 59 -#define SP_INC_59 60 -#define SP_INC_60 61 -#define SP_INC_61 62 -#define SP_INC_62 63 -#define SP_INC_63 64 -#define SP_INC_64 65 -#define SP_INC_65 66 -#define SP_INC_66 67 -#define SP_INC_67 68 -#define SP_INC_68 69 -#define SP_INC_69 70 -#define SP_INC_70 71 -#define SP_INC_71 72 -#define SP_INC_72 73 -#define SP_INC_73 74 -#define SP_INC_74 75 -#define SP_INC_75 76 -#define SP_INC_76 77 -#define SP_INC_77 78 -#define SP_INC_78 79 -#define SP_INC_79 80 -#define SP_INC_80 81 -#define SP_INC_81 82 -#define SP_INC_82 83 -#define SP_INC_83 84 -#define SP_INC_84 85 -#define SP_INC_85 86 -#define SP_INC_86 87 -#define SP_INC_87 88 -#define SP_INC_88 89 -#define SP_INC_89 90 -#define SP_INC_90 91 -#define SP_INC_91 92 -#define SP_INC_92 93 -#define SP_INC_93 94 -#define SP_INC_94 95 -#define SP_INC_95 96 -#define SP_INC_96 97 -#define SP_INC_97 98 -#define SP_INC_98 99 -#define SP_INC_99 100 -#define SP_INC_100 101 -#define SP_INC_101 102 -#define SP_INC_102 103 -#define SP_INC_103 104 -#define SP_INC_104 105 -#define SP_INC_105 106 -#define SP_INC_106 107 -#define SP_INC_107 108 -#define SP_INC_108 109 -#define SP_INC_109 110 -#define SP_INC_110 111 -#define SP_INC_111 112 -#define SP_INC_112 113 -#define SP_INC_113 114 -#define SP_INC_114 115 -#define SP_INC_115 116 -#define SP_INC_116 117 -#define SP_INC_117 118 -#define SP_INC_118 119 -#define SP_INC_119 120 -#define SP_INC_120 121 -#define SP_INC_121 122 -#define SP_INC_122 123 -#define SP_INC_123 124 -#define SP_INC_124 125 -#define SP_INC_125 126 -#define SP_INC_126 127 -#define SP_INC_127 128 -#define SP_INC_128 129 -#define SP_INC_129 130 -#define SP_INC_130 131 -#define SP_INC_131 132 -#define SP_INC_132 133 -#define SP_INC_133 134 -#define SP_INC_134 135 -#define SP_INC_135 136 -#define SP_INC_136 137 -#define SP_INC_137 138 -#define SP_INC_138 139 -#define SP_INC_139 140 -#define SP_INC_140 141 -#define SP_INC_141 142 -#define SP_INC_142 143 -#define SP_INC_143 144 -#define SP_INC_144 145 -#define SP_INC_145 146 -#define SP_INC_146 147 -#define SP_INC_147 148 -#define SP_INC_148 149 -#define SP_INC_149 150 -#define SP_INC_150 151 -#define SP_INC_151 152 -#define SP_INC_152 153 -#define SP_INC_153 154 -#define SP_INC_154 155 -#define SP_INC_155 156 -#define SP_INC_156 157 -#define SP_INC_157 158 -#define SP_INC_158 159 -#define SP_INC_159 160 -#define SP_INC_160 161 -#define SP_INC_161 162 -#define SP_INC_162 163 -#define SP_INC_163 164 -#define SP_INC_164 165 -#define SP_INC_165 166 -#define SP_INC_166 167 -#define SP_INC_167 168 -#define SP_INC_168 169 -#define SP_INC_169 170 -#define SP_INC_170 171 -#define SP_INC_171 172 -#define SP_INC_172 173 -#define SP_INC_173 174 -#define SP_INC_174 175 -#define SP_INC_175 176 -#define SP_INC_176 177 -#define SP_INC_177 178 -#define SP_INC_178 179 -#define SP_INC_179 180 -#define SP_INC_180 181 -#define SP_INC_181 182 -#define SP_INC_182 183 -#define SP_INC_183 184 -#define SP_INC_184 185 -#define SP_INC_185 186 -#define SP_INC_186 187 -#define SP_INC_187 188 -#define SP_INC_188 189 -#define SP_INC_189 190 -#define SP_INC_190 191 -#define SP_INC_191 192 -#define SP_INC_192 193 -#define SP_INC_193 194 -#define SP_INC_194 195 -#define SP_INC_195 196 -#define SP_INC_196 197 -#define SP_INC_197 198 -#define SP_INC_198 199 -#define SP_INC_199 200 -#define SP_INC_200 201 -#define SP_INC_201 202 -#define SP_INC_202 203 -#define SP_INC_203 204 -#define SP_INC_204 205 -#define SP_INC_205 206 -#define SP_INC_206 207 -#define SP_INC_207 208 -#define SP_INC_208 209 -#define SP_INC_209 210 -#define SP_INC_210 211 -#define SP_INC_211 212 -#define SP_INC_212 213 -#define SP_INC_213 214 -#define SP_INC_214 215 -#define SP_INC_215 216 -#define SP_INC_216 217 -#define SP_INC_217 218 -#define SP_INC_218 219 -#define SP_INC_219 220 -#define SP_INC_220 221 -#define SP_INC_221 222 -#define SP_INC_222 223 -#define SP_INC_223 224 -#define SP_INC_224 225 -#define SP_INC_225 226 -#define SP_INC_226 227 -#define SP_INC_227 228 -#define SP_INC_228 229 -#define SP_INC_229 230 -#define SP_INC_230 231 -#define SP_INC_231 232 -#define SP_INC_232 233 -#define SP_INC_233 234 -#define SP_INC_234 235 -#define SP_INC_235 236 -#define SP_INC_236 237 -#define SP_INC_237 238 -#define SP_INC_238 239 -#define SP_INC_239 240 -#define SP_INC_240 241 -#define SP_INC_241 242 -#define SP_INC_242 243 -#define SP_INC_243 244 -#define SP_INC_244 245 -#define SP_INC_245 246 -#define SP_INC_246 247 -#define SP_INC_247 248 -#define SP_INC_248 249 -#define SP_INC_249 250 -#define SP_INC_250 251 -#define SP_INC_251 252 -#define SP_INC_252 253 -#define SP_INC_253 254 -#define SP_INC_254 255 - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_list.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_list.h deleted file mode 100644 index 8d049ff1b..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/utils_list.h +++ /dev/null @@ -1,174 +0,0 @@ -/** - * \file - * - * \brief List declaration. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_LIST_H_INCLUDED -#define _UTILS_LIST_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup doc_driver_hal_utils_list - * - * @{ - */ - -#include - -/** - * \brief List element type - */ -struct list_element { - struct list_element *next; -}; - -/** - * \brief List head type - */ -struct list_descriptor { - struct list_element *head; -}; - -/** - * \brief Reset list - * - * \param[in] list The pointer to a list descriptor - */ -static inline void list_reset(struct list_descriptor *const list) -{ - list->head = NULL; -} - -/** - * \brief Retrieve list head - * - * \param[in] list The pointer to a list descriptor - * - * \return A pointer to the head of the given list or NULL if the list is - * empty - */ -static inline void *list_get_head(const struct list_descriptor *const list) -{ - return (void *)list->head; -} - -/** - * \brief Retrieve next list head - * - * \param[in] list The pointer to a list element - * - * \return A pointer to the next list element or NULL if there is not next - * element - */ -static inline void *list_get_next_element(const void *const element) -{ - return element ? ((struct list_element *)element)->next : NULL; -} - -/** - * \brief Insert an element as list head - * - * \param[in] list The pointer to a list element - * \param[in] element An element to insert to the given list - */ -void list_insert_as_head(struct list_descriptor *const list, void *const element); - -/** - * \brief Insert an element after the given list element - * - * \param[in] after An element to insert after - * \param[in] element Element to insert to the given list - */ -void list_insert_after(void *const after, void *const element); - -/** - * \brief Insert an element at list end - * - * \param[in] after An element to insert after - * \param[in] element Element to insert to the given list - */ -void list_insert_at_end(struct list_descriptor *const list, void *const element); - -/** - * \brief Check whether an element belongs to a list - * - * \param[in] list The pointer to a list - * \param[in] element An element to check - * - * \return The result of checking - * \retval true If the given element is an element of the given list - * \retval false Otherwise - */ -bool is_list_element(const struct list_descriptor *const list, const void *const element); - -/** - * \brief Removes list head - * - * This function removes the list head and sets the next element after the list - * head as a new list head. - * - * \param[in] list The pointer to a list - * - * \return The pointer to the new list head of NULL if the list head is NULL - */ -void *list_remove_head(struct list_descriptor *const list); - -/** - * \brief Removes the list element - * - * \param[in] list The pointer to a list - * \param[in] element An element to remove - * - * \return The result of element removing - * \retval true The given element is removed from the given list - * \retval false The given element is not an element of the given list - */ -bool list_delete_element(struct list_descriptor *const list, const void *const element); - -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_recursion_macro.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_recursion_macro.h deleted file mode 100644 index fcc625cd9..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/utils_recursion_macro.h +++ /dev/null @@ -1,79 +0,0 @@ -/** - * \file - * - * \brief Recursion macro. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_RECURSION_MACRO_H -#define _UTILS_RECURSION_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * \brief Macro recursion - * - * \param[in] macro Macro to be repeated recursively - * \param[in] arg A recursive threshold, building on this to decline by times - * defined with parameter n - * \param[in] n The number of repetitious calls to macro - */ -#define RECURSION_MACRO(macro, arg, n) RECURSION_MACRO_I(macro, arg, n) - -/* - * \brief Second level is needed to get integer literal from "n" if it is - * defined as macro - */ -#define RECURSION_MACRO_I(macro, arg, n) RECURSION##n(macro, arg) - -#define RECURSION0(macro, arg) -#define RECURSION1(macro, arg) RECURSION0(macro, DEC_VALUE(arg)) macro(arg, 0) -#define RECURSION2(macro, arg) RECURSION1(macro, DEC_VALUE(arg)) macro(arg, 1) -#define RECURSION3(macro, arg) RECURSION2(macro, DEC_VALUE(arg)) macro(arg, 2) -#define RECURSION4(macro, arg) RECURSION3(macro, DEC_VALUE(arg)) macro(arg, 3) -#define RECURSION5(macro, arg) RECURSION4(macro, DEC_VALUE(arg)) macro(arg, 4) - -#ifdef __cplusplus -} -#endif - -#include -#endif /* _UTILS_RECURSION_MACRO_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/include/utils_repeat_macro.h b/atmel-samd/asf4/samd51/hal/utils/include/utils_repeat_macro.h deleted file mode 100644 index aeed75d5c..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/include/utils_repeat_macro.h +++ /dev/null @@ -1,332 +0,0 @@ -/** - * \file - * - * \brief Repeat macro. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _UTILS_REPEAT_MACRO_H -#define _UTILS_REPEAT_MACRO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * \brief Sequently repeates specified macro for n times (255 max). - * - * Specified macro shall have two arguments: macro(arg, i) - * arg - user defined argument, which have the same value for all iterations. - * i - iteration number; numbering begins from zero and increments on each - * iteration. - * - * \param[in] macro - macro to be repeated - * \param[in] arg - user defined argument for repeated macro - * \param[in] n - total number of iterations (255 max) - */ -#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) - -/* - * \brief Second level is needed to get integer literal from "n" if it is - * defined as macro - */ -#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) - -#define REPEAT1(macro, arg, n) macro(arg, n) -#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) -#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) -#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) -#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) -#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) -#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) -#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) -#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) -#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) -#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) -#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) -#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) -#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) -#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) -#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) -#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) -#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) -#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) -#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) -#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) -#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) -#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) -#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) -#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) -#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) -#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) -#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) -#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) -#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) -#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) -#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) -#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) -#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) -#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) -#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) -#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) -#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) -#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) -#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) -#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) -#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) -#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) -#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) -#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) -#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) -#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) -#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) -#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) -#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) -#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) -#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) -#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) -#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) -#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) -#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) -#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) -#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) -#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) -#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) -#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) -#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) -#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) -#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) -#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) -#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) -#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) -#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) -#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) -#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) -#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) -#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) -#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) -#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) -#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) -#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) -#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) -#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) -#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) -#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) -#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) -#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) -#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) -#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) -#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) -#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) -#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) -#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) -#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) -#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) -#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) -#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) -#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) -#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) -#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) -#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) -#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) -#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) -#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) -#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) -#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) -#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) -#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) -#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) -#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) -#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) -#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) -#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) -#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) -#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) -#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) -#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) -#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) -#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) -#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) -#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) -#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) -#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) -#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) -#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) -#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) -#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) -#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) -#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) -#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) -#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) -#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) -#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) -#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) -#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) -#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) -#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) -#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) -#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) -#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) -#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) -#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) -#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) -#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) -#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) -#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) -#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) -#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) -#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) -#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) -#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) -#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) -#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) -#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) -#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) -#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) -#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) -#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) -#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) -#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) -#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) -#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) -#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) -#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) -#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) -#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) -#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) -#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) -#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) -#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) -#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) -#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) -#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) -#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) -#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) -#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) -#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) -#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) -#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) -#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) -#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) -#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) -#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) -#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) -#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) -#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) -#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) -#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) -#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) -#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) -#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) -#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) -#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) -#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) -#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) -#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) -#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) -#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) -#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) -#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) -#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) -#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) -#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) -#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) -#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) -#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) -#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) -#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) -#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) -#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) -#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) -#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) -#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) -#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) -#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) -#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) -#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) -#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) -#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) -#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) -#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) -#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) -#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) -#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) -#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) -#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) -#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) -#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) -#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) -#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) -#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) -#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) -#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) -#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) -#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) -#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) -#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) -#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) -#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) -#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) -#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) -#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) -#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) -#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) -#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) -#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) -#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) -#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) -#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) -#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) -#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) -#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) -#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) -#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) -#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) -#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) -#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) -#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) -#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) -#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) - -#ifdef __cplusplus -} -#endif - -#include -#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/atmel-samd/asf4/samd51/hal/utils/src/utils_assert.c b/atmel-samd/asf4/samd51/hal/utils/src/utils_assert.c deleted file mode 100644 index 9fe56827c..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/src/utils_assert.c +++ /dev/null @@ -1,56 +0,0 @@ -/** - * \file - * - * \brief Asserts related functionality. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUFDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include - -/** - * \brief Assert function - */ -void assert(const bool condition, const char *const file, const int line) -{ - if (!(condition)) { - __asm("BKPT #0"); - } - (void)file; - (void)line; -} diff --git a/atmel-samd/asf4/samd51/hal/utils/src/utils_event.c b/atmel-samd/asf4/samd51/hal/utils/src/utils_event.c deleted file mode 100644 index ab4e9eb3f..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/src/utils_event.c +++ /dev/null @@ -1,135 +0,0 @@ -/** - * \file - * - * \brief Events implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSEsD AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) - -static struct list_descriptor events; -static uint8_t subscribed[EVENT_MASK_SIZE]; - -int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - - ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); - - if (event->mask[position] & mask) { - return ERR_NO_CHANGE; /* Already subscribed */ - } - - if (!is_list_element(&events, event)) { - memset(event->mask, 0, EVENT_MASK_SIZE); - list_insert_as_head(&events, event); - } - event->cb = cb; - event->mask[position] |= mask; - - subscribed[position] |= mask; - - return ERR_NONE; -} - -int32_t event_unsubscribe(struct event *const event, const event_id_t id) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - const struct event *current; - uint8_t i; - - ASSERT(event && (id < EVENT_MAX_AMOUNT)); - - if (!(event->mask[position] & mask)) { - return ERR_NO_CHANGE; /* Already unsubscribed */ - } - - event->mask[position] &= ~mask; - - /* Check if there are more subscribers */ - for ((current = (const struct event *)list_get_head(&events)); current; - current = (const struct event *)list_get_next_element(current)) { - if (current->mask[position] & mask) { - break; - } - } - if (!current) { - subscribed[position] &= ~mask; - } - - /* Remove event from the list. Can be unsave, document it! */ - for (i = 0; i < ARRAY_SIZE(event->mask); i++) { - if (event->mask[i]) { - return ERR_NONE; - } - } - list_delete_element(&events, event); - - return ERR_NONE; -} - -void event_post(const event_id_t id, const event_data_t data) -{ - /* get byte and bit number of the given event in the event mask */ - const uint8_t position = id >> 3; - const uint8_t mask = 1 << (id & 0x7); - const struct event *current; - - ASSERT((id < EVENT_MAX_AMOUNT)); - - if (!(subscribed[position] & mask)) { - return; /* No subscribers */ - } - - /* Find all subscribers */ - for ((current = (const struct event *)list_get_head(&events)); current; - current = (const struct event *)list_get_next_element(current)) { - if (current->mask[position] & mask) { - current->cb(id, data); - } - } -} diff --git a/atmel-samd/asf4/samd51/hal/utils/src/utils_list.c b/atmel-samd/asf4/samd51/hal/utils/src/utils_list.c deleted file mode 100644 index eaf5f3410..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/src/utils_list.c +++ /dev/null @@ -1,146 +0,0 @@ -/** - * \file - * - * \brief List functionality implementation. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Check whether element belongs to list - */ -bool is_list_element(const struct list_descriptor *const list, const void *const element) -{ - struct list_element *it; - for (it = list->head; it; it = it->next) { - if (it == element) { - return true; - } - } - - return false; -} - -/** - * \brief Insert an element as list head - */ -void list_insert_as_head(struct list_descriptor *const list, void *const element) -{ - ASSERT(!is_list_element(list, element)); - - ((struct list_element *)element)->next = list->head; - list->head = (struct list_element *)element; -} - -/** - * \brief Insert an element after the given list element - */ -void list_insert_after(void *const after, void *const element) -{ - ((struct list_element *)element)->next = ((struct list_element *)after)->next; - ((struct list_element *)after)->next = (struct list_element *)element; -} - -/** - * \brief Insert an element at list end - */ -void list_insert_at_end(struct list_descriptor *const list, void *const element) -{ - struct list_element *it = list->head; - - ASSERT(!is_list_element(list, element)); - - if (!list->head) { - list->head = (struct list_element *)element; - ((struct list_element *)element)->next = NULL; - return; - } - - while (it->next) { - it = it->next; - } - it->next = (struct list_element *)element; - ((struct list_element *)element)->next = NULL; -} - -/** - * \brief Removes list head - */ -void *list_remove_head(struct list_descriptor *const list) -{ - if (list->head) { - struct list_element *tmp = list->head; - - list->head = list->head->next; - return (void *)tmp; - } - - return NULL; -} - -/** - * \brief Removes list element - */ -bool list_delete_element(struct list_descriptor *const list, const void *const element) -{ - if (!element) { - return false; - } - - if (list->head == element) { - list->head = list->head->next; - return true; - } else { - struct list_element *it = list->head; - - while (it && it->next != element) { - it = it->next; - } - if (it) { - it->next = ((struct list_element *)element)->next; - return true; - } - } - - return false; -} - -//@} diff --git a/atmel-samd/asf4/samd51/hal/utils/src/utils_syscalls.c b/atmel-samd/asf4/samd51/hal/utils/src/utils_syscalls.c deleted file mode 100644 index 7adad249a..000000000 --- a/atmel-samd/asf4/samd51/hal/utils/src/utils_syscalls.c +++ /dev/null @@ -1,162 +0,0 @@ -/** - * \file - * - * \brief Syscalls for SAM0 (GCC). - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#undef errno -extern int errno; -extern int _end; - -extern caddr_t _sbrk(int incr); -extern int link(char *old, char *_new); -extern int _close(int file); -extern int _fstat(int file, struct stat *st); -extern int _isatty(int file); -extern int _lseek(int file, int ptr, int dir); -extern void _exit(int status); -extern void _kill(int pid, int sig); -extern int _getpid(void); - -/** - * \brief Replacement of C library of _sbrk - */ -extern caddr_t _sbrk(int incr) -{ - static unsigned char *heap = NULL; - unsigned char * prev_heap; - - if (heap == NULL) { - heap = (unsigned char *)&_end; - } - prev_heap = heap; - - heap += incr; - - return (caddr_t)prev_heap; -} - -/** - * \brief Replacement of C library of link - */ -extern int link(char *old, char *_new) -{ - (void)old, (void)_new; - return -1; -} - -/** - * \brief Replacement of C library of _close - */ -extern int _close(int file) -{ - (void)file; - return -1; -} - -/** - * \brief Replacement of C library of _fstat - */ -extern int _fstat(int file, struct stat *st) -{ - (void)file; - st->st_mode = S_IFCHR; - - return 0; -} - -/** - * \brief Replacement of C library of _isatty - */ -extern int _isatty(int file) -{ - (void)file; - return 1; -} - -/** - * \brief Replacement of C library of _lseek - */ -extern int _lseek(int file, int ptr, int dir) -{ - (void)file, (void)ptr, (void)dir; - return 0; -} - -/** - * \brief Replacement of C library of _exit - */ -extern void _exit(int status) -{ - printf("Exiting with status %d.\n", status); - - for (;;) - ; -} - -/** - * \brief Replacement of C library of _kill - */ -extern void _kill(int pid, int sig) -{ - (void)pid, (void)sig; - return; -} - -/** - * \brief Replacement of C library of _getpid - */ -extern int _getpid(void) -{ - return -1; -} - -#ifdef __cplusplus -} -#endif diff --git a/atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c b/atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c deleted file mode 100644 index b35ee2aea..000000000 --- a/atmel-samd/asf4/samd51/hpl/adc/hpl_adc.c +++ /dev/null @@ -1,786 +0,0 @@ - -/** - * \file - * - * \brief SAM Analog Digital Converter - * - * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include -#include -#include - -#ifndef CONF_ADC_0_ENABLE -#define CONF_ADC_0_ENABLE 0 -#endif -#ifndef CONF_ADC_1_ENABLE -#define CONF_ADC_1_ENABLE 0 -#endif - -/** - * \brief Macro is used to fill ADC configuration structure based on its number - * - * \param[in] n The number of structures - */ -#define ADC_CONFIGURATION(n) \ - { \ - (n), (CONF_ADC_##n##_RUNSTDBY << ADC_CTRLA_RUNSTDBY_Pos) | (CONF_ADC_##n##_ONDEMAND << ADC_CTRLA_ONDEMAND_Pos) \ - | ADC_CTRLA_PRESCALER(CONF_ADC_##n##_PRESCALER), \ - ADC_CTRLB_RESSEL(CONF_ADC_##n##_RESSEL) | (CONF_ADC_##n##_CORREN << ADC_CTRLB_CORREN_Pos) \ - | (CONF_ADC_##n##_FREERUN << ADC_CTRLB_FREERUN_Pos) \ - | (CONF_ADC_##n##_LEFTADJ << ADC_CTRLB_LEFTADJ_Pos) | ADC_CTRLB_WINMODE(CONF_ADC_##n##_WINMODE), \ - (CONF_ADC_##n##_REFCOMP << ADC_REFCTRL_REFCOMP_Pos) | ADC_REFCTRL_REFSEL(CONF_ADC_##n##_REFSEL), \ - (CONF_ADC_##n##_WINMONEO << ADC_EVCTRL_WINMONEO_Pos) \ - | (CONF_ADC_##n##_RESRDYEO << ADC_EVCTRL_RESRDYEO_Pos) \ - | (CONF_ADC_##n##_STARTINV << ADC_EVCTRL_STARTINV_Pos) \ - | (CONF_ADC_##n##_FLUSHINV << ADC_EVCTRL_FLUSHINV_Pos) \ - | (CONF_ADC_##n##_STARTEI << ADC_EVCTRL_STARTEI_Pos) \ - | (CONF_ADC_##n##_FLUSHEI << ADC_EVCTRL_FLUSHEI_Pos), \ - (CONF_ADC_##n##_DIFFMODE << ADC_INPUTCTRL_DIFFMODE_Pos) | ADC_INPUTCTRL_MUXNEG(CONF_ADC_##n##_MUXNEG) \ - | ADC_INPUTCTRL_MUXPOS(CONF_ADC_##n##_MUXPOS), \ - ADC_AVGCTRL_ADJRES(CONF_ADC_##n##_ADJRES) | ADC_AVGCTRL_SAMPLENUM(CONF_ADC_##n##_SAMPLENUM), \ - (CONF_ADC_##n##_OFFCOMP << ADC_SAMPCTRL_OFFCOMP_Pos) | ADC_SAMPCTRL_SAMPLEN(CONF_ADC_##n##_SAMPLEN), \ - ADC_WINLT_WINLT(CONF_ADC_##n##_WINLT), ADC_WINUT_WINUT(CONF_ADC_##n##_WINUT), \ - ADC_GAINCORR_GAINCORR(CONF_ADC_##n##_GAINCORR), ADC_OFFSETCORR_OFFSETCORR(CONF_ADC_##n##_OFFSETCORR), \ - CONF_ADC_##n##_DBGRUN << ADC_DBGCTRL_DBGRUN_Pos, \ - } - -/** - * \brief ADC configuration - */ -struct adc_configuration { - uint8_t number; - hri_adc_ctrla_reg_t ctrl_a; - hri_adc_ctrlb_reg_t ctrl_b; - hri_adc_refctrl_reg_t ref_ctrl; - hri_adc_evctrl_reg_t ev_ctrl; - hri_adc_inputctrl_reg_t input_ctrl; - hri_adc_avgctrl_reg_t avg_ctrl; - hri_adc_sampctrl_reg_t samp_ctrl; - hri_adc_winlt_reg_t win_lt; - hri_adc_winut_reg_t win_ut; - hri_adc_gaincorr_reg_t gain_corr; - hri_adc_offsetcorr_reg_t offset_corr; - hri_adc_dbgctrl_reg_t dbg_ctrl; -}; - -#define ADC_AMOUNT (CONF_ADC_0_ENABLE + CONF_ADC_1_ENABLE) - -/** - * \brief Array of ADC configurations - */ -static const struct adc_configuration _adcs[] = { -#if CONF_ADC_0_ENABLE == 1 - ADC_CONFIGURATION(0), -#endif -#if CONF_ADC_1_ENABLE == 1 - ADC_CONFIGURATION(1), -#endif -}; - -static void _adc_set_reference_source(void *const hw, const adc_reference_t reference); - -/** - * \brief Retrieve ordinal number of the given adc hardware instance - */ -static uint8_t _adc_get_hardware_index(const void *const hw) -{ - return ((uint32_t)hw - (uint32_t)ADC0) >> 10; -} - -/** \brief Return the pointer to register settings of specific ADC - * \param[in] hw_addr The hardware register base address. - * \return Pointer to register settings of specific ADC. - */ -static uint8_t _adc_get_regs(const uint32_t hw_addr) -{ - uint8_t n = _adc_get_hardware_index((const void *)hw_addr); - uint8_t i; - - for (i = 0; i < sizeof(_adcs) / sizeof(struct adc_configuration); i++) { - if (_adcs[i].number == n) { - return i; - } - } - - ASSERT(false); - return 0; -} - -/** - * \brief Retrieve IRQ number for the given hardware instance - */ -static uint8_t _adc_get_irq_num(const struct _adc_async_device *const device) -{ - - return ADC0_0_IRQn + (_adc_get_hardware_index(device->hw) << 1); -} - -/** - * \brief Init irq param with the given afec hardware instance - */ -static void _adc_init_irq_param(const void *const hw, struct _adc_async_device *dev) -{ -} - -/** - * \brief Initialize ADC - * - * \param[in] hw The pointer to hardware instance - * \param[in] i The number of hardware instance - */ -static int32_t _adc_init(void *const hw, const uint8_t i) -{ - - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); - if (hri_adc_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_adc_set_CTRLA_SWRST_bit(hw); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); - - hri_adc_write_CTRLB_reg(hw, _adcs[i].ctrl_b); - hri_adc_write_REFCTRL_reg(hw, _adcs[i].ref_ctrl); - hri_adc_write_EVCTRL_reg(hw, _adcs[i].ev_ctrl); - hri_adc_write_INPUTCTRL_reg(hw, _adcs[i].input_ctrl); - hri_adc_write_AVGCTRL_reg(hw, _adcs[i].avg_ctrl); - hri_adc_write_SAMPCTRL_reg(hw, _adcs[i].samp_ctrl); - hri_adc_write_WINLT_reg(hw, _adcs[i].win_lt); - hri_adc_write_WINUT_reg(hw, _adcs[i].win_ut); - hri_adc_write_GAINCORR_reg(hw, _adcs[i].gain_corr); - hri_adc_write_OFFSETCORR_reg(hw, _adcs[i].offset_corr); - hri_adc_write_DBGCTRL_reg(hw, _adcs[i].dbg_ctrl); - hri_adc_write_CTRLA_reg(hw, _adcs[i].ctrl_a); - - return ERR_NONE; -} - -/** - * \brief De-initialize ADC - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _adc_deinit(void *hw) -{ - hri_adc_clear_CTRLA_ENABLE_bit(hw); - hri_adc_set_CTRLA_SWRST_bit(hw); -} - -/** - * \brief Initialize ADC - */ -int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw) -{ - ASSERT(device); - - device->hw = hw; - - return _adc_init(hw, _adc_get_regs((uint32_t)hw)); -} - -/** - * \brief Initialize ADC - */ -int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _adc_init(hw, _adc_get_regs((uint32_t)hw)); - if (init_status) { - return init_status; - } - device->hw = hw; - _adc_init_irq_param(hw, device); - NVIC_DisableIRQ(_adc_get_irq_num(device) + 0); - NVIC_ClearPendingIRQ(_adc_get_irq_num(device) + 0); - NVIC_EnableIRQ(_adc_get_irq_num(device) + 0); - NVIC_DisableIRQ(_adc_get_irq_num(device) + 1); - NVIC_ClearPendingIRQ(_adc_get_irq_num(device) + 1); - NVIC_EnableIRQ(_adc_get_irq_num(device) + 1); - return ERR_NONE; -} - -/** - * \brief Initialize ADC - */ -int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw) -{ - ASSERT(device); - - device->hw = hw; - - return _adc_init(hw, _adc_get_regs((uint32_t)hw)); -} - -/** - * \brief De-initialize ADC - */ -void _adc_sync_deinit(struct _adc_sync_device *const device) -{ - _adc_deinit(device->hw); -} - -/** - * \brief De-initialize ADC - */ -void _adc_async_deinit(struct _adc_async_device *const device) -{ - NVIC_DisableIRQ(_adc_get_irq_num(device)); - NVIC_ClearPendingIRQ(_adc_get_irq_num(device)); - - _adc_deinit(device->hw); -} - -/** - * \brief De-initialize ADC - */ -void _adc_dma_deinit(struct _adc_dma_device *const device) -{ - _adc_deinit(device->hw); -} - -/** - * \brief Enable ADC - */ -void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Enable ADC - */ -void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Enable ADC - */ -void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable ADC - */ -void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable ADC - */ -void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable ADC - */ -void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel) -{ - (void)channel; - - hri_adc_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Return address of ADC DMA source - */ -uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device) -{ - return (uint32_t) & (((Adc *)(device->hw))->RESULT.reg); -} - -/** - * \brief Retrieve ADC conversion data size - */ -uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device) -{ - return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; -} - -/** - * \brief Retrieve ADC conversion data size - */ -uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device) -{ - return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; -} - -/** - * \brief Retrieve ADC conversion data size - */ -uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device) -{ - return hri_adc_read_CTRLB_RESSEL_bf(device->hw) == ADC_CTRLB_RESSEL_8BIT_Val ? 1 : 2; -} - -/** - * \brief Check if conversion is done - */ -bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel) -{ - (void)channel; - - return hri_adc_get_interrupt_RESRDY_bit(device->hw); -} - -/** - * \brief Check if conversion is done - */ -bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel) -{ - (void)channel; - - return hri_adc_get_interrupt_RESRDY_bit(device->hw); -} - -/** - * \brief Check if conversion is done - */ -bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device) -{ - return hri_adc_get_interrupt_RESRDY_bit(device->hw); -} - -/** - * \brief Make conversion - */ -void _adc_sync_convert(struct _adc_sync_device *const device) -{ - hri_adc_set_SWTRIG_START_bit(device->hw); -} - -/** - * \brief Make conversion - */ -void _adc_async_convert(struct _adc_async_device *const device) -{ - hri_adc_set_SWTRIG_START_bit(device->hw); -} - -/** - * \brief Make conversion - */ -void _adc_dma_convert(struct _adc_dma_device *const device) -{ - hri_adc_set_SWTRIG_START_bit(device->hw); -} - -/** - * \brief Retrieve the conversion result - */ -uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel) -{ - (void)channel; - - return hri_adc_read_RESULT_reg(device->hw); -} - -/** - * \brief Retrieve the conversion result - */ -uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel) -{ - (void)channel; - - return hri_adc_read_RESULT_reg(device->hw); -} - -/** - * \brief Set reference source - */ -void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference) -{ - _adc_set_reference_source(device->hw, reference); -} - -/** - * \brief Set reference source - */ -void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference) -{ - _adc_set_reference_source(device->hw, reference); -} - -/** - * \brief Set reference source - */ -void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference) -{ - _adc_set_reference_source(device->hw, reference); -} - -/** - * \brief Set resolution - */ -void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution) -{ - hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution); -} - -/** - * \brief Set resolution - */ -void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution) -{ - hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution); -} - -/** - * \brief Set resolution - */ -void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution) -{ - hri_adc_write_CTRLB_RESSEL_bf(device->hw, resolution); -} - -/** - * \brief Set channels input sources - */ -void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel) -{ - (void)channel; - - hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); - hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); -} - -/** - * \brief Set channels input sources - */ -void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel) -{ - (void)channel; - - hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); - hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); -} - -/** - * \brief Set channels input source - */ -void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input, - const adc_neg_input_t neg_input, const uint8_t channel) -{ - (void)channel; - - hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input); - hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input); -} - -/** - * \brief Set thresholds - */ -void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold) -{ - hri_adc_write_WINLT_reg(device->hw, low_threshold); - hri_adc_write_WINUT_reg(device->hw, up_threshold); -} - -/** - * \brief Set thresholds - */ -void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold) -{ - hri_adc_write_WINLT_reg(device->hw, low_threshold); - hri_adc_write_WINUT_reg(device->hw, up_threshold); -} - -/** - * \brief Set thresholds - */ -void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold, - const adc_threshold_t up_threshold) -{ - hri_adc_write_WINLT_reg(device->hw, low_threshold); - hri_adc_write_WINUT_reg(device->hw, up_threshold); -} - -/** - * \brief Set gain - */ -void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain) -{ - (void)device, (void)channel, (void)gain; -} - -/** - * \brief Set gain - */ -void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain) -{ - (void)device, (void)channel, (void)gain; -} - -/** - * \brief Set gain - */ -void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain) -{ - (void)device, (void)channel, (void)gain; -} - -/** - * \brief Set conversion mode - */ -void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode) -{ - if (ADC_CONVERSION_MODE_FREERUN == mode) { - hri_adc_set_CTRLB_FREERUN_bit(device->hw); - } else { - hri_adc_clear_CTRLB_FREERUN_bit(device->hw); - } -} - -/** - * \brief Set conversion mode - */ -void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode) -{ - if (ADC_CONVERSION_MODE_FREERUN == mode) { - hri_adc_set_CTRLB_FREERUN_bit(device->hw); - } else { - hri_adc_clear_CTRLB_FREERUN_bit(device->hw); - } -} - -/** - * \brief Set conversion mode - */ -void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode) -{ - if (ADC_CONVERSION_MODE_FREERUN == mode) { - hri_adc_set_CTRLB_FREERUN_bit(device->hw); - } else { - hri_adc_clear_CTRLB_FREERUN_bit(device->hw); - } -} - -/** - * \brief Set differential mode - */ -void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel, - const enum adc_differential_mode mode) -{ - (void)channel; - - if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) { - hri_adc_set_INPUTCTRL_DIFFMODE_bit(device->hw); - } else { - hri_adc_clear_INPUTCTRL_DIFFMODE_bit(device->hw); - } -} - -/** - * \brief Set differential mode - */ -void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel, - const enum adc_differential_mode mode) -{ - (void)channel; - - if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) { - hri_adc_set_INPUTCTRL_DIFFMODE_bit(device->hw); - } else { - hri_adc_clear_INPUTCTRL_DIFFMODE_bit(device->hw); - } -} - -/** - * \brief Set differential mode - */ -void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel, - const enum adc_differential_mode mode) -{ - (void)channel; - - if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) { - hri_adc_set_INPUTCTRL_DIFFMODE_bit(device->hw); - } else { - hri_adc_clear_INPUTCTRL_DIFFMODE_bit(device->hw); - } -} - -/** - * \brief Set window mode - */ -void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode) -{ - hri_adc_write_CTRLB_WINMODE_bf(device->hw, mode); -} - -/** - * \brief Set window mode - */ -void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode) -{ - hri_adc_write_CTRLB_WINMODE_bf(device->hw, mode); -} - -/** - * \brief Set window mode - */ -void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode) -{ - hri_adc_write_CTRLB_WINMODE_bf(device->hw, mode); -} - -/** - * \brief Retrieve threshold state - */ -void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state) -{ - *state = hri_adc_get_interrupt_WINMON_bit(device->hw); -} - -/** - * \brief Retrieve threshold state - */ -void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state) -{ - *state = hri_adc_get_interrupt_WINMON_bit(device->hw); -} - -/** - * \brief Retrieve threshold state - */ -void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state) -{ - *state = hri_adc_get_interrupt_WINMON_bit(device->hw); -} - -/** - * \brief Enable/disable ADC channel interrupt - */ -void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel, - const enum _adc_async_callback_type type, const bool state) -{ - (void)channel; - - void *const hw = device->hw; - - if (ADC_ASYNC_DEVICE_MONITOR_CB == type) { - hri_adc_write_INTEN_WINMON_bit(hw, state); - } else if (ADC_ASYNC_DEVICE_ERROR_CB == type) { - hri_adc_write_INTEN_OVERRUN_bit(hw, state); - } else if (ADC_ASYNC_DEVICE_CONVERT_CB == type) { - hri_adc_write_INTEN_RESRDY_bit(hw, state); - } -} - -/** - * \internal ADC interrupt handler - * - * \param[in] p The pointer to interrupt parameter - */ -static void _adc_interrupt_handler(struct _adc_async_device *device) -{ - void *const hw = device->hw; - - if (hri_adc_get_interrupt_RESRDY_bit(hw)) { - hri_adc_clear_interrupt_RESRDY_bit(hw); - device->adc_async_ch_cb.convert_done(device, 0, hri_adc_read_RESULT_reg(hw)); - } else if (hri_adc_get_interrupt_OVERRUN_bit(hw)) { - hri_adc_clear_interrupt_OVERRUN_bit(hw); - device->adc_async_cb.error_cb(device, 0); - } else if (hri_adc_get_interrupt_WINMON_bit(hw)) { - hri_adc_clear_interrupt_WINMON_bit(hw); - device->adc_async_cb.window_cb(device, 0); - } -} - -/** - * \brief Retrieve ADC sync helper functions - */ -void *_adc_get_adc_sync(void) -{ - return (void *)NULL; -} - -/** - * \brief Retrieve ADC async helper functions - */ -void *_adc_get_adc_async(void) -{ - return (void *)NULL; -} - -/** - * \brief Set ADC reference source - * - * \param[in] hw The pointer to hardware instance - * \param[in] reference The reference to set - */ -static void _adc_set_reference_source(void *const hw, const adc_reference_t reference) -{ - bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw); - - hri_adc_clear_CTRLA_ENABLE_bit(hw); - hri_adc_write_REFCTRL_REFSEL_bf(hw, reference); - - if (enabled) { - hri_adc_set_CTRLA_ENABLE_bit(hw); - } -} diff --git a/atmel-samd/asf4/samd51/hpl/adc/hpl_adc_base.h b/atmel-samd/asf4/samd51/hpl/adc/hpl_adc_base.h deleted file mode 100644 index 2f9a333c9..000000000 --- a/atmel-samd/asf4/samd51/hpl/adc/hpl_adc_base.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * \file - * - * \brief ADC related functionality declaration. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_ADC_ADC_H_INCLUDED -#define _HPL_ADC_ADC_H_INCLUDED - -#include -#include - -/** - * \addtogroup HPL ADC - * - * \section hpl_adc_rev Revision History - * - v1.0.0 Initial Release - * - *@{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \name HPL functions - */ -//@{ - -/** - * \brief Retrieve ADC helper functions - * - * \return A pointer to set of ADC helper functions - */ -void *_adc_get_adc_sync(void); -void *_adc_get_adc_async(void); - -//@} - -#ifdef __cplusplus -} -#endif -/**@}*/ -#endif /* _HPL_USART_UART_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/core/hpl_core_m4.c b/atmel-samd/asf4/samd51/hpl/core/hpl_core_m4.c deleted file mode 100644 index cea8d7c3c..000000000 --- a/atmel-samd/asf4/samd51/hpl/core/hpl_core_m4.c +++ /dev/null @@ -1,213 +0,0 @@ -/** - * \file - * - * \brief Core related functionality implementation. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#ifndef _UNIT_TEST_ -#include -#endif -#include -#include - -#ifndef CONF_CPU_FREQUENCY -#define CONF_CPU_FREQUENCY 1000000 -#endif - -#if CONF_CPU_FREQUENCY < 1000 -#define CPU_FREQ_POWER 3 -#elif CONF_CPU_FREQUENCY < 10000 -#define CPU_FREQ_POWER 4 -#elif CONF_CPU_FREQUENCY < 100000 -#define CPU_FREQ_POWER 5 -#elif CONF_CPU_FREQUENCY < 1000000 -#define CPU_FREQ_POWER 6 -#elif CONF_CPU_FREQUENCY < 10000000 -#define CPU_FREQ_POWER 7 -#elif CONF_CPU_FREQUENCY < 100000000 -#define CPU_FREQ_POWER 8 -#elif CONF_CPU_FREQUENCY < 1000000000 -#define CPU_FREQ_POWER 9 -#endif - -/** - * \brief The array of interrupt handlers - */ -struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; - -/** - * \brief Reset MCU - */ -void _reset_mcu(void) -{ - NVIC_SystemReset(); -} - -/** - * \brief Put MCU to sleep - */ -void _go_to_sleep(void) -{ - __DSB(); - __WFI(); -} - -/** - * \brief Retrieve current IRQ number - */ -uint8_t _irq_get_current(void) -{ - return (uint8_t)__get_IPSR() - 16; -} - -/** - * \brief Disable the given IRQ - */ -void _irq_disable(uint8_t n) -{ - NVIC_DisableIRQ((IRQn_Type)n); -} - -/** - * \brief Set the given IRQ - */ -void _irq_set(uint8_t n) -{ - NVIC_SetPendingIRQ((IRQn_Type)n); -} - -/** - * \brief Clear the given IRQ - */ -void _irq_clear(uint8_t n) -{ - NVIC_ClearPendingIRQ((IRQn_Type)n); -} - -/** - * \brief Enable the given IRQ - */ -void _irq_enable(uint8_t n) -{ - NVIC_EnableIRQ((IRQn_Type)n); -} - -/** - * \brief Register IRQ handler - */ -void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) -{ - ASSERT(n < PERIPH_COUNT_IRQn); - - _irq_table[n] = irq; -} - -/** - * \brief Default interrupt handler for unused IRQs. - */ -void Default_Handler(void) -{ - while (1) { - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - */ -static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) -{ - switch (power) { - case 9: - return (us * (freq / 1000000) - 1) + 1; - case 8: - return (us * (freq / 100000) - 1) / 10 + 1; - case 7: - return (us * (freq / 10000) - 1) / 100 + 1; - case 6: - return (us * (freq / 1000) - 1) / 1000 + 1; - case 5: - return (us * (freq / 100) - 1) / 10000 + 1; - case 4: - return (us * (freq / 10) - 1) / 100000 + 1; - default: - return (us * freq - 1) / 1000000 + 1; - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of us - */ -uint32_t _get_cycles_for_us(const uint16_t us) -{ - return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - */ -static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) -{ - switch (power) { - case 9: - return (ms * (freq / 1000000)) * 1000; - case 8: - return (ms * (freq / 100000)) * 100; - case 7: - return (ms * (freq / 10000)) * 10; - case 6: - return (ms * (freq / 1000)); - case 5: - return (ms * (freq / 100) - 1) / 10 + 1; - case 4: - return (ms * (freq / 10) - 1) / 100 + 1; - default: - return (ms * freq - 1) / 1000 + 1; - } -} - -/** - * \brief Retrieve the amount of cycles to delay for the given amount of ms - */ -uint32_t _get_cycles_for_ms(const uint16_t ms) -{ - return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); -} diff --git a/atmel-samd/asf4/samd51/hpl/core/hpl_core_port.h b/atmel-samd/asf4/samd51/hpl/core/hpl_core_port.h deleted file mode 100644 index b068af839..000000000 --- a/atmel-samd/asf4/samd51/hpl/core/hpl_core_port.h +++ /dev/null @@ -1,71 +0,0 @@ -/** - * \file - * - * \brief Core related functionality implementation. - * - * Copyright (C) 2015 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_CORE_PORT_H_INCLUDED -#define _HPL_CORE_PORT_H_INCLUDED - -#include - -/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR - * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), - * there will be assembling errors. - * So the following things are not included for assembling. - */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) - -#ifndef _UNIT_TEST_ -#include -#endif - -/** - * \brief Check if it's in ISR handling - * \return \c true if it's in ISR - */ -static inline bool _is_in_isr(void) -{ - return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); -} - -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/core/hpl_init.c b/atmel-samd/asf4/samd51/hpl/core/hpl_init.c deleted file mode 100644 index 87c277b2b..000000000 --- a/atmel-samd/asf4/samd51/hpl/core/hpl_init.c +++ /dev/null @@ -1,69 +0,0 @@ -/** - * \file - * - * \brief HPL initialization related functionality implementation. - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -#include -#include - -/** - * \brief Initialize the hardware abstraction layer - */ -void _init_chip(void) -{ - - hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); - - _osc32kctrl_init_sources(); - _oscctrl_init_sources(); - _mclk_init(); - _gclk_init_generators(); - _oscctrl_init_referenced_generators(); - -#if CONF_DMAC_ENABLE - hri_mclk_set_AHBMASK_DMAC_bit(MCLK); - _dma_init(); -#endif -} diff --git a/atmel-samd/asf4/samd51/hpl/dac/hpl_dac.c b/atmel-samd/asf4/samd51/hpl/dac/hpl_dac.c deleted file mode 100644 index 411f4f5e9..000000000 --- a/atmel-samd/asf4/samd51/hpl/dac/hpl_dac.c +++ /dev/null @@ -1,326 +0,0 @@ - -/** -* \file -* -* \brief SAM Digital to Analog Converter -* -* Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. -* -* \asf_license_start -* -* \page License -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1. Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2. Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3. The name of Atmel may not be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* 4. This software may only be redistributed and used in connection with an -* Atmel microcontroller product. -* -* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED -* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR -* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -* DAMAGES (INCLUDING, BUT NOT LIMIT ED TO, PROCUREMENT OF SUBSTITUTE GOODS -* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -* \asf_license_stop -* -*/ - -#include -#include -#include -#include - -/** \conf INTERNAL */ -static int32_t _dac_init(void *const hw); -static inline void _dac_deinit(void *const hw); -static inline void _dac_enable_channel(void *const hw, const uint8_t ch); -static inline void _dac_disable_channel(void *const hw, const uint8_t ch); -static inline bool _dac_is_channel_enabled(void *const hw, const uint8_t ch); -/** \endcond */ - -/** - * \brief DAC configuration type - */ -struct dac_configuration { - hri_dac_ctrlb_reg_t ctrlb; - hri_dac_evctrl_reg_t ev_ctrl; - hri_dac_dacctrl_reg_t dac_ctrl0; - hri_dac_dacctrl_reg_t dac_ctrl1; - hri_dac_dbgctrl_reg_t dbg_ctrl; -}; - -/** - * \brief Array of DAC configurations - */ -static struct dac_configuration _dac - = {(CONF_DAC_DIFF << DAC_CTRLB_DIFF_Pos) | DAC_CTRLB_REFSEL(CONF_DAC_REFSEL), - (CONF_DAC_INVEI0 << DAC_EVCTRL_INVEI0_Pos) | (CONF_DAC_EMPTYEO0 << DAC_EVCTRL_EMPTYEO0_Pos) - | (CONF_DAC_STARTEI0 << DAC_EVCTRL_STARTEI0_Pos) - | (CONF_DAC_INVEI1 << DAC_EVCTRL_INVEI1_Pos) - | (CONF_DAC_EMPTYEO1 << DAC_EVCTRL_EMPTYEO1_Pos) - | (CONF_DAC_STARTEI1 << DAC_EVCTRL_STARTEI1_Pos), - (CONF_DAC0_LEFTADJ << DAC_DACCTRL_LEFTADJ_Pos) | DAC_DACCTRL_CCTRL(CONF_DAC0_CCTRL) - | (CONF_DAC0_RUNSTDBY << DAC_DACCTRL_RUNSTDBY_Pos) - | (CONF_DAC0_DITHER << DAC_DACCTRL_DITHER_Pos) - | (CONF_DAC0_REFRESH << DAC_DACCTRL_REFRESH_Pos), - (CONF_DAC1_LEFTADJ << DAC_DACCTRL_LEFTADJ_Pos) | DAC_DACCTRL_CCTRL(CONF_DAC1_CCTRL) - | (CONF_DAC1_RUNSTDBY << DAC_DACCTRL_RUNSTDBY_Pos) - | (CONF_DAC1_DITHER << DAC_DACCTRL_DITHER_Pos) - | (CONF_DAC1_REFRESH << DAC_DACCTRL_REFRESH_Pos), - (CONF_DAC_DBGRUN << DAC_DBGCTRL_DBGRUN_Pos)}; - -/*!< Pointer to hpl device */ -static struct _dac_async_device *_dac_dev = NULL; - -/** - * \brief Initialize synchronous DAC - */ -int32_t _dac_sync_init(struct _dac_sync_device *const device, void *const hw) -{ - ASSERT(device); - - device->hw = hw; - - return _dac_init(device->hw); -} - -/** -* \brief Initialize DAC -*/ -int32_t _dac_async_init(struct _dac_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _dac_init(hw); - if (init_status) { - return init_status; - } - device->hw = hw; - - _dac_dev = device; - NVIC_DisableIRQ(DAC_0_IRQn + 0); - NVIC_ClearPendingIRQ(DAC_0_IRQn + 0); - NVIC_EnableIRQ(DAC_0_IRQn + 0); - NVIC_DisableIRQ(DAC_0_IRQn + 1); - NVIC_ClearPendingIRQ(DAC_0_IRQn + 1); - NVIC_EnableIRQ(DAC_0_IRQn + 1); - NVIC_DisableIRQ(DAC_0_IRQn + 2); - NVIC_ClearPendingIRQ(DAC_0_IRQn + 2); - NVIC_EnableIRQ(DAC_0_IRQn + 2); - - return ERR_NONE; -} - -/** - * \brief De-initialize DAC - */ -void _dac_sync_deinit(struct _dac_sync_device *const device) -{ - _dac_deinit(device->hw); -} - -/** - * \brief De-initialize DAC - */ -void _dac_async_deinit(struct _dac_async_device *const device) -{ - NVIC_DisableIRQ(DAC_0_IRQn + 0); - NVIC_DisableIRQ(DAC_0_IRQn + 1); - NVIC_DisableIRQ(DAC_0_IRQn + 2); - - _dac_deinit(device->hw); -} - -/** - * \brief Enable DAC Channel - */ -void _dac_sync_enable_channel(struct _dac_sync_device *const device, const uint8_t ch) -{ - _dac_enable_channel(device->hw, ch); -} - -/** - * \brief Enable DAC Channel - */ -void _dac_async_enable_channel(struct _dac_async_device *const device, const uint8_t ch) -{ - _dac_enable_channel(device->hw, ch); -} - -/** - * \brief Disable DAC Channel - */ -void _dac_sync_disable_channel(struct _dac_sync_device *const device, const uint8_t ch) -{ - _dac_disable_channel(device->hw, ch); -} - -/** - * \brief Disable DAC Channel - */ -void _dac_async_disable_channel(struct _dac_async_device *const device, const uint8_t ch) -{ - _dac_disable_channel(device->hw, ch); -} - -/** - * \brief Checks if DAC channel is enabled - */ -bool _dac_sync_is_channel_enable(struct _dac_sync_device *const device, const uint8_t ch) -{ - return _dac_is_channel_enabled(device->hw, ch); -} - -/** - * \brief Checks if DAC channel is enabled - */ -bool _dac_async_is_channel_enable(struct _dac_async_device *const device, const uint8_t ch) -{ - return _dac_is_channel_enabled(device->hw, ch); -} - -/** - * \brief write synchronous DAC data for output - */ -void _dac_sync_write_data(struct _dac_sync_device *const device, const uint16_t data, const uint8_t ch) -{ - hri_dac_write_DATA_reg(device->hw, ch, data); -} - -/** - * \brief write DAC data for output - */ -void _dac_async_write_data(struct _dac_async_device *const device, const uint16_t data, const uint8_t ch) -{ - hri_dac_write_DATABUF_reg(device->hw, ch, data); -} - -/** - * \brief Enable/disable DAC interrupt - */ -void _dac_async_set_irq_state(struct _dac_async_device *const device, const enum _dac_callback_type type, - const bool state) -{ - void *hw = device->hw; - - if (DAC_DEVICE_CONVERSION_DONE_CB == type) { - hri_dac_write_INTEN_EMPTY0_bit(hw, state); - hri_dac_write_INTEN_EMPTY1_bit(hw, state); - } else if (DAC_DEVICE_ERROR_CB == type) { - hri_dac_write_INTEN_UNDERRUN0_bit(hw, state); - hri_dac_write_INTEN_UNDERRUN1_bit(hw, state); - } -} - -/** - * \internal Initialize DAC - * - * \param[in] hw The pointer to DAC hardware instance - * - * \return The status of initialization - */ -static int32_t _dac_init(void *const hw) -{ - ASSERT(hw == DAC); - - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); - if (hri_dac_get_CTRLA_ENABLE_bit(hw)) { - return ERR_BUSY; - } - hri_dac_set_CTRLA_SWRST_bit(hw); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); - - hri_dac_write_CTRLB_reg(hw, _dac.ctrlb); - hri_dac_write_EVCTRL_reg(hw, _dac.ev_ctrl); - hri_dac_write_DACCTRL_reg(hw, 0, _dac.dac_ctrl0); - hri_dac_write_DACCTRL_reg(hw, 1, _dac.dac_ctrl1); - hri_dac_write_DBGCTRL_reg(hw, _dac.dbg_ctrl); - - return ERR_NONE; -} - -/** - * \internal De-initialize DAC - * - * \param[in] hw The pointer to DAC hardware instance - */ -static inline void _dac_deinit(void *const hw) -{ - hri_dac_clear_CTRLA_ENABLE_bit(hw); - hri_dac_set_CTRLA_SWRST_bit(hw); -} - -/** - * \internal Enable DAC channel - * - * \param[in] hw The pointer to hardware instance - * \param[in] ch The channel to enable - */ -static inline void _dac_enable_channel(void *const hw, const uint8_t ch) -{ - ASSERT(ch <= 1); - - hri_dac_clear_CTRLA_ENABLE_bit(hw); - hri_dac_set_DACCTRL_ENABLE_bit(hw, ch); - hri_dac_set_CTRLA_ENABLE_bit(hw); - - if (0 == ch) { - while (!hri_dac_get_STATUS_READY0_bit(hw)) - ; - } else { - while (!hri_dac_get_STATUS_READY1_bit(hw)) - ; - } -} - -/** - * \internal Disable DAC channel - * - * \param[in] hw The pointer to hardware instance - * \param[in] ch The channel to disable - */ -static inline void _dac_disable_channel(void *const hw, const uint8_t ch) -{ - ASSERT(ch <= 1); - - hri_dac_clear_CTRLA_ENABLE_bit(hw); - hri_dac_clear_DACCTRL_ENABLE_bit(hw, ch); - - if (hri_dac_get_DACCTRL_ENABLE_bit(hw, !ch)) { - hri_dac_set_CTRLA_ENABLE_bit(hw); - } -} - -/** - * \internal Checks if DAC channel is enabled - * - * \param[in] hw The pointer to hardware instance - * \param[in] ch The channel to check - */ -static inline bool _dac_is_channel_enabled(void *const hw, const uint8_t ch) -{ - if (ch <= 1) { - return hri_dac_get_DACCTRL_ENABLE_bit(hw, ch); - } - - return false; -} diff --git a/atmel-samd/asf4/samd51/hpl/dmac/hpl_dmac.c b/atmel-samd/asf4/samd51/hpl/dmac/hpl_dmac.c deleted file mode 100644 index 9a6602eb3..000000000 --- a/atmel-samd/asf4/samd51/hpl/dmac/hpl_dmac.c +++ /dev/null @@ -1,262 +0,0 @@ - -/** - * \file - * - * \brief Generic DMAC related functionality. - * - * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include - -#if CONF_DMAC_ENABLE -/* Section containing first descriptors for all DMAC channels */ -COMPILER_ALIGNED(16) -static DmacDescriptor _descriptor_section[DMAC_CH_NUM]; - -/* Section containing current descriptors for all DMAC channels */ -COMPILER_ALIGNED(16) -static DmacDescriptor _write_back_section[DMAC_CH_NUM]; - -/* Array containing callbacks for DMAC channels */ -static struct _dma_resource _resources[DMAC_CH_NUM]; - -/* DMAC interrupt handler */ -static void _dmac_handler(void); - -/* This macro DMAC configuration */ -#define DMAC_CHANNEL_CFG(i, n) \ - {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | DMAC_CHCTRLA_TRIGACT(CONF_DMAC_TRIGACT_##n) \ - | DMAC_CHCTRLA_TRIGSRC(CONF_DMAC_TRIGSRC_##n), \ - DMAC_CHPRILVL_PRILVL(CONF_DMAC_LVL_##n), \ - (CONF_DMAC_EVIE_##n << DMAC_CHEVCTRL_EVIE_Pos) | (CONF_DMAC_EVOE_##n << DMAC_CHEVCTRL_EVOE_Pos) \ - | (CONF_DMAC_EVACT_##n << DMAC_CHEVCTRL_EVACT_Pos), \ - DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ - | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) \ - | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ - | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) \ - | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ - | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, - -/* DMAC channel configuration */ -struct dmac_channel_cfg { - uint32_t ctrla; - uint8_t prilvl; - uint8_t evctrl; - uint16_t btctrl; -}; - -/* DMAC channel configurations */ -const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; - -/** - * \brief Initialize DMAC - */ -int32_t _dma_init(void) -{ - uint8_t i; - - hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); - hri_dmac_clear_CRCCTRL_reg(DMAC, DMAC_CRCCTRL_CRCSRC_Msk); - hri_dmac_set_CTRL_SWRST_bit(DMAC); - while (hri_dmac_get_CTRL_SWRST_bit(DMAC)) - ; - - hri_dmac_write_CTRL_reg(DMAC, - (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) - | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) - | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); - hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); - - hri_dmac_write_PRICTRL0_reg(DMAC, - DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) - | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) - | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) - | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) - | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) - | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) - | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); - hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); - hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); - - for (i = 0; i < DMAC_CH_NUM; i++) { - hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla); - hri_dmac_write_CHPRILVL_reg(DMAC, i, _cfgs[i].prilvl); - hri_dmac_write_CHEVCTRL_reg(DMAC, i, _cfgs[i].evctrl); - hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); - } - - for (i = 0; i < 5; i++) { - NVIC_DisableIRQ(DMAC_0_IRQn + i); - NVIC_ClearPendingIRQ(DMAC_0_IRQn + i); - NVIC_EnableIRQ(DMAC_0_IRQn + i); - } - - hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); - - return ERR_NONE; -} - -/** - * \brief Enable/disable DMA interrupt - */ -void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) -{ - if (DMA_TRANSFER_COMPLETE_CB == type) { - hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state); - } else if (DMA_TRANSFER_ERROR_CB == type) { - hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state); - } -} - -int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) -{ - hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); - - return ERR_NONE; -} - -int32_t _dma_set_source_address(const uint8_t channel, const void *const src) -{ - hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); - - return ERR_NONE; -} - -int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) -{ - hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); - - return ERR_NONE; -} - -int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) -{ - uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); - uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); - - if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { - hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); - } - - address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); - - if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { - hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); - } - - hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); - - return ERR_NONE; -} - -int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) -{ - hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); - hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel); - - if (software_trigger) { - hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); - } - - return ERR_NONE; -} - -int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) -{ - *resource = &_resources[channel]; - - return ERR_NONE; -} - -/** - * \internal DMAC interrupt handler - */ -static void _dmac_handler(void) -{ - uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk); - struct _dma_resource *tmp_resource = &_resources[channel]; - - if (hri_dmac_get_CHINTFLAG_TERR_bit(DMAC, channel)) { - hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel); - tmp_resource->dma_cb.error(tmp_resource); - } else if (hri_dmac_get_CHINTFLAG_TCMPL_bit(DMAC, channel)) { - hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel); - tmp_resource->dma_cb.transfer_done(tmp_resource); - } -} -/** -* \brief DMAC interrupt handler -*/ -void DMAC_0_Handler(void) -{ - _dmac_handler(); -} -/** -* \brief DMAC interrupt handler -*/ -void DMAC_1_Handler(void) -{ - _dmac_handler(); -} -/** -* \brief DMAC interrupt handler -*/ -void DMAC_2_Handler(void) -{ - _dmac_handler(); -} -/** -* \brief DMAC interrupt handler -*/ -void DMAC_3_Handler(void) -{ - _dmac_handler(); -} -/** -* \brief DMAC interrupt handler -*/ -void DMAC_4_Handler(void) -{ - _dmac_handler(); -} - -#endif /* CONF_DMAC_ENABLE */ diff --git a/atmel-samd/asf4/samd51/hpl/evsys/hpl_evsys.c b/atmel-samd/asf4/samd51/hpl/evsys/hpl_evsys.c deleted file mode 100644 index 024d24527..000000000 --- a/atmel-samd/asf4/samd51/hpl/evsys/hpl_evsys.c +++ /dev/null @@ -1,151 +0,0 @@ - -/** - * \file - * - * \brief EVSYS related functionality implementation. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -/* Stub macros for reserved channel */ -#define CONF_CHANNEL_38 0 -#define CONF_ONDEMAND_38 0 -#define CONF_RUNSTDBY_38 0 -#define CONF_EDGSEL_38 0 -#define CONF_PATH_38 0 -#define CONF_EVGEN_38 0 - -#define CONF_CHANNEL_39 0 -#define CONF_ONDEMAND_39 0 -#define CONF_RUNSTDBY_39 0 -#define CONF_EDGSEL_39 0 -#define CONF_PATH_39 0 -#define CONF_EVGEN_39 0 - -#define CONF_CHANNEL_113 0 -#define CONF_ONDEMAND_113 0 -#define CONF_RUNSTDBY_113 0 -#define CONF_EDGSEL_113 0 -#define CONF_PATH_113 0 -#define CONF_EVGEN_113 0 - -/* Event user configuration */ -#define USER_MUX_CONF(i, n) EVSYS_USER_CHANNEL(CONF_CHANNEL_##n), - -/* This macro is used for repeat macro: i - unused, n - amount of channels. - * It contains channel configuration. */ -#define CHANNEL_CONF(i, n) \ - (CONF_ONDEMAND_##n << EVSYS_CHANNEL_ONDEMAND_Pos) | (CONF_RUNSTDBY_##n << EVSYS_CHANNEL_RUNSTDBY_Pos) \ - | EVSYS_CHANNEL_EDGSEL(CONF_EDGSEL_##n) | EVSYS_CHANNEL_PATH(CONF_PATH_##n) \ - | EVSYS_CHANNEL_EVGEN(CONF_EVGEN_##n), - -/* This macro is used for repeat macro: i - unused, n - amount of channels - * It contains interrupts configuration. */ -#define INT_CFG(i, n) (CONF_OVR_##n << EVSYS_CHINTFLAG_OVR_Pos) | (CONF_EVD_##n << EVSYS_CHINTFLAG_EVD_Pos), - -static const uint8_t user_mux_confs[] = {REPEAT_MACRO(USER_MUX_CONF, i, EVSYS_USERS)}; - -static const uint16_t channel_confs[] = {REPEAT_MACRO(CHANNEL_CONF, i, EVSYS_CHANNELS)}; - -static const uint32_t interrupt_cfg[] = {REPEAT_MACRO(INT_CFG, i, EVSYS_CHANNELS)}; - -/** - * \brief Initialize event system - */ -int32_t _event_system_init(void) -{ - uint8_t i; - - /* configure user multiplexers */ - for (i = 0; i < EVSYS_USERS; i++) { - hri_evsys_write_USER_reg(EVSYS, i, user_mux_confs[i]); - } - - /* configure channels */ - for (i = 0; i < EVSYS_CHANNELS; i++) { - hri_evsys_write_CHANNEL_reg(EVSYS, i, channel_confs[i]); - hri_evsys_write_CHINTEN_reg(EVSYS, i, interrupt_cfg[i]); - } - - return ERR_NONE; -} - -/** - * \brief De-initialize event system. - */ -int32_t _event_system_deinit() -{ - hri_evsys_write_CTRLA_reg(EVSYS, EVSYS_CTRLA_SWRST); - - return ERR_NONE; -} - -/** - * \brief Enable/disable event reception by the given user from the given - * channel - */ -int32_t _event_system_enable_user(const uint16_t user, const uint16_t channel, const bool on) -{ - if (on) { - hri_evsys_write_USER_reg(EVSYS, user, channel); - } else { - hri_evsys_write_USER_reg(EVSYS, user, 0); - } - - return ERR_NONE; -} - -/** - * \brief Enable/disable event generation by the given generator for the given - * channel - */ -int32_t _event_system_enable_generator(const uint16_t generator, const uint16_t channel, const bool on) -{ - if (on) { - hri_evsys_write_CHANNEL_EVGEN_bf(EVSYS, channel, generator); - } else { - hri_evsys_write_CHANNEL_EVGEN_bf(EVSYS, channel, 0); - } - - return ERR_NONE; -} diff --git a/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk.c b/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk.c deleted file mode 100644 index d022c24f9..000000000 --- a/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk.c +++ /dev/null @@ -1,200 +0,0 @@ - -/** - * \file - * - * \brief Generic Clock Controller related functionality. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Initializes generators - - */ -void _gclk_init_generators(void) -{ - -#if CONF_GCLK_GEN_0_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 0, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) - | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_0_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_0_SOURCE); -#endif -#if CONF_GCLK_GEN_1_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 1, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) - | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_1_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_1_SOURCE); -#endif -#if CONF_GCLK_GEN_2_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 2, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) - | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_2_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_2_SOURCE); -#endif -#if CONF_GCLK_GEN_3_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 3, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) - | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_3_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_3_SOURCE); -#endif -#if CONF_GCLK_GEN_4_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 4, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) - | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_4_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_4_SOURCE); -#endif -#if CONF_GCLK_GEN_5_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 5, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) - | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_5_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_5_SOURCE); -#endif -#if CONF_GCLK_GEN_6_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 6, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) - | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_6_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_6_SOURCE); -#endif -#if CONF_GCLK_GEN_7_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 7, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) - | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_7_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_7_SOURCE); -#endif -#if CONF_GCLK_GEN_8_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 8, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) - | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_8_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_8_SOURCE); -#endif -#if CONF_GCLK_GEN_9_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 9, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) - | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_9_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_9_SOURCE); -#endif -#if CONF_GCLK_GEN_10_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 10, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) - | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_10_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_10_SOURCE); -#endif -#if CONF_GCLK_GEN_11_GENEN == 1 - hri_gclk_write_GENCTRL_reg(GCLK, - 11, - GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) - | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) - | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) - | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) - | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) - | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) - | (CONF_GCLK_GEN_11_GENEN << GCLK_GENCTRL_GENEN_Pos) - | CONF_GCLK_GEN_11_SOURCE); -#endif -} diff --git a/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk_base.h b/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk_base.h deleted file mode 100644 index 701a03887..000000000 --- a/atmel-samd/asf4/samd51/hpl/gclk/hpl_gclk_base.h +++ /dev/null @@ -1,90 +0,0 @@ -/** - * \file - * - * \brief Generic Clock Controller. - * - * Copyright (C) 2014 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _HPL_GCLK_H_INCLUDED -#define _HPL_GCLK_H_INCLUDED - -#include -#ifdef _UNIT_TEST_ -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup gclk_group GCLK Hardware Proxy Layer - * - * \section gclk_hpl_rev Revision History - * - v0.0.0.1 Initial Commit - * - *@{ - */ - -/** - * \name HPL functions - */ -//@{ -/** - * \brief Enable clock on the given channel with the given clock source - * - * This function maps the given clock source to the given clock channel - * and enables channel. - * - * \param[in] channel The channel to enable clock for - * \param[in] source The clock source for the given channel - */ -static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) -{ - - hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); -} - -//@} -/**@}*/ -#ifdef __cplusplus -} -#endif - -#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/mclk/hpl_mclk.c b/atmel-samd/asf4/samd51/hpl/mclk/hpl_mclk.c deleted file mode 100644 index 0788a40c0..000000000 --- a/atmel-samd/asf4/samd51/hpl/mclk/hpl_mclk.c +++ /dev/null @@ -1,54 +0,0 @@ -/** - * \file - * - * \brief SAM Main Clock. - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Initialize master clock generator - */ -void _mclk_init(void) -{ - void *hw = (void *)MCLK; - hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); -} diff --git a/atmel-samd/asf4/samd51/hpl/nvmctrl/hpl_nvmctrl.c b/atmel-samd/asf4/samd51/hpl/nvmctrl/hpl_nvmctrl.c deleted file mode 100644 index 3d9df6db4..000000000 --- a/atmel-samd/asf4/samd51/hpl/nvmctrl/hpl_nvmctrl.c +++ /dev/null @@ -1,702 +0,0 @@ - -/** - * \file - * - * \brief Non-Volatile Memory Controller - * - * Copyright (C) 2016 -2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMIT ED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include -#include -#include - -#define NVM_MEMORY ((volatile uint32_t *)FLASH_ADDR) -#define NVMCTRL_BLOCK_PAGES (NVMCTRL_BLOCK_SIZE / NVMCTRL_PAGE_SIZE) -#define NVMCTRL_REGIONS_NUM 32 -#define NVMCTRL_INTFLAG_ERR \ - (NVMCTRL_INTFLAG_ADDRE | NVMCTRL_INTFLAG_PROGE | NVMCTRL_INTFLAG_LOCKE | NVMCTRL_INTFLAG_ECCSE \ - | NVMCTRL_INTFLAG_NVME \ - | NVMCTRL_INTFLAG_SEESOVF) -/** - * \brief NVM configuration type - */ -struct nvm_configuration { - hri_nvmctrl_ctrlb_reg_t ctrla; /*!< Control B Register */ -}; - -/** - * \brief Array of NVM configurations - */ -static struct nvm_configuration _nvm - = {(CONF_NVM_CACHE0 << NVMCTRL_CTRLA_CACHEDIS0_Pos) | (CONF_NVM_CACHE1 << NVMCTRL_CTRLA_CACHEDIS1_Pos) - | (NVMCTRL_CTRLA_PRM(CONF_NVM_SLEEPPRM))}; - -/*!< Pointer to hpl device */ -static struct _flash_device *_nvm_dev = NULL; - -static void _flash_erase_block(void *const hw, const uint32_t dst_addr); -static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size); - -/** - * \brief Initialize NVM - */ -int32_t _flash_init(struct _flash_device *const device, void *const hw) -{ - uint32_t ctrla; - - ASSERT(device && (hw == NVMCTRL)); - - device->hw = hw; - ctrla = hri_nvmctrl_read_CTRLA_reg(hw); - ctrla &= ~(NVMCTRL_CTRLA_CACHEDIS0 | NVMCTRL_CTRLA_CACHEDIS1 | NVMCTRL_CTRLA_PRM_Msk); - ctrla |= _nvm.ctrla; - hri_nvmctrl_write_CTRLA_reg(hw, ctrla); - - _nvm_dev = device; - NVIC_DisableIRQ(NVMCTRL_0_IRQn); - NVIC_DisableIRQ(NVMCTRL_1_IRQn); - NVIC_ClearPendingIRQ(NVMCTRL_0_IRQn); - NVIC_ClearPendingIRQ(NVMCTRL_1_IRQn); - NVIC_EnableIRQ(NVMCTRL_0_IRQn); - NVIC_EnableIRQ(NVMCTRL_1_IRQn); - - return ERR_NONE; -} - -/** - * \brief De-initialize NVM - */ -void _flash_deinit(struct _flash_device *const device) -{ - device->hw = NULL; - NVIC_DisableIRQ(NVMCTRL_0_IRQn); - NVIC_DisableIRQ(NVMCTRL_1_IRQn); -} - -/** - * \brief Get the flash page size. - */ -uint32_t _flash_get_page_size(struct _flash_device *const device) -{ - (void)device; - return (uint32_t)NVMCTRL_PAGE_SIZE; -} - -/** - * \brief Get the numbers of flash page. - */ -uint32_t _flash_get_total_pages(struct _flash_device *const device) -{ - (void)device; - return (uint32_t)hri_nvmctrl_read_PARAM_NVMP_bf(device->hw); -} - -/** - * \brief Get the number of wait states for read and write operations. - */ -uint8_t _flash_get_wait_state(struct _flash_device *const device) -{ - return hri_nvmctrl_get_CTRLA_reg(device->hw, NVMCTRL_CTRLA_RWS_Msk); -} - -/** - * \brief Set the number of wait states for read and write operations. - */ -void _flash_set_wait_state(struct _flash_device *const device, uint8_t state) -{ - hri_nvmctrl_write_CTRLA_RWS_bf(device->hw, state); -} - -/** - * \brief Reads a number of bytes to a page in the internal Flash. - */ -void _flash_read(struct _flash_device *const device, const uint32_t src_addr, uint8_t *buffer, uint32_t length) -{ - uint8_t *nvm_addr = (uint8_t *)NVM_MEMORY; - uint32_t i; - - /* Check if the module is busy */ - while (!hri_nvmctrl_get_STATUS_READY_bit(device->hw)) { - /* Wait until this module isn't busy */ - } - - for (i = 0; i < length; i++) { - buffer[i] = nvm_addr[src_addr + i]; - } -} - -/** - * \brief Writes a number of bytes to a page in the internal Flash. - */ -void _flash_write(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length) -{ - uint8_t tmp_buffer[NVMCTRL_BLOCK_PAGES][NVMCTRL_PAGE_SIZE]; - uint32_t block_start_addr, block_end_addr; - uint32_t i, j, k; - uint32_t wr_start_addr = dst_addr; - - do { - block_start_addr = wr_start_addr & ~(NVMCTRL_BLOCK_SIZE - 1); - block_end_addr = block_start_addr + NVMCTRL_BLOCK_SIZE - 1; - - /* store the erase data into temp buffer before write */ - for (i = 0; i < NVMCTRL_BLOCK_PAGES; i++) { - _flash_read(device, block_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); - } - - /* temp buffer update */ - j = (wr_start_addr - block_start_addr) / NVMCTRL_PAGE_SIZE; - k = wr_start_addr - block_start_addr - j * NVMCTRL_PAGE_SIZE; - while ((wr_start_addr <= block_end_addr) && (length > 0)) { - tmp_buffer[j][k] = *buffer; - k = (k + 1) % NVMCTRL_PAGE_SIZE; - - if (0 == k) { - j++; - } - - wr_start_addr++; - buffer++; - length--; - } - - /* erase row before write */ - _flash_erase_block(device->hw, block_start_addr); - - /* write buffer to flash */ - for (i = 0; i < NVMCTRL_BLOCK_PAGES; i++) { - _flash_program(device->hw, block_start_addr + i * NVMCTRL_PAGE_SIZE, tmp_buffer[i], NVMCTRL_PAGE_SIZE); - } - } while (block_end_addr < (wr_start_addr + length - 1)); -} - -/** - * \brief Appends a number of bytes in the internal Flash. - */ -void _flash_append(struct _flash_device *const device, const uint32_t dst_addr, const uint8_t *buffer, uint32_t length) -{ - uint32_t page_start_addr = dst_addr & ~(NVMCTRL_PAGE_SIZE - 1); - uint32_t size; - uint32_t offset = 0; - - if (dst_addr != page_start_addr) { - /* Need to write some data to the end of a page */ - size = min(length, NVMCTRL_PAGE_SIZE - (dst_addr - page_start_addr)); - _flash_program(device->hw, dst_addr, buffer, size); - page_start_addr += NVMCTRL_PAGE_SIZE; - offset += size; - } - - while (offset < length) { - size = min(length - offset, NVMCTRL_PAGE_SIZE); - _flash_program(device->hw, page_start_addr, buffer + offset, size); - page_start_addr += NVMCTRL_PAGE_SIZE; - offset += size; - } -} - -/** - * \brief Execute erase in the internal flash - */ -void _flash_erase(struct _flash_device *const device, uint32_t dst_addr, uint32_t page_nums) -{ - uint8_t tmp_buffer[NVMCTRL_PAGE_SIZE]; - uint32_t block_start_addr; - uint32_t i; - - block_start_addr = dst_addr & ~(NVMCTRL_BLOCK_SIZE - 1); - - memset(tmp_buffer, 0xFF, NVMCTRL_PAGE_SIZE); - - /* when address is not aligned with block start address */ - if (dst_addr != block_start_addr) { - block_start_addr += NVMCTRL_BLOCK_SIZE; - for (i = 0; i < NVMCTRL_BLOCK_PAGES - 1; i++) { - _flash_write(device, dst_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); - - if (--page_nums == 0) { - return; - } - - dst_addr += NVMCTRL_PAGE_SIZE; - - if (dst_addr == block_start_addr) { - break; - } - } - } - - while (page_nums >= NVMCTRL_BLOCK_PAGES) { - _flash_erase_block(device->hw, block_start_addr); - block_start_addr += NVMCTRL_PAGE_SIZE; - page_nums -= NVMCTRL_BLOCK_PAGES; - } - - if (page_nums != 0) { - for (i = 0; i < page_nums; i++) { - _flash_write(device, block_start_addr, tmp_buffer, NVMCTRL_PAGE_SIZE); - block_start_addr += NVMCTRL_PAGE_SIZE; - } - } -} - -/** - * \brief Execute lock in the internal flash - */ -int32_t _flash_lock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) -{ - uint32_t region_pages; - uint32_t block_start_addr; - - region_pages = (uint32_t)FLASH_SIZE / (NVMCTRL_REGIONS_NUM * NVMCTRL_PAGE_SIZE); - block_start_addr = dst_addr & ~(NVMCTRL_BLOCK_SIZE - 1); - - if ((page_nums != region_pages) || (dst_addr != block_start_addr)) { - return ERR_INVALID_ARG; - } - - while (!hri_nvmctrl_get_STATUS_READY_bit(device->hw)) { - /* Wait until this module isn't busy */ - } - - hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr); - hri_nvmctrl_write_CTRLB_reg(device->hw, NVMCTRL_CTRLB_CMD_LR | NVMCTRL_CTRLB_CMDEX_KEY); - - return (int32_t)FLASH_SIZE / (NVMCTRL_REGIONS_NUM * NVMCTRL_PAGE_SIZE); -} - -/** - * \brief Execute unlock in the internal flash - */ -int32_t _flash_unlock(struct _flash_device *const device, const uint32_t dst_addr, uint32_t page_nums) -{ - uint32_t region_pages; - uint32_t block_start_addr; - - region_pages = (uint32_t)FLASH_SIZE / (NVMCTRL_REGIONS_NUM * NVMCTRL_PAGE_SIZE); - block_start_addr = dst_addr & ~(NVMCTRL_BLOCK_SIZE - 1); - - if ((page_nums != region_pages) || (dst_addr != block_start_addr)) { - return ERR_INVALID_ARG; - } - - while (!hri_nvmctrl_get_STATUS_READY_bit(device->hw)) { - /* Wait until this module isn't busy */ - } - - hri_nvmctrl_write_ADDR_reg(device->hw, dst_addr); - hri_nvmctrl_write_CTRLB_reg(device->hw, NVMCTRL_CTRLB_CMD_UR | NVMCTRL_CTRLB_CMDEX_KEY); - - return (int32_t)FLASH_SIZE / (NVMCTRL_REGIONS_NUM * NVMCTRL_PAGE_SIZE); -} - -/** - * \brief check whether the region which is pointed by address - */ -bool _flash_is_locked(struct _flash_device *const device, const uint32_t dst_addr) -{ - uint16_t region_id; - - /* Get region for given page */ - region_id = dst_addr / (FLASH_SIZE / NVMCTRL_REGIONS_NUM); - - return !(hri_nvmctrl_get_RUNLOCK_reg(device->hw, 1 << region_id)); -} - -/** - * \brief Enable/disable Flash interrupt - */ -void _flash_set_irq_state(struct _flash_device *const device, const enum _flash_cb_type type, const bool state) -{ - ASSERT(device); - - if (FLASH_DEVICE_CB_READY == type) { - hri_nvmctrl_write_INTEN_DONE_bit(device->hw, state); - } else if (FLASH_DEVICE_CB_ERROR == type) { - if (state) { - hri_nvmctrl_write_INTEN_reg(device->hw, NVMCTRL_INTFLAG_ERR); - } else { - hri_nvmctrl_clear_INTEN_reg(device->hw, NVMCTRL_INTFLAG_ERR); - } - } -} - -/** - * \internal erase a row in flash - * \param[in] hw The pointer to hardware instance - * \param[in] dst_addr Destination page address to erase - */ -static void _flash_erase_block(void *const hw, const uint32_t dst_addr) -{ - while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - /* Set address and command */ - hri_nvmctrl_write_ADDR_reg(hw, dst_addr); - hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_EB | NVMCTRL_CTRLB_CMDEX_KEY); -} - -/** - * \internal write a page in flash - * \param[in] hw The pointer to hardware instance - * \param[in] dst_addr Destination page address to write - * \param[in] buffer Pointer to buffer where the data to - * write is stored - * \param[in] size The size of data to write to a page - */ -static void _flash_program(void *const hw, const uint32_t dst_addr, const uint8_t *buffer, const uint16_t size) -{ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wcast-align" - uint32_t *ptr_read = (uint32_t *)buffer; - #pragma GCC diagnostic pop - uint32_t nvm_address = dst_addr / 4; - uint16_t i; - - while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_PBC | NVMCTRL_CTRLB_CMDEX_KEY); - - while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - /* Writes to the page buffer must be 32 bits, perform manual copy - * to ensure alignment */ - for (i = 0; i < size; i += 4) { - NVM_MEMORY[nvm_address++] = *ptr_read; - ptr_read++; - } - - while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - hri_nvmctrl_write_ADDR_reg(hw, dst_addr); - hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_WP | NVMCTRL_CTRLB_CMDEX_KEY); -} - -/** - * \internal NVM interrupt handler - * - * \param[in] p The pointer to interrupt parameter - */ -static void _nvm_interrupt_handler(struct _flash_device *device) -{ - void *const hw = device->hw; - - if (hri_nvmctrl_get_INTFLAG_DONE_bit(hw)) { - hri_nvmctrl_clear_INTFLAG_DONE_bit(hw); - - if (NULL != device->flash_cb.ready_cb) { - device->flash_cb.ready_cb(device); - } - } else if (hri_nvmctrl_read_INTFLAG_reg(hw) && ~NVMCTRL_INTFLAG_ERR) { - hri_nvmctrl_clear_INTFLAG_reg(hw, NVMCTRL_INTFLAG_ERR); - - if (NULL != device->flash_cb.error_cb) { - device->flash_cb.error_cb(device); - } - } -} - -/** - * \internal NVM 0 interrupt handler - */ -void NVMCTRL_0_Handler(void) -{ - _nvm_interrupt_handler(_nvm_dev); -} - -/** - * \internal NVM 1 interrupt handler - */ -void NVMCTRL_1_Handler(void) -{ - _nvm_interrupt_handler(_nvm_dev); -} - -/* - The NVM User Row contains calibration data that are automatically read at device - power on. - The NVM User Row can be read at address 0x804000. - */ -#ifndef _NVM_USER_ROW_BASE -#define _NVM_USER_ROW_BASE 0x804000 -#endif -#define _NVM_USER_ROW_N_BITS 96 -#define _NVM_USER_ROW_N_BYTES (_NVM_USER_ROW_N_BITS / 8) -#define _NVM_USER_ROW_END (((uint8_t *)_NVM_USER_ROW_BASE) + _NVM_USER_ROW_N_BYTES - 1) -#define _IS_NVM_USER_ROW(b) \ - (((uint8_t *)(b) >= (uint8_t *)(_NVM_USER_ROW_BASE)) && ((uint8_t *)(b) <= (uint8_t *)(_NVM_USER_ROW_END))) -#define _IN_NVM_USER_ROW(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_USER_ROW_END)) - -/* - The NVM Software Calibration Area can be read at address 0x00800080. - The NVM Software Calibration Area can not be written. - */ -#ifndef _NVM_SW_CALIB_AREA_BASE -#define _NVM_SW_CALIB_AREA_BASE 0x00800080 -#endif -#define _NVM_SW_CALIB_AREA_N_BITS 45 -#define _NVM_SW_CALIB_AREA_N_BYTES (_NVM_SW_CALIB_AREA_N_BITS / 8) -#define _NVM_SW_CALIB_AREA_END (((uint8_t *)_NVM_SW_CALIB_AREA_BASE) + _NVM_SW_CALIB_AREA_N_BYTES - 1) -#define _IS_NVM_SW_CALIB_AREA(b) \ - (((uint8_t *)(b) >= (uint8_t *)_NVM_SW_CALIB_AREA_BASE) && ((uint8_t *)(b) <= (uint8_t *)_NVM_SW_CALIB_AREA_END)) -#define _IN_NVM_SW_CALIB_AREA(b, o) (((uint8_t *)(b) + (o)) <= (uint8_t *)(_NVM_SW_CALIB_AREA_END)) - -/** - * \internal Read left aligned data bits - * \param[in] base Base address for the data - * \param[in] bit_offset Offset for the bitfield start - * \param[in] n_bits Number of bits in the bitfield - */ -static inline uint32_t _user_area_read_l32_bits(const volatile uint32_t *base, const uint32_t bit_offset, - const uint8_t n_bits) -{ - return base[bit_offset >> 5] & ((1 << n_bits) - 1); -} - -/** - * \internal Read right aligned data bits - * \param[in] base Base address for the data - * \param[in] bit_offset Offset for the bitfield start - * \param[in] n_bits Number of bits in the bitfield - */ -static inline uint32_t _user_area_read_r32_bits(const volatile uint32_t *base, const uint32_t bit_offset, - const uint8_t n_bits) -{ - return (base[bit_offset >> 5] >> (bit_offset & 0x1F)) & ((1 << n_bits) - 1); -} - -int32_t _user_area_read(const void *base, const uint32_t offset, uint8_t *buf, uint32_t size) -{ - ASSERT(buf); - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - if (!_IN_NVM_USER_ROW(base, offset)) { - return ERR_BAD_ADDRESS; - } - - /* Cut off if request too many bytes */ - if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { - return ERR_INVALID_ARG; - } - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - if (!_IN_NVM_SW_CALIB_AREA(base, offset)) { - return ERR_BAD_ADDRESS; - } - - /* Cut off if request too many bytes */ - if (!_IN_NVM_SW_CALIB_AREA(base, offset + size - 1)) { - return ERR_INVALID_ARG; - } - } else { - return ERR_UNSUPPORTED_OP; - } - - /* Copy data */ - memcpy(buf, ((uint8_t *)base) + offset, size); - return ERR_NONE; -} - -uint32_t _user_area_read_bits(const void *base, const uint32_t bit_offset, const uint8_t n_bits) -{ - volatile uint32_t *mem_base = (volatile uint32_t *)base; - uint32_t l_off, l_bits; - uint32_t r_off, r_bits; - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - ASSERT(_IN_NVM_USER_ROW(base, bit_offset >> 3) && _IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)); - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - ASSERT(_IN_NVM_SW_CALIB_AREA(base, bit_offset >> 3) - && _IN_NVM_SW_CALIB_AREA(base, (bit_offset + n_bits - 1) >> 3)); - } else { - ASSERT(false); - } - - /* Since the bitfield can cross 32-bits boundaries, - * left and right bits are read from 32-bit aligned address - * and then combined together. */ - l_off = bit_offset & (~(32 - 1)); - r_off = l_off + 32; - l_bits = 32 - (bit_offset & (32 - 1)); - - if (n_bits > l_bits) { - r_bits = n_bits - l_bits; - } else { - l_bits = n_bits; - r_bits = 0; - } - - return _user_area_read_r32_bits(mem_base, bit_offset, l_bits) - + (_user_area_read_l32_bits(mem_base, r_off, r_bits) << l_bits); -} - -/** \internal Write 96-bit user row - * \param[in] _row Pointer to 96-bit user row data. - */ -static int32_t _user_row_write_exec(const uint32_t *_row) -{ - Nvmctrl *hw = NVMCTRL; - uint32_t ctrla = hri_nvmctrl_read_CTRLA_reg(NVMCTRL); - - /* Denied if Security Bit is set */ - if (DSU->STATUSB.bit.PROT) { - return ERR_DENIED; - } - - /* Do Save */ - - /* - Prepare. */ - while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - hri_nvmctrl_clear_CTRLA_WMODE_bf(NVMCTRL, NVMCTRL_CTRLA_WMODE_Msk); - - /* - Erase AUX row. */ - hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)_NVM_USER_ROW_BASE); - hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_EP | NVMCTRL_CTRLB_CMDEX_KEY); - while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - /* - Page buffer clear & write. */ - hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_PBC | NVMCTRL_CTRLB_CMDEX_KEY); - while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - *((uint32_t *)NVMCTRL_USER) = _row[0]; - *(((uint32_t *)NVMCTRL_USER) + 1) = _row[1]; - *(((uint32_t *)NVMCTRL_USER) + 2) = _row[2]; - *(((uint32_t *)NVMCTRL_USER) + 3) = 0xFFFFFFFF; - - /* - Write AUX row. */ - hri_nvmctrl_write_ADDR_reg(hw, (hri_nvmctrl_addr_reg_t)_NVM_USER_ROW_BASE); - hri_nvmctrl_write_CTRLB_reg(hw, NVMCTRL_CTRLB_CMD_WQW | NVMCTRL_CTRLB_CMDEX_KEY); - while (!hri_nvmctrl_get_STATUS_READY_bit(hw)) { - /* Wait until this module isn't busy */ - } - - /* Restore CTRLA */ - hri_nvmctrl_write_CTRLA_reg(NVMCTRL, ctrla); - - return ERR_NONE; -} - -int32_t _user_area_write(void *base, const uint32_t offset, const uint8_t *buf, const uint32_t size) -{ - uint32_t _row[3]; /* Copy of user row. */ - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - if (!_IN_NVM_USER_ROW(base, offset)) { - return ERR_BAD_ADDRESS; - } else if (!_IN_NVM_USER_ROW(base, offset + size - 1)) { - return ERR_INVALID_ARG; - } - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - return ERR_DENIED; - } else { - return ERR_UNSUPPORTED_OP; - } - - memcpy(_row, base, 12); /* Store previous data. */ - memcpy((uint8_t *)_row + offset, buf, size); /* Modify with buf data. */ - - return _user_row_write_exec(_row); -} - -int32_t _user_area_write_bits(void *base, const uint32_t bit_offset, const uint32_t bits, const uint8_t n_bits) -{ - uint32_t _row[3]; /* Copy of user row. */ - uint32_t l_off, l_bits; - uint32_t r_off, r_bits; - - /** Parameter check. */ - if (_IS_NVM_USER_ROW(base)) { - if (!_IN_NVM_USER_ROW(base, bit_offset >> 3)) { - return ERR_BAD_ADDRESS; - } else if (!_IN_NVM_USER_ROW(base, (bit_offset + n_bits - 1) >> 3)) { - return ERR_INVALID_ARG; - } - } else if (_IS_NVM_SW_CALIB_AREA(base)) { - return ERR_DENIED; - } else { - return ERR_UNSUPPORTED_OP; - } - - /* Since the bitfield can cross 32-bits boundaries, - * left and right bits are splitted for 32-bit aligned address - * and then saved. */ - l_off = bit_offset & (~(32 - 1)); - r_off = l_off + 32; - l_bits = 32 - (bit_offset & (32 - 1)); - - if (n_bits > l_bits) { - r_bits = n_bits - l_bits; - } else { - l_bits = n_bits; - r_bits = 0; - } - - memcpy(_row, base, 12); /* Store previous data. */ - - if (l_bits) { - uint32_t l_mask = ((1 << l_bits) - 1) << (bit_offset & (32 - 1)); - _row[bit_offset >> 5] &= ~l_mask; - _row[bit_offset >> 5] |= (bits << (bit_offset & (32 - 1))) & l_mask; - } - - if (r_bits) { - uint32_t r_mask = (1 << r_bits) - 1; - _row[r_off >> 5] &= ~r_mask; - _row[r_off >> 5] |= bits >> l_bits; - } - - return _user_row_write_exec(_row); -} diff --git a/atmel-samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c b/atmel-samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c deleted file mode 100644 index 99ed873b4..000000000 --- a/atmel-samd/asf4/samd51/hpl/osc32kctrl/hpl_osc32kctrl.c +++ /dev/null @@ -1,94 +0,0 @@ - -/** - * \file - * - * \brief SAM 32k Oscillators Controller. - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#include -#include - -/** - * \brief Initialize 32 kHz clock sources - */ -void _osc32kctrl_init_sources(void) -{ - void * hw = (void *)OSC32KCTRL; - uint16_t calib = 0; - -#if CONF_XOSC32K_CONFIG == 1 - hri_osc32kctrl_write_XOSC32K_reg(hw, - OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) - | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) - | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) - | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) - | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) - | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) - | -#ifdef CONF_XOSC32K_CGM - OSC32KCTRL_XOSC32K_CGM(CONF_XOSC32K_CGM) | -#endif - (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); - - hri_osc32kctrl_write_CFDCTRL_reg(hw, (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos)); - - hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); -#endif - -#if CONF_OSCULP32K_CONFIG == 1 - calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); - hri_osc32kctrl_write_OSCULP32K_reg(hw, -#if CONF_OSCULP32K_CALIB_ENABLE == 1 - OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) -#else - OSC32KCTRL_OSCULP32K_CALIB(calib) -#endif - ); -#endif - -#if CONF_XOSC32K_CONFIG -#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 - while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) - ; -#endif -#endif - - hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); - (void)calib; -} diff --git a/atmel-samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c b/atmel-samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c deleted file mode 100644 index 83f00dceb..000000000 --- a/atmel-samd/asf4/samd51/hpl/oscctrl/hpl_oscctrl.c +++ /dev/null @@ -1,244 +0,0 @@ - -/** - * \file - * - * \brief SAM Oscillators Controller. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/** - * \brief Initialize clock sources - */ -void _oscctrl_init_sources(void) -{ - void *hw = (void *)OSCCTRL; - -#if CONF_XOSC0_CONFIG == 1 - hri_oscctrl_write_XOSCCTRL_reg(hw, - 0, - OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC0_CFDPRESC) - | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC0_STARTUP) - | (CONF_XOSC0_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) - | (CONF_XOSC0_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) - | (CONF_XOSC0_ENALC << OSCCTRL_XOSCCTRL_ENALC_Pos) - | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC0_IMULT) - | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC0_IPTAT) - | (CONF_XOSC0_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) - | (CONF_XOSC0_ONDEMAND << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) - | (CONF_XOSC0_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) - | (CONF_XOSC0_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) - | (CONF_XOSC0_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); -#endif - -#if CONF_XOSC0_CONFIG == 1 -#if CONF_XOSC0_ENABLE == 1 - while (!hri_oscctrl_get_STATUS_XOSCRDY0_bit(hw)) - ; -#endif -#if CONF_XOSC0_ONDEMAND == 1 - hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 0); -#endif -#endif - -#if CONF_XOSC1_CONFIG == 1 - hri_oscctrl_write_XOSCCTRL_reg(hw, - 1, - OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC1_CFDPRESC) - | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC1_STARTUP) - | (CONF_XOSC1_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) - | (CONF_XOSC1_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) - | (CONF_XOSC1_ENALC << OSCCTRL_XOSCCTRL_ENALC_Pos) - | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC1_IMULT) - | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC1_IPTAT) - | (CONF_XOSC1_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) - | (CONF_XOSC1_ONDEMAND << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) - | (CONF_XOSC1_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) - | (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) - | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); -#endif - -#if CONF_XOSC1_CONFIG == 1 -#if CONF_XOSC1_ENABLE == 1 - while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw)) - ; -#endif -#if CONF_XOSC1_ONDEMAND == 1 - hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); -#endif -#endif - - (void)hw; -} - -void _oscctrl_init_referenced_generators(void) -{ - void *hw = (void *)OSCCTRL; - -#if CONF_DFLL_CONFIG == 1 - hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K); - uint8_t tmp; - hri_oscctrl_write_DFLLCTRLA_reg(hw, 0); -#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 - hri_gclk_write_PCHCTRL_reg( - GCLK, OSCCTRL_GCLK_ID_DFLL48, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); -#endif - - hri_oscctrl_write_DFLLMUL_reg(hw, - OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) - | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); - while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw)) - ; - - hri_oscctrl_write_DFLLCTRLB_reg(hw, 0); - while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) - ; - - tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE; - hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp); - while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw)) - ; - -#if CONF_DFLL_OVERWRITE_CALIBRATION == 1 - hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); -#endif - hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw)); - while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw)) - ; - - tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) - | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos) - | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos) - | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0; - hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp); - while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) - ; -#endif - -#if CONF_FDPLL0_CONFIG == 1 -#if CONF_FDPLL0_REFCLK == 0 - hri_gclk_write_PCHCTRL_reg( - GCLK, OSCCTRL_GCLK_ID_FDPLL0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL0_GCLK)); -#endif - hri_oscctrl_write_DPLLRATIO_reg( - hw, 0, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL0_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL0_LDR)); - hri_oscctrl_write_DPLLCTRLB_reg(hw, - 0, - OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL0_DIV) - | (CONF_FDPLL0_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) - | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL0_DCOFILTER) - | (CONF_FDPLL0_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) - | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL0_LTIME) - | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL0_REFCLK) - | (CONF_FDPLL0_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) - | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL0_FILTER)); - hri_oscctrl_write_DPLLCTRLA_reg(hw, - 0, - (CONF_FDPLL0_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) - | (CONF_FDPLL0_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); -#endif - -#if CONF_FDPLL1_CONFIG == 1 -#if CONF_FDPLL1_REFCLK == 0 - hri_gclk_write_PCHCTRL_reg( - GCLK, OSCCTRL_GCLK_ID_FDPLL1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL1_GCLK)); -#endif - hri_oscctrl_write_DPLLRATIO_reg( - hw, 1, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL1_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL1_LDR)); - hri_oscctrl_write_DPLLCTRLB_reg(hw, - 1, - OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL1_DIV) - | (CONF_FDPLL1_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) - | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL1_DCOFILTER) - | (CONF_FDPLL1_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) - | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL1_LTIME) - | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL1_REFCLK) - | (CONF_FDPLL1_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) - | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL1_FILTER)); - hri_oscctrl_write_DPLLCTRLA_reg(hw, - 1, - (CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) - | (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); -#endif - -#if CONF_DFLL_CONFIG == 1 - if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) { - hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; - - while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) - ; - } else { - while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) - ; - } -#if CONF_DFLL_ONDEMAND == 1 - hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(hw); -#endif -#endif - -#if CONF_FDPLL0_CONFIG == 1 -#if CONF_FDPLL0_ENABLE == 1 - while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0))) - ; -#endif -#if CONF_FDPLL0_ONDEMAND == 1 - hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 0); -#endif -#endif - -#if CONF_FDPLL1_CONFIG == 1 -#if CONF_FDPLL1_ENABLE == 1 - while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 1) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 1))) - ; -#endif -#if CONF_FDPLL1_ONDEMAND == 1 - hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1); -#endif -#endif - -#if CONF_DFLL_CONFIG == 1 - while (hri_gclk_read_SYNCBUSY_reg(GCLK)) - ; - hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); -#endif - (void)hw; -} diff --git a/atmel-samd/asf4/samd51/hpl/pm/hpl_pm.c b/atmel-samd/asf4/samd51/hpl/pm/hpl_pm.c deleted file mode 100644 index a46500e4a..000000000 --- a/atmel-samd/asf4/samd51/hpl/pm/hpl_pm.c +++ /dev/null @@ -1,65 +0,0 @@ - -/** - * \file - * - * \brief SAM Power manager - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include - -/** - * \brief Set the sleep mode for the device - */ -int32_t _set_sleep_mode(const uint8_t mode) -{ - switch (mode) { - case 2: - case 4: - case 5: - case 6: - hri_pm_write_SLEEPCFG_SLEEPMODE_bf(PM, mode); - break; - default: - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} diff --git a/atmel-samd/asf4/samd51/hpl/pm/hpl_pm_base.h b/atmel-samd/asf4/samd51/hpl/pm/hpl_pm_base.h deleted file mode 100644 index 34b044d7c..000000000 --- a/atmel-samd/asf4/samd51/hpl/pm/hpl_pm_base.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief SAM Power manager - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distributionn. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifndef _HPL_PM_BASE_H_INCLUDED -#define _HPL_PM_BASE_H_INCLUDED - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/port/hpl_gpio_base.h b/atmel-samd/asf4/samd51/hpl/port/hpl_gpio_base.h deleted file mode 100644 index 5ea315af3..000000000 --- a/atmel-samd/asf4/samd51/hpl/port/hpl_gpio_base.h +++ /dev/null @@ -1,172 +0,0 @@ -/** - * \file - * - * \brief SAM PORT. - * - * Copyright (C) 2014-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#include -#include -#include - -/** - * \brief Set direction on port with mask - */ -static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, - const enum gpio_direction direction) -{ - switch (direction) { - case GPIO_DIRECTION_OFF: - hri_port_clear_DIR_reg(PORT, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg( - PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); - break; - - case GPIO_DIRECTION_IN: - hri_port_clear_DIR_reg(PORT, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg(PORT, - port, - PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN - | ((mask & 0xffff0000) >> 16)); - break; - - case GPIO_DIRECTION_OUT: - hri_port_set_DIR_reg(PORT, port, mask); - hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); - hri_port_write_WRCONFIG_reg( - PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); - break; - - default: - ASSERT(false); - } -} - -/** - * \brief Set output level on port with mask - */ -static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) -{ - if (level) { - hri_port_set_OUT_reg(PORT, port, mask); - } else { - hri_port_clear_OUT_reg(PORT, port, mask); - } -} - -/** - * \brief Change output level to the opposite with mask - */ -static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) -{ - hri_port_toggle_OUT_reg(PORT, port, mask); -} - -/** - * \brief Get input levels on all port pins - */ -static inline uint32_t _gpio_get_level(const enum gpio_port port) -{ - uint32_t tmp; - - CRITICAL_SECTION_ENTER(); - - uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port); - - tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; - tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp; - - CRITICAL_SECTION_LEAVE(); - - return tmp; -} - -/** - * \brief Set pin pull mode - */ -static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, - const enum gpio_pull_mode pull_mode) -{ - switch (pull_mode) { - case GPIO_PULL_OFF: - hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); - break; - - case GPIO_PULL_UP: - hri_port_clear_DIR_reg(PORT, port, 1U << pin); - hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); - hri_port_set_OUT_reg(PORT, port, 1U << pin); - break; - - case GPIO_PULL_DOWN: - hri_port_clear_DIR_reg(PORT, port, 1U << pin); - hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); - hri_port_clear_OUT_reg(PORT, port, 1U << pin); - break; - - default: - ASSERT(false); - break; - } -} - -/** - * \brief Set gpio pin function - */ -static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) -{ - uint8_t port = GPIO_PORT(gpio); - uint8_t pin = GPIO_PIN(gpio); - - if (function == GPIO_PIN_FUNCTION_OFF) { - hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); - - } else { - hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); - - if (pin & 1) { - // Odd numbered pin - hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); - } else { - // Even numbered pin - hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); - } - } -} diff --git a/atmel-samd/asf4/samd51/hpl/ramecc/hpl_ramecc.c b/atmel-samd/asf4/samd51/hpl/ramecc/hpl_ramecc.c deleted file mode 100644 index c4daec518..000000000 --- a/atmel-samd/asf4/samd51/hpl/ramecc/hpl_ramecc.c +++ /dev/null @@ -1,93 +0,0 @@ -/** - * \file - * - * \brief Generic RAMECC related functionality. - * - * Copyright (C) 2016 -2107 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include - -/* RAMECC device descriptor */ -struct _ramecc_device device; - -/** - * \brief Initialize RAMECC - */ -int32_t _ramecc_init(void) -{ - if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) { - return ERR_ABORTED; - } - - NVIC_DisableIRQ(RAMECC_IRQn); - NVIC_ClearPendingIRQ(RAMECC_IRQn); - NVIC_EnableIRQ(RAMECC_IRQn); - - return ERR_NONE; -} - -void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb) -{ - if (RAMECC_DUAL_ERROR_CB == type) { - device.ramecc_cb.dual_bit_err = cb; - hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb); - } else if (RAMECC_SINGLE_ERROR_CB == type) { - device.ramecc_cb.single_bit_err = cb; - hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb); - } -} - -/** - * \internal RAMECC interrupt handler - */ -void RAMECC_Handler(void) -{ - struct _ramecc_device *dev = (struct _ramecc_device *)&device; - volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); - - if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { - dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); - } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { - dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); - } else { - return; - } -} diff --git a/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc.c b/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc.c deleted file mode 100644 index 6ef8a96ee..000000000 --- a/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc.c +++ /dev/null @@ -1,193 +0,0 @@ - -/** - * \file - * - * \brief RTC Driver - * - * Copyright (C) 2014 - 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -/*!< Pointer to hpl device */ - -static struct _timer_device *_rtc_dev = NULL; - -/** - * \brief Initialize Timer - */ -int32_t _timer_init(struct _timer_device *const dev, void *const hw) -{ - ASSERT(dev); - - dev->hw = hw; - - hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_SWRST); - hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST); - -#if CONF_RTC_EVENT_CONTROL_ENABLE == 1 - hri_rtcmode0_write_EVCTRL_reg(dev->hw, - (CONF_RTC_PEREO0 << RTC_MODE0_EVCTRL_PEREO0_Pos) - | (CONF_RTC_PEREO1 << RTC_MODE0_EVCTRL_PEREO1_Pos) - | (CONF_RTC_PEREO2 << RTC_MODE0_EVCTRL_PEREO2_Pos) - | (CONF_RTC_PEREO3 << RTC_MODE0_EVCTRL_PEREO3_Pos) - | (CONF_RTC_PEREO4 << RTC_MODE0_EVCTRL_PEREO4_Pos) - | (CONF_RTC_PEREO5 << RTC_MODE0_EVCTRL_PEREO5_Pos) - | (CONF_RTC_PEREO6 << RTC_MODE0_EVCTRL_PEREO6_Pos) - | (CONF_RTC_PEREO7 << RTC_MODE0_EVCTRL_PEREO7_Pos) - | (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos) - | (CONF_RTC_COMPE1 << RTC_MODE0_EVCTRL_CMPEO1_Pos) - | (CONF_RTC_TAMPEREO << RTC_MODE0_EVCTRL_TAMPEREO_Pos) - | (CONF_RTC_TAMPEVEI << RTC_MODE0_EVCTRL_TAMPEVEI_Pos) - | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos)); -#endif - - hri_rtcmode0_write_CTRLA_reg( - dev->hw, RTC_MODE0_CTRLA_PRESCALER(CONF_RTC_PRESCALER) | RTC_MODE0_CTRLA_COUNTSYNC | RTC_MODE0_CTRLA_MATCHCLR); - hri_rtcmode0_write_COMP_reg(dev->hw, 0, CONF_RTC_COMP_VAL); - hri_rtcmode0_set_INTEN_CMP0_bit(dev->hw); - - _rtc_dev = dev; - - return ERR_NONE; -} - -/** - * \brief De-initialize Timer - */ -void _timer_deinit(struct _timer_device *const dev) -{ - ASSERT(dev && dev->hw); - - NVIC_DisableIRQ(RTC_IRQn); - - hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_SWRST); -} - -/** - * \brief Start hardware timer - */ -void _timer_start(struct _timer_device *const dev) -{ - ASSERT(dev && dev->hw); - - NVIC_EnableIRQ(RTC_IRQn); - hri_rtcmode0_write_COUNT_reg(dev->hw, 0); - hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_COUNT); - hri_rtcmode0_set_CTRLA_ENABLE_bit(dev->hw); -} - -/** - * \brief Stop hardware timer - */ -void _timer_stop(struct _timer_device *const dev) -{ - ASSERT(dev && dev->hw); - - hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw); -} - -/** - * \brief Set timer period - */ -void _timer_set_period(struct _timer_device *const dev, const uint32_t clock_cycles) -{ - hri_rtcmode0_write_COMP_reg(dev->hw, 0, clock_cycles); -} - -/** - * \brief Retrieve timer period - */ -uint32_t _timer_get_period(const struct _timer_device *const dev) -{ - return hri_rtcmode0_read_COMP_reg(dev->hw, 0); -} - -/** - * \brief Check if timer is running - */ -bool _timer_is_started(const struct _timer_device *const dev) -{ - return hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw); -} - -/** - * \brief Set timer IRQ - */ -void _timer_set_irq(struct _timer_device *const dev) -{ - (void)dev; -} - -/** - * \brief RTC Timer interrupt handler - * - * \param[in] p The pointer to calendar device struct - */ -static void _rtc_timer_interrupt_handler(struct _timer_device *dev) -{ - /* Read and mask interrupt flag register */ - uint16_t flag = hri_rtcmode0_read_INTFLAG_reg(dev->hw); - - if (flag & RTC_MODE0_INTFLAG_CMP0) { - if (dev->timer_cb.period_expired) { - dev->timer_cb.period_expired(dev); - } - /* Clear interrupt flag */ - hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw); - } -} - -/** - * \brief Retrieve timer helper functions - */ -struct _timer_hpl_interface *_rtc_get_timer(void) -{ - return NULL; -} - -/** -* \brief Rtc interrupt handler -*/ -void RTC_Handler(void) -{ - _rtc_timer_interrupt_handler(_rtc_dev); -} diff --git a/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc_base.h b/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc_base.h deleted file mode 100644 index bbcf242b9..000000000 --- a/atmel-samd/asf4/samd51/hpl/rtc/hpl_rtc_base.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * \file - * - * \brief RTC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distributionn. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifndef _HPL_RTC2_V200_H_INCLUDED -#define _HPL_RTC2_V200_H_INCLUDED - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \brief Retrieve timer helper functions - * - * \return A pointer to set of timer helper functions - */ -struct _timer_hpl_interface *_rtc_get_timer(void); - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_RTC2_V200_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/sercom/hpl_sercom.c b/atmel-samd/asf4/samd51/hpl/sercom/hpl_sercom.c deleted file mode 100644 index 6b67934ee..000000000 --- a/atmel-samd/asf4/samd51/hpl/sercom/hpl_sercom.c +++ /dev/null @@ -1,2922 +0,0 @@ - -/** - * \file - * - * \brief SAM Serial Communication Interface - * - * Copyright (C) 2014-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONF_SERCOM_0_USART_ENABLE -#define CONF_SERCOM_0_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_USART_ENABLE -#define CONF_SERCOM_1_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_USART_ENABLE -#define CONF_SERCOM_2_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_USART_ENABLE -#define CONF_SERCOM_3_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_USART_ENABLE -#define CONF_SERCOM_4_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_USART_ENABLE -#define CONF_SERCOM_5_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_USART_ENABLE -#define CONF_SERCOM_6_USART_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_USART_ENABLE -#define CONF_SERCOM_7_USART_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as USART. */ -#define SERCOM_USART_AMOUNT \ - (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ - + CONF_SERCOM_4_USART_ENABLE \ - + CONF_SERCOM_5_USART_ENABLE \ - + CONF_SERCOM_6_USART_ENABLE \ - + CONF_SERCOM_7_USART_ENABLE) - -/** - * \brief Macro is used to fill usart configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define SERCOM_CONFIGURATION(n) \ - { \ - n, SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ - | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ - | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ - | (CONF_SERCOM_##n##_USART_TXINV << SERCOM_USART_CTRLA_TXINV_Pos) \ - | (CONF_SERCOM_##n##_USART_RXINV << SERCOM_USART_CTRLA_RXINV_Pos) \ - | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ - | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ - | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ - | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ - | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ - | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ - | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ - SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ - | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ - | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ - | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ - | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ - | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ - | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ - SERCOM_USART_CTRLC_GTIME(CONF_SERCOM_##n##_USART_GTIME) \ - | (CONF_SERCOM_##n##_USART_DSNACK << SERCOM_USART_CTRLC_DSNACK_Pos) \ - | (CONF_SERCOM_##n##_USART_INACK << SERCOM_USART_CTRLC_INACK_Pos) \ - | SERCOM_USART_CTRLC_MAXITER(CONF_SERCOM_##n##_USART_MAXITER), \ - (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ - CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ - } - -/** - * \brief SERCOM USART configuration type - */ -struct usart_configuration { - uint8_t number; - hri_sercomusart_ctrla_reg_t ctrl_a; - hri_sercomusart_ctrlb_reg_t ctrl_b; - hri_sercomusart_ctrlc_reg_t ctrl_c; - hri_sercomusart_baud_reg_t baud; - uint8_t fractional; - hri_sercomusart_rxpl_reg_t rxpl; - hri_sercomusart_dbgctrl_reg_t debug_ctrl; -}; - -#if SERCOM_USART_AMOUNT < 1 -/** Dummy array to pass compiling. */ -static struct usart_configuration _usarts[1] = {{0}}; -#else -/** - * \brief Array of SERCOM USART configurations - */ -static struct usart_configuration _usarts[] = { -#if CONF_SERCOM_0_USART_ENABLE == 1 - SERCOM_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_USART_ENABLE == 1 - SERCOM_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_USART_ENABLE == 1 - SERCOM_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_USART_ENABLE == 1 - SERCOM_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_USART_ENABLE == 1 - SERCOM_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_USART_ENABLE == 1 - SERCOM_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_USART_ENABLE == 1 - SERCOM_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_USART_ENABLE == 1 - SERCOM_CONFIGURATION(7), -#endif -}; -#endif - -static uint8_t _get_sercom_index(const void *const hw); -static uint8_t _sercom_get_irq_num(const void *const hw); -static void _sercom_init_irq_param(const void *const hw, void *dev); -static uint8_t _sercom_get_hardware_index(const void *const hw); - -static int32_t _usart_init(void *const hw); -static inline void _usart_deinit(void *const hw); -static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction); -static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); -static void _usart_set_data_order(void *const hw, const enum usart_data_order order); -static void _usart_set_mode(void *const hw, const enum usart_mode mode); -static void _usart_set_parity(void *const hw, const enum usart_parity parity); -static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); -static void _usart_set_character_size(void *const hw, const enum usart_character_size size); - -/** - * \brief Initialize synchronous SERCOM USART - */ -int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) -{ - ASSERT(device); - - device->hw = hw; - - return _usart_init(hw); -} - -/** - * \brief Initialize asynchronous SERCOM USART - */ -int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _usart_init(hw); - if (init_status) { - return init_status; - } - device->hw = hw; - _sercom_init_irq_param(hw, (void *)device); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - NVIC_EnableIRQ((IRQn_Type)irq); - irq++; - } - - return ERR_NONE; -} - -/** - * \brief De-initialize SERCOM USART - */ -void _usart_sync_deinit(struct _usart_sync_device *const device) -{ - _usart_deinit(device->hw); -} - -/** - * \brief De-initialize SERCOM USART - */ -void _usart_async_deinit(struct _usart_async_device *const device) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); - _usart_deinit(device->hw); -} - -/** - * \brief Calculate baud rate register value - */ -uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); -} - -/** - * \brief Calculate baud rate register value - */ -uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); -} - -/** - * \brief Enable SERCOM module - */ -void _usart_sync_enable(struct _usart_sync_device *const device) -{ - hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Enable SERCOM module - */ -void _usart_async_enable(struct _usart_async_device *const device) -{ - hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable SERCOM module - */ -void _usart_sync_disable(struct _usart_sync_device *const device) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Disable SERCOM module - */ -void _usart_async_disable(struct _usart_async_device *const device) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); -} - -/** - * \brief Set baud rate - */ -void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) -{ - _usart_set_baud_rate(device->hw, baud_rate); -} - -/** - * \brief Set baud rate - */ -void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) -{ - _usart_set_baud_rate(device->hw, baud_rate); -} - -/** - * \brief Set data order - */ -void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) -{ - _usart_set_data_order(device->hw, order); -} - -/** - * \brief Set data order - */ -void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) -{ - _usart_set_data_order(device->hw, order); -} - -/** - * \brief Set mode - */ -void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) -{ - _usart_set_mode(device->hw, mode); -} - -/** - * \brief Set mode - */ -void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) -{ - _usart_set_mode(device->hw, mode); -} - -/** - * \brief Set parity - */ -void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) -{ - _usart_set_parity(device->hw, parity); -} - -/** - * \brief Set parity - */ -void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) -{ - _usart_set_parity(device->hw, parity); -} - -/** - * \brief Set stop bits mode - */ -void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) -{ - _usart_set_stop_bits(device->hw, stop_bits); -} - -/** - * \brief Set stop bits mode - */ -void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) -{ - _usart_set_stop_bits(device->hw, stop_bits); -} - -/** - * \brief Set character size - */ -void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) -{ - _usart_set_character_size(device->hw, size); -} - -/** - * \brief Set character size - */ -void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) -{ - _usart_set_character_size(device->hw, size); -} - -/** - * \brief Retrieve SERCOM usart status - */ -uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_read_STATUS_reg(device->hw); -} - -/** - * \brief Retrieve SERCOM usart status - */ -uint32_t _usart_async_get_status(const struct _usart_async_device *const device) -{ - return hri_sercomusart_read_STATUS_reg(device->hw); -} - -/** - * \brief Write a byte to the given SERCOM USART instance - */ -void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) -{ - hri_sercomusart_write_DATA_reg(device->hw, data); -} - -/** - * \brief Write a byte to the given SERCOM USART instance - */ -void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) -{ - hri_sercomusart_write_DATA_reg(device->hw, data); -} - -/** - * \brief Read a byte from the given SERCOM USART instance - */ -uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_read_DATA_reg(device->hw); -} - -/** - * \brief Check if USART is ready to send next byte - */ -bool _usart_sync_is_byte_sent(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_DRE_bit(device->hw); -} - -/** - * \brief Check if USART is ready to send next byte - */ -bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) -{ - return hri_sercomusart_get_interrupt_DRE_bit(device->hw); -} - -/** - * \brief Check if there is data received by USART - */ -bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) -{ - return hri_sercomusart_get_interrupt_RXC_bit(device->hw); -} - -/** - * \brief Set the state of flow control pins - */ -void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, - const union usart_flow_control_state state) -{ - (void)device; - (void)state; -} - -/** - * \brief Set the state of flow control pins - */ -void _usart_async_set_flow_control_state(struct _usart_async_device *const device, - const union usart_flow_control_state state) -{ - (void)device; - (void)state; -} - -/** - * \brief Retrieve the state of flow control pins - */ -union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) -{ - (void)device; - union usart_flow_control_state state; - - state.value = 0; - state.bit.unavailable = 1; - return state; -} - -/** - * \brief Retrieve the state of flow control pins - */ -union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) -{ - (void)device; - union usart_flow_control_state state; - - state.value = 0; - state.bit.unavailable = 1; - return state; -} - -/** - * \brief Enable data register empty interrupt - */ -void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) -{ - hri_sercomusart_set_INTEN_DRE_bit(device->hw); -} - -/** - * \brief Enable transmission complete interrupt - */ -void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) -{ - hri_sercomusart_set_INTEN_TXC_bit(device->hw); -} - -/** - * \brief Retrieve ordinal number of the given sercom hardware instance - */ -static uint8_t _sercom_get_hardware_index(const void *const hw) -{ - Sercom *const sercom_modules[] = SERCOM_INSTS; - /* Find index for SERCOM instance. */ - for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { - if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { - return i; - } - } - return 0; -} - -/** - * \brief Retrieve ordinal number of the given SERCOM USART hardware instance - */ -uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) -{ - return _sercom_get_hardware_index(device->hw); -} - -/** - * \brief Retrieve ordinal number of the given SERCOM USART hardware instance - */ -uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) -{ - return _sercom_get_hardware_index(device->hw); -} - -/** - * \brief Enable/disable USART interrupt - */ -void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, - const bool state) -{ - ASSERT(device); - - if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { - hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); - hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); - } else if (USART_ASYNC_RX_DONE == type) { - hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); - } else if (USART_ASYNC_ERROR == type) { - hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - - * \return The ordinal number of the given sercom hardware instance - */ -static uint8_t _get_sercom_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_usarts); i++) { - if (_usarts[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return 0; -} - -/** - * \brief Init irq param with the given sercom hardware instance - */ -static void _sercom_init_irq_param(const void *const hw, void *dev) -{ -} - -/** - * \internal Initialize SERCOM USART - * - * \param[in] hw The pointer to hardware instance - * - * \return The status of initialization - */ -static int32_t _usart_init(void *const hw) -{ - uint8_t i = _get_sercom_index(hw); - - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - if (hri_sercomusart_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_sercomusart_set_CTRLA_SWRST_bit(hw); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - - hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); - hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); - hri_sercomusart_write_CTRLC_reg(hw, _usarts[i].ctrl_c); - if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { - ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; - ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; - } else { - hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); - } - - hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); - hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); - - return ERR_NONE; -} - -/** - * \internal De-initialize SERCOM USART - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _usart_deinit(void *const hw) -{ - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - hri_sercomusart_set_CTRLA_SWRST_bit(hw); -} - -/** - * \internal Calculate baud rate register value - * - * \param[in] baud Required baud rate - * \param[in] clock_rate SERCOM clock frequency - * \param[in] samples The number of samples - * \param[in] mode USART mode - * \param[in] fraction A fraction value - * - * \return Calculated baud rate register value - */ -static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, - const enum usart_baud_rate_mode mode, const uint8_t fraction) -{ - if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { - return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; - } - - if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { - return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); - } - - if (USART_BAUDRATE_SYNCH == mode) { - return clock_rate / baud / 2 - 1; - } - - return 0; -} - -/** - * \internal Set baud rate - * - * \param[in] device The pointer to USART device instance - * \param[in] baud_rate A baud rate to set - */ -static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_BAUD_reg(hw, baud_rate); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set data order - * - * \param[in] device The pointer to USART device instance - * \param[in] order A data order to set - */ -static void _usart_set_data_order(void *const hw, const enum usart_data_order order) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLA_DORD_bit(hw, order); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set mode - * - * \param[in] device The pointer to USART device instance - * \param[in] mode A mode to set - */ -static void _usart_set_mode(void *const hw, const enum usart_mode mode) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set parity - * - * \param[in] device The pointer to USART device instance - * \param[in] parity A parity to set - */ -static void _usart_set_parity(void *const hw, const enum usart_parity parity) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - - if (USART_PARITY_NONE != parity) { - hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); - } else { - hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); - } - - hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set stop bits mode - * - * \param[in] device The pointer to USART device instance - * \param[in] stop_bits A stop bits mode to set - */ -static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); - CRITICAL_SECTION_LEAVE() - - hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); -} - -/** - * \internal Set character size - * - * \param[in] device The pointer to USART device instance - * \param[in] size A character size to set - */ -static void _usart_set_character_size(void *const hw, const enum usart_character_size size) -{ - bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); - - hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); - hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); - CRITICAL_SECTION_LEAVE() - - if (enabled) { - hri_sercomusart_set_CTRLA_ENABLE_bit(hw); - } -} - -/* Sercom I2C implementation */ - -#ifndef CONF_SERCOM_0_I2CM_ENABLE -#define CONF_SERCOM_0_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_I2CM_ENABLE -#define CONF_SERCOM_1_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_I2CM_ENABLE -#define CONF_SERCOM_2_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_I2CM_ENABLE -#define CONF_SERCOM_3_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_I2CM_ENABLE -#define CONF_SERCOM_4_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_I2CM_ENABLE -#define CONF_SERCOM_5_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_I2CM_ENABLE -#define CONF_SERCOM_6_I2CM_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_I2CM_ENABLE -#define CONF_SERCOM_7_I2CM_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as I2C Master. */ -#define SERCOM_I2CM_AMOUNT \ - (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ - + CONF_SERCOM_4_I2CM_ENABLE \ - + CONF_SERCOM_5_I2CM_ENABLE \ - + CONF_SERCOM_6_I2CM_ENABLE \ - + CONF_SERCOM_7_I2CM_ENABLE) - -/** - * \brief Macro is used to fill i2cm configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define I2CM_CONFIGURATION(n) \ - { \ - (n), (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ - | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ - | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ - | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ - SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ - CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ - } - -#define ERROR_FLAG (1 << 7) -#define SB_FLAG (1 << 1) -#define MB_FLAG (1 << 0) - -#define CMD_STOP 0x3 -#define I2C_IDLE 0x1 -#define I2C_SM 0x0 -#define I2C_FM 0x1 -#define I2C_HS 0x2 -#define TEN_ADDR_FRAME 0x78 -#define TEN_ADDR_MASK 0x3ff -#define SEVEN_ADDR_MASK 0x7f - -/** - * \brief SERCOM I2CM configuration type - */ -struct i2cm_configuration { - uint8_t number; - hri_sercomi2cm_ctrla_reg_t ctrl_a; - hri_sercomi2cm_ctrlb_reg_t ctrl_b; - hri_sercomi2cm_baud_reg_t baud; - hri_sercomi2cm_dbgctrl_reg_t dbgctrl; - uint16_t trise; - uint32_t clk; /* SERCOM peripheral clock frequency */ -}; - -static inline void _i2c_m_enable_implementation(void *hw); -static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); - -#if SERCOM_I2CM_AMOUNT < 1 -/** Dummy array to pass compiling. */ -static struct i2cm_configuration _i2cms[1] = {{0}}; -#else -/** - * \brief Array of SERCOM I2CM configurations - */ -static struct i2cm_configuration _i2cms[] = { -#if CONF_SERCOM_0_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(5), -#endif -#if CONF_SERCOM_6_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(6), -#endif -#if CONF_SERCOM_7_I2CM_ENABLE == 1 - I2CM_CONFIGURATION(7), -#endif -}; -#endif - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - - * \return The ordinal number of the given sercom hardware instance - */ -static int8_t _get_i2cm_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { - if (_i2cms[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return -1; -} - -static inline void _sercom_i2c_send_stop(void *const hw) -{ - hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); -} - -/** - * \brief SERCOM I2CM analyze hardware status and transfer next byte - */ -static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) -{ - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); - - if (flags & MB_FLAG) { - /* tx error */ - if (status & SERCOM_I2CM_STATUS_ARBLOST) { - hri_sercomi2cm_clear_interrupt_MB_bit(hw); - msg->flags |= I2C_M_FAIL; - msg->flags &= ~I2C_M_BUSY; - - if (status & SERCOM_I2CM_STATUS_BUSERR) { - return I2C_ERR_BUS; - } - - return I2C_ERR_BAD_ADDRESS; - } else { - if (status & SERCOM_I2CM_STATUS_RXNACK) { - - /* Slave rejects to receive more data */ - if (msg->len > 0) { - msg->flags |= I2C_M_FAIL; - } - - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - - return I2C_NACK; - } - - if (msg->flags & I2C_M_TEN) { - hri_sercomi2cm_write_ADDR_reg(hw, - ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - msg->flags &= ~I2C_M_TEN; - - return I2C_OK; - } - - if (msg->len == 0) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - } else { - hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); - msg->buffer++; - msg->len--; - } - - return I2C_OK; - } - } else if (flags & SB_FLAG) { - if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { - msg->len--; - - /* last byte, send nack */ - if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } - - if (msg->len == 0) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - msg->flags &= ~I2C_M_BUSY; - } - - /* Accessing DATA.DATA auto-triggers I2C bus operations. - * The operation performed depends on the state of - * CTRLB.ACKACT, CTRLB.SMEN - **/ - *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); - } else { - hri_sercomi2cm_clear_interrupt_SB_bit(hw); - return I2C_NACK; - } - - hri_sercomi2cm_clear_interrupt_SB_bit(hw); - } - - return I2C_OK; -} - -/** - * \brief Enable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - _i2c_m_enable_implementation(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Disable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** - * \brief Set baudrate of master - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] clkrate The clock rate of i2c master, in KHz - * \param[in] baudrate The baud rate desired for i2c master, in KHz - */ -int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) -{ - uint32_t tmp; - void * hw = i2c_dev->hw; - - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - - tmp = _get_i2cm_index(hw); - clkrate = _i2cms[tmp].clk / 1000; - - if (i2c_dev->service.mode == I2C_STANDARD_MODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_FASTMODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { - tmp = (clkrate - 2 * baudrate) / (2 * baudrate); - hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); - } else { - /* error baudrate */ - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Retrieve IRQ number for the given hardware instance - */ -static uint8_t _sercom_get_irq_num(const void *const hw) -{ - return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2); -} - -/** - * \brief Initialize sercom i2c module to use in async mode - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) -{ - int32_t init_status; - - ASSERT(i2c_dev); - - i2c_dev->hw = hw; - - init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); - if (init_status) { - return init_status; - } - - _sercom_init_irq_param(hw, (void *)i2c_dev); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - NVIC_EnableIRQ((IRQn_Type)irq); - irq++; - } - return ERR_NONE; -} - -/** - * \brief Deinitialize sercom i2c module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); - hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Transfer the slave address to bus, which will start the transfer - * - * \param[in] i2c_dev The pointer to i2c device - */ -static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) -{ - void * hw = i2c_dev->hw; - struct _i2c_m_msg *msg = &i2c_dev->service.msg; - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - - ASSERT(i2c_dev); - - if (msg->len == 1 && sclsm) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } else { - hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); - } - - /* ten bit address */ - if (msg->addr & I2C_M_TEN) { - if (msg->flags & I2C_M_RD) { - msg->flags |= I2C_M_TEN; - } - - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } else { - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } - - return ERR_NONE; -} - -/** - * \brief Transfer data specified by msg - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] msg The pointer to i2c message - * - * \return Transfer status. - * \retval 0 Transfer success - * \retval <0 Transfer fail, return the error code - */ -int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) -{ - int ret; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - ASSERT(msg); - - if (msg->len == 0) { - return ERR_NONE; - } - - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return ERR_BUSY; - } - - msg->flags |= I2C_M_BUSY; - i2c_dev->service.msg = *msg; - - ret = _sercom_i2c_send_address(i2c_dev); - - if (ret) { - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - return ERR_NONE; -} - -/** - * \brief Set callback to be called in interrupt handler - * - * \param[in] i2c_dev The pointer to master i2c device - * \param[in] type The callback type - * \param[in] func The callback function pointer - */ -int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, - FUNC_PTR func) -{ - switch (type) { - case I2C_M_ASYNC_DEVICE_ERROR: - i2c_dev->cb.error = (_i2c_error_cb_t)func; - break; - case I2C_M_ASYNC_DEVICE_TX_COMPLETE: - i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; - break; - case I2C_M_ASYNC_DEVICE_RX_COMPLETE: - i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; - break; - default: - /* error */ - break; - } - - return ERR_NONE; -} - -/** - * \brief Set stop condition on I2C - * - * \param i2c_dev Pointer to master i2c device - * - * \return Operation status - * \retval I2C_OK Operation was successfull - */ -int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - _sercom_i2c_send_stop(hw); - - return I2C_OK; -} - -/** - * \brief Get number of bytes left in transfer buffer - * - * \param i2c_dev Pointer to i2c master device - * - * \return Bytes left in buffer - * \retval =>0 Bytes left in buffer - */ -int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) -{ - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return i2c_dev->service.msg.len; - } - - return 0; -} - -/** - * \brief Initialize sercom i2c module to use in sync mode - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) -{ - ASSERT(i2c_dev); - - i2c_dev->hw = hw; - - return _i2c_m_sync_init_impl(&i2c_dev->service, hw); -} - -/** - * \brief Deinitialize sercom i2c module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); - hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Enable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) -{ - ASSERT(i2c_dev); - - _i2c_m_enable_implementation(i2c_dev->hw); - - return ERR_NONE; -} - -/** - * \brief Disable the i2c master module - * - * \param[in] i2c_dev The pointer to i2c device - */ -int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - - hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** - * \brief Set baudrate of master - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] clkrate The clock rate of i2c master, in KHz - * \param[in] baudrate The baud rate desired for i2c master, in KHz - */ -int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) -{ - uint32_t tmp; - void * hw = i2c_dev->hw; - - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - - tmp = _get_i2cm_index(hw); - clkrate = _i2cms[tmp].clk / 1000; - - if (i2c_dev->service.mode == I2C_STANDARD_MODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_FASTMODE) { - tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) - / (2 * baudrate)); - hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); - } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { - tmp = (clkrate - 2 * baudrate) / (2 * baudrate); - hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); - } else { - /* error baudrate */ - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Enable/disable I2C master interrupt - */ -void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, - const bool state) -{ - if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { - hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); - hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); - } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { - hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); - } -} - -/** - * \brief Wait for bus response - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] flags Store the hardware response - * - * \return Bus response status. - * \retval 0 Bus response status OK - * \retval <0 Bus response fail - */ -inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) -{ - uint32_t timeout = 65535; - void * hw = i2c_dev->hw; - - do { - *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); - - if (timeout-- == 0) { - return I2C_ERR_BUS; - } - } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); - - return I2C_OK; -} - -/** - * \brief Send the slave address to bus, which will start the transfer - * - * \param[in] i2c_dev The pointer to i2c device - */ -static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) -{ - void * hw = i2c_dev->hw; - struct _i2c_m_msg *msg = &i2c_dev->service.msg; - int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); - uint32_t flags; - - ASSERT(i2c_dev); - - if (msg->len == 1 && sclsm) { - hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); - } else { - hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); - } - - /* ten bit address */ - if (msg->addr & I2C_M_TEN) { - if (msg->flags & I2C_M_RD) { - msg->flags |= I2C_M_TEN; - } - - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } else { - hri_sercomi2cm_write_ADDR_reg(hw, - ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) - | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); - } - - _sercom_i2c_sync_wait_bus(i2c_dev, &flags); - return _sercom_i2c_sync_analyse_flags(hw, flags, msg); -} - -/** - * \brief Transfer data specified by msg - * - * \param[in] i2c_dev The pointer to i2c device - * \param[in] msg The pointer to i2c message - * - * \return Transfer status. - * \retval 0 Transfer success - * \retval <0 Transfer fail or partial fail, return the error code - */ -int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) -{ - uint32_t flags; - int ret; - void * hw = i2c_dev->hw; - - ASSERT(i2c_dev); - ASSERT(i2c_dev->hw); - ASSERT(msg); - - if (i2c_dev->service.msg.flags & I2C_M_BUSY) { - return I2C_ERR_BUSY; - } - - msg->flags |= I2C_M_BUSY; - i2c_dev->service.msg = *msg; - - ret = _sercom_i2c_sync_send_address(i2c_dev); - - if (ret) { - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - while (i2c_dev->service.msg.flags & I2C_M_BUSY) { - ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); - - if (ret) { - if (msg->flags & I2C_M_STOP) { - _sercom_i2c_send_stop(hw); - } - - i2c_dev->service.msg.flags &= ~I2C_M_BUSY; - - return ret; - } - - ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); - } - - return ret; -} - -int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) -{ - void *hw = i2c_dev->hw; - - _sercom_i2c_send_stop(hw); - - return I2C_OK; -} - -static inline void _i2c_m_enable_implementation(void *const hw) -{ - int timeout = 65535; - - ASSERT(hw); - - /* Enable interrupts */ - hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); - - while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { - timeout--; - - if (timeout <= 0) { - hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); - } - } -} - -static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) -{ - uint8_t i = _get_i2cm_index(hw); - - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - /* Check if module is enabled. */ - if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_sercomi2cm_set_CTRLA_SWRST_bit(hw); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - - hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); - hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); - hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); - - service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); - - service->trise = _i2cms[i].trise; - - return ERR_NONE; -} - -/* SERCOM I2C slave */ - -#ifndef CONF_SERCOM_0_I2CS_ENABLE -#define CONF_SERCOM_0_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_I2CS_ENABLE -#define CONF_SERCOM_1_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_I2CS_ENABLE -#define CONF_SERCOM_2_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_I2CS_ENABLE -#define CONF_SERCOM_3_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_I2CS_ENABLE -#define CONF_SERCOM_4_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_I2CS_ENABLE -#define CONF_SERCOM_5_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_I2CS_ENABLE -#define CONF_SERCOM_6_I2CS_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_I2CS_ENABLE -#define CONF_SERCOM_7_I2CS_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as I2C Slave. */ -#define SERCOM_I2CS_AMOUNT \ - (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ - + CONF_SERCOM_4_I2CS_ENABLE \ - + CONF_SERCOM_5_I2CS_ENABLE \ - + CONF_SERCOM_6_I2CS_ENABLE \ - + CONF_SERCOM_7_I2CS_ENABLE) - -/** - * \brief Macro is used to fill I2C slave configuration structure based on - * its number - * - * \param[in] n The number of structures - */ -#define I2CS_CONFIGURATION(n) \ - { \ - n, SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ - | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ - | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ - | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ - | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ - | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ - SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ - (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ - | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ - | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ - | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ - } - -/** - * \brief Macro to check 10-bit addressing - */ -#define I2CS_7BIT_ADDRESSING_MASK 0x7F - -static int32_t _i2c_s_init(void *const hw); -static int8_t _get_i2c_s_index(const void *const hw); -static inline void _i2c_s_deinit(void *const hw); -static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); - -/** - * \brief SERCOM I2C slave configuration type - */ -struct i2cs_configuration { - uint8_t number; - hri_sercomi2cs_ctrla_reg_t ctrl_a; - hri_sercomi2cs_ctrlb_reg_t ctrl_b; - hri_sercomi2cs_addr_reg_t address; -}; - -#if SERCOM_I2CS_AMOUNT < 1 -/** Dummy array for compiling. */ -static struct i2cs_configuration _i2css[1] = {{0}}; -#else -/** - * \brief Array of SERCOM I2C slave configurations - */ -static struct i2cs_configuration _i2css[] = { -#if CONF_SERCOM_0_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(0), -#endif -#if CONF_SERCOM_1_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(1), -#endif -#if CONF_SERCOM_2_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(2), -#endif -#if CONF_SERCOM_3_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(3), -#endif -#if CONF_SERCOM_4_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(4), -#endif -#if CONF_SERCOM_5_I2CS_ENABLE == 1 - I2CS_CONFIGURATION(5), -#endif -}; -#endif - -/** - * \brief Initialize synchronous I2C slave - */ -int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) -{ - int32_t status; - - ASSERT(device); - - status = _i2c_s_init(hw); - if (status) { - return status; - } - device->hw = hw; - - return ERR_NONE; -} - -/** - * \brief Initialize asynchronous I2C slave - */ -int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) -{ - int32_t init_status; - - ASSERT(device); - - init_status = _i2c_s_init(hw); - if (init_status) { - return init_status; - } - - device->hw = hw; - _sercom_init_irq_param(hw, (void *)device); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - NVIC_EnableIRQ((IRQn_Type)irq); - irq++; - } - - return ERR_NONE; -} - -/** - * \brief Deinitialize synchronous I2C - */ -int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) -{ - _i2c_s_deinit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Deinitialize asynchronous I2C - */ -int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); - _i2c_s_deinit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable I2C module - */ -int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable I2C module - */ -int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Disable I2C module - */ -int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Disable I2C module - */ -int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Check if 10-bit addressing mode is on - */ -int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); -} - -/** - * \brief Check if 10-bit addressing mode is on - */ -int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) -{ - return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); -} - -/** - * \brief Set I2C slave address - */ -int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) -{ - return _i2c_s_set_address(device->hw, address); -} - -/** - * \brief Set I2C slave address - */ -int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) -{ - return _i2c_s_set_address(device->hw, address); -} - -/** - * \brief Write a byte to the given I2C instance - */ -void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) -{ - hri_sercomi2cs_write_DATA_reg(device->hw, data); -} - -/** - * \brief Write a byte to the given I2C instance - */ -void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) -{ - hri_sercomi2cs_write_DATA_reg(device->hw, data); -} - -/** - * \brief Read a byte from the given I2C instance - */ -uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_read_DATA_reg(device->hw); -} - -/** - * \brief Check if I2C is ready to send next byt - */ -bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); -} - -/** - * \brief Check if there is data received by I2C - */ -bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); -} - -/** - * \brief Retrieve I2C slave status - */ -i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) -{ - return hri_sercomi2cs_read_STATUS_reg(device->hw); -} - -/** - * \brief Retrieve I2C slave status - */ -i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) -{ - return hri_sercomi2cs_read_STATUS_reg(device->hw); -} - -/** - * \brief Abort data transmission - */ -int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) -{ - hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); - - return ERR_NONE; -} - -/** - * \brief Enable/disable I2C slave interrupt - */ -int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, - const bool state) -{ - ASSERT(device); - - if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { - hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); - } else if (I2C_S_DEVICE_ERROR == type) { - hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); - } - - return ERR_NONE; -} - -/** - * \internal Initalize i2c slave hardware - * - * \param[in] p The pointer to hardware instance - * - *\ return status of initialization - */ -static int32_t _i2c_s_init(void *const hw) -{ - int8_t i = _get_i2c_s_index(hw); - if (i == -1) { - return ERR_INVALID_ARG; - } - - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_CTRLA_SWRST); - if (hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_CTRLA_SWRST); - - hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); - hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); - hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); - - return ERR_NONE; -} - -/** - * \internal Retrieve ordinal number of the given sercom hardware instance - * - * \param[in] hw The pointer to hardware instance - * - * \return The ordinal number of the given sercom hardware instance - */ -static int8_t _get_i2c_s_index(const void *const hw) -{ - uint8_t sercom_offset = _sercom_get_hardware_index(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_i2css); i++) { - if (_i2css[i].number == sercom_offset) { - return i; - } - } - - ASSERT(false); - return -1; -} - -/** - * \internal De-initialize i2c slave - * - * \param[in] hw The pointer to hardware instance - */ -static inline void _i2c_s_deinit(void *const hw) -{ - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); -} - -/** - * \internal De-initialize i2c slave - * - * \param[in] hw The pointer to hardware instance - * \param[in] address Address to set - */ -static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) -{ - bool enabled; - - enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); - - CRITICAL_SECTION_ENTER() - hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); - hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); - CRITICAL_SECTION_LEAVE() - - if (enabled) { - hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); - } - - return ERR_NONE; -} - -/* Sercom SPI implementation */ - -#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE -#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) -#endif - -#define SPI_DEV_IRQ_MODE 0x8000 - -#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) -#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) - -COMPILER_PACK_SET(1) -/** Initialization configuration of registers. */ -struct sercomspi_regs_cfg { - uint32_t ctrla; - uint32_t ctrlb; - uint32_t addr; - uint8_t baud; - uint8_t dbgctrl; - uint16_t dummy_byte; - uint8_t n; -}; -COMPILER_PACK_RESET() - -/** Build configuration from header macros. */ -#define SERCOMSPI_REGS(n) \ - { \ - ((CONF_SERCOM_##n##_SPI_DORD) | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ - | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ - | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ - | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) \ - | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ - | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ - | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ - | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ - ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ - | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ - | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ - | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ - | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ - | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ - (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ - | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ - ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ - (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ - CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ - n /* sercom number */ \ - } - -#ifndef CONF_SERCOM_0_SPI_ENABLE -#define CONF_SERCOM_0_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_1_SPI_ENABLE -#define CONF_SERCOM_1_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_2_SPI_ENABLE -#define CONF_SERCOM_2_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_3_SPI_ENABLE -#define CONF_SERCOM_3_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_4_SPI_ENABLE -#define CONF_SERCOM_4_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_5_SPI_ENABLE -#define CONF_SERCOM_5_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_6_SPI_ENABLE -#define CONF_SERCOM_6_SPI_ENABLE 0 -#endif -#ifndef CONF_SERCOM_7_SPI_ENABLE -#define CONF_SERCOM_7_SPI_ENABLE 0 -#endif - -/** Amount of SERCOM that is used as SPI */ -#define SERCOM_SPI_AMOUNT \ - (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ - + CONF_SERCOM_4_SPI_ENABLE \ - + CONF_SERCOM_5_SPI_ENABLE \ - + CONF_SERCOM_6_SPI_ENABLE \ - + CONF_SERCOM_7_SPI_ENABLE) - -#if SERCOM_SPI_AMOUNT < 1 -/** Dummy array for compiling. */ -static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; -#else -/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ -static const struct sercomspi_regs_cfg sercomspi_regs[] = { -#if CONF_SERCOM_0_SPI_ENABLE - SERCOMSPI_REGS(0), -#endif -#if CONF_SERCOM_1_SPI_ENABLE - SERCOMSPI_REGS(1), -#endif -#if CONF_SERCOM_2_SPI_ENABLE - SERCOMSPI_REGS(2), -#endif -#if CONF_SERCOM_3_SPI_ENABLE - SERCOMSPI_REGS(3), -#endif -#if CONF_SERCOM_4_SPI_ENABLE - SERCOMSPI_REGS(4), -#endif -#if CONF_SERCOM_5_SPI_ENABLE - SERCOMSPI_REGS(5), -#endif -#if CONF_SERCOM_6_SPI_ENABLE - SERCOMSPI_REGS(6), -#endif -#if CONF_SERCOM_7_SPI_ENABLE - SERCOMSPI_REGS(7), -#endif -}; -#endif - -/** \internal De-initialize SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return De-initialization status - */ -static int32_t _spi_deinit(void *const hw) -{ - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - hri_sercomspi_set_CTRLA_SWRST_bit(hw); - - return ERR_NONE; -} - -/** \internal Enable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Enabling status - */ -static int32_t _spi_sync_enable(void *const hw) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - hri_sercomspi_set_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** \internal Enable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Enabling status - */ -static int32_t _spi_async_enable(void *const hw) -{ - _spi_sync_enable(hw); - NVIC_EnableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_EnableIRQ((IRQn_Type)irq++); - } - - return ERR_NONE; -} - -/** \internal Disable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Disabling status - */ -static int32_t _spi_sync_disable(void *const hw) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); - - return ERR_NONE; -} - -/** \internal Disable SERCOM SPI - * - * \param[in] hw Pointer to the hardware register base. - * - * \return Disabling status - */ -static int32_t _spi_async_disable(void *const hw) -{ - _spi_sync_disable(hw); - hri_sercomspi_clear_INTEN_reg( - hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq++); - } - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI mode - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] mode The mode to set - * - * \return Setting mode status - */ -static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) -{ - uint32_t ctrla; - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { - return ERR_BUSY; - } - - ctrla = hri_sercomspi_read_CTRLA_reg(hw); - ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); - ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; - hri_sercomspi_write_CTRLA_reg(hw, ctrla); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI baudrate - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * - * \return Setting baudrate status - */ -static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) -{ - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - hri_sercomspi_write_BAUD_reg(hw, baud_val); - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI char size - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * \param[out] size Stored char size - * - * \return Setting char size status - */ -static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) -{ - /* Only 8-bit or 9-bit accepted */ - if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { - return ERR_INVALID_ARG; - } - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { - return ERR_BUSY; - } - - hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); - *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; - - return ERR_NONE; -} - -/** \internal Set SERCOM SPI data order - * - * \param[in] hw Pointer to the hardware register base. - * \param[in] baud_val The baudrate to set - * - * \return Setting data order status - */ -static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) -{ - uint32_t ctrla; - - if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { - return ERR_BUSY; - } - - ctrla = hri_sercomspi_read_CTRLA_reg(hw); - - if (dord == SPI_DATA_ORDER_LSB_1ST) { - ctrla |= SERCOM_SPI_CTRLA_DORD; - } else { - ctrla &= ~SERCOM_SPI_CTRLA_DORD; - } - hri_sercomspi_write_CTRLA_reg(hw, ctrla); - - return ERR_NONE; -} - -/** \brief Load SERCOM registers to init for SPI master mode - * The settings will be applied with default master mode, unsupported things - * are ignored. - * \param[in, out] hw Pointer to the hardware register base. - * \param[in] regs Pointer to register configuration values. - */ -static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) -{ - ASSERT(hw && regs); - hri_sercomspi_write_CTRLA_reg( - hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); - hri_sercomspi_write_CTRLB_reg( - hw, - (regs->ctrlb - & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) - | (SERCOM_SPI_CTRLB_RXEN)); - hri_sercomspi_write_BAUD_reg(hw, regs->baud); - hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); -} - -/** \brief Load SERCOM registers to init for SPI slave mode - * The settings will be applied with default slave mode, unsupported things - * are ignored. - * \param[in, out] hw Pointer to the hardware register base. - * \param[in] regs Pointer to register configuration values. - */ -static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) -{ - ASSERT(hw && regs); - hri_sercomspi_write_CTRLA_reg( - hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); - hri_sercomspi_write_CTRLB_reg(hw, - (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) - | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); - hri_sercomspi_write_ADDR_reg(hw, regs->addr); - hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); - while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) - ; -} - -/** \brief Return the pointer to register settings of specific SERCOM - * \param[in] hw_addr The hardware register base address. - * \return Pointer to register settings of specific SERCOM. - */ -static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) -{ - uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); - uint8_t i; - - for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { - if (sercomspi_regs[i].n == n) { - return &sercomspi_regs[i]; - } - } - - return NULL; -} - -int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) -{ - const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); - - ASSERT(dev && hw); - - if (regs == NULL) { - return ERR_INVALID_ARG; - } - - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - if (hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_sercomspi_set_CTRLA_SWRST_bit(hw); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - dev->prvt = hw; - - if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { - _spi_load_regs_slave(hw, regs); - } else { - _spi_load_regs_master(hw, regs); - } - - /* Load character size from default hardware configuration */ - dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; - - dev->dummy_byte = regs->dummy_byte; - - return ERR_NONE; -} - -int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) -{ - return _spi_m_sync_init(dev, hw); -} - -int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) -{ - struct _spi_async_dev *spid = dev; - /* Do hardware initialize. */ - int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); - - if (rc < 0) { - return rc; - } - - _sercom_init_irq_param(hw, (void *)dev); - /* Initialize callbacks: must use them */ - spid->callbacks.complete = NULL; - spid->callbacks.rx = NULL; - spid->callbacks.tx = NULL; - uint8_t irq = _sercom_get_irq_num(hw); - for (uint32_t i = 0; i < 4; i++) { - NVIC_DisableIRQ((IRQn_Type)irq); - NVIC_ClearPendingIRQ((IRQn_Type)irq); - irq++; - } - - return ERR_NONE; -} - -int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) -{ - return _spi_m_async_init(dev, hw); -} - -int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - - return _spi_deinit(dev->prvt); -} - -int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) -{ - NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); - - return _spi_deinit(dev->prvt); -} - -int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) -{ - return _spi_deinit(dev->prvt); -} - -int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) -{ - return _spi_deinit(dev->prvt); -} - -int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_enable(dev->prvt); -} - -int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_enable(dev->prvt); -} - -int32_t _spi_m_async_enable(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_enable(dev->prvt); -} - -int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_enable(dev->prvt); -} - -int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_disable(dev->prvt); -} - -int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_sync_disable(dev->prvt); -} - -int32_t _spi_m_async_disable(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_disable(dev->prvt); -} - -int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return _spi_async_disable(dev->prvt); -} - -int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_mode(dev->prvt, mode); -} - -int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) -{ - int32_t rc; - ASSERT(dev); - - /* Not accept 0es */ - if (clk == 0 || baud == 0) { - return ERR_INVALID_ARG; - } - - /* Check baudrate range of current assigned clock */ - if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { - return ERR_INVALID_ARG; - } - - rc = ((clk >> 1) / baud) - 1; - return rc; -} - -int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_baudrate(dev->prvt, baud_val); -} - -int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_baudrate(dev->prvt, baud_val); -} - -int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); -} - -int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) -{ - ASSERT(dev && dev->prvt); - - return _spi_set_data_order(dev->prvt, dord); -} - -/** Wait until SPI bus idle. */ -static inline void _spi_wait_bus_idle(void *const hw) -{ - while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { - ; - } - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); -} - -/** Holds run time information for message sync transaction. */ -struct _spi_trans_ctrl { - /** Pointer to transmitting data buffer. */ - uint8_t *txbuf; - /** Pointer to receiving data buffer. */ - uint8_t *rxbuf; - /** Count number of data transmitted. */ - uint32_t txcnt; - /** Count number of data received. */ - uint32_t rxcnt; - /** Data character size. */ - uint8_t char_size; -}; - -/** Check interrupt flag of RXC and update transaction runtime information. */ -static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) -{ - uint32_t data; - - if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { - return false; - } - - data = hri_sercomspi_read_DATA_reg(hw); - - if (ctrl->rxbuf) { - *ctrl->rxbuf++ = (uint8_t)data; - - if (ctrl->char_size > 1) { - *ctrl->rxbuf++ = (uint8_t)(data >> 8); - } - } - - ctrl->rxcnt++; - - return true; -} - -/** Check interrupt flag of DRE and update transaction runtime information. */ -static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, - uint16_t dummy) -{ - uint32_t data; - - if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { - return; - } - - if (ctrl->txbuf) { - data = *ctrl->txbuf++; - - if (ctrl->char_size > 1) { - data |= (*ctrl->txbuf) << 8; - ctrl->txbuf++; - } - } else { - data = dummy; - } - - ctrl->txcnt++; - hri_sercomspi_write_DATA_reg(hw, data); -} - -/** Check interrupt flag of ERROR and update transaction runtime information. */ -static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) -{ - if (SERCOM_SPI_INTFLAG_ERROR & iflag) { - hri_sercomspi_clear_STATUS_reg(hw, ~0); - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); - return ERR_OVERFLOW; - } - - return ERR_NONE; -} - -int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) -{ - void * hw = dev->prvt; - int32_t rc = 0; - struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; - - ASSERT(dev && hw); - - /* If settings are not applied (pending), we can not go on */ - if (hri_sercomspi_is_syncing( - hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { - return ERR_BUSY; - } - - /* SPI must be enabled to start synchronous transfer */ - if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { - return ERR_NOT_INITIALIZED; - } - - for (;;) { - uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); - - if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { - /* In master mode, do not start next byte before previous byte received - * to make better output waveform */ - if (ctrl.rxcnt >= ctrl.txcnt) { - _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); - } - } - - rc = _spi_err_check(iflag, hw); - - if (rc < 0) { - break; - } - if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { - rc = ctrl.txcnt; - break; - } - } - /* Wait until SPI bus idle */ - _spi_wait_bus_idle(hw); - - return rc; -} - -int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (state) { - hri_sercomspi_set_INTEN_DRE_bit(hw); - } else { - hri_sercomspi_clear_INTEN_DRE_bit(hw); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_tx(dev, state); -} - -int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) -{ - void *hw = dev->prvt; - - ASSERT(dev); - ASSERT(hw); - - if (state) { - hri_sercomspi_set_INTEN_RXC_bit(hw); - } else { - hri_sercomspi_clear_INTEN_RXC_bit(hw); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_rx(dev, state); -} - -int32_t _spi_m_async_enable_ss_detect(struct _spi_async_dev *dev, bool state) -{ - ASSERT(dev && dev->prvt); - - if (state) { - hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); - } else { - hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); - } - - return ERR_NONE; -} - -int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) -{ - return _spi_m_async_enable_ss_detect(dev, state); -} - -int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) -{ - ASSERT(dev && dev->prvt); - - hri_sercomspi_write_DATA_reg(dev->prvt, data); - - return ERR_NONE; -} - -uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomspi_read_DATA_reg(dev->prvt); -} - -int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, - const FUNC_PTR func) -{ - typedef void (*func_t)(void); - struct _spi_async_dev *spid = dev; - - ASSERT(dev && (cb_type < SPI_DEV_CB_N)); - - func_t *p_ls = (func_t *)&spid->callbacks; - p_ls[cb_type] = (func_t)func; - - return ERR_NONE; -} - -int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, - const FUNC_PTR func) -{ - return _spi_m_async_register_callback(dev, cb_type, func); -} - -bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); -} - -bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) -{ - ASSERT(dev && dev->prvt); - - return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); -} - -bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); - return true; - } - return false; -} - -bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) -{ - void *hw = dev->prvt; - - ASSERT(dev && hw); - - if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { - hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); - hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); - return true; - } - return false; -} - -/** - * \brief Enable/disable SPI master interrupt - * - * param[in] device The pointer to SPI master device instance - * param[in] type The type of interrupt to disable/enable if applicable - * param[in] state Enable or disable - */ -void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, - const bool state) -{ - ASSERT(device); - - if (SPI_DEV_CB_COMPLETE == type) { - hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); - } -} diff --git a/atmel-samd/asf4/samd51/hpl/systick/hpl_systick.c b/atmel-samd/asf4/samd51/hpl/systick/hpl_systick.c deleted file mode 100644 index 5ea3aac34..000000000 --- a/atmel-samd/asf4/samd51/hpl/systick/hpl_systick.c +++ /dev/null @@ -1,117 +0,0 @@ - -/** - * \file - * - * \brief SysTick related functionality implementation. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#ifdef _UNIT_TEST_ -#include -#endif - -/** - * \brief Initialize system time module - */ -void _system_time_init(void *const hw) -{ - (void)hw; - SysTick->LOAD = (0xFFFFFF << SysTick_LOAD_RELOAD_Pos); - SysTick->CTRL = (1 << SysTick_CTRL_ENABLE_Pos) | (CONF_SYSTICK_TICKINT << SysTick_CTRL_TICKINT_Pos) - | (1 << SysTick_CTRL_CLKSOURCE_Pos); -} -/** - * \brief Initialize delay functionality - */ -void _delay_init(void *const hw) -{ - _system_time_init(hw); -} - -/** - * \brief De-initialize system time module - */ -void _system_time_deinit(void *const hw) -{ - (void)hw; - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; -} - -/** - * \brief Get system time - */ -system_time_t _system_time_get(const void *const hw) -{ - (void)hw; - return (system_time_t)SysTick->VAL; -} - -/** - * \brief Get maximum possible system time - */ -system_time_t _system_time_get_max_time_value(const void *const hw) -{ - (void)hw; - return 0xFFFFFF; -} -/** - * \brief Delay loop to delay n number of cycles - */ -void _delay_cycles(void *const hw, uint32_t cycles) -{ - (void)hw; - uint8_t n = cycles >> 24; - uint32_t buf = cycles; - - while (n--) { - SysTick->LOAD = 0xFFFFFF; - SysTick->VAL = 0xFFFFFF; - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) - ; - buf -= 0xFFFFFF; - } - - SysTick->LOAD = buf; - SysTick->VAL = buf; - while (!(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)) - ; -} diff --git a/atmel-samd/asf4/samd51/hpl/tc/hpl_tc.c b/atmel-samd/asf4/samd51/hpl/tc/hpl_tc.c deleted file mode 100644 index a897d8f39..000000000 --- a/atmel-samd/asf4/samd51/hpl/tc/hpl_tc.c +++ /dev/null @@ -1,377 +0,0 @@ - -/** - * \file - * - * \brief SAM TC - * - * Copyright (C) 2014 - 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include -#include -#include - -#ifndef CONF_TC0_ENABLE -#define CONF_TC0_ENABLE 0 -#endif -#ifndef CONF_TC1_ENABLE -#define CONF_TC1_ENABLE 0 -#endif -#ifndef CONF_TC2_ENABLE -#define CONF_TC2_ENABLE 0 -#endif -#ifndef CONF_TC3_ENABLE -#define CONF_TC3_ENABLE 0 -#endif -#ifndef CONF_TC4_ENABLE -#define CONF_TC4_ENABLE 0 -#endif -#ifndef CONF_TC5_ENABLE -#define CONF_TC5_ENABLE 0 -#endif -#ifndef CONF_TC6_ENABLE -#define CONF_TC6_ENABLE 0 -#endif -#ifndef CONF_TC7_ENABLE -#define CONF_TC7_ENABLE 0 -#endif - -/** - * \brief Macro is used to fill usart configuration structure based on its - * number - * - * \param[in] n The number of structures - */ -#define TC_CONFIGURATION(n) \ - { \ - n, TC##n##_IRQn, \ - TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC) \ - | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos) \ - | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos), \ - (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \ - | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \ - | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \ - (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1, \ - } -/** - * \brief TC configuration type - */ -struct tc_configuration { - uint8_t number; - IRQn_Type irq; - hri_tc_ctrla_reg_t ctrl_a; - hri_tc_evctrl_reg_t event_ctrl; - hri_tc_dbgctrl_reg_t dbg_ctrl; - hri_tc_per_reg_t per; - hri_tc_cc32_reg_t cc0; - hri_tc_cc32_reg_t cc1; -}; - -/** - * \brief Array of TC configurations - */ -static struct tc_configuration _tcs[] = { -#if CONF_TC0_ENABLE == 1 - TC_CONFIGURATION(0), -#endif -#if CONF_TC1_ENABLE == 1 - TC_CONFIGURATION(1), -#endif -#if CONF_TC2_ENABLE == 1 - TC_CONFIGURATION(2), -#endif -#if CONF_TC3_ENABLE == 1 - TC_CONFIGURATION(3), -#endif -#if CONF_TC4_ENABLE == 1 - TC_CONFIGURATION(4), -#endif -#if CONF_TC5_ENABLE == 1 - TC_CONFIGURATION(5), -#endif -#if CONF_TC6_ENABLE == 1 - TC_CONFIGURATION(6), -#endif -#if CONF_TC7_ENABLE == 1 - TC_CONFIGURATION(7), -#endif -}; - -static struct _pwm_device *_tc0_dev = NULL; - -static int8_t get_tc_index(const void *const hw); -static void _tc_init_irq_param(const void *const hw, void *dev); -static inline uint8_t _get_hardware_offset(const void *const hw); -/** - * \brief Initialize TC for PWM mode - */ -int32_t _pwm_init(struct _pwm_device *const device, void *const hw) -{ - int8_t i = get_tc_index(hw); - device->hw = hw; - - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - if (hri_tc_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_tc_set_CTRLA_SWRST_bit(hw); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - - hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); - hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); - hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); - hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MPWM_Val); - - if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { - hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); - hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); - } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { - hri_tccount16_write_CC_reg(hw, 0, (hri_tc_count16_reg_t)_tcs[i].cc0); - hri_tccount16_write_CC_reg(hw, 1, (hri_tc_count16_reg_t)_tcs[i].cc1); - } else { - /* 8-bit resolution is not accepted by duty cycle control */ - return -1; - } - - _tc_init_irq_param(hw, (void *)device); - NVIC_DisableIRQ(_tcs[i].irq); - NVIC_ClearPendingIRQ(_tcs[i].irq); - NVIC_EnableIRQ(_tcs[i].irq); - - return 0; -} -/** - * \brief De-initialize TC for PWM mode - */ -void _pwm_deinit(struct _pwm_device *const device) -{ - void *const hw = device->hw; - int8_t i = get_tc_index(hw); - ASSERT(ARRAY_SIZE(_tcs)); - - NVIC_DisableIRQ(_tcs[i].irq); - - hri_tc_clear_CTRLA_ENABLE_bit(hw); - hri_tc_set_CTRLA_SWRST_bit(hw); -} -/** - * \brief Start PWM - */ -void _pwm_enable(struct _pwm_device *const device) -{ - hri_tc_set_CTRLA_ENABLE_bit(device->hw); -} -/** - * \brief Stop PWM - */ -void _pwm_disable(struct _pwm_device *const device) -{ - hri_tc_clear_CTRLA_ENABLE_bit(device->hw); -} -/** - * \brief Set PWM parameter - */ -void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle) -{ - void *const hw = device->hw; - int8_t i = get_tc_index(hw); - - _tcs[i].cc0 = period; - _tcs[i].cc1 = duty_cycle; - if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { - hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); - hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); - } else { - hri_tccount16_write_CC_reg(hw, 0, _tcs[i].cc0); - hri_tccount16_write_CC_reg(hw, 1, _tcs[i].cc1); - } -} -/** - * \brief Get pwm waveform period value - */ -pwm_period_t _pwm_get_period(const struct _pwm_device *const device) -{ - void *const hw = device->hw; - int8_t i = get_tc_index(hw); - - if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { - return (pwm_period_t)(hri_tccount32_read_CC_reg(hw, 0)); - } else { - return (pwm_period_t)(hri_tccount16_read_CC_reg(hw, 0)); - } -} -/** - * \brief Get pwm waveform duty cycle - */ -uint32_t _pwm_get_duty(const struct _pwm_device *const device) -{ - void *const hw = device->hw; - int8_t i = get_tc_index(hw); - uint32_t per; - uint32_t duty_cycle; - - if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { - per = hri_tccount32_read_CC_reg(hw, 0); - duty_cycle = hri_tccount32_read_CC_reg(hw, 1); - } else { - per = hri_tccount16_read_CC_reg(hw, 0); - duty_cycle = hri_tccount16_read_CC_reg(hw, 1); - } - - return ((duty_cycle * 1000) / per); -} -/** - * \brief Check if PWM is running - */ -bool _pwm_is_enabled(const struct _pwm_device *const device) -{ - return hri_tc_get_CTRLA_ENABLE_bit(device->hw); -} -/** - * \brief Enable/disable PWM interrupt - */ -void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable) -{ - ASSERT(device); - - if (PWM_DEVICE_PERIOD_CB == type) { - hri_tc_write_INTEN_OVF_bit(device->hw, disable); - } else if (PWM_DEVICE_ERROR_CB == type) { - hri_tc_write_INTEN_ERR_bit(device->hw, disable); - } -} - -/** - * \brief Retrieve timer helper functions - */ -struct _timer_hpl_interface *_tc_get_timer(void) -{ - return NULL; -} - -/** - * \brief Retrieve pwm helper functions - */ -struct _pwm_hpl_interface *_tc_get_pwm(void) -{ - return NULL; -} -/** - * \internal TC interrupt handler for PWM - * - * \param[in] instance TC instance number - */ -static void tc_pwm_interrupt_handler(struct _pwm_device *device) -{ - void *const hw = device->hw; - - if (hri_tc_get_interrupt_OVF_bit(hw)) { - hri_tc_clear_interrupt_OVF_bit(hw); - if (NULL != device->callback.pwm_period_cb) { - device->callback.pwm_period_cb(device); - } - } - if (hri_tc_get_INTEN_ERR_bit(hw)) { - hri_tc_clear_interrupt_ERR_bit(hw); - if (NULL != device->callback.pwm_error_cb) { - device->callback.pwm_error_cb(device); - } - } -} - -/** -* \brief TC interrupt handler -*/ -void TC0_Handler(void) -{ - tc_pwm_interrupt_handler(_tc0_dev); -} - -/** - * \internal Retrieve TC index - * - * \param[in] hw The pointer to hardware instance - * - * \return The index of TC configuration - */ -static int8_t get_tc_index(const void *const hw) -{ - uint8_t index = _get_hardware_offset(hw); - uint8_t i; - - for (i = 0; i < ARRAY_SIZE(_tcs); i++) { - if (_tcs[i].number == index) { - return i; - } - } - - ASSERT(false); - return -1; -} - -/** - * \brief Init irq param with the given tc hardware instance - */ -static void _tc_init_irq_param(const void *const hw, void *dev) -{ - if (hw == TC0) { - _tc0_dev = (struct _pwm_device *)dev; - } -} - -/** - * \internal Retrieve TC hardware index - * - * \param[in] hw The pointer to hardware instance - */ -static inline uint8_t _get_hardware_offset(const void *const hw) -{ - /* List of available TC modules. */ - Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; - - /* Find index for TC instance. */ - for (uint32_t i = 0; i < TC_INST_NUM; i++) { - if ((uint32_t)hw == (uint32_t)tc_modules[i]) { - return i; - } - } - return 0; -} diff --git a/atmel-samd/asf4/samd51/hpl/tc/hpl_tc_base.h b/atmel-samd/asf4/samd51/hpl/tc/hpl_tc_base.h deleted file mode 100644 index 9d7f2c72a..000000000 --- a/atmel-samd/asf4/samd51/hpl/tc/hpl_tc_base.h +++ /dev/null @@ -1,87 +0,0 @@ -/** - * \file - * - * \brief SAM Timer/Counter - * - * Copyright (C) 2014 - 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distributionn. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifndef _HPL_TC_BASE_H_INCLUDED -#define _HPL_TC_BASE_H_INCLUDED - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \addtogroup tc_group TC Hardware Proxy Layer - * - * \section tc_hpl_rev Revision History - * - v0.0.0.1 Initial Commit - * - *@{ - */ - -/** - * \name HPL functions - */ -//@{ - -/** - * \brief Retrieve timer helper functions - * - * \return A pointer to set of timer helper functions - */ -struct _timer_hpl_interface *_tc_get_timer(void); - -/** - * \brief Retrieve pwm helper functions - * - * \return A pointer to set of pwm helper functions - */ -struct _pwm_hpl_interface *_tc_get_pwm(void); - -//@} -/**@}*/ - -#ifdef __cplusplus -} -#endif -#endif /* _HPL_TC_BASE_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/hpl/trng/hpl_trng.c b/atmel-samd/asf4/samd51/hpl/trng/hpl_trng.c deleted file mode 100644 index 2b1f35a16..000000000 --- a/atmel-samd/asf4/samd51/hpl/trng/hpl_trng.c +++ /dev/null @@ -1,120 +0,0 @@ -/** - * \file - * - * \brief True Random Number Generator - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -static inline int32_t _trng_init(void *hw) -{ - if (hri_trng_get_CTRLA_reg(hw, TRNG_CTRLA_ENABLE)) { - return ERR_DENIED; - } - if (CONF_TRNG_RUNSTDBY) { - hri_trng_set_CTRLA_RUNSTDBY_bit(hw); - } else { - hri_trng_clear_CTRLA_RUNSTDBY_bit(hw); - } - if (CONF_TRNG_DATARDYEO) { - hri_trng_set_EVCTRL_DATARDYEO_bit(hw); - } else { - hri_trng_clear_EVCTRL_DATARDYEO_bit(hw); - } - return ERR_NONE; -} - -int32_t _rand_sync_init(struct _rand_sync_dev *const dev, void *const hw) -{ - int32_t rc; - - ASSERT(dev && hw); - - rc = _trng_init(hw); - if (rc == ERR_NONE) { - dev->prvt = hw; - dev->n_bits = 32; - } - return rc; -} - -void _rand_sync_deinit(struct _rand_sync_dev *const dev) -{ - _rand_sync_disable(dev); -} - -int32_t _rand_sync_enable(struct _rand_sync_dev *const dev) -{ - ASSERT(dev); - ASSERT(dev->prvt); - - hri_trng_set_CTRLA_ENABLE_bit(dev->prvt); - return ERR_NONE; -} - -void _rand_sync_disable(struct _rand_sync_dev *const dev) -{ - ASSERT(dev); - ASSERT(dev->prvt); - - hri_trng_clear_CTRLA_ENABLE_bit(dev->prvt); -} - -int32_t _rand_sync_set_seed(struct _rand_sync_dev *const dev, const uint32_t seed) -{ - (void)dev; - (void)seed; - return ERR_UNSUPPORTED_OP; -} - -uint32_t _rand_sync_read_one(const struct _rand_sync_dev *const dev) -{ - ASSERT(dev); - ASSERT(dev->prvt); - ASSERT(hri_trng_get_CTRLA_reg(dev->prvt, TRNG_CTRLA_ENABLE)); - - while (!hri_trng_get_INTFLAG_reg(dev->prvt, TRNG_INTFLAG_DATARDY)) { - /* Wait until data ready. */ - } - return hri_trng_read_DATA_reg(dev->prvt); -} diff --git a/atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c b/atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c deleted file mode 100644 index b9cec2e28..000000000 --- a/atmel-samd/asf4/samd51/hpl/usb/hpl_usb.c +++ /dev/null @@ -1,2087 +0,0 @@ -/** - * \file - * - * \brief SAM USB HPL - * - * Copyright (C) 2015-2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include -#include -#include -#include - -#include -#include -#include - -/** - * \brief Dummy callback function - * \return Always false. - */ -static bool _dummy_func_no_return(uint32_t unused0, uint32_t unused1) -{ - (void)unused0; - (void)unused1; - return false; -} - -/** - * \brief Load USB calibration value from NVM - */ -static void _usb_load_calib(void) -{ -#define NVM_USB_PAD_TRANSN_POS 32 -#define NVM_USB_PAD_TRANSN_SIZE 5 -#define NVM_USB_PAD_TRANSP_POS 37 -#define NVM_USB_PAD_TRANSP_SIZE 5 -#define NVM_USB_PAD_TRIM_POS 42 -#define NVM_USB_PAD_TRIM_SIZE 3 - Usb * hw = USB; - uint32_t pad_transn - = (*((uint32_t *)(NVMCTRL_SW0) + (NVM_USB_PAD_TRANSN_POS / 32)) >> (NVM_USB_PAD_TRANSN_POS % 32)) - & ((1 << NVM_USB_PAD_TRANSN_SIZE) - 1); - uint32_t pad_transp - = (*((uint32_t *)(NVMCTRL_SW0) + (NVM_USB_PAD_TRANSP_POS / 32)) >> (NVM_USB_PAD_TRANSP_POS % 32)) - & ((1 << NVM_USB_PAD_TRANSP_SIZE) - 1); - uint32_t pad_trim = (*((uint32_t *)(NVMCTRL_SW0) + (NVM_USB_PAD_TRIM_POS / 32)) >> (NVM_USB_PAD_TRIM_POS % 32)) - & ((1 << NVM_USB_PAD_TRIM_SIZE) - 1); - if (pad_transn == 0 || pad_transn == 0x1F) { - pad_transn = 9; - } - if (pad_transp == 0 || pad_transp == 0x1F) { - pad_transp = 25; - } - if (pad_trim == 0 || pad_trim == 0x7) { - pad_trim = 6; - } - - hw->DEVICE.PADCAL.reg = USB_PADCAL_TRANSN(pad_transn) | USB_PADCAL_TRANSP(pad_transp) | USB_PADCAL_TRIM(pad_trim); - - hw->DEVICE.QOSCTRL.bit.CQOS = 3; - hw->DEVICE.QOSCTRL.bit.DQOS = 3; -} - -/** \name USB clock source management */ -/*@{*/ - -/** USB clock is generated by DFLL. */ -#define USB_CLK_SRC_DFLL 0 - -/** USB clock is generated by DPLL. */ -#define USB_CLK_SRC_DPLL 1 - -/** Uses DFLL as USB clock source. */ -#define CONF_USB_D_CLK_SRC USB_CLK_SRC_DFLL - -/** Retry for USB remote wakeup sending. */ -#define CONF_USB_RMT_WKUP_RETRY 5 - -/** - * \brief Wait DPLL clock to be ready - */ -static inline void _usb_d_dev_wait_dpll_rdy(void) -{ -#define DPLL_READY_FLAG (OSCCTRL_DPLLSTATUS_CLKRDY | OSCCTRL_DPLLSTATUS_LOCK) - while (hri_oscctrl_get_DPLLSTATUS_reg(OSCCTRL, 0, DPLL_READY_FLAG) != DPLL_READY_FLAG) - ; -} - -/** - * \brief Wait DFLL clock to be ready - */ -static inline void _usb_d_dev_wait_dfll_rdy(void) -{ - if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(OSCCTRL)) { - while (hri_oscctrl_get_STATUS_reg(OSCCTRL, (OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC)) - != (OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC)) - ; - } else { - while (hri_oscctrl_get_STATUS_reg(OSCCTRL, OSCCTRL_STATUS_DFLLRDY) != OSCCTRL_STATUS_DFLLRDY) - ; - } -} - -/** - * \brief Wait USB source clock to be ready - * \param[in] clk_src Clock source, could be \ref USB_CLK_SRC_DFLL or - * \ref USB_CLK_SRC_DPLL. - */ -static inline void _usb_d_dev_wait_clk_rdy(const uint8_t clk_src) -{ - if (clk_src == USB_CLK_SRC_DFLL) { - _usb_d_dev_wait_dfll_rdy(); - } else if (clk_src == USB_CLK_SRC_DPLL) { - _usb_d_dev_wait_dpll_rdy(); - } -} - -/*@}*/ - -/** \name USB general settings */ -/*@{*/ - -/** Increase the value to be aligned. */ -#define _usb_align_up(val) (((val)&0x3) ? (((val) + 4 - ((val)&0x3))) : (val)) - -/** Check if the buffer is in RAM (can DMA), or cache needed - * \param[in] a Buffer start address. - * \param[in] s Buffer size, in number of bytes. - * \return \c true If the buffer is in RAM. - */ -#define _IN_RAM(a, s) ((0x20000000 <= (uint32_t)(a)) && (((uint32_t)(a) + (s)) < 0x20008000)) - -/** Check if the address should be placed in RAM. */ -#define _usb_is_addr4dma(addr, size) _IN_RAM((addr), (size)) - -/** Check if the address is 32-bit aligned. */ -#define _usb_is_aligned(val) (((uint32_t)(val)&0x3) == 0) -/*@}*/ - -/* Cache static configurations. - * By default, all OUT endpoint have 64 bytes cache. */ -#ifndef CONF_USB_EP0_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP0_CACHE 64 -#endif - -#ifndef CONF_USB_EP0_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP0_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP1_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP1_CACHE 64 -#endif - -#ifndef CONF_USB_EP1_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP1_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP2_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP2_CACHE 64 -#endif - -#ifndef CONF_USB_EP2_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP2_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP3_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP3_CACHE 64 -#endif - -#ifndef CONF_USB_EP3_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP3_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP4_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP4_CACHE 64 -#endif - -#ifndef CONF_USB_EP4_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP4_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP5_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP5_CACHE 64 -#endif - -#ifndef CONF_USB_EP5_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP5_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP6_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP6_CACHE 64 -#endif - -#ifndef CONF_USB_EP6_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP6_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP7_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP7_CACHE 64 -#endif - -#ifndef CONF_USB_EP7_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP7_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP8_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP8_CACHE 64 -#endif - -#ifndef CONF_USB_EP8_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP8_I_CACHE 0 -#endif - -#ifndef CONF_USB_EP9_CACHE -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#define CONF_USB_EP9_CACHE 64 -#endif - -#ifndef CONF_USB_EP9_I_CACHE -/** Endpoint cache buffer for IN transactions (none-control). */ -#define CONF_USB_EP9_I_CACHE 0 -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP0_CACHE -static uint32_t _usb_ep0_cache[_usb_align_up(CONF_USB_EP0_CACHE) / 4]; -#else -#define _usb_ep0_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#define _usb_ep0_i_cache NULL - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP1_CACHE && CONF_USB_D_MAX_EP_N >= 1 -uint32_t _usb_ep1_cache[_usb_align_up(CONF_USB_EP1_CACHE) / 4]; -#else -#define _usb_ep1_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP1_I_CACHE && CONF_USB_D_MAX_EP_N >= 1 -uint32_t _usb_ep1_i_cache[_usb_align_up(CONF_USB_EP1_I_CACHE) / 4]; -#else -#define _usb_ep1_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP2_CACHE && CONF_USB_D_MAX_EP_N >= 2 -static uint32_t _usb_ep2_cache[_usb_align_up(CONF_USB_EP2_CACHE) / 4]; -#else -#define _usb_ep2_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP2_I_CACHE && CONF_USB_D_MAX_EP_N >= 2 -static uint32_t _usb_ep2_i_cache[_usb_align_up(CONF_USB_EP2_I_CACHE) / 4]; -#else -#define _usb_ep2_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP3_CACHE && CONF_USB_D_MAX_EP_N >= 3 -static uint32_t _usb_ep3_cache[_usb_align_up(CONF_USB_EP3_CACHE) / 4]; -#else -#define _usb_ep3_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP3_I_CACHE && CONF_USB_D_MAX_EP_N >= 3 -static uint32_t _usb_ep3_i_cache[_usb_align_up(CONF_USB_EP3_I_CACHE) / 4]; -#else -#define _usb_ep3_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP4_CACHE && CONF_USB_D_MAX_EP_N >= 4 -static uint32_t _usb_ep4_cache[_usb_align_up(CONF_USB_EP4_CACHE) / 4]; -#else -#define _usb_ep4_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP4_I_CACHE && CONF_USB_D_MAX_EP_N >= 4 -static uint32_t _usb_ep4_i_cache[_usb_align_up(CONF_USB_EP4_I_CACHE) / 4]; -#else -#define _usb_ep4_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP5_CACHE && CONF_USB_D_MAX_EP_N >= 5 -static uint32_t _usb_ep5_cache[_usb_align_up(CONF_USB_EP5_CACHE) / 4]; -#else -#define _usb_ep5_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP5_I_CACHE && CONF_USB_D_MAX_EP_N >= 5 -static uint32_t _usb_ep5_i_cache[_usb_align_up(CONF_USB_EP5_I_CACHE) / 4]; -#else -#define _usb_ep5_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP6_CACHE && CONF_USB_D_MAX_EP_N >= 6 -static uint32_t _usb_ep6_cache[_usb_align_up(CONF_USB_EP6_CACHE) / 4]; -#else -#define _usb_ep6_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP6_I_CACHE && CONF_USB_D_MAX_EP_N >= 6 -static uint32_t _usb_ep6_i_cache[_usb_align_up(CONF_USB_EP6_I_CACHE) / 4]; -#else -#define _usb_ep6_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP7_CACHE && CONF_USB_D_MAX_EP_N >= 7 -static uint32_t _usb_ep7_cache[_usb_align_up(CONF_USB_EP7_CACHE) / 4]; -#else -#define _usb_ep7_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP7_I_CACHE && CONF_USB_D_MAX_EP_N >= 7 -static uint32_t _usb_ep7_i_cache[_usb_align_up(CONF_USB_EP7_I_CACHE) / 4]; -#else -#define _usb_ep7_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP8_CACHE && CONF_USB_D_MAX_EP_N >= 8 -static uint32_t _usb_ep8_cache[_usb_align_up(CONF_USB_EP8_CACHE) / 4]; -#else -#define _usb_ep8_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP8_I_CACHE && CONF_USB_D_MAX_EP_N >= 8 -static uint32_t _usb_ep8_i_cache[_usb_align_up(CONF_USB_EP8_I_CACHE) / 4]; -#else -#define _usb_ep8_i_cache NULL -#endif - -/** Endpoint cache buffer for OUT transactions (none-control) or SETUP/IN/OUT - * transactions (control). */ -#if CONF_USB_EP9_CACHE && CONF_USB_D_MAX_EP_N >= 9 -static uint32_t _usb_ep9_cache[_usb_align_up(CONF_USB_EP9_CACHE) / 4]; -#else -#define _usb_ep9_cache NULL -#endif - -/** Endpoint cache buffer for IN transactions (none-control). */ -#if CONF_USB_EP9_I_CACHE && CONF_USB_D_MAX_EP_N >= 9 -static uint32_t _usb_ep9_i_cache[_usb_align_up(CONF_USB_EP9_I_CACHE) / 4]; -#else -#define _usb_ep9_i_cache NULL -#endif - -/** Access endpoint cache buffer for OUT transactions (none-control) or - * SETUP/IN/OUT transactions (control). */ -#define _USB_EP_CACHE(n) ((void *)_usb_ep##n##_cache) - -/** Access endpoint cache buffer for IN transactions (none-control). */ -#define _USB_EP_I_CACHE(n) ((void *)_usb_ep##n##_i_cache) - -/** The configuration settings for one of the endpoint hardware. */ -struct _usb_ep_cfg_item { - /* Endpoint cache buffer for OUT transactions (none-control) or - * SETUP/IN/OUT transactions (control). */ - void *cache; - /* endpoint cache buffer for IN transactions (none-control). */ - void *i_cache; - /* Cache buffer size for OUT transactions (none-control) or - * SETUP/IN/OUT transactions (control). */ - uint16_t size; - /* Cache buffer size for IN transactions (none-control). */ - uint16_t i_size; -}; - -/** Build the endpoint configuration settings for one endpoint. */ -#define _USB_EP_CFG_ITEM(n) \ - { \ - _USB_EP_CACHE(n), _USB_EP_I_CACHE(n), CONF_USB_EP##n##_CACHE, CONF_USB_EP##n##_I_CACHE, \ - } - -/** The configuration settings for all endpoint. */ -static const struct _usb_ep_cfg_item _usb_ep_cfgs[] = {_USB_EP_CFG_ITEM(0) -#if CONF_USB_D_MAX_EP_N >= 1 - , - _USB_EP_CFG_ITEM(1) -#endif -#if CONF_USB_D_MAX_EP_N >= 2 - , - _USB_EP_CFG_ITEM(2) -#endif -#if CONF_USB_D_MAX_EP_N >= 3 - , - _USB_EP_CFG_ITEM(3) -#endif -#if CONF_USB_D_MAX_EP_N >= 4 - , - _USB_EP_CFG_ITEM(4) -#endif -#if CONF_USB_D_MAX_EP_N >= 5 - , - _USB_EP_CFG_ITEM(5) -#endif -#if CONF_USB_D_MAX_EP_N >= 6 - , - _USB_EP_CFG_ITEM(6) -#endif -#if CONF_USB_D_MAX_EP_N >= 7 - , - _USB_EP_CFG_ITEM(7) -#endif -#if CONF_USB_D_MAX_EP_N >= 8 - , - _USB_EP_CFG_ITEM(8) -#endif -#if CONF_USB_D_MAX_EP_N >= 9 - , - _USB_EP_CFG_ITEM(9) -#endif -}; - -/** \name HW specific settings and implements */ -/*@{*/ - -/** Number of endpoints supported. */ -#define USB_D_N_EP (1 + CONF_USB_D_NUM_EP_SP * 2) - -/** HPL USB device endpoint struct. */ -struct _usb_d_dev_ep { - /** Pointer to transaction buffer. */ - uint8_t *trans_buf; - /** Transaction size. */ - uint32_t trans_size; - /** Transaction transferred count. */ - uint32_t trans_count; - - /** Pointer to cache buffer, must be aligned. */ - uint8_t *cache; - - /** Endpoint size. */ - uint16_t size; - /** Endpoint address. */ - uint8_t ep; - /** Feature flags. */ - union { - /** Interpreted by bit fields. */ - struct { - /** EPCFG.ETYPE. */ - uint8_t eptype : 3; - /** Stall status. */ - uint8_t is_stalled : 1; - /** Transaction auto ZLP. */ - uint8_t need_zlp : 1; - /** Transaction with cache */ - uint8_t use_cache : 1; - /** Endpoint is busy. */ - uint8_t is_busy : 1; - /** Transaction direction. */ - uint8_t dir : 1; - } bits; - uint8_t u8; - } flags; -}; - -/** Check if the endpoint is used. */ -#define _usb_d_dev_ep_is_used(ept) ((ept)->ep != 0xFF) - -/** Check if the endpoint is busy doing transactions. */ -#define _usb_d_dev_ep_is_busy(ept) ((ept)->flags.bits.is_busy) - -/** Check if the endpoint is control endpoint. */ -#define _usb_d_dev_ep_is_ctrl(ept) ((ept)->flags.bits.eptype == USB_D_EPTYPE_CTRL) - -/** Check if the endpoint transactions are IN. */ -#define _usb_d_dev_ep_is_in(ept) ((ept)->flags.bits.dir) - -/** Interrupt flags for SETUP transaction. */ -#define USB_D_SETUP_INT_FLAGS (USB_DEVICE_EPINTFLAG_RXSTP) - -/** Interrupt flags for BANK1 transactions. */ -#define USB_D_BANK1_INT_FLAGS (USB_DEVICE_EPINTFLAG_TRCPT1 | USB_DEVICE_EPINTFLAG_TRFAIL1 | USB_DEVICE_EPINTFLAG_STALL1) - -/** Interrupt flags for BANK0 transactions. */ -#define USB_D_BANK0_INT_FLAGS (USB_DEVICE_EPINTFLAG_TRCPT0 | USB_DEVICE_EPINTFLAG_TRFAIL0 | USB_DEVICE_EPINTFLAG_STALL0) - -/** Interrupt flags for SETUP/IN/OUT transactions. */ -#define USB_D_ALL_INT_FLAGS (0x7F) - -/** Interrupt flags for WAKEUP event. */ -#define USB_D_WAKEUP_INT_FLAGS (USB_DEVICE_INTFLAG_UPRSM | USB_DEVICE_INTFLAG_EORSM | USB_DEVICE_INTFLAG_WAKEUP) - -/** Interrupt flags for SUSPEND event. */ -#define USB_D_SUSPEND_INT_FLAGS (USB_DEVICE_INTFLAG_LPMSUSP | USB_DEVICE_INTFLAG_SUSPEND) - -/** Max data bytes for a single DMA transfer. */ -#define USB_D_DEV_TRANS_MAX 8192 /* 14-bits, uses 13-bits. */ - -/** Endpoint type setting to disable. */ -#define USB_D_EPTYPE_DISABLE 0 - -/** Endpoint type setting to work as control endpoint. */ -#define USB_D_EPTYPE_CTRL 1 - -/** Endpoint type setting to work as isochronous endpoint. */ -#define USB_D_EPTYPE_ISOCH 2 - -/** Endpoint type setting to work as interrupt endpoint. */ -#define USB_D_EPTYPE_INT 3 - -/** Endpoint type setting to work as bulk endpoint. */ -#define USB_D_EPTYPE_BULK 4 - -/** Endpoint type setting for dual bank endpoint. */ -#define USB_D_EPTYPE_DUAL 5 - -/** EPCFG register value for control endpoints. */ -#define USB_D_EPCFG_CTRL 0x11 - -/** HPL USB device struct. */ -struct _usb_d_dev { - /** Callbacks of USB device. */ - struct _usb_d_dev_callbacks callbacks; - /** Endpoint transaction callbacks. */ - struct _usb_d_dev_ep_callbacks ep_callbacks; - /** Endpoints (ep0 + others). */ - struct _usb_d_dev_ep ep[USB_D_N_EP]; -}; - -/** Private data for SAM0 USB peripheral. - */ -typedef struct _usb_d_dev_prvt { - /** USB device descriptor table for peripheral to work. */ - UsbDeviceDescriptor desc_table[CONF_USB_D_MAX_EP_N + 1]; -} usb_d_dev_prvt_t; - -/*@}*/ - -/** USB device driver instance. */ -static struct _usb_d_dev dev_inst; - -/** USB device driver private data instance. */ -static struct _usb_d_dev_prvt prvt_inst; - -static void _usb_d_dev_reset_epts(void); - -static void _usb_d_dev_trans_done(struct _usb_d_dev_ep *ept, const int32_t status); -static void _usb_d_dev_trans_stop(struct _usb_d_dev_ep *ept, bool dir, const int32_t code); - -static void _usb_d_dev_in_next(struct _usb_d_dev_ep *ept, bool isr); -static void _usb_d_dev_out_next(struct _usb_d_dev_ep *ept, bool isr); - -static inline void _usb_d_dev_trans_setup(struct _usb_d_dev_ep *ept); - -/** \brief ACK the endpoint interrupt - * \param[in] epn Endpoint number. - * \param[in] flags Interrupt flags. - */ -static inline void _usbd_ep_int_ack(uint8_t epn, uint32_t flags) -{ - hri_usbendpoint_clear_EPINTFLAG_reg(USB, epn, flags); -} - -/** \brief Enable the endpoint interrupt - * \param[in] epn Endpoint number. - * \param[in] flags Interrupt flags. - */ -static inline void _usbd_ep_int_en(uint8_t epn, uint32_t flags) -{ - hri_usbendpoint_set_EPINTEN_reg(USB, epn, flags); -} - -/** \brief Disable the endpoint interrupt - * \param[in] epn Endpoint number. - * \param[in] flags Interrupt flags. - */ -static inline void _usbd_ep_int_dis(uint8_t epn, uint32_t flags) -{ - hri_usbendpoint_clear_EPINTEN_reg(USB, epn, flags); -} - -/** \brief Check if endpoint is control endpoint - * \param[in] epn Endpoint number. - */ -static inline bool _usbd_ep_is_ctrl(uint8_t epn) -{ - return (hri_usbendpoint_read_EPCFG_reg(USB, epn) == USB_D_EPCFG_CTRL); -} - -/** \brief Set endpoint stall - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] st Stall status. - */ -static inline void _usbd_ep_set_stall(uint8_t epn, uint8_t bank_n, bool st) -{ - if (st) { - hri_usbendpoint_set_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); - } else { - hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); - } -} - -/** \brief Check if the endpoint is stalled - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \return \c true if it's stalled. - */ -static inline bool _usbd_ep_is_stalled(uint8_t epn, uint8_t bank_n) -{ - Usb *hw = USB; - return (hri_usbendpoint_read_EPSTATUS_reg(hw, epn) & (USB_DEVICE_EPSTATUS_STALLRQ0 << bank_n)); -} - -/** \brief Check if stall has been sent from the endpoint - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \return \c true if it's sent. - */ -static inline bool _usbd_ep_is_stall_sent(uint8_t epn, uint8_t bank_n) -{ - Usb *hw = USB; - return (hri_usbendpoint_read_EPINTFLAG_reg(hw, epn) & (USB_DEVICE_EPINTFLAG_STALL0 << bank_n)); -} - -/** \brief ACK endpoint STALL interrupt - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - */ -static inline void _usbd_ep_ack_stall(uint8_t epn, uint8_t bank_n) -{ - _usbd_ep_int_ack(epn, (USB_DEVICE_EPINTFLAG_STALL0 << bank_n)); -} - -/** \brief Enable/disable endpoint STALL interrupt - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] en \c true to enable, \c false to disable. - */ -static inline void _usbd_ep_int_stall_en(uint8_t epn, uint8_t bank_n, const bool en) -{ - if (en) { - _usbd_ep_int_en(epn, USB_DEVICE_EPINTFLAG_STALL0 << bank_n); - } else { - _usbd_ep_int_dis(epn, USB_DEVICE_EPINTFLAG_STALL0 << bank_n); - } -} - -/** \brief Stop SETUP transactions - * \param[in] epn Endpoint number. - */ -static inline void _usbd_ep_stop_setup(uint8_t epn) -{ - hri_usbendpoint_clear_EPINTEN_RXSTP_bit(USB, epn); -} - -/** \brief Check if SETUP packet is ready in cache - * \param[in] epn Endpoint number. - */ -static inline bool _usbd_ep_is_setup(uint8_t epn) -{ - return hri_usbendpoint_get_EPINTFLAG_reg(USB, epn, USB_DEVICE_EPINTFLAG_RXSTP); -} - -/** \brief ACK endpoint SETUP interrupt - * \param[in] epn Endpoint number. - */ -static inline void _usbd_ep_ack_setup(uint8_t epn) -{ - _usbd_ep_int_ack(epn, USB_DEVICE_EPINTFLAG_RXSTP); -} - -/** \brief Set endpoint toggle value - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] tgl Toggle value. - */ -static inline void _usbd_ep_set_toggle(uint8_t epn, uint8_t bank_n, uint8_t tgl) -{ - if (tgl) { - hri_usbendpoint_set_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_DTGLOUT << bank_n)); - } else { - hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, (USB_DEVICE_EPSTATUS_DTGLOUT << bank_n)); - } -} - -/** \brief ACK IN/OUT complete interrupt - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - */ -static inline void _usbd_ep_ack_io_cpt(uint8_t epn, uint8_t bank_n) -{ - _usbd_ep_int_ack(epn, USB_DEVICE_EPINTFLAG_TRCPT0 << bank_n); -} - -/** \brief Set DMA buffer used for bank data - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] addr DMA buffer address to set. - */ -static inline void _usbd_ep_set_buf(uint8_t epn, uint8_t bank_n, uint32_t addr) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->ADDR.reg = addr; -} - -/** \brief Set bank count for IN transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] count Data count for IN. - */ -static inline void _usbd_ep_set_in_count(uint8_t epn, uint8_t bank_n, uint16_t count) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->PCKSIZE.bit.MULTI_PACKET_SIZE = count; -} - -/** \brief Set bank size for IN transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] size Data size for IN. - */ -static inline void _usbd_ep_set_in_size(uint8_t epn, uint8_t bank_n, uint16_t size) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->PCKSIZE.bit.BYTE_COUNT = size; -} - -/** \brief Set bank count for OUT transaction - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] count Data count for OUT. - */ -static inline void _usbd_ep_set_out_count(uint8_t epn, uint8_t bank_n, uint16_t count) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->PCKSIZE.bit.BYTE_COUNT = count; -} - -/** \brief Set bank size for OUT transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] size Data size for OUT. - */ -static inline void _usbd_ep_set_out_size(uint8_t epn, uint8_t bank_n, uint16_t size) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->PCKSIZE.bit.MULTI_PACKET_SIZE = size; -} - -/** Set bank size and count for IN transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] size Data size. - * \param[in] count Initial data count. - */ -static inline void _usbd_ep_set_in_trans(uint8_t epn, uint8_t bank_n, uint32_t size, uint32_t count) -{ - _usbd_ep_set_in_size(epn, bank_n, size); - _usbd_ep_set_in_count(epn, bank_n, count); -} - -/** \brief Set bank size and count for OUT transaction - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] size Data size. - * \param[in] count Initial data count. - */ -static inline void _usbd_ep_set_out_trans(uint8_t epn, uint8_t bank_n, uint32_t size, uint32_t count) -{ - _usbd_ep_set_out_size(epn, bank_n, size); - _usbd_ep_set_out_count(epn, bank_n, count); -} - -/** \brief Clear bank status - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - */ -static inline void _usbd_ep_clear_bank_status(uint8_t epn, uint8_t bank_n) -{ - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[bank_n]; - bank->STATUS_BK.reg = 0; -} - -/** Set IN ready for IN transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] rdy Set to \c true to indicate IN packet ready to TX. - */ -static inline void _usbd_ep_set_in_rdy(uint8_t epn, uint8_t bank_n, const bool rdy) -{ - if (rdy) { - hri_usbendpoint_set_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); - } else { - hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); - } -} - -/** \brief Set bank ready for OUT transactions - * \param[in] epn Endpoint number. - * \param[in] bank_n Endpoint bank number. - * \param[in] rdy Set to \c true to indicate OUT bank ready to RX. - */ -static inline void _usbd_ep_set_out_rdy(uint8_t epn, uint8_t bank_n, const bool rdy) -{ - if (rdy) { - hri_usbendpoint_clear_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); - } else { - hri_usbendpoint_set_EPSTATUS_reg(USB, epn, USB_DEVICE_EPSTATUS_BK0RDY << bank_n); - } -} - -/** - * \brief Convert USB endpoint size to HW PCKSIZE.SIZE - * \param[in] n Number of bytes of endpoint size. - */ -static inline uint8_t _usbd_ep_pcksize_size(uint16_t n) -{ - return ( - (n > 512) - ? 7 - : ((n > 256) ? 6 : ((n > 128) ? 5 : ((n > 64) ? 4 : ((n > 32) ? 3 : ((n > 16) ? 2 : ((n > 8) ? 1 : 0))))))); -} - -/** - * \brief Obtain endpoint descriptor pointer - * \param[in] epn Endpoint number. - * \param[in] dir Endpoint direction. - */ -static inline struct _usb_d_dev_ep *_usb_d_dev_ept(uint8_t epn, bool dir) -{ - uint8_t ep_index = (epn == 0) ? 0 : (dir ? (epn + CONF_USB_D_MAX_EP_N) : epn); - return &dev_inst.ep[ep_index]; -} - -/** - * \brief Handles USB SOF interrupt - */ -static inline void _usb_d_dev_sof(void) -{ - /* ACK SOF interrupt. */ - hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_SOF); - dev_inst.callbacks.sof(); -} - -/** - * \brief Handles USB LPM Suspend interrupt - */ -static inline void _usb_d_dev_lpmsusp(void) -{ - uint8_t i; - uint32_t lpm_variable = 0; - - /* ACK LPMSUSP interrupt. */ - hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_SUSPEND_INT_FLAGS); - /* Change interrupt masks */ - hri_usbdevice_clear_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); - hri_usbdevice_set_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); - - /* Find LPM data */ - for (i = 0; i < CONF_USB_D_MAX_EP_N; i++) { - UsbDeviceDescBank *bank = &prvt_inst.desc_table[i].DeviceDescBank[0]; - if (bank->EXTREG.bit.SUBPID == 0x3) { - /* Save LPM variable */ - lpm_variable = bank->EXTREG.bit.VARIABLE; - /* Clear */ - bank->EXTREG.reg = 0; - break; - } - } - dev_inst.callbacks.event(USB_EV_LPM_SUSPEND, lpm_variable); -} - -/** - * \brief Handles USB RAM Error interrupt - */ -static inline void _usb_d_dev_ramerr(void) -{ - hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_RAMACER); - dev_inst.callbacks.event(USB_EV_ERROR, 0); -} - -/** - * \brief Handles USB resume/wakeup interrupts - */ -static inline void _usb_d_dev_wakeup(void) -{ - hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_WAKEUP_INT_FLAGS); - hri_usbdevice_clear_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); - hri_usbdevice_set_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); - - _usb_d_dev_wait_clk_rdy(CONF_USB_D_CLK_SRC); - dev_inst.callbacks.event(USB_EV_WAKEUP, 0); -} - -/** - * \brief Handles USB signal reset interrupt - */ -static inline void _usb_d_dev_reset(void) -{ - /* EP0 will not be reseted by USB RESET, disable manually. */ - hri_usbendpoint_write_EPCFG_reg(USB, 0, 0); - - hri_usbdevice_clear_INTFLAG_reg(USB, USB_DEVICE_INTFLAG_EORST); - hri_usbdevice_clear_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); - hri_usbdevice_set_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); - - _usb_d_dev_reset_epts(); - dev_inst.callbacks.event(USB_EV_RESET, 0); -} - -static inline void _usb_d_dev_suspend(void) -{ - hri_usbdevice_clear_INTFLAG_reg(USB, USB_D_SUSPEND_INT_FLAGS); - hri_usbdevice_clear_INTEN_reg(USB, USB_D_SUSPEND_INT_FLAGS); - hri_usbdevice_set_INTEN_reg(USB, USB_D_WAKEUP_INT_FLAGS); - - dev_inst.callbacks.event(USB_EV_SUSPEND, 0); -} - -/** - * \brief Handles USB non-endpoint interrupt - */ -static inline bool _usb_d_dev_handle_nep(void) -{ - bool rc = true; - uint16_t flags = hri_usbdevice_read_INTFLAG_reg(USB); - flags &= hri_usbdevice_read_INTEN_reg(USB); - - if (flags & USB_DEVICE_INTFLAG_SOF) { - _usb_d_dev_sof(); - return true; - } - if (flags & USB_DEVICE_INTFLAG_LPMSUSP) { - _usb_d_dev_lpmsusp(); - } else if (flags & USB_DEVICE_INTFLAG_RAMACER) { - _usb_d_dev_ramerr(); - } else if (flags & USB_D_WAKEUP_INT_FLAGS) { - _usb_d_dev_wakeup(); - } else if (flags & USB_DEVICE_INTFLAG_EORST) { - _usb_d_dev_reset(); - } else if (flags & USB_DEVICE_INTFLAG_SUSPEND) { - _usb_d_dev_suspend(); - } else { - rc = false; - } - return rc; -} - -/** - * \brief Prepare next IN transactions - * \param[in] ept Pointer to endpoint information. - * \param[in] isr Invoked from ISR. - */ -static void _usb_d_dev_in_next(struct _usb_d_dev_ep *ept, bool isr) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ept->ep); - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[0]; - uint16_t trans_count = isr ? bank[1].PCKSIZE.bit.BYTE_COUNT : 0; - uint16_t trans_next; - uint16_t last_pkt = trans_count & ((ept->size == 1023) ? ept->size : (ept->size - 1)); - uint8_t inten = 0; - bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); - - if (isr) { - _usbd_ep_ack_io_cpt(epn, 1); - } - - ept->trans_count += trans_count; - /* Send more data. */ - if (ept->trans_count < ept->trans_size) { - trans_next = ept->trans_size - ept->trans_count; - if (ept->flags.bits.use_cache) { - if (trans_next > ept->size) { - trans_next = ept->size; - } - memcpy(ept->cache, &ept->trans_buf[ept->trans_count], trans_next); - _usbd_ep_set_buf(epn, 1, (uint32_t)ept->cache); - } else { - if (trans_next > USB_D_DEV_TRANS_MAX) { - trans_next = USB_D_DEV_TRANS_MAX; - } - _usbd_ep_set_buf(epn, 1, (uint32_t)&ept->trans_buf[ept->trans_count]); - } - _usbd_ep_set_in_trans(epn, 1, trans_next, 0); - goto _in_tx_exec; - } else if (ept->flags.bits.need_zlp) { - ept->flags.bits.need_zlp = 0; - _usbd_ep_set_in_trans(epn, 1, 0, 0); - goto _in_tx_exec; - } - /* Complete. */ - if (is_ctrl) { - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK1_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRCPT0); - } else { - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK1_INT_FLAGS); - } - - /* No ping-pong, so ask more data without background transfer. */ - if (last_pkt == ept->size) { - ept->flags.bits.is_busy = 0; - if (dev_inst.ep_callbacks.more(ept->ep, ept->trans_count)) { - /* More data added. */ - return; - } - ept->flags.bits.is_busy = 1; - } - /* Finish normally. */ - _usb_d_dev_trans_done(ept, USB_TRANS_DONE); - return; - -_in_tx_exec: - if (!isr) { - if (is_ctrl) { - /* Control endpoint: SETUP or OUT will abort IN transaction. - * SETUP: terminate the IN without any notification. Trigger - * SETUP callback. - * OUT NAK: terminate IN. - */ - inten = USB_D_BANK1_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL0; - } else { - /* Initialize normal IN transaction. */ - inten = USB_D_BANK1_INT_FLAGS; - } - hri_usbendpoint_set_EPINTEN_reg(hw, epn, inten); - } - _usbd_ep_set_in_rdy(epn, 1, true); -} - -/** - * \brief Prepare next OUT transactions - * \param[in] ept Pointer to endpoint information. - * \param[in] isr Invoked from ISR. - */ -static void _usb_d_dev_out_next(struct _usb_d_dev_ep *ept, bool isr) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ept->ep); - UsbDeviceDescBank *bank = &prvt_inst.desc_table[epn].DeviceDescBank[0]; - uint16_t trans_size = isr ? bank->PCKSIZE.bit.MULTI_PACKET_SIZE : 0; - uint16_t last_trans = isr ? bank->PCKSIZE.bit.BYTE_COUNT : 0; - uint16_t size_mask = (ept->size == 1023) ? 1023 : (ept->size - 1); - uint16_t last_pkt = last_trans & size_mask; - uint16_t trans_next; - uint8_t inten; - bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); - - if (isr) { - _usbd_ep_ack_io_cpt(epn, 0); - } - - /* If cache is used, copy data to buffer. */ - if (ept->flags.bits.use_cache && ept->trans_size) { - uint16_t buf_remain = ept->trans_size - ept->trans_count; - memcpy(&ept->trans_buf[ept->trans_count], ept->cache, (buf_remain > last_pkt) ? last_pkt : buf_remain); - } - - /* Force wait ZLP */ - if (ept->trans_size == 0 && ept->flags.bits.need_zlp) { - ept->flags.bits.need_zlp = 0; - ept->flags.bits.use_cache = 1; - _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); - _usbd_ep_set_out_trans(epn, 0, ept->size, 0); - goto _out_rx_exec; - } else if (isr && last_pkt < ept->size) { - /* Short packet. */ - ept->flags.bits.need_zlp = 0; - ept->trans_count += last_trans; - } else { - /* Full packets. */ - ept->trans_count += trans_size; - - /* Wait more data */ - if (ept->trans_count < ept->trans_size) { - /* Continue OUT */ - trans_next = ept->trans_size - ept->trans_count; - if (ept->flags.bits.use_cache) { - /* Expect single packet each time. */ - if (trans_next > ept->size) { - trans_next = ept->size; - } - _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); - } else { - /* Multiple packets each time. */ - if (trans_next > ept->size) { - if (trans_next > USB_D_DEV_TRANS_MAX) { - trans_next = USB_D_DEV_TRANS_MAX; - } else { - /* Must expect multiple of ep size. */ - trans_next -= trans_next & size_mask; - } - } else if (trans_next < ept->size) { - /* Last un-aligned packet should be cached. */ - ept->flags.bits.use_cache = 1; - } - _usbd_ep_set_buf(epn, 0, (uint32_t)&ept->trans_buf[ept->trans_count]); - } - _usbd_ep_set_out_trans(epn, 0, trans_next, 0); - goto _out_rx_exec; - } - } - /* Finish normally. */ - if (is_ctrl) { - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK0_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL1); - } else { - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_BANK0_INT_FLAGS); - } - /* Use ep0 out cache for next setup packets */ - if (0 == epn) { - _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); - } - _usb_d_dev_trans_done(ept, USB_TRANS_DONE); - return; - -_out_rx_exec: - if (!isr) { - if (is_ctrl) { - /* Initialize control OUT transaction. */ - - /* Control transfer: SETUP or IN request will abort the - * OUT transactions. - * SETUP: terminate OUT without any notification. - * Trigger SETUP notification. - * IN NAK: finish OUT normally. Notify data done. - */ - _usbd_ep_clear_bank_status(epn, 1); - /* Detect OUT, SETUP, NAK IN */ - inten = USB_D_BANK0_INT_FLAGS | USB_DEVICE_EPINTFLAG_TRFAIL1; - } else { - /* Initialize normal OUT transaction. */ - inten = USB_D_BANK0_INT_FLAGS; - } - hri_usbendpoint_set_EPINTEN_reg(hw, epn, inten); - } - _usbd_ep_set_out_rdy(epn, 0, true); -} - -/** - * \brief Handles setup received interrupt - * \param[in] ept Pointer to endpoint information. - */ -static void _usb_d_dev_handle_setup(struct _usb_d_dev_ep *ept) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); - - if (!is_ctrl) { - /* Should never be here! */ - _usbd_ep_ack_setup(epn); - _usbd_ep_stop_setup(epn); - return; - } - /* Control transfer: - * SETUP transaction will terminate IN/OUT transaction, - * and start new transaction with received SETUP packet. - */ - if (_usb_d_dev_ep_is_busy(ept)) { - ept->flags.bits.is_busy = 0; - - /* Stop transfer on either direction. */ - _usbd_ep_set_in_rdy(epn, 1, false); - _usbd_ep_set_out_rdy(epn, 0, false); - } - ept->flags.bits.is_stalled = 0; - - /* Clear status and notify SETUP */ - _usbd_ep_clear_bank_status(epn, 0); - _usbd_ep_clear_bank_status(epn, 1); - _usbd_ep_int_ack(epn, USB_D_BANK0_INT_FLAGS | USB_D_BANK1_INT_FLAGS); - _usbd_ep_int_dis(epn, USB_D_BANK0_INT_FLAGS | USB_D_BANK1_INT_FLAGS); - /* Invoke callback. */ - dev_inst.ep_callbacks.setup(ept->ep); -} - -/** - * \brief Handles stall sent interrupt - * \param[in] ept Pointer to endpoint information. - * \param[in] bank_n Bank number. - */ -static void _usb_d_dev_handle_stall(struct _usb_d_dev_ep *ept, const uint8_t bank_n) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - /* Clear interrupt enable. Leave status there for status check. */ - _usbd_ep_int_stall_en(epn, bank_n, false); - dev_inst.ep_callbacks.done(ept->ep, USB_TRANS_STALL, ept->trans_count); -} - -/** - * \brief Handles transaction fail interrupt - * \param[in] ept Pointer to endpoint information. - * \param[in] bank_n Bank number. - */ -static void _usb_d_dev_handle_trfail(struct _usb_d_dev_ep *ept, const uint8_t bank_n) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ept->ep); - const uint8_t fail[2] = {USB_DEVICE_EPINTFLAG_TRFAIL0, USB_DEVICE_EPINTFLAG_TRFAIL1}; - UsbDeviceDescBank *bank = prvt_inst.desc_table[epn].DeviceDescBank; - uint8_t eptype - = bank_n ? hri_usbendpoint_read_EPCFG_EPTYPE1_bf(hw, epn) : hri_usbendpoint_read_EPCFG_EPTYPE0_bf(hw, epn); - bool is_ctrl = _usb_d_dev_ep_is_ctrl(ept); - USB_DEVICE_STATUS_BK_Type st; - st.reg = bank[bank_n].STATUS_BK.reg; - - if ((eptype == USB_D_EPTYPE_ISOCH) && st.bit.CRCERR) { - bank[bank_n].STATUS_BK.bit.CRCERR = 0; - hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); - _usb_d_dev_trans_stop(ept, bank_n, USB_TRANS_ERROR); - } else if (st.bit.ERRORFLOW) { - bank[bank_n].STATUS_BK.bit.ERRORFLOW = 0; - hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); - /* Abort control transfer. */ - if (is_ctrl && _usb_d_dev_ep_is_busy(ept)) { - if (bank_n != _usb_d_dev_ep_is_in(ept)) { - _usb_d_dev_trans_stop(ept, _usb_d_dev_ep_is_in(ept), USB_TRANS_DONE); - } - } - } else { - _usbd_ep_clear_bank_status(epn, bank_n); - hri_usbendpoint_clear_EPINTFLAG_reg(hw, epn, fail[bank_n]); - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, fail[bank_n]); - } -} - -/** - * \brief Analyze flags for setup transaction - * \param[in] ept Pointer to endpoint information. - * \param[in] flags Endpoint interrupt flags. - */ -static inline void _usb_d_dev_trans_setup_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) -{ - /* - * SETPU is automatically ACKed by hardware - * OUT & IN should be set to NAK when checking SETUP - * No need to check OUT & IN status. - */ - if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { - _usb_d_dev_handle_setup(ept); - } else if (flags & USB_DEVICE_EPINTFLAG_STALL1) { - _usb_d_dev_handle_stall(ept, 1); - } else if (flags & USB_DEVICE_EPINTFLAG_STALL0) { - _usb_d_dev_handle_stall(ept, 0); - } -} - -/** - * \brief Analyze flags for IN transactions - * \param[in] ept Pointer to endpoint information. - * \param[in] flags Endpoint interrupt flags. - */ -static inline void _usb_d_dev_trans_in_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) -{ - /* - * Check IN flags - * If control endpoint, SETUP & OUT is checked to see if abort - */ - if (flags & USB_DEVICE_EPINTFLAG_STALL1) { - _usb_d_dev_handle_stall(ept, 1); - } else if (flags & USB_DEVICE_EPINTFLAG_TRFAIL1) { - _usb_d_dev_handle_trfail(ept, 1); - } else if (flags & USB_DEVICE_EPINTFLAG_TRCPT1) { - _usb_d_dev_in_next(ept, true); - } else if (_usb_d_dev_ep_is_ctrl(ept)) { - /* Check OUT NAK - * Check SETUP - */ - if (flags & USB_DEVICE_EPINTFLAG_TRFAIL0) { - _usb_d_dev_handle_trfail(ept, 0); - } else if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { - _usb_d_dev_handle_setup(ept); - } - } -} - -/** - * \brief Analyze flags for OUT transactions - * \param[in] ept Pointer to endpoint information. - * \param[in] flags Endpoint interrupt flags. - */ -static inline void _usb_d_dev_trans_out_isr(struct _usb_d_dev_ep *ept, const uint8_t flags) -{ - /* - * Check OUT flags. - * If control endpoint, SETUP & IN NAK is checked to see if abort - */ - if (flags & USB_DEVICE_EPINTFLAG_STALL0) { - _usb_d_dev_handle_stall(ept, 0); - } else if (flags & USB_DEVICE_EPINTFLAG_TRFAIL0) { - _usb_d_dev_handle_trfail(ept, 0); - } else if (flags & USB_DEVICE_EPINTFLAG_TRCPT0) { - _usb_d_dev_out_next(ept, true); - } else if (_usb_d_dev_ep_is_ctrl(ept)) { - /* Check IN NAK - * Check SETUP - */ - if (flags & USB_DEVICE_EPINTFLAG_TRFAIL1) { - _usb_d_dev_handle_trfail(ept, 1); - } else if (flags & USB_DEVICE_EPINTFLAG_RXSTP) { - _usb_d_dev_handle_setup(ept); - } - } -} - -/** - * \brief Handles the endpoint interrupts. - * \param[in] epint Endpoint interrupt summary (by bits). - * \param[in] ept Pointer to endpoint information. - */ -static inline void _usb_d_dev_handle_eps(uint32_t epint, struct _usb_d_dev_ep *ept) -{ - Usb *hw = USB; - - uint8_t flags, mask; - uint8_t epn = USB_EP_GET_N(ept->ep); - - if (!(epint & (1u << epn))) { - return; - } - flags = hw->DEVICE.DeviceEndpoint[epn].EPINTFLAG.reg; - mask = hw->DEVICE.DeviceEndpoint[epn].EPINTENSET.reg; - flags &= mask; - if (flags) { - if ((ept->flags.bits.eptype == 0x1) && !_usb_d_dev_ep_is_busy(ept)) { - _usb_d_dev_trans_setup_isr(ept, flags); - } else if (_usb_d_dev_ep_is_in(ept)) { - _usb_d_dev_trans_in_isr(ept, flags); - } else { - _usb_d_dev_trans_out_isr(ept, flags); - } - } -} - -/** - * \brief USB device interrupt handler - * \param[in] unused The parameter is not used - */ -static void _usb_d_dev_handler(void) -{ - Usb * hw = USB; - uint8_t i; - - uint16_t epint = hw->DEVICE.EPINTSMRY.reg; - if (0 == epint) { - if (_usb_d_dev_handle_nep()) { - return; - } - } - /* Handle endpoints */ - for (i = 0; i < USB_D_N_EP; i++) { - struct _usb_d_dev_ep *ept = &dev_inst.ep[i]; - if (ept->ep == 0xFF) { - continue; - } - _usb_d_dev_handle_eps(epint, ept); - } -} - -/** - * \brief Reset all endpoint software instances - */ -static void _usb_d_dev_reset_epts(void) -{ - uint8_t i; - for (i = 0; i < USB_D_N_EP; i++) { - _usb_d_dev_trans_done(&dev_inst.ep[i], USB_TRANS_RESET); - dev_inst.ep[i].ep = 0xFF; - dev_inst.ep[i].flags.u8 = 0; - } - memset(prvt_inst.desc_table, 0, sizeof(UsbDeviceDescriptor) * (CONF_USB_D_MAX_EP_N + 1)); -} - -int32_t _usb_d_dev_init(void) -{ - Usb * hw = USB; - uint8_t speed = CONF_USB_D_SPEED; - const uint8_t spdconf[4] = { - USB_DEVICE_CTRLB_SPDCONF(1), /* LS */ - USB_DEVICE_CTRLB_SPDCONF(0), /* FS */ - 0, - 0 /* Reserved */ - }; - - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - if (hri_usbdevice_get_CTRLA_ENABLE_bit(hw)) { - return ERR_DENIED; - } - hri_usbdevice_set_CTRLA_SWRST_bit(hw); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - - dev_inst.callbacks.sof = (_usb_d_dev_sof_cb_t)_dummy_func_no_return; - dev_inst.callbacks.event = (_usb_d_dev_event_cb_t)_dummy_func_no_return; - - dev_inst.ep_callbacks.setup = (_usb_d_dev_ep_cb_setup_t)_dummy_func_no_return; - dev_inst.ep_callbacks.more = (_usb_d_dev_ep_cb_more_t)_dummy_func_no_return; - dev_inst.ep_callbacks.done = (_usb_d_dev_ep_cb_done_t)_dummy_func_no_return; - - _usb_d_dev_reset_epts(); - - _usb_load_calib(); - - hri_usbdevice_write_CTRLA_reg(hw, USB_CTRLA_RUNSTDBY); - hri_usbdevice_write_DESCADD_reg(hw, (uint32_t)prvt_inst.desc_table); - hri_usbdevice_write_CTRLB_reg(hw, spdconf[speed] | USB_DEVICE_CTRLB_DETACH); - - return ERR_NONE; -} - -void _usb_d_dev_deinit(void) -{ - Usb *hw = USB; - - while (_usb_d_dev_disable() < 0) - ; - - hri_usbdevice_write_CTRLA_reg(hw, USB_CTRLA_SWRST); - - NVIC_DisableIRQ(USB_0_IRQn); - NVIC_ClearPendingIRQ(USB_0_IRQn); - NVIC_DisableIRQ(USB_1_IRQn); - NVIC_ClearPendingIRQ(USB_1_IRQn); - NVIC_DisableIRQ(USB_2_IRQn); - NVIC_ClearPendingIRQ(USB_2_IRQn); - NVIC_DisableIRQ(USB_3_IRQn); - NVIC_ClearPendingIRQ(USB_3_IRQn); -} - -int32_t _usb_d_dev_enable(void) -{ - Usb * hw = USB; - uint8_t ctrla; - - if (hri_usbdevice_get_SYNCBUSY_reg(hw, (USB_SYNCBUSY_ENABLE | USB_SYNCBUSY_SWRST))) { - return -USB_ERR_DENIED; - } - ctrla = hri_usbdevice_read_CTRLA_reg(hw); - if ((ctrla & USB_CTRLA_ENABLE) == 0) { - hri_usbdevice_write_CTRLA_reg(hw, ctrla | USB_CTRLA_ENABLE); - } - - NVIC_EnableIRQ(USB_0_IRQn); - NVIC_EnableIRQ(USB_1_IRQn); - NVIC_EnableIRQ(USB_2_IRQn); - NVIC_EnableIRQ(USB_3_IRQn); - - hri_usbdevice_set_INTEN_reg(hw, - USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST | USB_DEVICE_INTENSET_RAMACER - | USB_D_SUSPEND_INT_FLAGS); - - return ERR_NONE; -} - -int32_t _usb_d_dev_disable(void) -{ - Usb * hw = USB; - uint8_t ctrla; - - if (hri_usbdevice_get_SYNCBUSY_reg(hw, (USB_SYNCBUSY_ENABLE | USB_SYNCBUSY_SWRST))) { - return -USB_ERR_DENIED; - } - - ctrla = hri_usbdevice_read_CTRLA_reg(hw); - if (ctrla & USB_CTRLA_ENABLE) { - hri_usbdevice_write_CTRLA_reg(hw, ctrla & ~USB_CTRLA_ENABLE); - } - - NVIC_DisableIRQ(USB_0_IRQn); - NVIC_DisableIRQ(USB_1_IRQn); - NVIC_DisableIRQ(USB_2_IRQn); - NVIC_DisableIRQ(USB_3_IRQn); - - hri_usbdevice_clear_INTEN_reg(hw, - USB_DEVICE_INTENSET_SOF | USB_DEVICE_INTENSET_EORST | USB_DEVICE_INTENSET_RAMACER - | USB_D_SUSPEND_INT_FLAGS - | USB_D_WAKEUP_INT_FLAGS); - - return ERR_NONE; -} - -void _usb_d_dev_attach(void) -{ - hri_usbdevice_clear_CTRLB_DETACH_bit(USB); -} - -void _usb_d_dev_detach(void) -{ - hri_usbdevice_set_CTRLB_DETACH_bit(USB); -} - -#ifndef USB_FSMSTATUS_FSMSTATE_ON -#define USB_FSMSTATUS_FSMSTATE_ON USB_FSMSTATUS_FSMSTATE(2ul) -#endif -void _usb_d_dev_send_remotewakeup(void) -{ - uint32_t retry = CONF_USB_RMT_WKUP_RETRY; - _usb_d_dev_wait_clk_rdy(CONF_USB_D_CLK_SRC); - while ((USB_FSMSTATUS_FSMSTATE_ON != hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(USB)) && (retry--)) { - USB->DEVICE.CTRLB.bit.UPRSM = 1; - } -} - -enum usb_speed _usb_d_dev_get_speed(void) -{ - uint8_t sp = (enum usb_speed)hri_usbdevice_read_STATUS_SPEED_bf(USB); - const enum usb_speed speed[2] = {USB_SPEED_FS, USB_SPEED_LS}; - - return speed[sp]; -} - -void _usb_d_dev_set_address(uint8_t addr) -{ - hri_usbdevice_write_DADD_reg(USB, USB_DEVICE_DADD_ADDEN | USB_DEVICE_DADD_DADD(addr)); -} - -uint8_t _usb_d_dev_get_address(void) -{ - uint8_t addr = hri_usbdevice_read_DADD_DADD_bf(USB); - return addr; -} - -uint16_t _usb_d_dev_get_frame_n(void) -{ - uint16_t fn = hri_usbdevice_read_FNUM_FNUM_bf(USB); - return fn; -} - -uint8_t _usb_d_dev_get_uframe_n(void) -{ - uint8_t ufn = hri_usbdevice_read_FNUM_MFNUM_bf(USB); - return ufn; -} - -/** - * \brief Start a setup transaction - * \param[in] ept Endpoint information. - */ -static inline void _usb_d_dev_trans_setup(struct _usb_d_dev_ep *ept) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ept->ep); - - _usbd_ep_set_buf(epn, 0, (uint32_t)ept->cache); - _usbd_ep_set_out_trans(epn, 0, ept->size, 0); - - hri_usbendpoint_clear_EPSTATUS_reg(hw, epn, USB_DEVICE_EPSTATUS_STALLRQ(0x3) | USB_DEVICE_EPSTATUS_BK1RDY); - _usbd_ep_set_out_rdy(epn, 0, false); - - hri_usbendpoint_set_EPINTEN_reg(hw, epn, USB_D_SETUP_INT_FLAGS); -} - -int32_t _usb_d_dev_ep0_init(const uint8_t max_pkt_siz) -{ - return _usb_d_dev_ep_init(0, USB_EP_XTYPE_CTRL, max_pkt_siz); -} - -int32_t _usb_d_dev_ep_init(const uint8_t ep, const uint8_t attr, const uint16_t max_pkt_siz) -{ - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - - uint8_t ep_type = attr & USB_EP_XTYPE_MASK; - const struct _usb_ep_cfg_item *pcfg = &_usb_ep_cfgs[epn]; - - if (epn > CONF_USB_D_MAX_EP_N) { - return -USB_ERR_PARAM; - } - if (ept->ep != 0xFF) { - return -USB_ERR_REDO; - } - if (ep_type == USB_EP_XTYPE_CTRL) { - struct _usb_d_dev_ep *ept_in = _usb_d_dev_ept(epn, !dir); - if (ept_in->ep != 0xFF) { - return -USB_ERR_REDO; - } - if (pcfg->cache == NULL) { - return -USB_ERR_FUNC; - } - } - if ((dir ? pcfg->i_cache : pcfg->cache) && ((dir ? pcfg->i_size : pcfg->size) < max_pkt_siz)) { - return -USB_ERR_FUNC; - } - - /* Initialize EP n settings */ - ept->cache = (uint8_t *)(dir ? pcfg->i_cache : pcfg->cache); - ept->size = max_pkt_siz; - ept->flags.u8 = (ep_type + 1); - ept->ep = ep; - - return USB_OK; -} - -void _usb_d_dev_ep_deinit(uint8_t ep) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - - if (epn > CONF_USB_D_MAX_EP_N || !_usb_d_dev_ep_is_used(ept)) { - return; - } - - /* Finish pending transactions. */ - _usb_d_dev_trans_stop(ept, dir, USB_TRANS_RESET); - - /* Disable the endpoint. */ - if (_usb_d_dev_ep_is_ctrl(ept)) { - hw->DEVICE.DeviceEndpoint[ep].EPCFG.reg = 0; - } else if (USB_EP_GET_DIR(ep)) { - hw->DEVICE.DeviceEndpoint[USB_EP_GET_N(ep)].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - } else { - hw->DEVICE.DeviceEndpoint[ep].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - } - ept->flags.u8 = 0; - ept->ep = 0xFF; -} - -int32_t _usb_d_dev_ep_enable(const uint8_t ep) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - uint8_t epcfg = hri_usbendpoint_read_EPCFG_reg(hw, epn); - UsbDeviceDescBank * bank; - - if (epn > CONF_USB_D_MAX_EP_N || !_usb_d_dev_ep_is_used(ept)) { - return -USB_ERR_PARAM; - } - - bank = prvt_inst.desc_table[epn].DeviceDescBank; - if (ept->flags.bits.eptype == USB_D_EPTYPE_CTRL) { - if (epcfg & (USB_DEVICE_EPCFG_EPTYPE1_Msk | USB_DEVICE_EPCFG_EPTYPE0_Msk)) { - return -USB_ERR_REDO; - } - hri_usbendpoint_write_EPCFG_reg(hw, epn, USB_D_EPCFG_CTRL); - bank[0].PCKSIZE.reg = USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(ept->size) - | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); - bank[1].PCKSIZE.reg - = USB_DEVICE_PCKSIZE_BYTE_COUNT(ept->size) | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); - /* By default, control endpoint accept SETUP and NAK all other token. */ - _usbd_ep_set_out_rdy(epn, 0, false); - _usbd_ep_set_in_rdy(epn, 1, false); - - _usbd_ep_clear_bank_status(epn, 0); - _usbd_ep_clear_bank_status(epn, 1); - - /* Enable SETUP reception for control endpoint. */ - _usb_d_dev_trans_setup(ept); - - } else if (dir) { - if (epcfg & USB_DEVICE_EPCFG_EPTYPE1_Msk) { - return -USB_ERR_REDO; - } - epcfg |= USB_DEVICE_EPCFG_EPTYPE1(ept->flags.bits.eptype); - hri_usbendpoint_write_EPCFG_reg(hw, epn, epcfg); - - bank[1].PCKSIZE.reg - = USB_DEVICE_PCKSIZE_BYTE_COUNT(ept->size) | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); - - /* By default, IN endpoint will NAK all token. */ - _usbd_ep_set_in_rdy(epn, 1, false); - _usbd_ep_clear_bank_status(epn, 1); - - } else { - - if (epcfg & USB_DEVICE_EPCFG_EPTYPE0_Msk) { - return -USB_ERR_REDO; - } - epcfg |= USB_DEVICE_EPCFG_EPTYPE0(ept->flags.bits.eptype); - hri_usbendpoint_write_EPCFG_reg(hw, epn, epcfg); - - bank[0].PCKSIZE.reg = USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(ept->size) - | USB_DEVICE_PCKSIZE_SIZE(_usbd_ep_pcksize_size(ept->size)); - - /* By default, OUT endpoint will NAK all token. */ - _usbd_ep_set_out_rdy(epn, 0, false); - _usbd_ep_clear_bank_status(epn, 0); - } - - return USB_OK; -} - -void _usb_d_dev_ep_disable(const uint8_t ep) -{ - Usb * hw = USB; - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - - _usb_d_dev_trans_stop(ept, dir, USB_TRANS_RESET); - if (_usb_d_dev_ep_is_ctrl(ept)) { - hri_usbendpoint_clear_EPINTEN_reg(hw, epn, USB_D_ALL_INT_FLAGS); - } -} - -/** - * \brief Get endpoint stall status - * \param[in] ept Pointer to endpoint information. - * \param[in] dir Endpoint direction. - * \return Stall status. - * \retval \c true Endpoint is stalled. - * \retval \c false Endpoint is not stalled. - */ -static inline int32_t _usb_d_dev_ep_stall_get(struct _usb_d_dev_ep *ept, bool dir) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - return _usbd_ep_is_stalled(epn, dir); -} - -/** - * \brief Set endpoint stall - * \param[in, out] ept Pointer to endpoint information. - * \param[in] dir Endpoint direction. - * \return Always 0, success. - */ -static inline int32_t _usb_d_dev_ep_stall_set(struct _usb_d_dev_ep *ept, bool dir) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - _usbd_ep_set_stall(epn, dir, true); - _usbd_ep_int_en(epn, USB_DEVICE_EPINTFLAG_STALL0 << dir); - ept->flags.bits.is_stalled = 1; - /* In stall interrupt abort the transfer. */ - return ERR_NONE; -} - -/** - * \brief Clear endpoint stall - * \param[in, out] ept Pointer to endpoint information. - * \param[in] dir Endpoint direction. - * \return Always 0, success. - */ -static inline int32_t _usb_d_dev_ep_stall_clr(struct _usb_d_dev_ep *ept, bool dir) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - bool is_stalled = _usbd_ep_is_stalled(epn, dir); - if (!is_stalled) { - return ERR_NONE; - } - _usbd_ep_set_stall(epn, dir, false); - _usbd_ep_int_dis(epn, USB_DEVICE_EPINTFLAG_STALL0 << dir); - if (_usbd_ep_is_stall_sent(epn, dir)) { - _usbd_ep_ack_stall(epn, dir); - _usbd_ep_set_toggle(epn, dir, 0); - } - if (_usb_d_dev_ep_is_ctrl(ept)) { - if ((hri_usbendpoint_read_EPSTATUS_reg(USB, epn) & USB_DEVICE_EPSTATUS_STALLRQ_Msk) == 0) { - ept->flags.bits.is_stalled = 0; - } - } else { - ept->flags.bits.is_stalled = 0; - } - return ERR_NONE; -} - -int32_t _usb_d_dev_ep_stall(const uint8_t ep, const enum usb_ep_stall_ctrl ctrl) -{ - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - int32_t rc; - - if (epn > CONF_USB_D_MAX_EP_N) { - return -USB_ERR_PARAM; - } - - if (USB_EP_STALL_SET == ctrl) { - rc = _usb_d_dev_ep_stall_set(ept, dir); - } else if (USB_EP_STALL_CLR == ctrl) { - rc = _usb_d_dev_ep_stall_clr(ept, dir); - } else { - rc = _usb_d_dev_ep_stall_get(ept, dir); - } - return rc; -} - -/** - * \brief Finish the transaction and invoke callback - * \param[in, out] ept Pointer to endpoint information. - * \param[in] code Information code passed. - */ -static void _usb_d_dev_trans_done(struct _usb_d_dev_ep *ept, const int32_t code) -{ - if (!(_usb_d_dev_ep_is_used(ept) && _usb_d_dev_ep_is_busy(ept))) { - return; - } - ept->flags.bits.is_busy = 0; - dev_inst.ep_callbacks.done(ept->ep, code, ept->trans_count); -} - -/** - * \brief Terminate the transaction with specific status code - * \param[in, out] ept Pointer to endpoint information. - * \param[in] dir Endpoint direction. - * \param[in] code Information code passed. - */ -static void _usb_d_dev_trans_stop(struct _usb_d_dev_ep *ept, bool dir, const int32_t code) -{ - uint8_t epn = USB_EP_GET_N(ept->ep); - ; - const uint8_t intflags[2] = {USB_D_BANK0_INT_FLAGS, USB_D_BANK1_INT_FLAGS}; - if (!(_usb_d_dev_ep_is_used(ept) && _usb_d_dev_ep_is_busy(ept))) { - return; - } - /* Stop transfer */ - if (dir) { - /* NAK IN */ - _usbd_ep_set_in_rdy(epn, 1, false); - } else { - /* NAK OUT */ - _usbd_ep_set_out_rdy(epn, 0, false); - } - _usbd_ep_int_ack(epn, intflags[dir]); - _usbd_ep_int_dis(epn, intflags[dir]); - _usb_d_dev_trans_done(ept, code); -} - -int32_t _usb_d_dev_ep_read_req(const uint8_t ep, uint8_t *req_buf) -{ - uint8_t epn = USB_EP_GET_N(ep); - UsbDeviceDescBank *bank = prvt_inst.desc_table[epn].DeviceDescBank; - uint32_t addr = bank[0].ADDR.reg; - uint16_t bytes = bank[0].PCKSIZE.bit.BYTE_COUNT; - - if (epn > CONF_USB_D_MAX_EP_N || !req_buf) { - return -USB_ERR_PARAM; - } - if (!_usbd_ep_is_ctrl(epn)) { - return -USB_ERR_FUNC; - } - if (!_usbd_ep_is_setup(epn)) { - return ERR_NONE; - } - memcpy(req_buf, (void *)addr, 8); - _usbd_ep_ack_setup(epn); - - return bytes; -} - -int32_t _usb_d_dev_ep_trans(const struct usb_d_transfer *trans) -{ - uint8_t epn = USB_EP_GET_N(trans->ep); - bool dir = USB_EP_GET_DIR(trans->ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - - uint16_t size_mask = (ept->size == 1023) ? 1023 : (ept->size - 1); - bool size_n_aligned = (trans->size & size_mask); - - bool use_cache = false; - - volatile hal_atomic_t flags; - - if (epn > CONF_USB_D_MAX_EP_N) { - return -USB_ERR_PARAM; - } - - /* Cases that needs cache: - * 1. Buffer not in RAM (cache all). - * 2. IN/OUT with unaligned buffer (cache all). - * 3. OUT with unaligned packet size (cache last packet). - * 4. OUT size < 8 (sub-case for 3). - */ - if (!_usb_is_addr4dma(trans->buf, trans->size) || (!_usb_is_aligned(trans->buf)) - || (!dir && (trans->size < ept->size))) { - if (!ept->cache) { - return -USB_ERR_FUNC; - } - /* Use cache all the time. */ - use_cache = true; - } - if (!dir && size_n_aligned) { - if (!ept->cache) { - return -USB_ERR_PARAM; - } - /* Set 'use_cache' on last packet. */ - } - - /* Check halt */ - if (ept->flags.bits.is_stalled) { - return USB_HALTED; - } - - /* Try to start transactions. */ - - atomic_enter_critical(&flags); - if (_usb_d_dev_ep_is_busy(ept)) { - atomic_leave_critical(&flags); - return USB_BUSY; - } - ept->flags.bits.is_busy = 1; - atomic_leave_critical(&flags); - - /* Copy transaction information. */ - ept->trans_buf = trans->buf; - ept->trans_size = trans->size; - ept->trans_count = 0; - - ept->flags.bits.dir = dir; - ept->flags.bits.use_cache = use_cache; - ept->flags.bits.need_zlp = (trans->zlp && (!size_n_aligned)); - - if (dir) { - _usb_d_dev_in_next(ept, false); - } else { - _usb_d_dev_out_next(ept, false); - } - - return ERR_NONE; -} - -void _usb_d_dev_ep_abort(const uint8_t ep) -{ - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - if (epn > CONF_USB_D_MAX_EP_N) { - return; - } - _usb_d_dev_trans_stop(ept, dir, USB_TRANS_ABORT); -} - -int32_t _usb_d_dev_ep_get_status(const uint8_t ep, struct usb_d_trans_status *stat) -{ - uint8_t epn = USB_EP_GET_N(ep); - bool dir = USB_EP_GET_DIR(ep); - struct _usb_d_dev_ep *ept = _usb_d_dev_ept(epn, dir); - bool busy, stall; - - if (epn > CONF_USB_D_MAX_EP_N) { - return USB_ERR_PARAM; - } - busy = ept->flags.bits.is_busy; - stall = ept->flags.bits.is_stalled; - if (stat) { - stat->stall = stall; - stat->busy = busy; - stat->setup = USB->DEVICE.DeviceEndpoint[epn].EPINTFLAG.bit.RXSTP; - stat->dir = ept->flags.bits.dir; - stat->size = ept->trans_size; - stat->count = ept->trans_count; - stat->ep = ep; - stat->xtype = ept->flags.bits.eptype - 1; - } - if (stall) { - return USB_HALTED; - } - if (busy) { - return USB_BUSY; - } - return USB_OK; -} - -void _usb_d_dev_register_callback(const enum usb_d_cb_type type, const FUNC_PTR func) -{ - FUNC_PTR f = (func == NULL) ? (FUNC_PTR)_dummy_func_no_return : (FUNC_PTR)func; - if (type == USB_D_CB_EVENT) { - dev_inst.callbacks.event = (_usb_d_dev_event_cb_t)f; - } else if (type == USB_D_CB_SOF) { - dev_inst.callbacks.sof = (_usb_d_dev_sof_cb_t)f; - } -} - -void _usb_d_dev_register_ep_callback(const enum usb_d_dev_ep_cb_type type, const FUNC_PTR func) -{ - FUNC_PTR f = (func == NULL) ? (FUNC_PTR)_dummy_func_no_return : (FUNC_PTR)func; - if (type == USB_D_DEV_EP_CB_SETUP) { - dev_inst.ep_callbacks.setup = (_usb_d_dev_ep_cb_setup_t)f; - } else if (type == USB_D_DEV_EP_CB_MORE) { - dev_inst.ep_callbacks.more = (_usb_d_dev_ep_cb_more_t)f; - } else if (type == USB_D_DEV_EP_CB_DONE) { - dev_inst.ep_callbacks.done = (_usb_d_dev_ep_cb_done_t)f; - } -} - -/** -* \brief USB interrupt handler -*/ -void USB_0_Handler(void) -{ - - _usb_d_dev_handler(); -} -/** -* \brief USB interrupt handler -*/ -void USB_1_Handler(void) -{ - - _usb_d_dev_handler(); -} -/** -* \brief USB interrupt handler -*/ -void USB_2_Handler(void) -{ - - _usb_d_dev_handler(); -} -/** -* \brief USB interrupt handler -*/ -void USB_3_Handler(void) -{ - - _usb_d_dev_handler(); -} diff --git a/atmel-samd/asf4/samd51/hri/hri_ac_d51.h b/atmel-samd/asf4/samd51/hri/hri_ac_d51.h deleted file mode 100644 index 37688c2ce..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_ac_d51.h +++ /dev/null @@ -1,1827 +0,0 @@ -/** - * \file - * - * \brief SAM AC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_AC_COMPONENT_ -#ifndef _HRI_AC_D51_H_INCLUDED_ -#define _HRI_AC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_AC_CRITICAL_SECTIONS) -#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define AC_CRITICAL_SECTION_ENTER() -#define AC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_ac_calib_reg_t; -typedef uint16_t hri_ac_evctrl_reg_t; -typedef uint32_t hri_ac_compctrl_reg_t; -typedef uint32_t hri_ac_syncbusy_reg_t; -typedef uint8_t hri_ac_ctrla_reg_t; -typedef uint8_t hri_ac_ctrlb_reg_t; -typedef uint8_t hri_ac_dbgctrl_reg_t; -typedef uint8_t hri_ac_intenset_reg_t; -typedef uint8_t hri_ac_intflag_reg_t; -typedef uint8_t hri_ac_scaler_reg_t; -typedef uint8_t hri_ac_statusa_reg_t; -typedef uint8_t hri_ac_statusb_reg_t; -typedef uint8_t hri_ac_winctrl_reg_t; - -static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) -{ - while (((Ac *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) -{ - return ((Ac *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; -} - -static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; -} - -static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; - } -} - -static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; -} - -static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; -} - -static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; -} - -static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; - } -} - -static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; -} - -static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; -} - -static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; -} - -static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; - } else { - ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; - } -} - -static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; -} - -static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - ((Ac *)hw)->INTENSET.reg = mask; -} - -static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) -{ - return ((Ac *)hw)->INTENSET.reg; -} - -static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) -{ - ((Ac *)hw)->INTENSET.reg = data; - ((Ac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) -{ - ((Ac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; -} - -static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; -} - -static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; -} - -static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; -} - -static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; -} - -static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; -} - -static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; -} - -static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; -} - -static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; -} - -static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; -} - -static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) -{ - return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; -} - -static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) -{ - ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; -} - -static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) -{ - return ((Ac *)hw)->INTFLAG.reg; -} - -static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) -{ - ((Ac *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLB.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= ~AC_CTRLA_ENABLE; - tmp |= value << AC_CTRLA_ENABLE_Pos; - ((Ac *)hw)->CTRLA.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); - ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CTRLA.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) -{ - return ((Ac *)hw)->CTRLA.reg; -} - -static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEO0; - tmp |= value << AC_EVCTRL_COMPEO0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEO1; - tmp |= value << AC_EVCTRL_COMPEO1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_WINEO0; - tmp |= value << AC_EVCTRL_WINEO0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEI0; - tmp |= value << AC_EVCTRL_COMPEI0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_COMPEI1; - tmp |= value << AC_EVCTRL_COMPEI1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_INVEI0; - tmp |= value << AC_EVCTRL_INVEI0_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= ~AC_EVCTRL_INVEI1; - tmp |= value << AC_EVCTRL_INVEI1_Pos; - ((Ac *)hw)->EVCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->EVCTRL.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) -{ - return ((Ac *)hw)->EVCTRL.reg; -} - -static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp &= ~AC_DBGCTRL_DBGRUN; - tmp |= value << AC_DBGCTRL_DBGRUN_Pos; - ((Ac *)hw)->DBGCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->DBGCTRL.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Ac *)hw)->DBGCTRL.reg; -} - -static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= ~AC_WINCTRL_WEN0; - tmp |= value << AC_WINCTRL_WEN0_Pos; - ((Ac *)hw)->WINCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; - return tmp; -} - -static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= ~AC_WINCTRL_WINTSEL0_Msk; - tmp |= AC_WINCTRL_WINTSEL0(data); - ((Ac *)hw)->WINCTRL.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; - return tmp; -} - -static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->WINCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->WINCTRL.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) -{ - return ((Ac *)hw)->WINCTRL.reg; -} - -static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, - hri_ac_scaler_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; - return tmp; -} - -static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) -{ - uint8_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp &= ~AC_SCALER_VALUE_Msk; - tmp |= AC_SCALER_VALUE(data); - ((Ac *)hw)->SCALER[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; - return tmp; -} - -static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->SCALER[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->SCALER[index].reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) -{ - return ((Ac *)hw)->SCALER[index].reg; -} - -static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_ENABLE; - tmp |= value << AC_COMPCTRL_ENABLE_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SINGLE; - tmp |= value << AC_COMPCTRL_SINGLE_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_RUNSTDBY; - tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SWAP; - tmp |= value << AC_COMPCTRL_SWAP_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; - return (bool)tmp; -} - -static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_HYSTEN; - tmp |= value << AC_COMPCTRL_HYSTEN_Pos; - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_INTSEL_Msk; - tmp |= AC_COMPCTRL_INTSEL(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_MUXNEG_Msk; - tmp |= AC_COMPCTRL_MUXNEG(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_MUXPOS_Msk; - tmp |= AC_COMPCTRL_MUXPOS(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_SPEED_Msk; - tmp |= AC_COMPCTRL_SPEED(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_HYST_Msk; - tmp |= AC_COMPCTRL_HYST(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_FLEN_Msk; - tmp |= AC_COMPCTRL_FLEN(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - uint32_t tmp; - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= ~AC_COMPCTRL_OUT_Msk; - tmp |= AC_COMPCTRL_OUT(data); - ((Ac *)hw)->COMPCTRL[index].reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); - ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; - return tmp; -} - -static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, - hri_ac_compctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->COMPCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->COMPCTRL[index].reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Ac *)hw)->COMPCTRL[index].reg; -} - -static inline void hri_ac_set_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg |= AC_CALIB_BIAS0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_get_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->CALIB.reg; - tmp = (tmp & AC_CALIB_BIAS0(mask)) >> AC_CALIB_BIAS0_Pos; - return tmp; -} - -static inline void hri_ac_write_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t data) -{ - uint16_t tmp; - AC_CRITICAL_SECTION_ENTER(); - tmp = ((Ac *)hw)->CALIB.reg; - tmp &= ~AC_CALIB_BIAS0_Msk; - tmp |= AC_CALIB_BIAS0(data); - ((Ac *)hw)->CALIB.reg = tmp; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg &= ~AC_CALIB_BIAS0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg ^= AC_CALIB_BIAS0(mask); - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_read_CALIB_BIAS0_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->CALIB.reg; - tmp = (tmp & AC_CALIB_BIAS0_Msk) >> AC_CALIB_BIAS0_Pos; - return tmp; -} - -static inline void hri_ac_set_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg |= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_get_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Ac *)hw)->CALIB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ac_write_CALIB_reg(const void *const hw, hri_ac_calib_reg_t data) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg = data; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_clear_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg &= ~mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ac_toggle_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) -{ - AC_CRITICAL_SECTION_ENTER(); - ((Ac *)hw)->CALIB.reg ^= mask; - AC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ac_calib_reg_t hri_ac_read_CALIB_reg(const void *const hw) -{ - return ((Ac *)hw)->CALIB.reg; -} - -static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; -} - -static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) -{ - return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; -} - -static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) -{ - return ((Ac *)hw)->STATUSA.reg; -} - -static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; -} - -static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) -{ - return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; -} - -static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ac *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) -{ - return ((Ac *)hw)->STATUSB.reg; -} - -static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; -} - -static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) -{ - return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; -} - -static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ac *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Ac *)hw)->SYNCBUSY.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_AC_D51_H_INCLUDED */ -#endif /* _SAMD51_AC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_adc_d51.h b/atmel-samd/asf4/samd51/hri/hri_adc_d51.h deleted file mode 100644 index be2d352d2..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_adc_d51.h +++ /dev/null @@ -1,3736 +0,0 @@ -/** - * \file - * - * \brief SAM ADC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_ADC_COMPONENT_ -#ifndef _HRI_ADC_D51_H_INCLUDED_ -#define _HRI_ADC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_ADC_CRITICAL_SECTIONS) -#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define ADC_CRITICAL_SECTION_ENTER() -#define ADC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_adc_calib_reg_t; -typedef uint16_t hri_adc_ctrla_reg_t; -typedef uint16_t hri_adc_ctrlb_reg_t; -typedef uint16_t hri_adc_gaincorr_reg_t; -typedef uint16_t hri_adc_inputctrl_reg_t; -typedef uint16_t hri_adc_offsetcorr_reg_t; -typedef uint16_t hri_adc_ress_reg_t; -typedef uint16_t hri_adc_result_reg_t; -typedef uint16_t hri_adc_winlt_reg_t; -typedef uint16_t hri_adc_winut_reg_t; -typedef uint32_t hri_adc_dseqctrl_reg_t; -typedef uint32_t hri_adc_dseqdata_reg_t; -typedef uint32_t hri_adc_dseqstat_reg_t; -typedef uint32_t hri_adc_syncbusy_reg_t; -typedef uint8_t hri_adc_avgctrl_reg_t; -typedef uint8_t hri_adc_dbgctrl_reg_t; -typedef uint8_t hri_adc_evctrl_reg_t; -typedef uint8_t hri_adc_intenset_reg_t; -typedef uint8_t hri_adc_intflag_reg_t; -typedef uint8_t hri_adc_refctrl_reg_t; -typedef uint8_t hri_adc_sampctrl_reg_t; -typedef uint8_t hri_adc_status_reg_t; -typedef uint8_t hri_adc_swtrig_reg_t; - -static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) -{ - while (((Adc *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) -{ - return ((Adc *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; -} - -static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; -} - -static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; - } -} - -static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; -} - -static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; -} - -static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; -} - -static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; - } -} - -static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; -} - -static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; -} - -static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; -} - -static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; - } else { - ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; - } -} - -static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; -} - -static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - ((Adc *)hw)->INTENSET.reg = mask; -} - -static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) -{ - return ((Adc *)hw)->INTENSET.reg; -} - -static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) -{ - ((Adc *)hw)->INTENSET.reg = data; - ((Adc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) -{ - ((Adc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; -} - -static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; -} - -static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; -} - -static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; -} - -static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; -} - -static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; -} - -static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; -} - -static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; -} - -static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; -} - -static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; -} - -static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) -{ - return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; -} - -static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) -{ - ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; -} - -static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) -{ - return ((Adc *)hw)->INTFLAG.reg; -} - -static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) -{ - ((Adc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQDATA.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_ENABLE; - tmp |= value << ADC_CTRLA_ENABLE_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_SLAVEEN; - tmp |= value << ADC_CTRLA_SLAVEEN_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_RUNSTDBY; - tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_ONDEMAND; - tmp |= value << ADC_CTRLA_ONDEMAND_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_R2R; - tmp |= value << ADC_CTRLA_R2R_Pos; - ((Adc *)hw)->CTRLA.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_DUALSEL_Msk; - tmp |= ADC_CTRLA_DUALSEL(data); - ((Adc *)hw)->CTRLA.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= ~ADC_CTRLA_PRESCALER_Msk; - tmp |= ADC_CTRLA_PRESCALER(data); - ((Adc *)hw)->CTRLA.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLA.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) -{ - return ((Adc *)hw)->CTRLA.reg; -} - -static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_FLUSHEI; - tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_STARTEI; - tmp |= value << ADC_EVCTRL_STARTEI_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_FLUSHINV; - tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_STARTINV; - tmp |= value << ADC_EVCTRL_STARTINV_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_RESRDYEO; - tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= ~ADC_EVCTRL_WINMONEO; - tmp |= value << ADC_EVCTRL_WINMONEO_Pos; - ((Adc *)hw)->EVCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->EVCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->EVCTRL.reg; -} - -static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp &= ~ADC_DBGCTRL_DBGRUN; - tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; - ((Adc *)hw)->DBGCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DBGCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->DBGCTRL.reg; -} - -static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_DIFFMODE; - tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos; - ((Adc *)hw)->INPUTCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_DSEQSTOP; - tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos; - ((Adc *)hw)->INPUTCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; - tmp |= ADC_INPUTCTRL_MUXPOS(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, - hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; - tmp |= ADC_INPUTCTRL_MUXNEG(data); - ((Adc *)hw)->INPUTCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; - return tmp; -} - -static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->INPUTCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->INPUTCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->INPUTCTRL.reg; -} - -static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_LEFTADJ; - tmp |= value << ADC_CTRLB_LEFTADJ_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_FREERUN; - tmp |= value << ADC_CTRLB_FREERUN_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_CORREN; - tmp |= value << ADC_CTRLB_CORREN_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_WINSS; - tmp |= value << ADC_CTRLB_WINSS_Pos; - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_RESSEL_Msk; - tmp |= ADC_CTRLB_RESSEL(data); - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos; - return tmp; -} - -static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= ~ADC_CTRLB_WINMODE_Msk; - tmp |= ADC_CTRLB_WINMODE(data); - ((Adc *)hw)->CTRLB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos; - return tmp; -} - -static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CTRLB.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) -{ - return ((Adc *)hw)->CTRLB.reg; -} - -static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= ~ADC_REFCTRL_REFCOMP; - tmp |= value << ADC_REFCTRL_REFCOMP_Pos; - ((Adc *)hw)->REFCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; - return tmp; -} - -static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= ~ADC_REFCTRL_REFSEL_Msk; - tmp |= ADC_REFCTRL_REFSEL(data); - ((Adc *)hw)->REFCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; - return tmp; -} - -static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->REFCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->REFCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->REFCTRL.reg; -} - -static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; - tmp |= ADC_AVGCTRL_SAMPLENUM(data); - ((Adc *)hw)->AVGCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; - return tmp; -} - -static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= ~ADC_AVGCTRL_ADJRES_Msk; - tmp |= ADC_AVGCTRL_ADJRES(data); - ((Adc *)hw)->AVGCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; - return tmp; -} - -static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->AVGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->AVGCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->AVGCTRL.reg; -} - -static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= ~ADC_SAMPCTRL_OFFCOMP; - tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; - ((Adc *)hw)->SAMPCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; - return tmp; -} - -static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; - tmp |= ADC_SAMPCTRL_SAMPLEN(data); - ((Adc *)hw)->SAMPCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; - return tmp; -} - -static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SAMPCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SAMPCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->SAMPCTRL.reg; -} - -static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; - return tmp; -} - -static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp &= ~ADC_WINLT_WINLT_Msk; - tmp |= ADC_WINLT_WINLT(data); - ((Adc *)hw)->WINLT.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); - tmp = ((Adc *)hw)->WINLT.reg; - tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; - return tmp; -} - -static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->WINLT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINLT.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) -{ - return ((Adc *)hw)->WINLT.reg; -} - -static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; - return tmp; -} - -static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp &= ~ADC_WINUT_WINUT_Msk; - tmp |= ADC_WINUT_WINUT(data); - ((Adc *)hw)->WINUT.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); - tmp = ((Adc *)hw)->WINUT.reg; - tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; - return tmp; -} - -static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->WINUT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->WINUT.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) -{ - return ((Adc *)hw)->WINUT.reg; -} - -static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; - return tmp; -} - -static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp &= ~ADC_GAINCORR_GAINCORR_Msk; - tmp |= ADC_GAINCORR_GAINCORR(data); - ((Adc *)hw)->GAINCORR.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; - return tmp; -} - -static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->GAINCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->GAINCORR.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) -{ - return ((Adc *)hw)->GAINCORR.reg; -} - -static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, - hri_adc_offsetcorr_reg_t mask) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; - return tmp; -} - -static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; - tmp |= ADC_OFFSETCORR_OFFSETCORR(data); - ((Adc *)hw)->OFFSETCORR.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) -{ - uint16_t tmp; - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; - return tmp; -} - -static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->OFFSETCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->OFFSETCORR.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) -{ - return ((Adc *)hw)->OFFSETCORR.reg; -} - -static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= ~ADC_SWTRIG_FLUSH; - tmp |= value << ADC_SWTRIG_FLUSH_Pos; - ((Adc *)hw)->SWTRIG.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) -{ - uint8_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= ~ADC_SWTRIG_START; - tmp |= value << ADC_SWTRIG_START_Pos; - ((Adc *)hw)->SWTRIG.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->SWTRIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->SWTRIG.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) -{ - return ((Adc *)hw)->SWTRIG.reg; -} - -static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_INPUTCTRL; - tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_CTRLB; - tmp |= value << ADC_DSEQCTRL_CTRLB_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_REFCTRL; - tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_AVGCTRL; - tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_SAMPCTRL; - tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_WINLT; - tmp |= value << ADC_DSEQCTRL_WINLT_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_WINUT; - tmp |= value << ADC_DSEQCTRL_WINUT_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_GAINCORR; - tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - uint32_t tmp; - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_OFFSETCORR; - tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos; - return (bool)tmp; -} - -static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= ~ADC_DSEQCTRL_AUTOSTART; - tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos; - ((Adc *)hw)->DSEQCTRL.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw) -{ - ADC_CRITICAL_SECTION_ENTER(); - hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); - ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->DSEQCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->DSEQCTRL.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw) -{ - return ((Adc *)hw)->DSEQCTRL.reg; -} - -static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIASCOMP_Msk; - tmp |= ADC_CALIB_BIASCOMP(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIASR2R_Msk; - tmp |= ADC_CALIB_BIASR2R(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; - return tmp; -} - -static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) -{ - uint16_t tmp; - ADC_CRITICAL_SECTION_ENTER(); - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= ~ADC_CALIB_BIASREFBUF_Msk; - tmp |= ADC_CALIB_BIASREFBUF(data); - ((Adc *)hw)->CALIB.reg = tmp; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; - return tmp; -} - -static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg |= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->CALIB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg = data; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg &= ~mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) -{ - ADC_CRITICAL_SECTION_ENTER(); - ((Adc *)hw)->CALIB.reg ^= mask; - ADC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) -{ - return ((Adc *)hw)->CALIB.reg; -} - -static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw) -{ - return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos; -} - -static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask) -{ - return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos; -} - -static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw) -{ - return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos; -} - -static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Adc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw) -{ - return ((Adc *)hw)->STATUS.reg; -} - -static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; -} - -static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) -{ - return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; -} - -static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Adc *)hw)->SYNCBUSY.reg; -} - -static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw) -{ - hri_adc_wait_for_sync(hw, - ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL - | ADC_SYNCBUSY_SAMPCTRL - | ADC_SYNCBUSY_WINLT - | ADC_SYNCBUSY_WINUT - | ADC_SYNCBUSY_GAINCORR - | ADC_SYNCBUSY_OFFSETCORR); - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos; -} - -static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw) -{ - return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos; -} - -static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask) -{ - uint32_t tmp; - tmp = ((Adc *)hw)->DSEQSTAT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw) -{ - return ((Adc *)hw)->DSEQSTAT.reg; -} - -static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) -{ - return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; -} - -static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) -{ - return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; -} - -static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->RESULT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) -{ - return ((Adc *)hw)->RESULT.reg; -} - -static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask) -{ - return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos; -} - -static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw) -{ - return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos; -} - -static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask) -{ - uint16_t tmp; - tmp = ((Adc *)hw)->RESS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw) -{ - return ((Adc *)hw)->RESS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_ADC_D51_H_INCLUDED */ -#endif /* _SAMD51_ADC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_aes_d51.h b/atmel-samd/asf4/samd51/hri/hri_aes_d51.h deleted file mode 100644 index c9b1313d9..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_aes_d51.h +++ /dev/null @@ -1,1296 +0,0 @@ -/** - * \file - * - * \brief SAM AES - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_AES_COMPONENT_ -#ifndef _HRI_AES_D51_H_INCLUDED_ -#define _HRI_AES_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_AES_CRITICAL_SECTIONS) -#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define AES_CRITICAL_SECTION_ENTER() -#define AES_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_aes_ciplen_reg_t; -typedef uint32_t hri_aes_ctrla_reg_t; -typedef uint32_t hri_aes_ghash_reg_t; -typedef uint32_t hri_aes_hashkey_reg_t; -typedef uint32_t hri_aes_indata_reg_t; -typedef uint32_t hri_aes_intvectv_reg_t; -typedef uint32_t hri_aes_keyword_reg_t; -typedef uint32_t hri_aes_randseed_reg_t; -typedef uint8_t hri_aes_ctrlb_reg_t; -typedef uint8_t hri_aes_databufptr_reg_t; -typedef uint8_t hri_aes_dbgctrl_reg_t; -typedef uint8_t hri_aes_intenset_reg_t; -typedef uint8_t hri_aes_intflag_reg_t; - -static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; -} - -static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; -} - -static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; - } else { - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; - } -} - -static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; -} - -static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; -} - -static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; -} - -static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; - } else { - ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; - } -} - -static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; -} - -static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - ((Aes *)hw)->INTENSET.reg = mask; -} - -static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) -{ - return ((Aes *)hw)->INTENSET.reg; -} - -static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) -{ - ((Aes *)hw)->INTENSET.reg = data; - ((Aes *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) -{ - ((Aes *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; -} - -static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; -} - -static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; -} - -static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; -} - -static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; -} - -static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; -} - -static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) -{ - return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; -} - -static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) -{ - ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; -} - -static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) -{ - return ((Aes *)hw)->INTFLAG.reg; -} - -static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) -{ - ((Aes *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->KEYWORD[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INTVECTV[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_ENABLE; - tmp |= value << AES_CTRLA_ENABLE_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CIPHER; - tmp |= value << AES_CTRLA_CIPHER_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_STARTMODE; - tmp |= value << AES_CTRLA_STARTMODE_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_LOD; - tmp |= value << AES_CTRLA_LOD_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_KEYGEN; - tmp |= value << AES_CTRLA_KEYGEN_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_XORKEY; - tmp |= value << AES_CTRLA_XORKEY_Pos; - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_AESMODE_Msk; - tmp |= AES_CTRLA_AESMODE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CFBS_Msk; - tmp |= AES_CTRLA_CFBS(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_KEYSIZE_Msk; - tmp |= AES_CTRLA_KEYSIZE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; - return tmp; -} - -static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) -{ - uint32_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= ~AES_CTRLA_CTYPE_Msk; - tmp |= AES_CTRLA_CTYPE(data); - ((Aes *)hw)->CTRLA.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; - return tmp; -} - -static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLA.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) -{ - return ((Aes *)hw)->CTRLA.reg; -} - -static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_START; - tmp |= value << AES_CTRLB_START_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_NEWMSG; - tmp |= value << AES_CTRLB_NEWMSG_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_EOM; - tmp |= value << AES_CTRLB_EOM_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= ~AES_CTRLB_GFMUL; - tmp |= value << AES_CTRLB_GFMUL_Pos; - ((Aes *)hw)->CTRLB.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CTRLB.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) -{ - return ((Aes *)hw)->CTRLB.reg; -} - -static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, - hri_aes_databufptr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; - return tmp; -} - -static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; - tmp |= AES_DATABUFPTR_INDATAPTR(data); - ((Aes *)hw)->DATABUFPTR.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; - return tmp; -} - -static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DATABUFPTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DATABUFPTR.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) -{ - return ((Aes *)hw)->DATABUFPTR.reg; -} - -static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DBGCTRL.reg; - tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - AES_CRITICAL_SECTION_ENTER(); - tmp = ((Aes *)hw)->DBGCTRL.reg; - tmp &= ~AES_DBGCTRL_DBGRUN; - tmp |= value << AES_DBGCTRL_DBGRUN_Pos; - ((Aes *)hw)->DBGCTRL.reg = tmp; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Aes *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->DBGCTRL.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw) -{ - return ((Aes *)hw)->DBGCTRL.reg; -} - -static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->INDATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->INDATA.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) -{ - return ((Aes *)hw)->INDATA.reg; -} - -static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, - hri_aes_hashkey_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->HASHKEY[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->HASHKEY[index].reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) -{ - return ((Aes *)hw)->HASHKEY[index].reg; -} - -static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->GHASH[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->GHASH[index].reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) -{ - return ((Aes *)hw)->GHASH[index].reg; -} - -static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->CIPLEN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->CIPLEN.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) -{ - return ((Aes *)hw)->CIPLEN.reg; -} - -static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg |= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - uint32_t tmp; - tmp = ((Aes *)hw)->RANDSEED.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg = data; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg &= ~mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) -{ - AES_CRITICAL_SECTION_ENTER(); - ((Aes *)hw)->RANDSEED.reg ^= mask; - AES_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) -{ - return ((Aes *)hw)->RANDSEED.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_AES_D51_H_INCLUDED */ -#endif /* _SAMD51_AES_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_ccl_d51.h b/atmel-samd/asf4/samd51/hri/hri_ccl_d51.h deleted file mode 100644 index e218cc997..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_ccl_d51.h +++ /dev/null @@ -1,785 +0,0 @@ -/** - * \file - * - * \brief SAM CCL - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_CCL_COMPONENT_ -#ifndef _HRI_CCL_D51_H_INCLUDED_ -#define _HRI_CCL_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_CCL_CRITICAL_SECTIONS) -#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define CCL_CRITICAL_SECTION_ENTER() -#define CCL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_ccl_lutctrl_reg_t; -typedef uint8_t hri_ccl_ctrl_reg_t; -typedef uint8_t hri_ccl_seqctrl_reg_t; - -static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= ~CCL_CTRL_ENABLE; - tmp |= value << CCL_CTRL_ENABLE_Pos; - ((Ccl *)hw)->CTRL.reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= ~CCL_CTRL_RUNSTDBY; - tmp |= value << CCL_CTRL_RUNSTDBY_Pos; - ((Ccl *)hw)->CTRL.reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->CTRL.reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) -{ - return ((Ccl *)hw)->CTRL.reg; -} - -static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, - hri_ccl_seqctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; - return tmp; -} - -static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) -{ - uint8_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; - tmp |= CCL_SEQCTRL_SEQSEL(data); - ((Ccl *)hw)->SEQCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; - return tmp; -} - -static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, - hri_ccl_seqctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ccl *)hw)->SEQCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Ccl *)hw)->SEQCTRL[index].reg; -} - -static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_ENABLE; - tmp |= value << CCL_LUTCTRL_ENABLE_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_EDGESEL; - tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INVEI; - tmp |= value << CCL_LUTCTRL_INVEI_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_LUTEI; - tmp |= value << CCL_LUTCTRL_LUTEI_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; - return (bool)tmp; -} - -static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_LUTEO; - tmp |= value << CCL_LUTCTRL_LUTEO_Pos; - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; - tmp |= CCL_LUTCTRL_FILTSEL(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL0_Msk; - tmp |= CCL_LUTCTRL_INSEL0(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL1_Msk; - tmp |= CCL_LUTCTRL_INSEL1(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_INSEL2_Msk; - tmp |= CCL_LUTCTRL_INSEL2(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - uint32_t tmp; - CCL_CRITICAL_SECTION_ENTER(); - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= ~CCL_LUTCTRL_TRUTH_Msk; - tmp |= CCL_LUTCTRL_TRUTH(data); - ((Ccl *)hw)->LUTCTRL[index].reg = tmp; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; - return tmp; -} - -static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg |= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, - hri_ccl_lutctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ccl *)hw)->LUTCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg = data; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) -{ - CCL_CRITICAL_SECTION_ENTER(); - ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; - CCL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Ccl *)hw)->LUTCTRL[index].reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_CCL_D51_H_INCLUDED */ -#endif /* _SAMD51_CCL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_cmcc_d51.h b/atmel-samd/asf4/samd51/hri/hri_cmcc_d51.h deleted file mode 100644 index d67c14b7c..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_cmcc_d51.h +++ /dev/null @@ -1,370 +0,0 @@ -/** - * \file - * - * \brief SAM CMCC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_CMCC_COMPONENT_ -#ifndef _HRI_CMCC_D51_H_INCLUDED_ -#define _HRI_CMCC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_CMCC_CRITICAL_SECTIONS) -#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define CMCC_CRITICAL_SECTION_ENTER() -#define CMCC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_cmcc_cfg_reg_t; -typedef uint32_t hri_cmcc_ctrl_reg_t; -typedef uint32_t hri_cmcc_lckway_reg_t; -typedef uint32_t hri_cmcc_maint0_reg_t; -typedef uint32_t hri_cmcc_maint1_reg_t; -typedef uint32_t hri_cmcc_mcfg_reg_t; -typedef uint32_t hri_cmcc_mctrl_reg_t; -typedef uint32_t hri_cmcc_men_reg_t; -typedef uint32_t hri_cmcc_msr_reg_t; -typedef uint32_t hri_cmcc_sr_reg_t; -typedef uint32_t hri_cmcc_type_reg_t; - -static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CTRL.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MAINT0.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MAINT1.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCTRL.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->CFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->CFG.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw) -{ - return ((Cmcc *)hw)->CFG.reg; -} - -static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->LCKWAY.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->LCKWAY.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw) -{ - return ((Cmcc *)hw)->LCKWAY.reg; -} - -static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->MCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MCFG.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw) -{ - return ((Cmcc *)hw)->MCFG.reg; -} - -static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg |= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->MEN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg = data; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg &= ~mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) -{ - CMCC_CRITICAL_SECTION_ENTER(); - ((Cmcc *)hw)->MEN.reg ^= mask; - CMCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw) -{ - return ((Cmcc *)hw)->MEN.reg; -} - -static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; -} - -static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; -} - -static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw) -{ - return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->TYPE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw) -{ - return ((Cmcc *)hw)->TYPE.reg; -} - -static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw) -{ - return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos; -} - -static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->SR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw) -{ - return ((Cmcc *)hw)->SR.reg; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask) -{ - return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw) -{ - return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Cmcc *)hw)->MSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw) -{ - return ((Cmcc *)hw)->MSR.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_CMCC_D51_H_INCLUDED */ -#endif /* _SAMD51_CMCC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_d51.h b/atmel-samd/asf4/samd51/hri/hri_d51.h deleted file mode 100644 index fe1b0f91b..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_d51.h +++ /dev/null @@ -1,85 +0,0 @@ -/** - * \file - * - * \brief SAM D51 HRI top-level header file - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifndef _HRI_D51_H_INCLUDED_ -#define _HRI_D51_H_INCLUDED_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#endif /* _HRI_D51_H_INCLUDED_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_dac_d51.h b/atmel-samd/asf4/samd51/hri/hri_dac_d51.h deleted file mode 100644 index ba27fd529..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_dac_d51.h +++ /dev/null @@ -1,1701 +0,0 @@ -/** - * \file - * - * \brief SAM DAC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_DAC_COMPONENT_ -#ifndef _HRI_DAC_D51_H_INCLUDED_ -#define _HRI_DAC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DAC_CRITICAL_SECTIONS) -#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DAC_CRITICAL_SECTION_ENTER() -#define DAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_dac_dacctrl_reg_t; -typedef uint16_t hri_dac_data_reg_t; -typedef uint16_t hri_dac_databuf_reg_t; -typedef uint16_t hri_dac_result_reg_t; -typedef uint32_t hri_dac_syncbusy_reg_t; -typedef uint8_t hri_dac_ctrla_reg_t; -typedef uint8_t hri_dac_ctrlb_reg_t; -typedef uint8_t hri_dac_dbgctrl_reg_t; -typedef uint8_t hri_dac_evctrl_reg_t; -typedef uint8_t hri_dac_intenset_reg_t; -typedef uint8_t hri_dac_intflag_reg_t; -typedef uint8_t hri_dac_status_reg_t; - -static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) -{ - while (((Dac *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) -{ - return ((Dac *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; -} - -static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; -} - -static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; - } -} - -static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; -} - -static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; -} - -static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; -} - -static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; - } -} - -static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; -} - -static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; -} - -static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; -} - -static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; - } -} - -static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; -} - -static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; -} - -static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos; -} - -static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; - } -} - -static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; -} - -static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; -} - -static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos; -} - -static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; - } -} - -static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; -} - -static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; -} - -static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos; -} - -static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; - } -} - -static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; -} - -static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; -} - -static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos; -} - -static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; - } -} - -static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; -} - -static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; -} - -static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos; -} - -static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; - } else { - ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; - } -} - -static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; -} - -static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - ((Dac *)hw)->INTENSET.reg = mask; -} - -static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) -{ - return ((Dac *)hw)->INTENSET.reg; -} - -static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) -{ - ((Dac *)hw)->INTENSET.reg = data; - ((Dac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) -{ - ((Dac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; -} - -static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; -} - -static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; -} - -static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; -} - -static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; -} - -static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; -} - -static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; -} - -static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; -} - -static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; -} - -static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; -} - -static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; -} - -static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; -} - -static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; -} - -static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; -} - -static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; -} - -static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; -} - -static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; -} - -static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; -} - -static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; -} - -static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; -} - -static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; -} - -static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; -} - -static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; -} - -static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; -} - -static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw) -{ - return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; -} - -static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw) -{ - ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; -} - -static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) -{ - return ((Dac *)hw)->INTFLAG.reg; -} - -static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) -{ - ((Dac *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATA[index].reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DATABUF[index].reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); - ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->CTRLA.reg; - tmp &= ~DAC_CTRLA_ENABLE; - tmp |= value << DAC_CTRLA_ENABLE_Pos; - ((Dac *)hw)->CTRLA.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); - ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLA.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) -{ - return ((Dac *)hw)->CTRLA.reg; -} - -static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_DIFF; - tmp |= value << DAC_CTRLB_DIFF_Pos; - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; - return tmp; -} - -static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= ~DAC_CTRLB_REFSEL_Msk; - tmp |= DAC_CTRLB_REFSEL(data); - ((Dac *)hw)->CTRLB.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; - return tmp; -} - -static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->CTRLB.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) -{ - return ((Dac *)hw)->CTRLB.reg; -} - -static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_STARTEI0; - tmp |= value << DAC_EVCTRL_STARTEI0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_STARTEI1; - tmp |= value << DAC_EVCTRL_STARTEI1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_EMPTYEO0; - tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_EMPTYEO1; - tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_INVEI0; - tmp |= value << DAC_EVCTRL_INVEI0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_INVEI1; - tmp |= value << DAC_EVCTRL_INVEI1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_RESRDYEO0; - tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= ~DAC_EVCTRL_RESRDYEO1; - tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos; - ((Dac *)hw)->EVCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->EVCTRL.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) -{ - return ((Dac *)hw)->EVCTRL.reg; -} - -static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_LEFTADJ; - tmp |= value << DAC_DACCTRL_LEFTADJ_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_ENABLE; - tmp |= value << DAC_DACCTRL_ENABLE_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_FEXT; - tmp |= value << DAC_DACCTRL_FEXT_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_RUNSTDBY; - tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_DITHER; - tmp |= value << DAC_DACCTRL_DITHER_Pos; - ((Dac *)hw)->DACCTRL[index].reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_CCTRL_Msk; - tmp |= DAC_DACCTRL_CCTRL(data); - ((Dac *)hw)->DACCTRL[index].reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos; - return tmp; -} - -static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_REFRESH_Msk; - tmp |= DAC_DACCTRL_REFRESH(data); - ((Dac *)hw)->DACCTRL[index].reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos; - return tmp; -} - -static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - uint16_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= ~DAC_DACCTRL_OSR_Msk; - tmp |= DAC_DACCTRL_OSR(data); - ((Dac *)hw)->DACCTRL[index].reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); - ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask); - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos; - return tmp; -} - -static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index, - hri_dac_dacctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->DACCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DACCTRL[index].reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Dac *)hw)->DACCTRL[index].reg; -} - -static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->DBGCTRL.reg; - tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dac *)hw)->DBGCTRL.reg; - tmp &= ~DAC_DBGCTRL_DBGRUN; - tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; - ((Dac *)hw)->DBGCTRL.reg = tmp; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg |= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg = data; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg &= ~mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) -{ - DAC_CRITICAL_SECTION_ENTER(); - ((Dac *)hw)->DBGCTRL.reg ^= mask; - DAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Dac *)hw)->DBGCTRL.reg; -} - -static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos; -} - -static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos; -} - -static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos; -} - -static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw) -{ - return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos; -} - -static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dac *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) -{ - return ((Dac *)hw)->STATUS.reg; -} - -static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos; -} - -static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw) -{ - return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos; -} - -static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dac *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Dac *)hw)->SYNCBUSY.reg; -} - -static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index, - hri_dac_result_reg_t mask) -{ - return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos; -} - -static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index) -{ - return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos; -} - -static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index, - hri_dac_result_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dac *)hw)->RESULT[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index) -{ - return ((Dac *)hw)->RESULT[index].reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DAC_D51_H_INCLUDED */ -#endif /* _SAMD51_DAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_dmac_d51.h b/atmel-samd/asf4/samd51/hri/hri_dmac_d51.h deleted file mode 100644 index 71aeb73c1..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_dmac_d51.h +++ /dev/null @@ -1,6844 +0,0 @@ -/** - * \file - * - * \brief SAM DMAC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_DMAC_COMPONENT_ -#ifndef _HRI_DMAC_D51_H_INCLUDED_ -#define _HRI_DMAC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) -#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DMAC_CRITICAL_SECTION_ENTER() -#define DMAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_dmac_crcctrl_reg_t; -typedef uint16_t hri_dmac_ctrl_reg_t; -typedef uint16_t hri_dmac_intpend_reg_t; -typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; -typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; -typedef uint32_t hri_dmac_active_reg_t; -typedef uint32_t hri_dmac_baseaddr_reg_t; -typedef uint32_t hri_dmac_busych_reg_t; -typedef uint32_t hri_dmac_chctrla_reg_t; -typedef uint32_t hri_dmac_crcchksum_reg_t; -typedef uint32_t hri_dmac_crcdatain_reg_t; -typedef uint32_t hri_dmac_intstatus_reg_t; -typedef uint32_t hri_dmac_pendch_reg_t; -typedef uint32_t hri_dmac_prictrl0_reg_t; -typedef uint32_t hri_dmac_swtrigctrl_reg_t; -typedef uint32_t hri_dmac_wrbaddr_reg_t; -typedef uint32_t hri_dmacchannel_chctrla_reg_t; -typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; -typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; -typedef uint8_t hri_dmac_chctrlb_reg_t; -typedef uint8_t hri_dmac_chevctrl_reg_t; -typedef uint8_t hri_dmac_chintenset_reg_t; -typedef uint8_t hri_dmac_chintflag_reg_t; -typedef uint8_t hri_dmac_chprilvl_reg_t; -typedef uint8_t hri_dmac_chstatus_reg_t; -typedef uint8_t hri_dmac_crcstatus_reg_t; -typedef uint8_t hri_dmac_dbgctrl_reg_t; -typedef uint8_t hri_dmacchannel_chctrlb_reg_t; -typedef uint8_t hri_dmacchannel_chevctrl_reg_t; -typedef uint8_t hri_dmacchannel_chintenset_reg_t; -typedef uint8_t hri_dmacchannel_chintflag_reg_t; -typedef uint8_t hri_dmacchannel_chprilvl_reg_t; -typedef uint8_t hri_dmacchannel_chstatus_reg_t; - -static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_DMAENABLE; - tmp |= value << DMAC_CTRL_DMAENABLE_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN0; - tmp |= value << DMAC_CTRL_LVLEN0_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN1; - tmp |= value << DMAC_CTRL_LVLEN1_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN2; - tmp |= value << DMAC_CTRL_LVLEN2_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= ~DMAC_CTRL_LVLEN3; - tmp |= value << DMAC_CTRL_LVLEN3_Pos; - ((Dmac *)hw)->CTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->CTRL.reg; -} - -static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, - hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; - tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; - tmp |= DMAC_CRCCTRL_CRCPOLY(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; - tmp |= DMAC_CRCCTRL_CRCSRC(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk; - tmp |= DMAC_CRCCTRL_CRCMODE(data); - ((Dmac *)hw)->CRCCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->CRCCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCCTRL.reg; -} - -static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, - hri_dmac_crcdatain_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; - tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); - ((Dmac *)hw)->CRCDATAIN.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCDATAIN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCDATAIN.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCDATAIN.reg; -} - -static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, - hri_dmac_crcchksum_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; - return tmp; -} - -static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; - tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); - ((Dmac *)hw)->CRCCHKSUM.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; - return tmp; -} - -static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->CRCCHKSUM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCCHKSUM.reg; -} - -static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp &= ~DMAC_DBGCTRL_DBGRUN; - tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; - ((Dmac *)hw)->DBGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->DBGCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->DBGCTRL.reg; -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31; - tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos; - ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, - hri_dmac_swtrigctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) -{ - return ((Dmac *)hw)->SWTRIGCTRL.reg; -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN0; - tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN1; - tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN2; - tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_RRLVLEN3; - tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI0(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS0_Msk; - tmp |= DMAC_PRICTRL0_QOS0(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI1(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS1_Msk; - tmp |= DMAC_PRICTRL0_QOS1(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI2(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS2_Msk; - tmp |= DMAC_PRICTRL0_QOS2(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, - hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; - tmp |= DMAC_PRICTRL0_LVLPRI3(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= ~DMAC_PRICTRL0_QOS3_Msk; - tmp |= DMAC_PRICTRL0_QOS3(data); - ((Dmac *)hw)->PRICTRL0.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos; - return tmp; -} - -static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PRICTRL0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->PRICTRL0.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) -{ - return ((Dmac *)hw)->PRICTRL0.reg; -} - -static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_TERR; - tmp |= value << DMAC_INTPEND_TERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_TCMPL; - tmp |= value << DMAC_INTPEND_TCMPL_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_SUSP; - tmp |= value << DMAC_INTPEND_SUSP_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_CRCERR; - tmp |= value << DMAC_INTPEND_CRCERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_FERR; - tmp |= value << DMAC_INTPEND_FERR_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_BUSY; - tmp |= value << DMAC_INTPEND_BUSY_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_PEND; - tmp |= value << DMAC_INTPEND_PEND_Pos; - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= ~DMAC_INTPEND_ID_Msk; - tmp |= DMAC_INTPEND_ID(data); - ((Dmac *)hw)->INTPEND.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Dmac *)hw)->INTPEND.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->INTPEND.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) -{ - return ((Dmac *)hw)->INTPEND.reg; -} - -static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, - hri_dmac_baseaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; - return tmp; -} - -static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; - tmp |= DMAC_BASEADDR_BASEADDR(data); - ((Dmac *)hw)->BASEADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; - return tmp; -} - -static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BASEADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->BASEADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) -{ - return ((Dmac *)hw)->BASEADDR.reg; -} - -static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; - return tmp; -} - -static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; - tmp |= DMAC_WRBADDR_WRBADDR(data); - ((Dmac *)hw)->WRBADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; - return tmp; -} - -static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->WRBADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->WRBADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) -{ - return ((Dmac *)hw)->WRBADDR.reg; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos; -} - -static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw) -{ - return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos; -} - -static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->INTSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->INTSTATUS.reg; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos; -} - -static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw) -{ - return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos; -} - -static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->BUSYCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) -{ - return ((Dmac *)hw)->BUSYCH.reg; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos; -} - -static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw) -{ - return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos; -} - -static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->PENDCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) -{ - return ((Dmac *)hw)->PENDCH.reg; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; -} - -static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) -{ - return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; -} - -static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->ACTIVE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) -{ - return ((Dmac *)hw)->ACTIVE.reg; -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw) -{ - return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos; -} - -static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->CRCSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->CRCSTATUS.reg = mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) -{ - return ((Dmac *)hw)->CRCSTATUS.reg; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t -hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk; - tmp |= DMAC_DSTADDR_CRC_CHKINIT(data); - ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t -hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; - tmp |= DMAC_DSTADDR_DSTADDR(data); - ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_CRC_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t -hri_dmacdescriptor_get_DSTADDR_CRC_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_CRC_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->DSTADDR.reg; -} - -static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, - hri_dmacdescriptor_dstaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->DSTADDR.reg; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_VALID; - tmp |= value << DMAC_BTCTRL_VALID_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_SRCINC; - tmp |= value << DMAC_BTCTRL_SRCINC_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_DSTINC; - tmp |= value << DMAC_BTCTRL_DSTINC_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; - return (bool)tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_STEPSEL; - tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; - tmp |= DMAC_BTCTRL_EVOSEL(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; - tmp |= DMAC_BTCTRL_BLOCKACT(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; - tmp |= DMAC_BTCTRL_BEATSIZE(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t -hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; - tmp |= DMAC_BTCTRL_STEPSIZE(data); - ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, - hri_dmacdescriptor_btctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->BTCTRL.reg; -} - -static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, - hri_dmacdescriptor_btcnt_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) -{ - uint16_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp &= ~DMAC_BTCNT_BTCNT_Msk; - tmp |= DMAC_BTCNT_BTCNT(data); - ((DmacDescriptor *)hw)->BTCNT.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, - hri_dmacdescriptor_btcnt_reg_t mask) -{ - uint16_t tmp; - tmp = ((DmacDescriptor *)hw)->BTCNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->BTCNT.reg; -} - -static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t -hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; - tmp |= DMAC_SRCADDR_SRCADDR(data); - ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, - hri_dmacdescriptor_srcaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->SRCADDR.reg; -} - -static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t -hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; - tmp |= DMAC_DESCADDR_DESCADDR(data); - ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, - hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; - return tmp; -} - -static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t -hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) -{ - return ((DmacDescriptor *)hw)->DESCADDR.reg; -} - -static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; -} - -static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; -} - -static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; - } else { - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; - } -} - -static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; -} - -static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; -} - -static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; - } else { - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; - } -} - -static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; -} - -static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; -} - -static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; - } else { - ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; - } -} - -static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; -} - -static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = mask; -} - -static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const hw, - hri_dmac_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHINTENSET.reg; -} - -static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) -{ - ((DmacChannel *)hw)->CHINTENSET.reg = data; - ((DmacChannel *)hw)->CHINTENCLR.reg = ~data; -} - -static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) -{ - ((DmacChannel *)hw)->CHINTENCLR.reg = mask; -} - -static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const hw, - hri_dmac_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHINTFLAG.reg; -} - -static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) -{ - ((DmacChannel *)hw)->CHINTFLAG.reg = mask; -} - -static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_ENABLE; - tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_RUNSTDBY; - tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; - tmp |= DMAC_CHCTRLA_TRIGSRC(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; - tmp |= DMAC_CHCTRLA_TRIGACT(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; - tmp |= DMAC_CHCTRLA_BURSTLEN(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const hw, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; - tmp |= DMAC_CHCTRLA_THRESHOLD(data); - ((DmacChannel *)hw)->CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLA.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHCTRLA.reg; -} - -static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const hw, - hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_CMD_Msk; - tmp |= DMAC_CHCTRLB_CMD(data); - ((DmacChannel *)hw)->CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHCTRLB.reg; -} - -static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const hw, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; - tmp |= DMAC_CHPRILVL_PRILVL(data); - ((DmacChannel *)hw)->CHPRILVL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const hw, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHPRILVL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHPRILVL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHPRILVL.reg; -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVIE; - tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; - return (bool)tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOE; - tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const hw, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; - tmp |= DMAC_CHEVCTRL_EVACT(data); - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const hw, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; - tmp |= DMAC_CHEVCTRL_EVOMODE(data); - ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const hw, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHEVCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHEVCTRL.reg; -} - -static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw) -{ - return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const hw, - hri_dmac_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((DmacChannel *)hw)->CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((DmacChannel *)hw)->CHSTATUS.reg = mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw) -{ - return ((DmacChannel *)hw)->CHSTATUS.reg; -} - -static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; -} - -static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; -} - -static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; - } else { - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; - } -} - -static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; -} - -static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; -} - -static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; - } else { - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; - } -} - -static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; -} - -static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; -} - -static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; -} - -static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; - } else { - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; - } -} - -static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; -} - -static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t mask) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; -} - -static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; -} - -static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t data) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data; - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; -} - -static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintenset_reg_t mask) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; -} - -static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; -} - -static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; -} - -static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; -} - -static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; -} - -static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; -} - -static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; -} - -static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; -} - -static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chintflag_reg_t mask) -{ - ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; -} - -static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_ENABLE; - tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_RUNSTDBY; - tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; - tmp |= DMAC_CHCTRLA_TRIGSRC(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; - tmp |= DMAC_CHCTRLA_TRIGACT(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; - tmp |= DMAC_CHCTRLA_BURSTLEN(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - uint32_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; - tmp |= DMAC_CHCTRLA_THRESHOLD(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrla_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; -} - -static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp &= ~DMAC_CHCTRLB_CMD_Msk; - tmp |= DMAC_CHCTRLB_CMD(data); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chctrlb_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; -} - -static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; - tmp |= DMAC_CHPRILVL_PRILVL(data); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chprilvl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; -} - -static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVIE; - tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; - return (bool)tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOE; - tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; - tmp |= DMAC_CHEVCTRL_EVACT(data); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t data) -{ - uint8_t tmp; - DMAC_CRITICAL_SECTION_ENTER(); - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; - tmp |= DMAC_CHEVCTRL_EVOMODE(data); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; - return tmp; -} - -static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t data) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chevctrl_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; -} - -static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; -} - -static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_dmac_chstatus_reg_t mask) -{ - DMAC_CRITICAL_SECTION_ENTER(); - ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask; - DMAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DMAC_D51_H_INCLUDED */ -#endif /* _SAMD51_DMAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_dsu_d51.h b/atmel-samd/asf4/samd51/hri/hri_dsu_d51.h deleted file mode 100644 index b7128008d..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_dsu_d51.h +++ /dev/null @@ -1,3766 +0,0 @@ -/** - * \file - * - * \brief SAM DSU - * - * Copyright (C) 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_DSU_COMPONENT_ -#ifndef _HRI_DSU_D51_H_INCLUDED_ -#define _HRI_DSU_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_DSU_CRITICAL_SECTIONS) -#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define DSU_CRITICAL_SECTION_ENTER() -#define DSU_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_dsu_addr_reg_t; -typedef uint32_t hri_dsu_cfg_reg_t; -typedef uint32_t hri_dsu_cid0_reg_t; -typedef uint32_t hri_dsu_cid1_reg_t; -typedef uint32_t hri_dsu_cid2_reg_t; -typedef uint32_t hri_dsu_cid3_reg_t; -typedef uint32_t hri_dsu_data_reg_t; -typedef uint32_t hri_dsu_dcc_reg_t; -typedef uint32_t hri_dsu_dcfg_reg_t; -typedef uint32_t hri_dsu_did_reg_t; -typedef uint32_t hri_dsu_end_reg_t; -typedef uint32_t hri_dsu_entry0_reg_t; -typedef uint32_t hri_dsu_entry1_reg_t; -typedef uint32_t hri_dsu_length_reg_t; -typedef uint32_t hri_dsu_mbafail_reg_t; -typedef uint32_t hri_dsu_mbbusy0_reg_t; -typedef uint32_t hri_dsu_mbconfig_reg_t; -typedef uint32_t hri_dsu_mbcontext_reg_t; -typedef uint32_t hri_dsu_mbctrl_reg_t; -typedef uint32_t hri_dsu_mbdexp_reg_t; -typedef uint32_t hri_dsu_mbdfail_reg_t; -typedef uint32_t hri_dsu_mbenable0_reg_t; -typedef uint32_t hri_dsu_mbgstat_reg_t; -typedef uint32_t hri_dsu_mbstatus0_reg_t; -typedef uint32_t hri_dsu_mbword_reg_t; -typedef uint32_t hri_dsu_memtype_reg_t; -typedef uint32_t hri_dsu_pid0_reg_t; -typedef uint32_t hri_dsu_pid1_reg_t; -typedef uint32_t hri_dsu_pid2_reg_t; -typedef uint32_t hri_dsu_pid3_reg_t; -typedef uint32_t hri_dsu_pid4_reg_t; -typedef uint32_t hri_dsu_pid5_reg_t; -typedef uint32_t hri_dsu_pid6_reg_t; -typedef uint32_t hri_dsu_pid7_reg_t; -typedef uint8_t hri_dsu_ctrl_reg_t; -typedef uint8_t hri_dsu_statusa_reg_t; -typedef uint8_t hri_dsu_statusb_reg_t; - -static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; -} - -static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; -} - -static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; -} - -static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos; -} - -static inline bool hri_dsu_get_STATUSB_TDCCD0_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_TDCCD0) >> DSU_STATUSB_TDCCD0_Pos; -} - -static inline bool hri_dsu_get_STATUSB_TDCCD1_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_TDCCD1) >> DSU_STATUSB_TDCCD1_Pos; -} - -static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dsu *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) -{ - return ((Dsu *)hw)->STATUSB.reg; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) -{ - return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; -} - -static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DID.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) -{ - return ((Dsu *)hw)->DID.reg; -} - -static inline hri_dsu_mbdfail_reg_t hri_dsu_get_MBDFAIL_DATA_bf(const void *const hw, hri_dsu_mbdfail_reg_t mask) -{ - return (((Dsu *)hw)->MBDFAIL.reg & DSU_MBDFAIL_DATA(mask)) >> DSU_MBDFAIL_DATA_Pos; -} - -static inline hri_dsu_mbdfail_reg_t hri_dsu_read_MBDFAIL_DATA_bf(const void *const hw) -{ - return (((Dsu *)hw)->MBDFAIL.reg & DSU_MBDFAIL_DATA_Msk) >> DSU_MBDFAIL_DATA_Pos; -} - -static inline hri_dsu_mbdfail_reg_t hri_dsu_get_MBDFAIL_reg(const void *const hw, hri_dsu_mbdfail_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBDFAIL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_mbdfail_reg_t hri_dsu_read_MBDFAIL_reg(const void *const hw) -{ - return ((Dsu *)hw)->MBDFAIL.reg; -} - -static inline hri_dsu_mbdexp_reg_t hri_dsu_get_MBDEXP_DATA_bf(const void *const hw, hri_dsu_mbdexp_reg_t mask) -{ - return (((Dsu *)hw)->MBDEXP.reg & DSU_MBDEXP_DATA(mask)) >> DSU_MBDEXP_DATA_Pos; -} - -static inline hri_dsu_mbdexp_reg_t hri_dsu_read_MBDEXP_DATA_bf(const void *const hw) -{ - return (((Dsu *)hw)->MBDEXP.reg & DSU_MBDEXP_DATA_Msk) >> DSU_MBDEXP_DATA_Pos; -} - -static inline hri_dsu_mbdexp_reg_t hri_dsu_get_MBDEXP_reg(const void *const hw, hri_dsu_mbdexp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBDEXP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_mbdexp_reg_t hri_dsu_read_MBDEXP_reg(const void *const hw) -{ - return ((Dsu *)hw)->MBDEXP.reg; -} - -static inline hri_dsu_mbafail_reg_t hri_dsu_get_MBAFAIL_ADDR_bf(const void *const hw, hri_dsu_mbafail_reg_t mask) -{ - return (((Dsu *)hw)->MBAFAIL.reg & DSU_MBAFAIL_ADDR(mask)) >> DSU_MBAFAIL_ADDR_Pos; -} - -static inline hri_dsu_mbafail_reg_t hri_dsu_read_MBAFAIL_ADDR_bf(const void *const hw) -{ - return (((Dsu *)hw)->MBAFAIL.reg & DSU_MBAFAIL_ADDR_Msk) >> DSU_MBAFAIL_ADDR_Pos; -} - -static inline hri_dsu_mbafail_reg_t hri_dsu_get_MBAFAIL_reg(const void *const hw, hri_dsu_mbafail_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBAFAIL.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_mbafail_reg_t hri_dsu_read_MBAFAIL_reg(const void *const hw) -{ - return ((Dsu *)hw)->MBAFAIL.reg; -} - -static inline bool hri_dsu_get_MBCONTEXT_PORT_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBCONTEXT.reg & DSU_MBCONTEXT_PORT) >> DSU_MBCONTEXT_PORT_Pos; -} - -static inline hri_dsu_mbcontext_reg_t hri_dsu_get_MBCONTEXT_SUBSTEP_bf(const void *const hw, - hri_dsu_mbcontext_reg_t mask) -{ - return (((Dsu *)hw)->MBCONTEXT.reg & DSU_MBCONTEXT_SUBSTEP(mask)) >> DSU_MBCONTEXT_SUBSTEP_Pos; -} - -static inline hri_dsu_mbcontext_reg_t hri_dsu_read_MBCONTEXT_SUBSTEP_bf(const void *const hw) -{ - return (((Dsu *)hw)->MBCONTEXT.reg & DSU_MBCONTEXT_SUBSTEP_Msk) >> DSU_MBCONTEXT_SUBSTEP_Pos; -} - -static inline hri_dsu_mbcontext_reg_t hri_dsu_get_MBCONTEXT_STEP_bf(const void *const hw, hri_dsu_mbcontext_reg_t mask) -{ - return (((Dsu *)hw)->MBCONTEXT.reg & DSU_MBCONTEXT_STEP(mask)) >> DSU_MBCONTEXT_STEP_Pos; -} - -static inline hri_dsu_mbcontext_reg_t hri_dsu_read_MBCONTEXT_STEP_bf(const void *const hw) -{ - return (((Dsu *)hw)->MBCONTEXT.reg & DSU_MBCONTEXT_STEP_Msk) >> DSU_MBCONTEXT_STEP_Pos; -} - -static inline hri_dsu_mbcontext_reg_t hri_dsu_get_MBCONTEXT_reg(const void *const hw, hri_dsu_mbcontext_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBCONTEXT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_mbcontext_reg_t hri_dsu_read_MBCONTEXT_reg(const void *const hw) -{ - return ((Dsu *)hw)->MBCONTEXT.reg; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY0_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY0) >> DSU_MBBUSY0_BUSY0_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY1_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY1) >> DSU_MBBUSY0_BUSY1_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY2_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY2) >> DSU_MBBUSY0_BUSY2_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY3_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY3) >> DSU_MBBUSY0_BUSY3_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY4_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY4) >> DSU_MBBUSY0_BUSY4_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY5_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY5) >> DSU_MBBUSY0_BUSY5_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY6_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY6) >> DSU_MBBUSY0_BUSY6_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY7_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY7) >> DSU_MBBUSY0_BUSY7_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY8_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY8) >> DSU_MBBUSY0_BUSY8_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY9_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY9) >> DSU_MBBUSY0_BUSY9_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY10_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY10) >> DSU_MBBUSY0_BUSY10_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY11_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY11) >> DSU_MBBUSY0_BUSY11_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY12_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY12) >> DSU_MBBUSY0_BUSY12_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY13_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY13) >> DSU_MBBUSY0_BUSY13_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY14_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY14) >> DSU_MBBUSY0_BUSY14_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY15_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY15) >> DSU_MBBUSY0_BUSY15_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY16_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY16) >> DSU_MBBUSY0_BUSY16_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY17_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY17) >> DSU_MBBUSY0_BUSY17_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY18_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY18) >> DSU_MBBUSY0_BUSY18_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY19_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY19) >> DSU_MBBUSY0_BUSY19_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY20_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY20) >> DSU_MBBUSY0_BUSY20_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY21_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY21) >> DSU_MBBUSY0_BUSY21_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY22_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY22) >> DSU_MBBUSY0_BUSY22_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY23_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY23) >> DSU_MBBUSY0_BUSY23_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY24_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY24) >> DSU_MBBUSY0_BUSY24_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY25_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY25) >> DSU_MBBUSY0_BUSY25_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY26_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY26) >> DSU_MBBUSY0_BUSY26_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY27_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY27) >> DSU_MBBUSY0_BUSY27_Pos; -} - -static inline bool hri_dsu_get_MBBUSY0_BUSY28_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBBUSY0.reg & DSU_MBBUSY0_BUSY28) >> DSU_MBBUSY0_BUSY28_Pos; -} - -static inline hri_dsu_mbbusy0_reg_t hri_dsu_get_MBBUSY0_reg(const void *const hw, hri_dsu_mbbusy0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBBUSY0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_mbbusy0_reg_t hri_dsu_read_MBBUSY0_reg(const void *const hw) -{ - return ((Dsu *)hw)->MBBUSY0.reg; -} - -static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; -} - -static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) -{ - return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ENTRY0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) -{ - return ((Dsu *)hw)->ENTRY0.reg; -} - -static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ENTRY1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) -{ - return ((Dsu *)hw)->ENTRY1.reg; -} - -static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) -{ - return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; -} - -static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) -{ - return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; -} - -static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->END.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) -{ - return ((Dsu *)hw)->END.reg; -} - -static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) -{ - return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; -} - -static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MEMTYPE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) -{ - return ((Dsu *)hw)->MEMTYPE.reg; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID4.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID4.reg; -} - -static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID5.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID5.reg; -} - -static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID6.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID6.reg; -} - -static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID7.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID7.reg; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) -{ - return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID0.reg; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID1.reg; -} - -static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID2.reg; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) -{ - return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->PID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) -{ - return ((Dsu *)hw)->PID3.reg; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) -{ - return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID0.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID0.reg; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID1.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID1.reg; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) -{ - return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID2.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID2.reg; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) -{ - return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) -{ - return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CID3.reg; - tmp &= mask; - return tmp; -} - -static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) -{ - return ((Dsu *)hw)->CID3.reg; -} - -static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; - return tmp; -} - -static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= ~DSU_ADDR_AMOD_Msk; - tmp |= DSU_ADDR_AMOD(data); - ((Dsu *)hw)->ADDR.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; - return tmp; -} - -static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= ~DSU_ADDR_ADDR_Msk; - tmp |= DSU_ADDR_ADDR(data); - ((Dsu *)hw)->ADDR.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->ADDR.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) -{ - return ((Dsu *)hw)->ADDR.reg; -} - -static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; - return tmp; -} - -static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp &= ~DSU_LENGTH_LENGTH_Msk; - tmp |= DSU_LENGTH_LENGTH(data); - ((Dsu *)hw)->LENGTH.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; - return tmp; -} - -static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->LENGTH.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) -{ - return ((Dsu *)hw)->LENGTH.reg; -} - -static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DATA.reg; - tmp &= ~DSU_DATA_DATA_Msk; - tmp |= DSU_DATA_DATA(data); - ((Dsu *)hw)->DATA.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DATA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DATA.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) -{ - return ((Dsu *)hw)->DATA.reg; -} - -static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp &= ~DSU_DCC_DATA_Msk; - tmp |= DSU_DCC_DATA(data); - ((Dsu *)hw)->DCC[index].reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCC[index].reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) -{ - return ((Dsu *)hw)->DCC[index].reg; -} - -static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= ~DSU_CFG_ETBRAMEN; - tmp |= value << DSU_CFG_ETBRAMEN_Pos; - ((Dsu *)hw)->CFG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos; - return tmp; -} - -static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= ~DSU_CFG_LQOS_Msk; - tmp |= DSU_CFG_LQOS(data); - ((Dsu *)hw)->CFG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos; - return tmp; -} - -static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos; - return tmp; -} - -static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= ~DSU_CFG_DCCDMALEVEL_Msk; - tmp |= DSU_CFG_DCCDMALEVEL(data); - ((Dsu *)hw)->CFG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos; - return tmp; -} - -static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->CFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CFG.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw) -{ - return ((Dsu *)hw)->CFG.reg; -} - -static inline void hri_dsu_set_MBCTRL_SWRST_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCTRL.reg |= DSU_MBCTRL_SWRST; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBCTRL_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBCTRL.reg; - tmp = (tmp & DSU_MBCTRL_SWRST) >> DSU_MBCTRL_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_set_MBCTRL_ENABLE_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCTRL.reg |= DSU_MBCTRL_ENABLE; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBCTRL_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBCTRL.reg; - tmp = (tmp & DSU_MBCTRL_ENABLE) >> DSU_MBCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBCTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBCTRL.reg; - tmp &= ~DSU_MBCTRL_ENABLE; - tmp |= value << DSU_MBCTRL_ENABLE_Pos; - ((Dsu *)hw)->MBCTRL.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBCTRL_ENABLE_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCTRL.reg &= ~DSU_MBCTRL_ENABLE; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBCTRL_ENABLE_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCTRL.reg ^= DSU_MBCTRL_ENABLE; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBCTRL_reg(const void *const hw, hri_dsu_mbctrl_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCTRL.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbctrl_reg_t hri_dsu_get_MBCTRL_reg(const void *const hw, hri_dsu_mbctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_MBCTRL_reg(const void *const hw, hri_dsu_mbctrl_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCTRL.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBCTRL_reg(const void *const hw, hri_dsu_mbctrl_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCTRL.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBCTRL_reg(const void *const hw, hri_dsu_mbctrl_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCTRL.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbctrl_reg_t hri_dsu_read_MBCTRL_reg(const void *const hw) -{ - return ((Dsu *)hw)->MBCTRL.reg; -} - -static inline void hri_dsu_set_MBCONFIG_DEFRDMARGIN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg |= DSU_MBCONFIG_DEFRDMARGIN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBCONFIG_DEFRDMARGIN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBCONFIG.reg; - tmp = (tmp & DSU_MBCONFIG_DEFRDMARGIN) >> DSU_MBCONFIG_DEFRDMARGIN_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBCONFIG_DEFRDMARGIN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBCONFIG.reg; - tmp &= ~DSU_MBCONFIG_DEFRDMARGIN; - tmp |= value << DSU_MBCONFIG_DEFRDMARGIN_Pos; - ((Dsu *)hw)->MBCONFIG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBCONFIG_DEFRDMARGIN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg &= ~DSU_MBCONFIG_DEFRDMARGIN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBCONFIG_DEFRDMARGIN_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg ^= DSU_MBCONFIG_DEFRDMARGIN; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBCONFIG_DBG_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg |= DSU_MBCONFIG_DBG; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBCONFIG_DBG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBCONFIG.reg; - tmp = (tmp & DSU_MBCONFIG_DBG) >> DSU_MBCONFIG_DBG_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBCONFIG_DBG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBCONFIG.reg; - tmp &= ~DSU_MBCONFIG_DBG; - tmp |= value << DSU_MBCONFIG_DBG_Pos; - ((Dsu *)hw)->MBCONFIG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBCONFIG_DBG_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg &= ~DSU_MBCONFIG_DBG; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBCONFIG_DBG_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg ^= DSU_MBCONFIG_DBG; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBCONFIG_ALGO_bf(const void *const hw, hri_dsu_mbconfig_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg |= DSU_MBCONFIG_ALGO(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbconfig_reg_t hri_dsu_get_MBCONFIG_ALGO_bf(const void *const hw, hri_dsu_mbconfig_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBCONFIG.reg; - tmp = (tmp & DSU_MBCONFIG_ALGO(mask)) >> DSU_MBCONFIG_ALGO_Pos; - return tmp; -} - -static inline void hri_dsu_write_MBCONFIG_ALGO_bf(const void *const hw, hri_dsu_mbconfig_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBCONFIG.reg; - tmp &= ~DSU_MBCONFIG_ALGO_Msk; - tmp |= DSU_MBCONFIG_ALGO(data); - ((Dsu *)hw)->MBCONFIG.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBCONFIG_ALGO_bf(const void *const hw, hri_dsu_mbconfig_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg &= ~DSU_MBCONFIG_ALGO(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBCONFIG_ALGO_bf(const void *const hw, hri_dsu_mbconfig_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg ^= DSU_MBCONFIG_ALGO(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbconfig_reg_t hri_dsu_read_MBCONFIG_ALGO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBCONFIG.reg; - tmp = (tmp & DSU_MBCONFIG_ALGO_Msk) >> DSU_MBCONFIG_ALGO_Pos; - return tmp; -} - -static inline void hri_dsu_set_MBCONFIG_reg(const void *const hw, hri_dsu_mbconfig_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbconfig_reg_t hri_dsu_get_MBCONFIG_reg(const void *const hw, hri_dsu_mbconfig_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBCONFIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_MBCONFIG_reg(const void *const hw, hri_dsu_mbconfig_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBCONFIG_reg(const void *const hw, hri_dsu_mbconfig_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBCONFIG_reg(const void *const hw, hri_dsu_mbconfig_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBCONFIG.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbconfig_reg_t hri_dsu_read_MBCONFIG_reg(const void *const hw) -{ - return ((Dsu *)hw)->MBCONFIG.reg; -} - -static inline void hri_dsu_set_MBWORD_DATA_bf(const void *const hw, hri_dsu_mbword_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBWORD.reg |= DSU_MBWORD_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbword_reg_t hri_dsu_get_MBWORD_DATA_bf(const void *const hw, hri_dsu_mbword_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBWORD.reg; - tmp = (tmp & DSU_MBWORD_DATA(mask)) >> DSU_MBWORD_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_write_MBWORD_DATA_bf(const void *const hw, hri_dsu_mbword_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBWORD.reg; - tmp &= ~DSU_MBWORD_DATA_Msk; - tmp |= DSU_MBWORD_DATA(data); - ((Dsu *)hw)->MBWORD.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBWORD_DATA_bf(const void *const hw, hri_dsu_mbword_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBWORD.reg &= ~DSU_MBWORD_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBWORD_DATA_bf(const void *const hw, hri_dsu_mbword_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBWORD.reg ^= DSU_MBWORD_DATA(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbword_reg_t hri_dsu_read_MBWORD_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBWORD.reg; - tmp = (tmp & DSU_MBWORD_DATA_Msk) >> DSU_MBWORD_DATA_Pos; - return tmp; -} - -static inline void hri_dsu_set_MBWORD_reg(const void *const hw, hri_dsu_mbword_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBWORD.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbword_reg_t hri_dsu_get_MBWORD_reg(const void *const hw, hri_dsu_mbword_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBWORD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_MBWORD_reg(const void *const hw, hri_dsu_mbword_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBWORD.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBWORD_reg(const void *const hw, hri_dsu_mbword_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBWORD.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBWORD_reg(const void *const hw, hri_dsu_mbword_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBWORD.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbword_reg_t hri_dsu_read_MBWORD_reg(const void *const hw) -{ - return ((Dsu *)hw)->MBWORD.reg; -} - -static inline void hri_dsu_set_MBGSTAT_ALLDONE_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg |= DSU_MBGSTAT_ALLDONE; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBGSTAT_ALLDONE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBGSTAT.reg; - tmp = (tmp & DSU_MBGSTAT_ALLDONE) >> DSU_MBGSTAT_ALLDONE_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBGSTAT_ALLDONE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBGSTAT.reg; - tmp &= ~DSU_MBGSTAT_ALLDONE; - tmp |= value << DSU_MBGSTAT_ALLDONE_Pos; - ((Dsu *)hw)->MBGSTAT.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBGSTAT_ALLDONE_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg &= ~DSU_MBGSTAT_ALLDONE; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBGSTAT_ALLDONE_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg ^= DSU_MBGSTAT_ALLDONE; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBGSTAT_FAILED_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg |= DSU_MBGSTAT_FAILED; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBGSTAT_FAILED_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBGSTAT.reg; - tmp = (tmp & DSU_MBGSTAT_FAILED) >> DSU_MBGSTAT_FAILED_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBGSTAT_FAILED_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBGSTAT.reg; - tmp &= ~DSU_MBGSTAT_FAILED; - tmp |= value << DSU_MBGSTAT_FAILED_Pos; - ((Dsu *)hw)->MBGSTAT.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBGSTAT_FAILED_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg &= ~DSU_MBGSTAT_FAILED; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBGSTAT_FAILED_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg ^= DSU_MBGSTAT_FAILED; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBGSTAT_ERRINFO_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg |= DSU_MBGSTAT_ERRINFO; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBGSTAT_ERRINFO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBGSTAT.reg; - tmp = (tmp & DSU_MBGSTAT_ERRINFO) >> DSU_MBGSTAT_ERRINFO_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBGSTAT_ERRINFO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBGSTAT.reg; - tmp &= ~DSU_MBGSTAT_ERRINFO; - tmp |= value << DSU_MBGSTAT_ERRINFO_Pos; - ((Dsu *)hw)->MBGSTAT.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBGSTAT_ERRINFO_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg &= ~DSU_MBGSTAT_ERRINFO; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBGSTAT_ERRINFO_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg ^= DSU_MBGSTAT_ERRINFO; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBGSTAT_CONFIGURED_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg |= DSU_MBGSTAT_CONFIGURED; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBGSTAT_CONFIGURED_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBGSTAT.reg; - tmp = (tmp & DSU_MBGSTAT_CONFIGURED) >> DSU_MBGSTAT_CONFIGURED_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBGSTAT_CONFIGURED_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBGSTAT.reg; - tmp &= ~DSU_MBGSTAT_CONFIGURED; - tmp |= value << DSU_MBGSTAT_CONFIGURED_Pos; - ((Dsu *)hw)->MBGSTAT.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBGSTAT_CONFIGURED_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg &= ~DSU_MBGSTAT_CONFIGURED; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBGSTAT_CONFIGURED_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg ^= DSU_MBGSTAT_CONFIGURED; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBGSTAT_reg(const void *const hw, hri_dsu_mbgstat_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbgstat_reg_t hri_dsu_get_MBGSTAT_reg(const void *const hw, hri_dsu_mbgstat_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBGSTAT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_MBGSTAT_reg(const void *const hw, hri_dsu_mbgstat_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBGSTAT_reg(const void *const hw, hri_dsu_mbgstat_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBGSTAT_reg(const void *const hw, hri_dsu_mbgstat_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBGSTAT.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbgstat_reg_t hri_dsu_read_MBGSTAT_reg(const void *const hw) -{ - return ((Dsu *)hw)->MBGSTAT.reg; -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE0_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE0; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE0) >> DSU_MBENABLE0_ENABLE0_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE0; - tmp |= value << DSU_MBENABLE0_ENABLE0_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE0_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE0; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE0_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE0; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE1_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE1; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE1) >> DSU_MBENABLE0_ENABLE1_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE1; - tmp |= value << DSU_MBENABLE0_ENABLE1_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE1_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE1; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE1_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE1; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE2_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE2; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE2) >> DSU_MBENABLE0_ENABLE2_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE2; - tmp |= value << DSU_MBENABLE0_ENABLE2_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE2_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE2; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE2_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE2; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE3_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE3; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE3) >> DSU_MBENABLE0_ENABLE3_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE3; - tmp |= value << DSU_MBENABLE0_ENABLE3_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE3_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE3; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE3_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE3; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE4_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE4; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE4) >> DSU_MBENABLE0_ENABLE4_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE4; - tmp |= value << DSU_MBENABLE0_ENABLE4_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE4_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE4; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE4_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE4; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE5_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE5; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE5) >> DSU_MBENABLE0_ENABLE5_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE5; - tmp |= value << DSU_MBENABLE0_ENABLE5_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE5_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE5; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE5_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE5; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE6_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE6; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE6) >> DSU_MBENABLE0_ENABLE6_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE6; - tmp |= value << DSU_MBENABLE0_ENABLE6_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE6_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE6; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE6_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE6; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE7_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE7; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE7) >> DSU_MBENABLE0_ENABLE7_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE7; - tmp |= value << DSU_MBENABLE0_ENABLE7_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE7_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE7; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE7_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE7; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE8_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE8; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE8) >> DSU_MBENABLE0_ENABLE8_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE8; - tmp |= value << DSU_MBENABLE0_ENABLE8_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE8_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE8; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE8_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE8; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE9_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE9; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE9) >> DSU_MBENABLE0_ENABLE9_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE9; - tmp |= value << DSU_MBENABLE0_ENABLE9_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE9_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE9; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE9_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE9; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE10_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE10; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE10) >> DSU_MBENABLE0_ENABLE10_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE10; - tmp |= value << DSU_MBENABLE0_ENABLE10_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE10_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE10; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE10_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE10; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE11_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE11; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE11) >> DSU_MBENABLE0_ENABLE11_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE11; - tmp |= value << DSU_MBENABLE0_ENABLE11_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE11_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE11; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE11_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE11; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE12_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE12; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE12) >> DSU_MBENABLE0_ENABLE12_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE12; - tmp |= value << DSU_MBENABLE0_ENABLE12_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE12_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE12; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE12_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE12; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE13_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE13; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE13) >> DSU_MBENABLE0_ENABLE13_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE13; - tmp |= value << DSU_MBENABLE0_ENABLE13_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE13_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE13; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE13_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE13; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE14_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE14; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE14) >> DSU_MBENABLE0_ENABLE14_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE14; - tmp |= value << DSU_MBENABLE0_ENABLE14_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE14_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE14; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE14_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE14; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE15_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE15; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE15) >> DSU_MBENABLE0_ENABLE15_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE15; - tmp |= value << DSU_MBENABLE0_ENABLE15_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE15_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE15; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE15_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE15; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE16_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE16; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE16) >> DSU_MBENABLE0_ENABLE16_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE16; - tmp |= value << DSU_MBENABLE0_ENABLE16_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE16_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE16; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE16_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE16; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE17_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE17; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE17) >> DSU_MBENABLE0_ENABLE17_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE17; - tmp |= value << DSU_MBENABLE0_ENABLE17_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE17_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE17; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE17_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE17; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE18_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE18; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE18) >> DSU_MBENABLE0_ENABLE18_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE18; - tmp |= value << DSU_MBENABLE0_ENABLE18_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE18_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE18; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE18_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE18; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE19_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE19; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE19) >> DSU_MBENABLE0_ENABLE19_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE19; - tmp |= value << DSU_MBENABLE0_ENABLE19_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE19_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE19; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE19_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE19; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE20_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE20; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE20) >> DSU_MBENABLE0_ENABLE20_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE20; - tmp |= value << DSU_MBENABLE0_ENABLE20_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE20_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE20; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE20_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE20; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE21_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE21; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE21) >> DSU_MBENABLE0_ENABLE21_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE21; - tmp |= value << DSU_MBENABLE0_ENABLE21_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE21_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE21; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE21_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE21; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE22_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE22; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE22) >> DSU_MBENABLE0_ENABLE22_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE22; - tmp |= value << DSU_MBENABLE0_ENABLE22_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE22_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE22; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE22_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE22; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE23_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE23; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE23) >> DSU_MBENABLE0_ENABLE23_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE23; - tmp |= value << DSU_MBENABLE0_ENABLE23_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE23_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE23; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE23_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE23; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE24_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE24; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE24) >> DSU_MBENABLE0_ENABLE24_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE24; - tmp |= value << DSU_MBENABLE0_ENABLE24_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE24_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE24; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE24_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE24; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE25_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE25; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE25) >> DSU_MBENABLE0_ENABLE25_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE25; - tmp |= value << DSU_MBENABLE0_ENABLE25_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE25_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE25; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE25_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE25; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE26_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE26; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE26) >> DSU_MBENABLE0_ENABLE26_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE26; - tmp |= value << DSU_MBENABLE0_ENABLE26_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE26_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE26; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE26_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE26; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE27_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE27; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE27) >> DSU_MBENABLE0_ENABLE27_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE27; - tmp |= value << DSU_MBENABLE0_ENABLE27_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE27_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE27; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE27_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE27; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_ENABLE28_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= DSU_MBENABLE0_ENABLE28; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBENABLE0_ENABLE28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp = (tmp & DSU_MBENABLE0_ENABLE28) >> DSU_MBENABLE0_ENABLE28_Pos; - return (bool)tmp; -} - -static inline void hri_dsu_write_MBENABLE0_ENABLE28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= ~DSU_MBENABLE0_ENABLE28; - tmp |= value << DSU_MBENABLE0_ENABLE28_Pos; - ((Dsu *)hw)->MBENABLE0.reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_ENABLE28_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~DSU_MBENABLE0_ENABLE28; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_ENABLE28_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= DSU_MBENABLE0_ENABLE28; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_set_MBENABLE0_reg(const void *const hw, hri_dsu_mbenable0_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbenable0_reg_t hri_dsu_get_MBENABLE0_reg(const void *const hw, hri_dsu_mbenable0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBENABLE0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_MBENABLE0_reg(const void *const hw, hri_dsu_mbenable0_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_MBENABLE0_reg(const void *const hw, hri_dsu_mbenable0_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_MBENABLE0_reg(const void *const hw, hri_dsu_mbenable0_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBENABLE0.reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbenable0_reg_t hri_dsu_read_MBENABLE0_reg(const void *const hw) -{ - return ((Dsu *)hw)->MBENABLE0.reg; -} - -static inline void hri_dsu_set_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg |= DSU_DCFG_DCFG(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp = (tmp & DSU_DCFG_DCFG(mask)) >> DSU_DCFG_DCFG_Pos; - return tmp; -} - -static inline void hri_dsu_write_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) -{ - uint32_t tmp; - DSU_CRITICAL_SECTION_ENTER(); - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp &= ~DSU_DCFG_DCFG_Msk; - tmp |= DSU_DCFG_DCFG(data); - ((Dsu *)hw)->DCFG[index].reg = tmp; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg &= ~DSU_DCFG_DCFG(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCFG_DCFG_bf(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg ^= DSU_DCFG_DCFG(mask); - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_DCFG_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp = (tmp & DSU_DCFG_DCFG_Msk) >> DSU_DCFG_DCFG_Pos; - return tmp; -} - -static inline void hri_dsu_set_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg |= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_get_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->DCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_write_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_clear_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg &= ~mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_dsu_toggle_DCFG_reg(const void *const hw, uint8_t index, hri_dsu_dcfg_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->DCFG[index].reg ^= mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_dcfg_reg_t hri_dsu_read_DCFG_reg(const void *const hw, uint8_t index) -{ - return ((Dsu *)hw)->DCFG[index].reg; -} - -static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; -} - -static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; -} - -static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; -} - -static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; -} - -static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) -{ - return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; -} - -static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) -{ - uint8_t tmp; - tmp = ((Dsu *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->STATUSA.reg = mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) -{ - return ((Dsu *)hw)->STATUSA.reg; -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS0_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS0) >> DSU_MBSTATUS0_STATUS0_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS0_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS0; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS1_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS1) >> DSU_MBSTATUS0_STATUS1_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS1_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS1; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS2_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS2) >> DSU_MBSTATUS0_STATUS2_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS2_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS2; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS3_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS3) >> DSU_MBSTATUS0_STATUS3_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS3_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS3; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS4_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS4) >> DSU_MBSTATUS0_STATUS4_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS4_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS4; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS5_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS5) >> DSU_MBSTATUS0_STATUS5_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS5_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS5; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS6_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS6) >> DSU_MBSTATUS0_STATUS6_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS6_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS6; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS7_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS7) >> DSU_MBSTATUS0_STATUS7_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS7_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS7; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS8_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS8) >> DSU_MBSTATUS0_STATUS8_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS8_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS8; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS9_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS9) >> DSU_MBSTATUS0_STATUS9_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS9_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS9; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS10_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS10) >> DSU_MBSTATUS0_STATUS10_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS10_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS10; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS11_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS11) >> DSU_MBSTATUS0_STATUS11_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS11_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS11; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS12_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS12) >> DSU_MBSTATUS0_STATUS12_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS12_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS12; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS13_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS13) >> DSU_MBSTATUS0_STATUS13_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS13_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS13; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS14_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS14) >> DSU_MBSTATUS0_STATUS14_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS14_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS14; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS15_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS15) >> DSU_MBSTATUS0_STATUS15_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS15_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS15; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS16_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS16) >> DSU_MBSTATUS0_STATUS16_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS16_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS16; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS17_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS17) >> DSU_MBSTATUS0_STATUS17_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS17_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS17; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS18_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS18) >> DSU_MBSTATUS0_STATUS18_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS18_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS18; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS19_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS19) >> DSU_MBSTATUS0_STATUS19_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS19_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS19; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS20_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS20) >> DSU_MBSTATUS0_STATUS20_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS20_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS20; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS21_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS21) >> DSU_MBSTATUS0_STATUS21_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS21_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS21; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS22_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS22) >> DSU_MBSTATUS0_STATUS22_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS22_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS22; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS23_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS23) >> DSU_MBSTATUS0_STATUS23_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS23_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS23; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS24_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS24) >> DSU_MBSTATUS0_STATUS24_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS24_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS24; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS25_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS25) >> DSU_MBSTATUS0_STATUS25_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS25_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS25; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS26_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS26) >> DSU_MBSTATUS0_STATUS26_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS26_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS26; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS27_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS27) >> DSU_MBSTATUS0_STATUS27_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS27_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS27; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_dsu_get_MBSTATUS0_STATUS28_bit(const void *const hw) -{ - return (((Dsu *)hw)->MBSTATUS0.reg & DSU_MBSTATUS0_STATUS28) >> DSU_MBSTATUS0_STATUS28_Pos; -} - -static inline void hri_dsu_clear_MBSTATUS0_STATUS28_bit(const void *const hw) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = DSU_MBSTATUS0_STATUS28; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbstatus0_reg_t hri_dsu_get_MBSTATUS0_reg(const void *const hw, hri_dsu_mbstatus0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Dsu *)hw)->MBSTATUS0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_dsu_clear_MBSTATUS0_reg(const void *const hw, hri_dsu_mbstatus0_reg_t mask) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->MBSTATUS0.reg = mask; - DSU_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_dsu_mbstatus0_reg_t hri_dsu_read_MBSTATUS0_reg(const void *const hw) -{ - return ((Dsu *)hw)->MBSTATUS0.reg; -} - -static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) -{ - DSU_CRITICAL_SECTION_ENTER(); - ((Dsu *)hw)->CTRL.reg = data; - DSU_CRITICAL_SECTION_LEAVE(); -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_DSU_D51_H_INCLUDED */ -#endif /* _SAMD51_DSU_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_eic_d51.h b/atmel-samd/asf4/samd51/hri/hri_eic_d51.h deleted file mode 100644 index 267a0a0ce..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_eic_d51.h +++ /dev/null @@ -1,1841 +0,0 @@ -/** - * \file - * - * \brief SAM EIC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_EIC_COMPONENT_ -#ifndef _HRI_EIC_D51_H_INCLUDED_ -#define _HRI_EIC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_EIC_CRITICAL_SECTIONS) -#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define EIC_CRITICAL_SECTION_ENTER() -#define EIC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_eic_nmiflag_reg_t; -typedef uint32_t hri_eic_asynch_reg_t; -typedef uint32_t hri_eic_config_reg_t; -typedef uint32_t hri_eic_debouncen_reg_t; -typedef uint32_t hri_eic_dprescaler_reg_t; -typedef uint32_t hri_eic_evctrl_reg_t; -typedef uint32_t hri_eic_intenset_reg_t; -typedef uint32_t hri_eic_intflag_reg_t; -typedef uint32_t hri_eic_pinstate_reg_t; -typedef uint32_t hri_eic_syncbusy_reg_t; -typedef uint8_t hri_eic_ctrla_reg_t; -typedef uint8_t hri_eic_nmictrl_reg_t; - -static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) -{ - while (((Eic *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) -{ - return ((Eic *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); -} - -static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; - return tmp; -} - -static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; - return tmp; -} - -static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) -{ - ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); - ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); -} - -static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); -} - -static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENSET.reg = mask; -} - -static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) -{ - return ((Eic *)hw)->INTENSET.reg; -} - -static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) -{ - ((Eic *)hw)->INTENSET.reg = data; - ((Eic *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) -{ - ((Eic *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) -{ - return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; -} - -static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) -{ - ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; -} - -static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Eic *)hw)->NMIFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) -{ - return ((Eic *)hw)->NMIFLAG.reg; -} - -static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) -{ - ((Eic *)hw)->NMIFLAG.reg = mask; -} - -static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) -{ - return ((Eic *)hw)->INTFLAG.reg; -} - -static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) -{ - ((Eic *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= ~EIC_CTRLA_ENABLE; - tmp |= value << EIC_CTRLA_ENABLE_Pos; - ((Eic *)hw)->CTRLA.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); - ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->CTRLA.reg; - tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= ~EIC_CTRLA_CKSEL; - tmp |= value << EIC_CTRLA_CKSEL_Pos; - ((Eic *)hw)->CTRLA.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); - ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CTRLA.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) -{ - return ((Eic *)hw)->CTRLA.reg; -} - -static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMIFILTEN; - tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMIASYNCH; - tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; - return tmp; -} - -static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) -{ - uint8_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= ~EIC_NMICTRL_NMISENSE_Msk; - tmp |= EIC_NMICTRL_NMISENSE(data); - ((Eic *)hw)->NMICTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; - return tmp; -} - -static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Eic *)hw)->NMICTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->NMICTRL.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) -{ - return ((Eic *)hw)->NMICTRL.reg; -} - -static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; - return tmp; -} - -static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; - tmp |= EIC_EVCTRL_EXTINTEO(data); - ((Eic *)hw)->EVCTRL.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; - return tmp; -} - -static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->EVCTRL.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) -{ - return ((Eic *)hw)->EVCTRL.reg; -} - -static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; - return tmp; -} - -static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp &= ~EIC_ASYNCH_ASYNCH_Msk; - tmp |= EIC_ASYNCH_ASYNCH(data); - ((Eic *)hw)->ASYNCH.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; - return tmp; -} - -static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->ASYNCH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->ASYNCH.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) -{ - return ((Eic *)hw)->ASYNCH.reg; -} - -static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN0; - tmp |= value << EIC_CONFIG_FILTEN0_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN1; - tmp |= value << EIC_CONFIG_FILTEN1_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN2; - tmp |= value << EIC_CONFIG_FILTEN2_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN3; - tmp |= value << EIC_CONFIG_FILTEN3_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN4; - tmp |= value << EIC_CONFIG_FILTEN4_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN5; - tmp |= value << EIC_CONFIG_FILTEN5_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN6; - tmp |= value << EIC_CONFIG_FILTEN6_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_FILTEN7; - tmp |= value << EIC_CONFIG_FILTEN7_Pos; - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE0_Msk; - tmp |= EIC_CONFIG_SENSE0(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE1_Msk; - tmp |= EIC_CONFIG_SENSE1(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE2_Msk; - tmp |= EIC_CONFIG_SENSE2(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE3_Msk; - tmp |= EIC_CONFIG_SENSE3(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE4_Msk; - tmp |= EIC_CONFIG_SENSE4(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE5_Msk; - tmp |= EIC_CONFIG_SENSE5(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE6_Msk; - tmp |= EIC_CONFIG_SENSE6(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; - return tmp; -} - -static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= ~EIC_CONFIG_SENSE7_Msk; - tmp |= EIC_CONFIG_SENSE7(data); - ((Eic *)hw)->CONFIG[index].reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; - return tmp; -} - -static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, - hri_eic_config_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->CONFIG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->CONFIG[index].reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) -{ - return ((Eic *)hw)->CONFIG[index].reg; -} - -static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, - hri_eic_debouncen_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; - return tmp; -} - -static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk; - tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data); - ((Eic *)hw)->DEBOUNCEN.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; - return tmp; -} - -static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DEBOUNCEN.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DEBOUNCEN.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw) -{ - return ((Eic *)hw)->DEBOUNCEN.reg; -} - -static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_STATES0; - tmp |= value << EIC_DPRESCALER_STATES0_Pos; - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_STATES1; - tmp |= value << EIC_DPRESCALER_STATES1_Pos; - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos; - return (bool)tmp; -} - -static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_TICKON; - tmp |= value << EIC_DPRESCALER_TICKON_Pos; - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const hw, - hri_eic_dprescaler_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos; - return tmp; -} - -static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk; - tmp |= EIC_DPRESCALER_PRESCALER0(data); - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos; - return tmp; -} - -static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const hw, - hri_eic_dprescaler_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos; - return tmp; -} - -static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data) -{ - uint32_t tmp; - EIC_CRITICAL_SECTION_ENTER(); - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk; - tmp |= EIC_DPRESCALER_PRESCALER1(data); - ((Eic *)hw)->DPRESCALER.reg = tmp; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask); - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos; - return tmp; -} - -static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg |= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->DPRESCALER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg = data; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg &= ~mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) -{ - EIC_CRITICAL_SECTION_ENTER(); - ((Eic *)hw)->DPRESCALER.reg ^= mask; - EIC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw) -{ - return ((Eic *)hw)->DPRESCALER.reg; -} - -static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Eic *)hw)->SYNCBUSY.reg; -} - -static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask) -{ - return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos; -} - -static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw) -{ - return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos; -} - -static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask) -{ - uint32_t tmp; - tmp = ((Eic *)hw)->PINSTATE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw) -{ - return ((Eic *)hw)->PINSTATE.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_EIC_D51_H_INCLUDED */ -#endif /* _SAMD51_EIC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_evsys_d51.h b/atmel-samd/asf4/samd51/hri/hri_evsys_d51.h deleted file mode 100644 index 0663068fa..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_evsys_d51.h +++ /dev/null @@ -1,1716 +0,0 @@ -/** - * \file - * - * \brief SAM EVSYS - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_EVSYS_COMPONENT_ -#ifndef _HRI_EVSYS_D51_H_INCLUDED_ -#define _HRI_EVSYS_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) -#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define EVSYS_CRITICAL_SECTION_ENTER() -#define EVSYS_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_evsys_intpend_reg_t; -typedef uint32_t hri_evsys_busych_reg_t; -typedef uint32_t hri_evsys_channel_reg_t; -typedef uint32_t hri_evsys_intstatus_reg_t; -typedef uint32_t hri_evsys_readyusr_reg_t; -typedef uint32_t hri_evsys_swevt_reg_t; -typedef uint32_t hri_evsys_user_reg_t; -typedef uint32_t hri_evsyschannel_channel_reg_t; -typedef uint8_t hri_evsys_chintenset_reg_t; -typedef uint8_t hri_evsys_chintflag_reg_t; -typedef uint8_t hri_evsys_chstatus_reg_t; -typedef uint8_t hri_evsys_ctrla_reg_t; -typedef uint8_t hri_evsys_prictrl_reg_t; -typedef uint8_t hri_evsyschannel_chintenset_reg_t; -typedef uint8_t hri_evsyschannel_chintflag_reg_t; -typedef uint8_t hri_evsyschannel_chstatus_reg_t; - -static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->SWEVT.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->CTRLA.reg; - tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->CTRLA.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) -{ - return ((Evsys *)hw)->CTRLA.reg; -} - -static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp &= ~EVSYS_PRICTRL_RREN; - tmp |= value << EVSYS_PRICTRL_RREN_Pos; - ((Evsys *)hw)->PRICTRL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos; - return tmp; -} - -static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data) -{ - uint8_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp &= ~EVSYS_PRICTRL_PRI_Msk; - tmp |= EVSYS_PRICTRL_PRI(data); - ((Evsys *)hw)->PRICTRL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos; - return tmp; -} - -static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->PRICTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->PRICTRL.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw) -{ - return ((Evsys *)hw)->PRICTRL.reg; -} - -static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_OVR; - tmp |= value << EVSYS_INTPEND_OVR_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_EVD; - tmp |= value << EVSYS_INTPEND_EVD_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_READY; - tmp |= value << EVSYS_INTPEND_READY_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_BUSY; - tmp |= value << EVSYS_INTPEND_BUSY_Pos; - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data) -{ - uint16_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= ~EVSYS_INTPEND_ID_Msk; - tmp |= EVSYS_INTPEND_ID(data); - ((Evsys *)hw)->INTPEND.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos; - return tmp; -} - -static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - uint16_t tmp; - tmp = ((Evsys *)hw)->INTPEND.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->INTPEND.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw) -{ - return ((Evsys *)hw)->INTPEND.reg; -} - -static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, - hri_evsys_user_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->USER[index].reg; - tmp &= ~EVSYS_USER_CHANNEL_Msk; - tmp |= EVSYS_USER_CHANNEL(data); - ((Evsys *)hw)->USER[index].reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; - return tmp; -} - -static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, - hri_evsys_user_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->USER[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->USER[index].reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) -{ - return ((Evsys *)hw)->USER[index].reg; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos; -} - -static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw) -{ - return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos; -} - -static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const hw, - hri_evsys_intstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->INTSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw) -{ - return ((Evsys *)hw)->INTSTATUS.reg; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos; -} - -static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw) -{ - return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos; -} - -static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->BUSYCH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw) -{ - return ((Evsys *)hw)->BUSYCH.reg; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos; -} - -static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw) -{ - return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos; -} - -static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->READYUSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw) -{ - return ((Evsys *)hw)->READYUSR.reg; -} - -static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; -} - -static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; -} - -static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; - } else { - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; - } -} - -static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; -} - -static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; -} - -static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; -} - -static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; - } else { - ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; - } -} - -static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; -} - -static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = mask; -} - -static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const hw, - hri_evsys_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((EvsysChannel *)hw)->CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHINTENSET.reg; -} - -static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data) -{ - ((EvsysChannel *)hw)->CHINTENSET.reg = data; - ((EvsysChannel *)hw)->CHINTENCLR.reg = ~data; -} - -static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) -{ - ((EvsysChannel *)hw)->CHINTENCLR.reg = mask; -} - -static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const hw, - hri_evsys_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHINTFLAG.reg; -} - -static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask) -{ - ((EvsysChannel *)hw)->CHINTFLAG.reg = mask; -} - -static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_RUNSTDBY; - tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_ONDEMAND; - tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; - tmp |= EVSYS_CHANNEL_EVGEN(data); - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_PATH_Msk; - tmp |= EVSYS_CHANNEL_PATH(data); - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; - tmp |= EVSYS_CHANNEL_EDGSEL(data); - ((EvsysChannel *)hw)->CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const hw, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((EvsysChannel *)hw)->CHANNEL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((EvsysChannel *)hw)->CHANNEL.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHANNEL.reg; -} - -static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; -} - -static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw) -{ - return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; -} - -static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const hw, - hri_evsys_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((EvsysChannel *)hw)->CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw) -{ - return ((EvsysChannel *)hw)->CHSTATUS.reg; -} - -static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; -} - -static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; -} - -static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; - } else { - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; - } -} - -static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; -} - -static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; -} - -static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; -} - -static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; - } else { - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; - } -} - -static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; -} - -static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t mask) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; -} - -static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; -} - -static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t data) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data; - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; -} - -static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintenset_reg_t mask) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; -} - -static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; -} - -static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; -} - -static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; -} - -static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; -} - -static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; -} - -static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chintflag_reg_t mask) -{ - ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; -} - -static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_RUNSTDBY; - tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_ONDEMAND; - tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; - tmp |= EVSYS_CHANNEL_EVGEN(data); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_PATH_Msk; - tmp |= EVSYS_CHANNEL_PATH(data); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - uint32_t tmp; - EVSYS_CRITICAL_SECTION_ENTER(); - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; - tmp |= EVSYS_CHANNEL_EDGSEL(data); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; - return tmp; -} - -static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - uint32_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t data) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_channel_reg_t mask) -{ - EVSYS_CRITICAL_SECTION_ENTER(); - ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask; - EVSYS_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; -} - -static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; -} - -static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; -} - -static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_evsys_chstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_EVSYS_D51_H_INCLUDED */ -#endif /* _SAMD51_EVSYS_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_freqm_d51.h b/atmel-samd/asf4/samd51/hri/hri_freqm_d51.h deleted file mode 100644 index 17f510ef4..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_freqm_d51.h +++ /dev/null @@ -1,467 +0,0 @@ -/** - * \file - * - * \brief SAM FREQM - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_FREQM_COMPONENT_ -#ifndef _HRI_FREQM_D51_H_INCLUDED_ -#define _HRI_FREQM_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) -#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define FREQM_CRITICAL_SECTION_ENTER() -#define FREQM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_freqm_cfga_reg_t; -typedef uint32_t hri_freqm_syncbusy_reg_t; -typedef uint32_t hri_freqm_value_reg_t; -typedef uint8_t hri_freqm_ctrla_reg_t; -typedef uint8_t hri_freqm_ctrlb_reg_t; -typedef uint8_t hri_freqm_intenset_reg_t; -typedef uint8_t hri_freqm_intflag_reg_t; -typedef uint8_t hri_freqm_status_reg_t; - -static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) -{ - while (((Freqm *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) -{ - return ((Freqm *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; -} - -static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; -} - -static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; - } else { - ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; - } -} - -static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; -} - -static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - ((Freqm *)hw)->INTENSET.reg = mask; -} - -static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) -{ - return ((Freqm *)hw)->INTENSET.reg; -} - -static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) -{ - ((Freqm *)hw)->INTENSET.reg = data; - ((Freqm *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) -{ - ((Freqm *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; -} - -static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; -} - -static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) -{ - return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; -} - -static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) -{ - ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; -} - -static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) -{ - return ((Freqm *)hw)->INTFLAG.reg; -} - -static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) -{ - ((Freqm *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLB.reg = data; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); - ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - FREQM_CRITICAL_SECTION_ENTER(); - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp &= ~FREQM_CTRLA_ENABLE; - tmp |= value << FREQM_CTRLA_ENABLE_Pos; - ((Freqm *)hw)->CTRLA.reg = tmp; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); - ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg |= mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg = data; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg &= ~mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CTRLA.reg ^= mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) -{ - return ((Freqm *)hw)->CTRLA.reg; -} - -static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; - return tmp; -} - -static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) -{ - uint16_t tmp; - FREQM_CRITICAL_SECTION_ENTER(); - tmp = ((Freqm *)hw)->CFGA.reg; - tmp &= ~FREQM_CFGA_REFNUM_Msk; - tmp |= FREQM_CFGA_REFNUM(data); - ((Freqm *)hw)->CFGA.reg = tmp; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; - return tmp; -} - -static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg |= mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - uint16_t tmp; - tmp = ((Freqm *)hw)->CFGA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg = data; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg &= ~mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->CFGA.reg ^= mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) -{ - return ((Freqm *)hw)->CFGA.reg; -} - -static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Freqm *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Freqm *)hw)->SYNCBUSY.reg; -} - -static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) -{ - return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; -} - -static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) -{ - return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; -} - -static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) -{ - uint32_t tmp; - tmp = ((Freqm *)hw)->VALUE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) -{ - return ((Freqm *)hw)->VALUE.reg; -} - -static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) -{ - return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; -} - -static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) -{ - return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; -} - -static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Freqm *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) -{ - FREQM_CRITICAL_SECTION_ENTER(); - ((Freqm *)hw)->STATUS.reg = mask; - FREQM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) -{ - return ((Freqm *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_FREQM_D51_H_INCLUDED */ -#endif /* _SAMD51_FREQM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_gclk_d51.h b/atmel-samd/asf4/samd51/hri/hri_gclk_d51.h deleted file mode 100644 index 17d82e20d..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_gclk_d51.h +++ /dev/null @@ -1,770 +0,0 @@ -/** - * \file - * - * \brief SAM GCLK - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_GCLK_COMPONENT_ -#ifndef _HRI_GCLK_D51_H_INCLUDED_ -#define _HRI_GCLK_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) -#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define GCLK_CRITICAL_SECTION_ENTER() -#define GCLK_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_gclk_genctrl_reg_t; -typedef uint32_t hri_gclk_pchctrl_reg_t; -typedef uint32_t hri_gclk_syncbusy_reg_t; -typedef uint8_t hri_gclk_ctrla_reg_t; - -static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) -{ - while (((Gclk *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) -{ - return ((Gclk *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) -{ - GCLK_CRITICAL_SECTION_ENTER(); - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); - tmp = ((Gclk *)hw)->CTRLA.reg; - tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg |= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Gclk *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg = data; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg &= ~mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->CTRLA.reg ^= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) -{ - return ((Gclk *)hw)->CTRLA.reg; -} - -static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_GENEN; - tmp |= value << GCLK_GENCTRL_GENEN_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_IDC; - tmp |= value << GCLK_GENCTRL_IDC_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_OOV; - tmp |= value << GCLK_GENCTRL_OOV_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_OE; - tmp |= value << GCLK_GENCTRL_OE_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_DIVSEL; - tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_RUNSTDBY; - tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_SRC_Msk; - tmp |= GCLK_GENCTRL_SRC(data); - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= ~GCLK_GENCTRL_DIV_Msk; - tmp |= GCLK_GENCTRL_DIV(data); - ((Gclk *)hw)->GENCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; - return tmp; -} - -static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg |= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, - hri_gclk_genctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->GENCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg = data; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->GENCTRL[index].reg ^= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Gclk *)hw)->GENCTRL[index].reg; -} - -static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_CHEN; - tmp |= value << GCLK_PCHCTRL_CHEN_Pos; - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_WRTLOCK; - tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, - hri_gclk_pchctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; - return tmp; -} - -static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) -{ - uint32_t tmp; - GCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= ~GCLK_PCHCTRL_GEN_Msk; - tmp |= GCLK_PCHCTRL_GEN(data); - ((Gclk *)hw)->PCHCTRL[index].reg = tmp; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; - return tmp; -} - -static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg |= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, - hri_gclk_pchctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->PCHCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg = data; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) -{ - GCLK_CRITICAL_SECTION_ENTER(); - ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; - GCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Gclk *)hw)->PCHCTRL[index].reg; -} - -static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos; -} - -static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw) -{ - return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos; -} - -static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Gclk *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Gclk *)hw)->SYNCBUSY.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_GCLK_D51_H_INCLUDED */ -#endif /* _SAMD51_GCLK_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_hmatrixb_d51.h b/atmel-samd/asf4/samd51/hri/hri_hmatrixb_d51.h deleted file mode 100644 index 0d00c8782..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_hmatrixb_d51.h +++ /dev/null @@ -1,246 +0,0 @@ -/** - * \file - * - * \brief SAM HMATRIXB - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_HMATRIXB_COMPONENT_ -#ifndef _HRI_HMATRIXB_D51_H_INCLUDED_ -#define _HRI_HMATRIXB_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) -#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define HMATRIXB_CRITICAL_SECTION_ENTER() -#define HMATRIXB_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_hmatrixb_pras_reg_t; -typedef uint32_t hri_hmatrixb_prbs_reg_t; -typedef uint32_t hri_hmatrixbprs_pras_reg_t; -typedef uint32_t hri_hmatrixbprs_prbs_reg_t; - -static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - uint32_t tmp; - tmp = ((HmatrixbPrs *)hw)->PRAS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) -{ - return ((HmatrixbPrs *)hw)->PRAS.reg; -} - -static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - uint32_t tmp; - tmp = ((HmatrixbPrs *)hw)->PRBS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) -{ - return ((HmatrixbPrs *)hw)->PRBS.reg; -} - -static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - uint32_t tmp; - tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_pras_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; -} - -static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - uint32_t tmp; - tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t data) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, - hri_hmatrixb_prbs_reg_t mask) -{ - HMATRIXB_CRITICAL_SECTION_ENTER(); - ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; - HMATRIXB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_HMATRIXB_D51_H_INCLUDED */ -#endif /* _SAMD51_HMATRIXB_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_i2s_d51.h b/atmel-samd/asf4/samd51/hri/hri_i2s_d51.h deleted file mode 100644 index e03430339..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_i2s_d51.h +++ /dev/null @@ -1,3107 +0,0 @@ -/** - * \file - * - * \brief SAM I2S - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_I2S_COMPONENT_ -#ifndef _HRI_I2S_D51_H_INCLUDED_ -#define _HRI_I2S_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_I2S_CRITICAL_SECTIONS) -#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define I2S_CRITICAL_SECTION_ENTER() -#define I2S_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_i2s_intenset_reg_t; -typedef uint16_t hri_i2s_intflag_reg_t; -typedef uint16_t hri_i2s_syncbusy_reg_t; -typedef uint32_t hri_i2s_clkctrl_reg_t; -typedef uint32_t hri_i2s_rxctrl_reg_t; -typedef uint32_t hri_i2s_rxdata_reg_t; -typedef uint32_t hri_i2s_txctrl_reg_t; -typedef uint32_t hri_i2s_txdata_reg_t; -typedef uint8_t hri_i2s_ctrla_reg_t; - -static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg) -{ - while (((I2s *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg) -{ - return ((I2s *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; -} - -static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos; -} - -static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; - } -} - -static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; -} - -static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; -} - -static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos; -} - -static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; - } -} - -static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; -} - -static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; -} - -static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos; -} - -static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; - } -} - -static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; -} - -static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; -} - -static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos; -} - -static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; - } -} - -static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; -} - -static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; -} - -static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos; -} - -static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; - } -} - -static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; -} - -static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; -} - -static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos; -} - -static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; - } -} - -static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; -} - -static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; -} - -static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos; -} - -static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; - } -} - -static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; -} - -static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; -} - -static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos; -} - -static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; - } else { - ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; - } -} - -static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; -} - -static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - ((I2s *)hw)->INTENSET.reg = mask; -} - -static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw) -{ - return ((I2s *)hw)->INTENSET.reg; -} - -static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data) -{ - ((I2s *)hw)->INTENSET.reg = data; - ((I2s *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) -{ - ((I2s *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; -} - -static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; -} - -static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; -} - -static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; -} - -static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; -} - -static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; -} - -static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; -} - -static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; -} - -static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; -} - -static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; -} - -static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; -} - -static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; -} - -static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; -} - -static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; -} - -static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; -} - -static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; -} - -static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; -} - -static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw) -{ - return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; -} - -static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw) -{ - ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; -} - -static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw) -{ - return ((I2s *)hw)->INTFLAG.reg; -} - -static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) -{ - ((I2s *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXDATA.reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_ENABLE; - tmp |= value << I2S_CTRLA_ENABLE_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_CKEN0; - tmp |= value << I2S_CTRLA_CKEN0_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_CKEN1; - tmp |= value << I2S_CTRLA_CKEN1_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_TXEN; - tmp |= value << I2S_CTRLA_TXEN_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw) -{ - uint8_t tmp; - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= ~I2S_CTRLA_RXEN; - tmp |= value << I2S_CTRLA_RXEN_Pos; - ((I2s *)hw)->CTRLA.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - hri_i2s_wait_for_sync(hw, - I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_CKEN0 | I2S_SYNCBUSY_CKEN1 - | I2S_SYNCBUSY_TXEN - | I2S_SYNCBUSY_RXEN); - ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((I2s *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CTRLA.reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw) -{ - return ((I2s *)hw)->CTRLA.reg; -} - -static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_BITDELAY; - tmp |= value << I2S_CLKCTRL_BITDELAY_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSSEL; - tmp |= value << I2S_CLKCTRL_FSSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSINV; - tmp |= value << I2S_CLKCTRL_FSINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSOUTINV; - tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SCKSEL; - tmp |= value << I2S_CLKCTRL_SCKSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SCKOUTINV; - tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKSEL; - tmp |= value << I2S_CLKCTRL_MCKSEL_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKEN; - tmp |= value << I2S_CLKCTRL_MCKEN_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKOUTINV; - tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos; - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk; - tmp |= I2S_CLKCTRL_SLOTSIZE(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk; - tmp |= I2S_CLKCTRL_NBSLOTS(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk; - tmp |= I2S_CLKCTRL_FSWIDTH(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKDIV_Msk; - tmp |= I2S_CLKCTRL_MCKDIV(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk; - tmp |= I2S_CLKCTRL_MCKOUTDIV(data); - ((I2s *)hw)->CLKCTRL[index].reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos; - return tmp; -} - -static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index, - hri_i2s_clkctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->CLKCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->CLKCTRL[index].reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index) -{ - return ((I2s *)hw)->CLKCTRL[index].reg; -} - -static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_TXSAME; - tmp |= value << I2S_TXCTRL_TXSAME_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTADJ; - tmp |= value << I2S_TXCTRL_SLOTADJ_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_WORDADJ; - tmp |= value << I2S_TXCTRL_WORDADJ_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_BITREV; - tmp |= value << I2S_TXCTRL_BITREV_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS0; - tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS1; - tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS2; - tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS3; - tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS4; - tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS5; - tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS6; - tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_SLOTDIS7; - tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_MONO; - tmp |= value << I2S_TXCTRL_MONO_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_DMA; - tmp |= value << I2S_TXCTRL_DMA_Pos; - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk; - tmp |= I2S_TXCTRL_TXDEFAULT(data); - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos; - return tmp; -} - -static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_DATASIZE_Msk; - tmp |= I2S_TXCTRL_DATASIZE(data); - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= ~I2S_TXCTRL_EXTEND_Msk; - tmp |= I2S_TXCTRL_EXTEND(data); - ((I2s *)hw)->TXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->TXCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->TXCTRL.reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw) -{ - return ((I2s *)hw)->TXCTRL.reg; -} - -static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_CLKSEL; - tmp |= value << I2S_RXCTRL_CLKSEL_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTADJ; - tmp |= value << I2S_RXCTRL_SLOTADJ_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_WORDADJ; - tmp |= value << I2S_RXCTRL_WORDADJ_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_BITREV; - tmp |= value << I2S_RXCTRL_BITREV_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS0; - tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS1; - tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS2; - tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS3; - tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS4; - tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS5; - tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS6; - tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SLOTDIS7; - tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_MONO; - tmp |= value << I2S_RXCTRL_MONO_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_DMA; - tmp |= value << I2S_RXCTRL_DMA_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos; - return (bool)tmp; -} - -static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_RXLOOP; - tmp |= value << I2S_RXCTRL_RXLOOP_Pos; - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_SERMODE_Msk; - tmp |= I2S_RXCTRL_SERMODE(data); - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos; - return tmp; -} - -static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_DATASIZE_Msk; - tmp |= I2S_RXCTRL_DATASIZE(data); - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos; - return tmp; -} - -static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - uint32_t tmp; - I2S_CRITICAL_SECTION_ENTER(); - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= ~I2S_RXCTRL_EXTEND_Msk; - tmp |= I2S_RXCTRL_EXTEND(data); - ((I2s *)hw)->RXCTRL.reg = tmp; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask); - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos; - return tmp; -} - -static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg |= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg = data; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg &= ~mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) -{ - I2S_CRITICAL_SECTION_ENTER(); - ((I2s *)hw)->RXCTRL.reg ^= mask; - I2S_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw) -{ - return ((I2s *)hw)->RXCTRL.reg; -} - -static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos; -} - -static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw) -{ - return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos; -} - -static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask) -{ - uint16_t tmp; - tmp = ((I2s *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw) -{ - return ((I2s *)hw)->SYNCBUSY.reg; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask) -{ - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw) -{ - hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); - return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask) -{ - uint32_t tmp; - tmp = ((I2s *)hw)->RXDATA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw) -{ - return ((I2s *)hw)->RXDATA.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_I2S_D51_H_INCLUDED */ -#endif /* _SAMD51_I2S_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_icm_d51.h b/atmel-samd/asf4/samd51/hri/hri_icm_d51.h deleted file mode 100644 index ce434a275..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_icm_d51.h +++ /dev/null @@ -1,770 +0,0 @@ -/** - * \file - * - * \brief SAM ICM - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_ICM_COMPONENT_ -#ifndef _HRI_ICM_D51_H_INCLUDED_ -#define _HRI_ICM_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_ICM_CRITICAL_SECTIONS) -#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define ICM_CRITICAL_SECTION_ENTER() -#define ICM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_icm_cfg_reg_t; -typedef uint32_t hri_icm_ctrl_reg_t; -typedef uint32_t hri_icm_dscr_reg_t; -typedef uint32_t hri_icm_hash_reg_t; -typedef uint32_t hri_icm_imr_reg_t; -typedef uint32_t hri_icm_isr_reg_t; -typedef uint32_t hri_icm_sr_reg_t; -typedef uint32_t hri_icm_uasr_reg_t; -typedef uint32_t hri_icm_uihval_reg_t; -typedef uint32_t hri_icmdescriptor_raddr_reg_t; -typedef uint32_t hri_icmdescriptor_rcfg_reg_t; -typedef uint32_t hri_icmdescriptor_rctrl_reg_t; -typedef uint32_t hri_icmdescriptor_rnext_reg_t; - -static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const hw, - hri_icmdescriptor_raddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RADDR.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RADDR.reg; -} - -static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const hw, - hri_icmdescriptor_rcfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCFG.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RCFG.reg; -} - -static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const hw, - hri_icmdescriptor_rctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RCTRL.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RCTRL.reg; -} - -static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const hw, - hri_icmdescriptor_rnext_reg_t mask) -{ - uint32_t tmp; - tmp = ((IcmDescriptor *)hw)->RNEXT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((IcmDescriptor *)hw)->RNEXT.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw) -{ - return ((IcmDescriptor *)hw)->RNEXT.reg; -} - -static inline void hri_icm_set_IMR_URAD_bit(const void *const hw) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_URAD; -} - -static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw) -{ - return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos; -} - -static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; - } else { - ((Icm *)hw)->IER.reg = ICM_IMR_URAD; - } -} - -static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; -} - -static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data); -} - -static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask); -} - -static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data); -} - -static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask); -} - -static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data); -} - -static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask); -} - -static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RWC(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data); -} - -static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask); -} - -static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_REC(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_REC(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data); -} - -static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask); -} - -static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask); -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos; - return tmp; -} - -static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = ICM_IMR_RSU(data); - ((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data); -} - -static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask); -} - -static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IER.reg = mask; -} - -static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->IMR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw) -{ - return ((Icm *)hw)->IMR.reg; -} - -static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data) -{ - ((Icm *)hw)->IER.reg = data; - ((Icm *)hw)->IDR.reg = ~data; -} - -static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) -{ - ((Icm *)hw)->IDR.reg = mask; -} - -static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CTRL.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->UIHVAL[index].reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->CFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->CFG.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw) -{ - return ((Icm *)hw)->CFG.reg; -} - -static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->DSCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->DSCR.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw) -{ - return ((Icm *)hw)->DSCR.reg; -} - -static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg |= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->HASH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg = data; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg &= ~mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) -{ - ICM_CRITICAL_SECTION_ENTER(); - ((Icm *)hw)->HASH.reg ^= mask; - ICM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw) -{ - return ((Icm *)hw)->HASH.reg; -} - -static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw) -{ - return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos; -} - -static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->SR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw) -{ - return ((Icm *)hw)->SR.reg; -} - -static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw) -{ - return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos; -} - -static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->ISR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw) -{ - return ((Icm *)hw)->ISR.reg; -} - -static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask) -{ - return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos; -} - -static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw) -{ - return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos; -} - -static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Icm *)hw)->UASR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw) -{ - return ((Icm *)hw)->UASR.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_ICM_D51_H_INCLUDED */ -#endif /* _SAMD51_ICM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_mclk_d51.h b/atmel-samd/asf4/samd51/hri/hri_mclk_d51.h deleted file mode 100644 index 59e769882..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_mclk_d51.h +++ /dev/null @@ -1,3445 +0,0 @@ -/** - * \file - * - * \brief SAM MCLK - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_MCLK_COMPONENT_ -#ifndef _HRI_MCLK_D51_H_INCLUDED_ -#define _HRI_MCLK_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) -#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define MCLK_CRITICAL_SECTION_ENTER() -#define MCLK_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_mclk_ahbmask_reg_t; -typedef uint32_t hri_mclk_apbamask_reg_t; -typedef uint32_t hri_mclk_apbbmask_reg_t; -typedef uint32_t hri_mclk_apbcmask_reg_t; -typedef uint32_t hri_mclk_apbdmask_reg_t; -typedef uint8_t hri_mclk_cpudiv_reg_t; -typedef uint8_t hri_mclk_hsdiv_reg_t; -typedef uint8_t hri_mclk_intenset_reg_t; -typedef uint8_t hri_mclk_intflag_reg_t; - -static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; -} - -static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; -} - -static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; - } else { - ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; - } -} - -static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; -} - -static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - ((Mclk *)hw)->INTENSET.reg = mask; -} - -static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) -{ - return ((Mclk *)hw)->INTENSET.reg; -} - -static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) -{ - ((Mclk *)hw)->INTENSET.reg = data; - ((Mclk *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) -{ - ((Mclk *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; -} - -static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; -} - -static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) -{ - return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; -} - -static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) -{ - ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; -} - -static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) -{ - return ((Mclk *)hw)->INTFLAG.reg; -} - -static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) -{ - ((Mclk *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos; - return tmp; -} - -static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) -{ - uint8_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp &= ~MCLK_CPUDIV_DIV_Msk; - tmp |= MCLK_CPUDIV_DIV(data); - ((Mclk *)hw)->CPUDIV.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask); - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos; - return tmp; -} - -static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->CPUDIV.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->CPUDIV.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) -{ - return ((Mclk *)hw)->CPUDIV.reg; -} - -static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB0; - tmp |= value << MCLK_AHBMASK_HPB0_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB1; - tmp |= value << MCLK_AHBMASK_HPB1_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB2; - tmp |= value << MCLK_AHBMASK_HPB2_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HPB3; - tmp |= value << MCLK_AHBMASK_HPB3_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_DSU; - tmp |= value << MCLK_AHBMASK_DSU_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HMATRIX; - tmp |= value << MCLK_AHBMASK_HMATRIX_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_NVMCTRL; - tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_HSRAM; - tmp |= value << MCLK_AHBMASK_HSRAM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_CMCC; - tmp |= value << MCLK_AHBMASK_CMCC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_DMAC; - tmp |= value << MCLK_AHBMASK_DMAC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_USB; - tmp |= value << MCLK_AHBMASK_USB_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_BKUPRAM; - tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_PAC; - tmp |= value << MCLK_AHBMASK_PAC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_QSPI; - tmp |= value << MCLK_AHBMASK_QSPI_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_SDHC0; - tmp |= value << MCLK_AHBMASK_SDHC0_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_SDHC1; - tmp |= value << MCLK_AHBMASK_SDHC1_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_ICM; - tmp |= value << MCLK_AHBMASK_ICM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_PUKCC; - tmp |= value << MCLK_AHBMASK_PUKCC_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_QSPI_2X; - tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; - tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE; - tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos; - ((Mclk *)hw)->AHBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->AHBMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->AHBMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->AHBMASK.reg; -} - -static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_PAC; - tmp |= value << MCLK_APBAMASK_PAC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_PM; - tmp |= value << MCLK_APBAMASK_PM_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_MCLK; - tmp |= value << MCLK_APBAMASK_MCLK_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_RSTC; - tmp |= value << MCLK_APBAMASK_RSTC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_OSCCTRL; - tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_OSC32KCTRL; - tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_SUPC; - tmp |= value << MCLK_APBAMASK_SUPC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_GCLK; - tmp |= value << MCLK_APBAMASK_GCLK_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_WDT; - tmp |= value << MCLK_APBAMASK_WDT_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_RTC; - tmp |= value << MCLK_APBAMASK_RTC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_EIC; - tmp |= value << MCLK_APBAMASK_EIC_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_FREQM; - tmp |= value << MCLK_APBAMASK_FREQM_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_SERCOM0; - tmp |= value << MCLK_APBAMASK_SERCOM0_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_SERCOM1; - tmp |= value << MCLK_APBAMASK_SERCOM1_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_TC0; - tmp |= value << MCLK_APBAMASK_TC0_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= ~MCLK_APBAMASK_TC1; - tmp |= value << MCLK_APBAMASK_TC1_Pos; - ((Mclk *)hw)->APBAMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBAMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBAMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBAMASK.reg; -} - -static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_USB; - tmp |= value << MCLK_APBBMASK_USB_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_DSU; - tmp |= value << MCLK_APBBMASK_DSU_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_NVMCTRL; - tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_PORT; - tmp |= value << MCLK_APBBMASK_PORT_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_HMATRIX; - tmp |= value << MCLK_APBBMASK_HMATRIX_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_EVSYS; - tmp |= value << MCLK_APBBMASK_EVSYS_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_SERCOM2; - tmp |= value << MCLK_APBBMASK_SERCOM2_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_SERCOM3; - tmp |= value << MCLK_APBBMASK_SERCOM3_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TCC0; - tmp |= value << MCLK_APBBMASK_TCC0_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TCC1; - tmp |= value << MCLK_APBBMASK_TCC1_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TC2; - tmp |= value << MCLK_APBBMASK_TC2_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TC3; - tmp |= value << MCLK_APBBMASK_TC3_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_TAL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TAL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_TAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_TAL) >> MCLK_APBBMASK_TAL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_TAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_TAL; - tmp |= value << MCLK_APBBMASK_TAL_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_TAL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TAL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_TAL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TAL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= ~MCLK_APBBMASK_RAMECC; - tmp |= value << MCLK_APBBMASK_RAMECC_Pos; - ((Mclk *)hw)->APBBMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBBMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBBMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBBMASK.reg; -} - -static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TCC2; - tmp |= value << MCLK_APBCMASK_TCC2_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TCC3; - tmp |= value << MCLK_APBCMASK_TCC3_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TC4; - tmp |= value << MCLK_APBCMASK_TC4_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TC5; - tmp |= value << MCLK_APBCMASK_TC5_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_PDEC; - tmp |= value << MCLK_APBCMASK_PDEC_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_AC; - tmp |= value << MCLK_APBCMASK_AC_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_AES; - tmp |= value << MCLK_APBCMASK_AES_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_TRNG; - tmp |= value << MCLK_APBCMASK_TRNG_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_ICM; - tmp |= value << MCLK_APBCMASK_ICM_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_QSPI; - tmp |= value << MCLK_APBCMASK_QSPI_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= ~MCLK_APBCMASK_CCL; - tmp |= value << MCLK_APBCMASK_CCL_Pos; - ((Mclk *)hw)->APBCMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBCMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBCMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBCMASK.reg; -} - -static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM4; - tmp |= value << MCLK_APBDMASK_SERCOM4_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM5; - tmp |= value << MCLK_APBDMASK_SERCOM5_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM6; - tmp |= value << MCLK_APBDMASK_SERCOM6_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_SERCOM7; - tmp |= value << MCLK_APBDMASK_SERCOM7_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_TCC4; - tmp |= value << MCLK_APBDMASK_TCC4_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_TC6; - tmp |= value << MCLK_APBDMASK_TC6_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_TC7; - tmp |= value << MCLK_APBDMASK_TC7_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_ADC0; - tmp |= value << MCLK_APBDMASK_ADC0_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_ADC1; - tmp |= value << MCLK_APBDMASK_ADC1_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_DAC; - tmp |= value << MCLK_APBDMASK_DAC_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_I2S; - tmp |= value << MCLK_APBDMASK_I2S_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos; - return (bool)tmp; -} - -static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - MCLK_CRITICAL_SECTION_ENTER(); - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= ~MCLK_APBDMASK_PCC; - tmp |= value << MCLK_APBDMASK_PCC_Pos; - ((Mclk *)hw)->APBDMASK.reg = tmp; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg |= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Mclk *)hw)->APBDMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg = data; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg &= ~mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) -{ - MCLK_CRITICAL_SECTION_ENTER(); - ((Mclk *)hw)->APBDMASK.reg ^= mask; - MCLK_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw) -{ - return ((Mclk *)hw)->APBDMASK.reg; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask) -{ - return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw) -{ - return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask) -{ - uint8_t tmp; - tmp = ((Mclk *)hw)->HSDIV.reg; - tmp &= mask; - return tmp; -} - -static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw) -{ - return ((Mclk *)hw)->HSDIV.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_MCLK_D51_H_INCLUDED */ -#endif /* _SAMD51_MCLK_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_nvmctrl_d51.h b/atmel-samd/asf4/samd51/hri/hri_nvmctrl_d51.h deleted file mode 100644 index 94f2e9b7e..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_nvmctrl_d51.h +++ /dev/null @@ -1,1627 +0,0 @@ -/** - * \file - * - * \brief SAM NVMCTRL - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_NVMCTRL_COMPONENT_ -#ifndef _HRI_NVMCTRL_D51_H_INCLUDED_ -#define _HRI_NVMCTRL_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) -#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define NVMCTRL_CRITICAL_SECTION_ENTER() -#define NVMCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_nvmctrl_ctrla_reg_t; -typedef uint16_t hri_nvmctrl_ctrlb_reg_t; -typedef uint16_t hri_nvmctrl_intenset_reg_t; -typedef uint16_t hri_nvmctrl_intflag_reg_t; -typedef uint16_t hri_nvmctrl_status_reg_t; -typedef uint32_t hri_nvmctrl_addr_reg_t; -typedef uint32_t hri_nvmctrl_eccerr_reg_t; -typedef uint32_t hri_nvmctrl_param_reg_t; -typedef uint32_t hri_nvmctrl_pbldata_reg_t; -typedef uint32_t hri_nvmctrl_runlock_reg_t; -typedef uint32_t hri_nvmctrl_seestat_reg_t; -typedef uint8_t hri_nvmctrl_dbgctrl_reg_t; -typedef uint8_t hri_nvmctrl_seecfg_reg_t; - -static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; -} - -static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; -} - -static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; -} - -static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; -} - -static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; -} - -static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; -} - -static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; -} - -static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; -} - -static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; -} - -static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; -} - -static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; -} - -static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; - } -} - -static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; -} - -static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; -} - -static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; - } -} - -static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; -} - -static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; -} - -static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; -} - -static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; -} - -static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; -} - -static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; -} - -static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; -} - -static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; -} - -static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos; -} - -static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; - } else { - ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; - } -} - -static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; -} - -static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) -{ - ((Nvmctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, - hri_nvmctrl_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->INTENSET.reg; -} - -static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) -{ - ((Nvmctrl *)hw)->INTENSET.reg = data; - ((Nvmctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) -{ - ((Nvmctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; -} - -static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; -} - -static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; -} - -static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; -} - -static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; -} - -static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; -} - -static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; -} - -static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; -} - -static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; -} - -static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; -} - -static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; -} - -static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; -} - -static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; -} - -static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; -} - -static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; -} - -static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; -} - -static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, - hri_nvmctrl_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) -{ - ((Nvmctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLB.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_AUTOWS; - tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_SUSPEN; - tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_AHBNS0; - tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_AHBNS1; - tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_CACHEDIS0; - tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_CACHEDIS1; - tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos; - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_WMODE_Msk; - tmp |= NVMCTRL_CTRLA_WMODE(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_PRM_Msk; - tmp |= NVMCTRL_CTRLA_PRM(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - uint16_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= ~NVMCTRL_CTRLA_RWS_Msk; - tmp |= NVMCTRL_CTRLA_RWS(data); - ((Nvmctrl *)hw)->CTRLA.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->CTRLA.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->CTRLA.reg; -} - -static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) -{ - uint32_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp &= ~NVMCTRL_ADDR_ADDR_Msk; - tmp |= NVMCTRL_ADDR_ADDR(data); - ((Nvmctrl *)hw)->ADDR.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->ADDR.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->ADDR.reg; -} - -static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp &= ~NVMCTRL_DBGCTRL_ECCDIS; - tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos; - ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp &= ~NVMCTRL_DBGCTRL_ECCELOG; - tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos; - ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const hw, - hri_nvmctrl_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->DBGCTRL.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->DBGCTRL.reg; -} - -static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp &= ~NVMCTRL_SEECFG_WMODE; - tmp |= value << NVMCTRL_SEECFG_WMODE_Pos; - ((Nvmctrl *)hw)->SEECFG.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos; - return (bool)tmp; -} - -static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - NVMCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp &= ~NVMCTRL_SEECFG_APRDIS; - tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos; - ((Nvmctrl *)hw)->SEECFG.reg = tmp; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg |= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Nvmctrl *)hw)->SEECFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg = data; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg &= ~mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) -{ - NVMCTRL_CRITICAL_SECTION_ENTER(); - ((Nvmctrl *)hw)->SEECFG.reg ^= mask; - NVMCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->SEECFG.reg; -} - -static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PARAM.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->PARAM.reg; -} - -static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos; -} - -static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const hw, - hri_nvmctrl_status_reg_t mask) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Nvmctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->STATUS.reg; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const hw, - hri_nvmctrl_runlock_reg_t mask) -{ - return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const hw, - hri_nvmctrl_runlock_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->RUNLOCK.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->RUNLOCK.reg; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index, - hri_nvmctrl_pbldata_reg_t mask) -{ - return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index) -{ - return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index, - hri_nvmctrl_pbldata_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index) -{ - return ((Nvmctrl *)hw)->PBLDATA[index].reg; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const hw, - hri_nvmctrl_eccerr_reg_t mask) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const hw, - hri_nvmctrl_eccerr_reg_t mask) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const hw, - hri_nvmctrl_eccerr_reg_t mask) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->ECCERR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->ECCERR.reg; -} - -static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos; -} - -static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const hw, - hri_nvmctrl_seestat_reg_t mask) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const hw, - hri_nvmctrl_seestat_reg_t mask) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw) -{ - return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const hw, - hri_nvmctrl_seestat_reg_t mask) -{ - uint32_t tmp; - tmp = ((Nvmctrl *)hw)->SEESTAT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw) -{ - return ((Nvmctrl *)hw)->SEESTAT.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_NVMCTRL_D51_H_INCLUDED */ -#endif /* _SAMD51_NVMCTRL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_osc32kctrl_d51.h b/atmel-samd/asf4/samd51/hri/hri_osc32kctrl_d51.h deleted file mode 100644 index 3d5b853ff..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_osc32kctrl_d51.h +++ /dev/null @@ -1,1208 +0,0 @@ -/** - * \file - * - * \brief SAM OSC32KCTRL - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_OSC32KCTRL_COMPONENT_ -#ifndef _HRI_OSC32KCTRL_D51_H_INCLUDED_ -#define _HRI_OSC32KCTRL_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) -#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define OSC32KCTRL_CRITICAL_SECTION_ENTER() -#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; -typedef uint32_t hri_osc32kctrl_intenset_reg_t; -typedef uint32_t hri_osc32kctrl_intflag_reg_t; -typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; -typedef uint32_t hri_osc32kctrl_status_reg_t; -typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; -typedef uint8_t hri_osc32kctrl_evctrl_reg_t; -typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t; - -static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; - } else { - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; - } -} - -static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; -} - -static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; -} - -static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos; -} - -static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; - } else { - ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; - } -} - -static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; -} - -static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, - hri_osc32kctrl_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->INTENSET.reg; -} - -static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) -{ - ((Osc32kctrl *)hw)->INTENSET.reg = data; - ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; -} - -static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; -} - -static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; -} - -static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; -} - -static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; -} - -static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, - hri_osc32kctrl_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) -{ - ((Osc32kctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, - hri_osc32kctrl_rtcctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; - tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); - ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, - hri_osc32kctrl_rtcctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->RTCCTRL.reg; -} - -static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; - tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; - tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_EN32K; - tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_EN1K; - tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; - tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; - tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; - tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, - hri_osc32kctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; - tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const hw, - hri_osc32kctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) -{ - uint16_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk; - tmp |= OSC32KCTRL_XOSC32K_CGM(data); - ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, - hri_osc32kctrl_xosc32k_reg_t mask) -{ - uint16_t tmp; - tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->XOSC32K.reg; -} - -static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; - tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; - tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; - tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; - ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, - hri_osc32kctrl_cfdctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->CFDCTRL.reg; -} - -static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; - tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; - ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, - hri_osc32kctrl_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->EVCTRL.reg; -} - -static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_EN32K; - tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_EN1K; - tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; - tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, - hri_osc32kctrl_osculp32k_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) -{ - uint32_t tmp; - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; - tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); - ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; - return tmp; -} - -static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, - hri_osc32kctrl_osculp32k_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg = data; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) -{ - OSC32KCTRL_CRITICAL_SECTION_ENTER(); - ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; - OSC32KCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->OSCULP32K.reg; -} - -static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; -} - -static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos; -} - -static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw) -{ - return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos; -} - -static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, - hri_osc32kctrl_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Osc32kctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) -{ - return ((Osc32kctrl *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_OSC32KCTRL_D51_H_INCLUDED */ -#endif /* _SAMD51_OSC32KCTRL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_oscctrl_d51.h b/atmel-samd/asf4/samd51/hri/hri_oscctrl_d51.h deleted file mode 100644 index abb2b47f7..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_oscctrl_d51.h +++ /dev/null @@ -1,4360 +0,0 @@ -/** - * \file - * - * \brief SAM OSCCTRL - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_OSCCTRL_COMPONENT_ -#ifndef _HRI_OSCCTRL_D51_H_INCLUDED_ -#define _HRI_OSCCTRL_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) -#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define OSCCTRL_CRITICAL_SECTION_ENTER() -#define OSCCTRL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_oscctrl_dfllmul_reg_t; -typedef uint32_t hri_oscctrl_dfllval_reg_t; -typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; -typedef uint32_t hri_oscctrl_dpllratio_reg_t; -typedef uint32_t hri_oscctrl_dpllstatus_reg_t; -typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t; -typedef uint32_t hri_oscctrl_intenset_reg_t; -typedef uint32_t hri_oscctrl_intflag_reg_t; -typedef uint32_t hri_oscctrl_status_reg_t; -typedef uint32_t hri_oscctrl_xoscctrl_reg_t; -typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t; -typedef uint32_t hri_oscctrldpll_dpllratio_reg_t; -typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t; -typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t; -typedef uint8_t hri_oscctrl_dfllctrla_reg_t; -typedef uint8_t hri_oscctrl_dfllctrlb_reg_t; -typedef uint8_t hri_oscctrl_dfllsync_reg_t; -typedef uint8_t hri_oscctrl_dpllctrla_reg_t; -typedef uint8_t hri_oscctrl_evctrl_reg_t; -typedef uint8_t hri_oscctrldpll_dpllctrla_reg_t; - -static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; - tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const hw, - hri_oscctrl_dpllctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw) -{ - return ((OscctrlDpll *)hw)->DPLLCTRLA.reg; -} - -static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDR(data); - ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); - ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const hw, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw) -{ - return ((OscctrlDpll *)hw)->DPLLRATIO.reg; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_WUF; - tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; - tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; - tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; - tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DIV(data); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const hw, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw) -{ - return ((OscctrlDpll *)hw)->DPLLCTRLB.reg; -} - -static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) - >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const hw, - hri_oscctrl_dpllsyncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw) -{ - return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; -} - -static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; -} - -static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) -{ - return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const hw, - hri_oscctrl_dpllstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw) -{ - return ((OscctrlDpll *)hw)->DPLLSTATUS.reg; -} - -static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; - tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; -} - -static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t -hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDR(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t -hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; - tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllratio_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_WUF; - tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; - tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; - tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; - tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t -hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; - tmp |= OSCCTRL_DPLLCTRLB_DIV(data); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; -} - -static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) - >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) - >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t -hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; -} - -static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) - >> OSCCTRL_DPLLSTATUS_LOCK_Pos; -} - -static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) - >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_oscctrl_dpllstatus_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; -} - -static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; -} - -static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; -} - -static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; -} - -static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; -} - -static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos; -} - -static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; - } -} - -static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; -} - -static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; -} - -static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; -} - -static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; -} - -static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; -} - -static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; -} - -static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; - } -} - -static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; -} - -static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; -} - -static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; -} - -static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos; -} - -static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; - } else { - ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; - } -} - -static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; -} - -static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) -{ - ((Oscctrl *)hw)->INTENSET.reg = mask; -} - -static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, - hri_oscctrl_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->INTENSET.reg; -} - -static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) -{ - ((Oscctrl *)hw)->INTENSET.reg = data; - ((Oscctrl *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) -{ - ((Oscctrl *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; -} - -static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; -} - -static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; -} - -static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; -} - -static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; -} - -static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; -} - -static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw) -{ - ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; -} - -static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, - hri_oscctrl_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->INTFLAG.reg; -} - -static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) -{ - ((Oscctrl *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp &= ~OSCCTRL_EVCTRL_CFDEO0; - tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos; - ((Oscctrl *)hw)->EVCTRL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp &= ~OSCCTRL_EVCTRL_CFDEO1; - tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos; - ((Oscctrl *)hw)->EVCTRL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->EVCTRL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->EVCTRL.reg; -} - -static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; - tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; - tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; - tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; - tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; - tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_ENALC; - tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; - tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; - tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk; - tmp |= OSCCTRL_XOSCCTRL_IPTAT(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk; - tmp |= OSCCTRL_XOSCCTRL_IMULT(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; - tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk; - tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index, - hri_oscctrl_xoscctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index) -{ - return ((Oscctrl *)hw)->XOSCCTRL[index].reg; -} - -static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE; - tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos; - ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; - tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; - ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; - tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; - ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const hw, - hri_oscctrl_dfllctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLCTRLA.reg; -} - -static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_MODE; - tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_STABLE; - tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_LLAW; - tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM; - tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS; - tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS; - tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC; - tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; - tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; - ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const hw, - hri_oscctrl_dfllctrlb_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLCTRLB.reg; -} - -static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; - tmp |= OSCCTRL_DFLLVAL_FINE(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; - tmp |= OSCCTRL_DFLLVAL_COARSE(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; - tmp |= OSCCTRL_DFLLVAL_DIFF(data); - ((Oscctrl *)hw)->DFLLVAL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, - hri_oscctrl_dfllval_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLVAL.reg; -} - -static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; - tmp |= OSCCTRL_DFLLMUL_MUL(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; - tmp |= OSCCTRL_DFLLMUL_FSTEP(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - uint32_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; - tmp |= OSCCTRL_DFLLMUL_CSTEP(data); - ((Oscctrl *)hw)->DFLLMUL.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; - return tmp; -} - -static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, - hri_oscctrl_dfllmul_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->DFLLMUL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLMUL.reg; -} - -static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_ENABLE; - tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; - tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL; - tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos; - return (bool)tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - OSCCTRL_CRITICAL_SECTION_ENTER(); - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL; - tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos; - ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, - hri_oscctrl_dfllsync_reg_t mask) -{ - uint8_t tmp; - tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg = data; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) -{ - OSCCTRL_CRITICAL_SECTION_ENTER(); - ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; - OSCCTRL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->DFLLSYNC.reg; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos; -} - -static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw) -{ - return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos; -} - -static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Oscctrl *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) -{ - return ((Oscctrl *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_OSCCTRL_D51_H_INCLUDED */ -#endif /* _SAMD51_OSCCTRL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_pac_d51.h b/atmel-samd/asf4/samd51/hri/hri_pac_d51.h deleted file mode 100644 index 6830c5d84..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_pac_d51.h +++ /dev/null @@ -1,1493 +0,0 @@ -/** - * \file - * - * \brief SAM PAC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_PAC_COMPONENT_ -#ifndef _HRI_PAC_D51_H_INCLUDED_ -#define _HRI_PAC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PAC_CRITICAL_SECTIONS) -#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PAC_CRITICAL_SECTION_ENTER() -#define PAC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_pac_intflaga_reg_t; -typedef uint32_t hri_pac_intflagahb_reg_t; -typedef uint32_t hri_pac_intflagb_reg_t; -typedef uint32_t hri_pac_intflagc_reg_t; -typedef uint32_t hri_pac_intflagd_reg_t; -typedef uint32_t hri_pac_statusa_reg_t; -typedef uint32_t hri_pac_statusb_reg_t; -typedef uint32_t hri_pac_statusc_reg_t; -typedef uint32_t hri_pac_statusd_reg_t; -typedef uint32_t hri_pac_wrctrl_reg_t; -typedef uint8_t hri_pac_evctrl_reg_t; -typedef uint8_t hri_pac_intenset_reg_t; - -static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) -{ - ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; -} - -static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; -} - -static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; - } else { - ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; - } -} - -static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; -} - -static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - ((Pac *)hw)->INTENSET.reg = mask; -} - -static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) -{ - return ((Pac *)hw)->INTENSET.reg; -} - -static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) -{ - ((Pac *)hw)->INTENSET.reg = data; - ((Pac *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) -{ - ((Pac *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; -} - -static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT; -} - -static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR; -} - -static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; -} - -static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3; -} - -static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC; -} - -static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0; -} - -static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1; -} - -static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI; -} - -static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos; -} - -static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM; -} - -static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGAHB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGAHB.reg; -} - -static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) -{ - ((Pac *)hw)->INTFLAGAHB.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; -} - -static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; -} - -static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; -} - -static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; -} - -static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; -} - -static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; -} - -static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; -} - -static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; -} - -static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; -} - -static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; -} - -static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; -} - -static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; -} - -static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0; -} - -static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1; -} - -static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0; -} - -static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1; -} - -static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGA.reg; -} - -static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) -{ - ((Pac *)hw)->INTFLAGA.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; -} - -static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; -} - -static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; -} - -static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC; -} - -static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; -} - -static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; -} - -static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX; -} - -static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS; -} - -static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2; -} - -static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3; -} - -static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0; -} - -static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1; -} - -static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2; -} - -static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3; -} - -static inline bool hri_pac_get_INTFLAGB_TAL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TAL) >> PAC_INTFLAGB_TAL_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_TAL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TAL; -} - -static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos; -} - -static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC; -} - -static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGB.reg; -} - -static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) -{ - ((Pac *)hw)->INTFLAGB.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; -} - -static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3; -} - -static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4; -} - -static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5; -} - -static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC; -} - -static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; -} - -static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; -} - -static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; -} - -static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM; -} - -static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC; -} - -static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI; -} - -static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; -} - -static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; -} - -static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGC.reg; -} - -static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) -{ - ((Pac *)hw)->INTFLAGC.reg = mask; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6; -} - -static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7; -} - -static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4; -} - -static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6; -} - -static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7; -} - -static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0; -} - -static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1; -} - -static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC; -} - -static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S; -} - -static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw) -{ - return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos; -} - -static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw) -{ - ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC; -} - -static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->INTFLAGD.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw) -{ - return ((Pac *)hw)->INTFLAGD.reg; -} - -static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) -{ - ((Pac *)hw)->INTFLAGD.reg = mask; -} - -static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - uint32_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= ~PAC_WRCTRL_PERID_Msk; - tmp |= PAC_WRCTRL_PERID(data); - ((Pac *)hw)->WRCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; - return tmp; -} - -static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - uint32_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= ~PAC_WRCTRL_KEY_Msk; - tmp |= PAC_WRCTRL_KEY(data); - ((Pac *)hw)->WRCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; - return tmp; -} - -static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg |= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->WRCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg = data; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg &= ~mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->WRCTRL.reg ^= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) -{ - return ((Pac *)hw)->WRCTRL.reg; -} - -static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; - return (bool)tmp; -} - -static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PAC_CRITICAL_SECTION_ENTER(); - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp &= ~PAC_EVCTRL_ERREO; - tmp |= value << PAC_EVCTRL_ERREO_Pos; - ((Pac *)hw)->EVCTRL.reg = tmp; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg |= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pac *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg = data; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg &= ~mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) -{ - PAC_CRITICAL_SECTION_ENTER(); - ((Pac *)hw)->EVCTRL.reg ^= mask; - PAC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) -{ - return ((Pac *)hw)->EVCTRL.reg; -} - -static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; -} - -static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; -} - -static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; -} - -static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; -} - -static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; -} - -static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; -} - -static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; -} - -static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; -} - -static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; -} - -static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; -} - -static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos; -} - -static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos; -} - -static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos; -} - -static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos; -} - -static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSA.reg; -} - -static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; -} - -static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; -} - -static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; -} - -static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos; -} - -static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; -} - -static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; -} - -static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos; -} - -static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos; -} - -static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos; -} - -static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos; -} - -static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos; -} - -static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos; -} - -static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos; -} - -static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos; -} - -static inline bool hri_pac_get_STATUSB_TAL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TAL) >> PAC_STATUSB_TAL_Pos; -} - -static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos; -} - -static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSB.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSB.reg; -} - -static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; -} - -static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos; -} - -static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos; -} - -static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos; -} - -static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos; -} - -static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; -} - -static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; -} - -static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; -} - -static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos; -} - -static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos; -} - -static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos; -} - -static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; -} - -static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSC.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSC.reg; -} - -static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos; -} - -static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos; -} - -static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos; -} - -static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos; -} - -static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos; -} - -static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos; -} - -static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos; -} - -static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos; -} - -static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos; -} - -static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos; -} - -static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos; -} - -static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw) -{ - return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos; -} - -static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pac *)hw)->STATUSD.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw) -{ - return ((Pac *)hw)->STATUSD.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PAC_D51_H_INCLUDED */ -#endif /* _SAMD51_PAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_pcc_d51.h b/atmel-samd/asf4/samd51/hri/hri_pcc_d51.h deleted file mode 100644 index 334e116d4..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_pcc_d51.h +++ /dev/null @@ -1,307 +0,0 @@ -/** - * \file - * - * \brief SAM PCC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_PCC_COMPONENT_ -#ifndef _HRI_PCC_D51_H_INCLUDED_ -#define _HRI_PCC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PCC_CRITICAL_SECTIONS) -#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PCC_CRITICAL_SECTION_ENTER() -#define PCC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_pcc_imr_reg_t; -typedef uint32_t hri_pcc_isr_reg_t; -typedef uint32_t hri_pcc_mr_reg_t; -typedef uint32_t hri_pcc_rhr_reg_t; -typedef uint32_t hri_pcc_wpmr_reg_t; -typedef uint32_t hri_pcc_wpsr_reg_t; - -static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw) -{ - ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; -} - -static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw) -{ - return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos; -} - -static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; - } else { - ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; - } -} - -static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw) -{ - ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; -} - -static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw) -{ - ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; -} - -static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw) -{ - return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos; -} - -static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; - } else { - ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; - } -} - -static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw) -{ - ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; -} - -static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) -{ - ((Pcc *)hw)->IER.reg = mask; -} - -static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->IMR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw) -{ - return ((Pcc *)hw)->IMR.reg; -} - -static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data) -{ - ((Pcc *)hw)->IER.reg = data; - ((Pcc *)hw)->IDR.reg = ~data; -} - -static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) -{ - ((Pcc *)hw)->IDR.reg = mask; -} - -static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg |= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->MR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg = data; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg &= ~mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->MR.reg ^= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw) -{ - return ((Pcc *)hw)->MR.reg; -} - -static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg |= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->WPMR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg = data; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg &= ~mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) -{ - PCC_CRITICAL_SECTION_ENTER(); - ((Pcc *)hw)->WPMR.reg ^= mask; - PCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw) -{ - return ((Pcc *)hw)->WPMR.reg; -} - -static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw) -{ - return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos; -} - -static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw) -{ - return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos; -} - -static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->ISR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw) -{ - return ((Pcc *)hw)->ISR.reg; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask) -{ - return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw) -{ - return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->RHR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw) -{ - return ((Pcc *)hw)->RHR.reg; -} - -static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw) -{ - return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask) -{ - return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw) -{ - return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pcc *)hw)->WPSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw) -{ - return ((Pcc *)hw)->WPSR.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PCC_D51_H_INCLUDED */ -#endif /* _SAMD51_PCC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_pdec_d51.h b/atmel-samd/asf4/samd51/hri/hri_pdec_d51.h deleted file mode 100644 index afaa30f20..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_pdec_d51.h +++ /dev/null @@ -1,2642 +0,0 @@ -/** - * \file - * - * \brief SAM PDEC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_PDEC_COMPONENT_ -#ifndef _HRI_PDEC_D51_H_INCLUDED_ -#define _HRI_PDEC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PDEC_CRITICAL_SECTIONS) -#define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PDEC_CRITICAL_SECTION_ENTER() -#define PDEC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_pdec_evctrl_reg_t; -typedef uint16_t hri_pdec_status_reg_t; -typedef uint32_t hri_pdec_cc_reg_t; -typedef uint32_t hri_pdec_ccbuf_reg_t; -typedef uint32_t hri_pdec_count_reg_t; -typedef uint32_t hri_pdec_ctrla_reg_t; -typedef uint32_t hri_pdec_syncbusy_reg_t; -typedef uint8_t hri_pdec_ctrlbset_reg_t; -typedef uint8_t hri_pdec_dbgctrl_reg_t; -typedef uint8_t hri_pdec_filter_reg_t; -typedef uint8_t hri_pdec_filterbuf_reg_t; -typedef uint8_t hri_pdec_intenset_reg_t; -typedef uint8_t hri_pdec_intflag_reg_t; -typedef uint8_t hri_pdec_presc_reg_t; -typedef uint8_t hri_pdec_prescbuf_reg_t; - -static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg) -{ - while (((Pdec *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg) -{ - return ((Pdec *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; -} - -static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; - } else { - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; - } -} - -static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; -} - -static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask); -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->CTRLBSET.reg; - tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->CTRLBSET.reg; - tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data) -{ - ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data); - ((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data); -} - -static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask); -} - -static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBSET.reg = mask; -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw) -{ - return ((Pdec *)hw)->CTRLBSET.reg; -} - -static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data) -{ - ((Pdec *)hw)->CTRLBSET.reg = data; - ((Pdec *)hw)->CTRLBCLR.reg = ~data; -} - -static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) -{ - ((Pdec *)hw)->CTRLBCLR.reg = mask; -} - -static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; -} - -static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos; -} - -static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; - } -} - -static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; -} - -static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; -} - -static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos; -} - -static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; - } -} - -static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; -} - -static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; -} - -static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos; -} - -static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; - } -} - -static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; -} - -static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; -} - -static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos; -} - -static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; - } -} - -static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; -} - -static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; -} - -static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos; -} - -static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; - } -} - -static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; -} - -static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; -} - -static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos; -} - -static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; - } else { - ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; - } -} - -static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; -} - -static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) -{ - ((Pdec *)hw)->INTENSET.reg = mask; -} - -static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw) -{ - return ((Pdec *)hw)->INTENSET.reg; -} - -static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data) -{ - ((Pdec *)hw)->INTENSET.reg = data; - ((Pdec *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) -{ - ((Pdec *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; -} - -static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; -} - -static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; -} - -static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; -} - -static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; -} - -static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; -} - -static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; -} - -static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; -} - -static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; -} - -static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; -} - -static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; -} - -static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; -} - -static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; -} - -static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; -} - -static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; -} - -static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; -} - -static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; -} - -static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; -} - -static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; -} - -static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw) -{ - return ((Pdec *)hw)->INTFLAG.reg; -} - -static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) -{ - ((Pdec *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_ENABLE; - tmp |= value << PDEC_CTRLA_ENABLE_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_RUNSTDBY; - tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_ALOCK; - tmp |= value << PDEC_CTRLA_ALOCK_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_SWAP; - tmp |= value << PDEC_CTRLA_SWAP_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PEREN; - tmp |= value << PDEC_CTRLA_PEREN_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINEN0; - tmp |= value << PDEC_CTRLA_PINEN0_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINEN1; - tmp |= value << PDEC_CTRLA_PINEN1_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINEN2; - tmp |= value << PDEC_CTRLA_PINEN2_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINVEN0; - tmp |= value << PDEC_CTRLA_PINVEN0_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINVEN1; - tmp |= value << PDEC_CTRLA_PINVEN1_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_PINVEN2; - tmp |= value << PDEC_CTRLA_PINVEN2_Pos; - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_MODE_Msk; - tmp |= PDEC_CTRLA_MODE(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_CONF_Msk; - tmp |= PDEC_CTRLA_CONF(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_ANGULAR_Msk; - tmp |= PDEC_CTRLA_ANGULAR(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= ~PDEC_CTRLA_MAXCMP_Msk; - tmp |= PDEC_CTRLA_MAXCMP(data); - ((Pdec *)hw)->CTRLA.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos; - return tmp; -} - -static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CTRLA.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw) -{ - return ((Pdec *)hw)->CTRLA.reg; -} - -static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_OVFEO; - tmp |= value << PDEC_EVCTRL_OVFEO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_ERREO; - tmp |= value << PDEC_EVCTRL_ERREO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_DIREO; - tmp |= value << PDEC_EVCTRL_DIREO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_VLCEO; - tmp |= value << PDEC_EVCTRL_VLCEO_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_MCEO0; - tmp |= value << PDEC_EVCTRL_MCEO0_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_MCEO1; - tmp |= value << PDEC_EVCTRL_MCEO1_Pos; - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_EVACT_Msk; - tmp |= PDEC_EVCTRL_EVACT(data); - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_EVINV_Msk; - tmp |= PDEC_EVCTRL_EVINV(data); - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos; - return tmp; -} - -static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - uint16_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= ~PDEC_EVCTRL_EVEI_Msk; - tmp |= PDEC_EVCTRL_EVEI(data); - ((Pdec *)hw)->EVCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos; - return tmp; -} - -static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->EVCTRL.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw) -{ - return ((Pdec *)hw)->EVCTRL.reg; -} - -static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->DBGCTRL.reg; - tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - tmp = ((Pdec *)hw)->DBGCTRL.reg; - tmp &= ~PDEC_DBGCTRL_DBGRUN; - tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos; - ((Pdec *)hw)->DBGCTRL.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->DBGCTRL.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw) -{ - return ((Pdec *)hw)->DBGCTRL.reg; -} - -static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - ((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - tmp = ((Pdec *)hw)->PRESC.reg; - tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos; - return tmp; -} - -static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - tmp = ((Pdec *)hw)->PRESC.reg; - tmp &= ~PDEC_PRESC_PRESC_Msk; - tmp |= PDEC_PRESC_PRESC(data); - ((Pdec *)hw)->PRESC.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - ((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - ((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); - tmp = ((Pdec *)hw)->PRESC.reg; - tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos; - return tmp; -} - -static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->PRESC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESC.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw) -{ - return ((Pdec *)hw)->PRESC.reg; -} - -static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - ((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - tmp = ((Pdec *)hw)->FILTER.reg; - tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos; - return tmp; -} - -static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - tmp = ((Pdec *)hw)->FILTER.reg; - tmp &= ~PDEC_FILTER_FILTER_Msk; - tmp |= PDEC_FILTER_FILTER(data); - ((Pdec *)hw)->FILTER.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - ((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - ((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw) -{ - uint8_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); - tmp = ((Pdec *)hw)->FILTER.reg; - tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos; - return tmp; -} - -static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->FILTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTER.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw) -{ - return ((Pdec *)hw)->FILTER.reg; -} - -static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const hw, - hri_pdec_prescbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk; - tmp |= PDEC_PRESCBUF_PRESCBUF(data); - ((Pdec *)hw)->PRESCBUF.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->PRESCBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->PRESCBUF.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw) -{ - return ((Pdec *)hw)->PRESCBUF.reg; -} - -static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const hw, - hri_pdec_filterbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos; - return tmp; -} - -static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data) -{ - uint8_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk; - tmp |= PDEC_FILTERBUF_FILTERBUF(data); - ((Pdec *)hw)->FILTERBUF.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos; - return tmp; -} - -static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pdec *)hw)->FILTERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->FILTERBUF.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw) -{ - return ((Pdec *)hw)->FILTERBUF.reg; -} - -static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - ((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - tmp = ((Pdec *)hw)->COUNT.reg; - tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - tmp = ((Pdec *)hw)->COUNT.reg; - tmp &= ~PDEC_COUNT_COUNT_Msk; - tmp |= PDEC_COUNT_COUNT(data); - ((Pdec *)hw)->COUNT.reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - ((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - ((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); - tmp = ((Pdec *)hw)->COUNT.reg; - tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->COUNT.reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw) -{ - return ((Pdec *)hw)->COUNT.reg; -} - -static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CC[index].reg; - tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos; - return tmp; -} - -static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CC[index].reg; - tmp &= ~PDEC_CC_CC_Msk; - tmp |= PDEC_CC_CC(data); - ((Pdec *)hw)->CC[index].reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CC[index].reg; - tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos; - return tmp; -} - -static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CC[index].reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index) -{ - return ((Pdec *)hw)->CC[index].reg; -} - -static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_pdec_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) -{ - uint32_t tmp; - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp &= ~PDEC_CCBUF_CCBUF_Msk; - tmp |= PDEC_CCBUF_CCBUF(data); - ((Pdec *)hw)->CCBUF[index].reg = tmp; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask); - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg |= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_pdec_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg = data; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg &= ~mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->CCBUF[index].reg ^= mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - return ((Pdec *)hw)->CCBUF[index].reg; -} - -static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos; -} - -static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Pdec *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Pdec *)hw)->SYNCBUSY.reg; -} - -static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos; -} - -static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos; -} - -static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos; -} - -static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos; -} - -static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos; -} - -static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos; -} - -static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw) -{ - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos; -} - -static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw) -{ - PDEC_CRITICAL_SECTION_ENTER(); - hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); - ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Pdec *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) -{ - PDEC_CRITICAL_SECTION_ENTER(); - ((Pdec *)hw)->STATUS.reg = mask; - PDEC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw) -{ - return ((Pdec *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PDEC_D51_H_INCLUDED */ -#endif /* _SAMD51_PDEC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_pm_d51.h b/atmel-samd/asf4/samd51/hri/hri_pm_d51.h deleted file mode 100644 index 3dde1282f..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_pm_d51.h +++ /dev/null @@ -1,829 +0,0 @@ -/** - * \file - * - * \brief SAM PM - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_PM_COMPONENT_ -#ifndef _HRI_PM_D51_H_INCLUDED_ -#define _HRI_PM_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PM_CRITICAL_SECTIONS) -#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PM_CRITICAL_SECTION_ENTER() -#define PM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint8_t hri_pm_bkupcfg_reg_t; -typedef uint8_t hri_pm_ctrla_reg_t; -typedef uint8_t hri_pm_hibcfg_reg_t; -typedef uint8_t hri_pm_intenset_reg_t; -typedef uint8_t hri_pm_intflag_reg_t; -typedef uint8_t hri_pm_pwsakdly_reg_t; -typedef uint8_t hri_pm_sleepcfg_reg_t; -typedef uint8_t hri_pm_stdbycfg_reg_t; - -static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; -} - -static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos; -} - -static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; - } else { - ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; - } -} - -static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; -} - -static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - ((Pm *)hw)->INTENSET.reg = mask; -} - -static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) -{ - return ((Pm *)hw)->INTENSET.reg; -} - -static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) -{ - ((Pm *)hw)->INTENSET.reg = data; - ((Pm *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) -{ - ((Pm *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; -} - -static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; -} - -static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw) -{ - return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; -} - -static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw) -{ - ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; -} - -static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) -{ - return ((Pm *)hw)->INTFLAG.reg; -} - -static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) -{ - ((Pm *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CTRLA.reg; - tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->CTRLA.reg; - tmp &= ~PM_CTRLA_IORET; - tmp |= value << PM_CTRLA_IORET_Pos; - ((Pm *)hw)->CTRLA.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->CTRLA.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) -{ - return ((Pm *)hw)->CTRLA.reg; -} - -static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; - return tmp; -} - -static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; - tmp |= PM_SLEEPCFG_SLEEPMODE(data); - ((Pm *)hw)->SLEEPCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; - return tmp; -} - -static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->SLEEPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->SLEEPCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->SLEEPCFG.reg; -} - -static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= ~PM_STDBYCFG_RAMCFG_Msk; - tmp |= PM_STDBYCFG_RAMCFG(data); - ((Pm *)hw)->STDBYCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= ~PM_STDBYCFG_FASTWKUP_Msk; - tmp |= PM_STDBYCFG_FASTWKUP(data); - ((Pm *)hw)->STDBYCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos; - return tmp; -} - -static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->STDBYCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->STDBYCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->STDBYCFG.reg; -} - -static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp &= ~PM_HIBCFG_RAMCFG_Msk; - tmp |= PM_HIBCFG_RAMCFG(data); - ((Pm *)hw)->HIBCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp &= ~PM_HIBCFG_BRAMCFG_Msk; - tmp |= PM_HIBCFG_BRAMCFG(data); - ((Pm *)hw)->HIBCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->HIBCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->HIBCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->HIBCFG.reg; -} - -static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp &= ~PM_BKUPCFG_BRAMCFG_Msk; - tmp |= PM_BKUPCFG_BRAMCFG(data); - ((Pm *)hw)->BKUPCFG.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos; - return tmp; -} - -static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->BKUPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->BKUPCFG.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw) -{ - return ((Pm *)hw)->BKUPCFG.reg; -} - -static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos; - return (bool)tmp; -} - -static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp &= ~PM_PWSAKDLY_IGNACK; - tmp |= value << PM_PWSAKDLY_IGNACK_Pos; - ((Pm *)hw)->PWSAKDLY.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos; - return tmp; -} - -static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data) -{ - uint8_t tmp; - PM_CRITICAL_SECTION_ENTER(); - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp &= ~PM_PWSAKDLY_DLYVAL_Msk; - tmp |= PM_PWSAKDLY_DLYVAL(data); - ((Pm *)hw)->PWSAKDLY.reg = tmp; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask); - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos; - return tmp; -} - -static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg |= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - uint8_t tmp; - tmp = ((Pm *)hw)->PWSAKDLY.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg = data; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg &= ~mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) -{ - PM_CRITICAL_SECTION_ENTER(); - ((Pm *)hw)->PWSAKDLY.reg ^= mask; - PM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw) -{ - return ((Pm *)hw)->PWSAKDLY.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PM_D51_H_INCLUDED */ -#endif /* _SAMD51_PM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_port_d51.h b/atmel-samd/asf4/samd51/hri/hri_port_d51.h deleted file mode 100644 index cc2decac8..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_port_d51.h +++ /dev/null @@ -1,2537 +0,0 @@ -/** - * \file - * - * \brief SAM PORT - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_PORT_COMPONENT_ -#ifndef _HRI_PORT_D51_H_INCLUDED_ -#define _HRI_PORT_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_PORT_CRITICAL_SECTIONS) -#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define PORT_CRITICAL_SECTION_ENTER() -#define PORT_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_port_ctrl_reg_t; -typedef uint32_t hri_port_dir_reg_t; -typedef uint32_t hri_port_evctrl_reg_t; -typedef uint32_t hri_port_in_reg_t; -typedef uint32_t hri_port_out_reg_t; -typedef uint32_t hri_port_wrconfig_reg_t; -typedef uint32_t hri_portgroup_ctrl_reg_t; -typedef uint32_t hri_portgroup_dir_reg_t; -typedef uint32_t hri_portgroup_evctrl_reg_t; -typedef uint32_t hri_portgroup_in_reg_t; -typedef uint32_t hri_portgroup_out_reg_t; -typedef uint32_t hri_portgroup_wrconfig_reg_t; -typedef uint8_t hri_port_pincfg_reg_t; -typedef uint8_t hri_port_pmux_reg_t; -typedef uint8_t hri_portgroup_pincfg_reg_t; -typedef uint8_t hri_portgroup_pmux_reg_t; - -static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); -} - -static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) -{ - ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); - ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); -} - -static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRSET.reg = mask; -} - -static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->DIR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) -{ - return ((PortGroup *)hw)->DIR.reg; -} - -static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) -{ - ((PortGroup *)hw)->DIRSET.reg = data; - ((PortGroup *)hw)->DIRCLR.reg = ~data; -} - -static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRCLR.reg = mask; -} - -static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) -{ - ((PortGroup *)hw)->DIRTGL.reg = mask; -} - -static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); -} - -static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) -{ - ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); - ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); -} - -static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTSET.reg = mask; -} - -static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->OUT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) -{ - return ((PortGroup *)hw)->OUT.reg; -} - -static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) -{ - ((PortGroup *)hw)->OUTSET.reg = data; - ((PortGroup *)hw)->OUTCLR.reg = ~data; -} - -static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTCLR.reg = mask; -} - -static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) -{ - ((PortGroup *)hw)->OUTTGL.reg = mask; -} - -static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->WRCONFIG.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp &= ~PORT_CTRL_SAMPLING_Msk; - tmp |= PORT_CTRL_SAMPLING(data); - ((PortGroup *)hw)->CTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->CTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) -{ - return ((PortGroup *)hw)->CTRL.reg; -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI0; - tmp |= value << PORT_EVCTRL_PORTEI0_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI1; - tmp |= value << PORT_EVCTRL_PORTEI1_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI2; - tmp |= value << PORT_EVCTRL_PORTEI2_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI3; - tmp |= value << PORT_EVCTRL_PORTEI3_Pos; - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID0_Msk; - tmp |= PORT_EVCTRL_PID0(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT0_Msk; - tmp |= PORT_EVCTRL_EVACT0(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID1_Msk; - tmp |= PORT_EVCTRL_PID1(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT1_Msk; - tmp |= PORT_EVCTRL_EVACT1(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID2_Msk; - tmp |= PORT_EVCTRL_PID2(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT2_Msk; - tmp |= PORT_EVCTRL_EVACT2(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID3_Msk; - tmp |= PORT_EVCTRL_PID3(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT3_Msk; - tmp |= PORT_EVCTRL_EVACT3(data); - ((PortGroup *)hw)->EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->EVCTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) -{ - return ((PortGroup *)hw)->EVCTRL.reg; -} - -static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXE_Msk; - tmp |= PORT_PMUX_PMUXE(data); - ((PortGroup *)hw)->PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXO_Msk; - tmp |= PORT_PMUX_PMUXO(data); - ((PortGroup *)hw)->PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PMUX[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PMUX[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) -{ - return ((PortGroup *)hw)->PMUX[index].reg; -} - -static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PMUXEN; - tmp |= value << PORT_PINCFG_PMUXEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_INEN; - tmp |= value << PORT_PINCFG_INEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PULLEN; - tmp |= value << PORT_PINCFG_PULLEN_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; - return (bool)tmp; -} - -static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= ~PORT_PINCFG_DRVSTR; - tmp |= value << PORT_PINCFG_DRVSTR_Pos; - ((PortGroup *)hw)->PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((PortGroup *)hw)->PINCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((PortGroup *)hw)->PINCFG[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) -{ - return ((PortGroup *)hw)->PINCFG[index].reg; -} - -static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) -{ - return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) -{ - return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) -{ - uint32_t tmp; - tmp = ((PortGroup *)hw)->IN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) -{ - return ((PortGroup *)hw)->IN.reg; -} - -static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); -} - -static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, - hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; - return tmp; -} - -static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); -} - -static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); -} - -static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; -} - -static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, - hri_port_dir_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].DIR.reg; -} - -static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; -} - -static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; -} - -static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; -} - -static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); -} - -static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, - hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; - return tmp; -} - -static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); -} - -static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); -} - -static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; -} - -static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, - hri_port_out_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].OUT.reg; -} - -static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) -{ - ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; -} - -static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; -} - -static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) -{ - ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; -} - -static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, - hri_port_wrconfig_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp &= ~PORT_CTRL_SAMPLING_Msk; - tmp |= PORT_CTRL_SAMPLING(data); - ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; - return tmp; -} - -static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, - hri_port_ctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].CTRL.reg; -} - -static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI0; - tmp |= value << PORT_EVCTRL_PORTEI0_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI1; - tmp |= value << PORT_EVCTRL_PORTEI1_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI2; - tmp |= value << PORT_EVCTRL_PORTEI2_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PORTEI3; - tmp |= value << PORT_EVCTRL_PORTEI3_Pos; - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID0_Msk; - tmp |= PORT_EVCTRL_PID0(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT0_Msk; - tmp |= PORT_EVCTRL_EVACT0(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID1_Msk; - tmp |= PORT_EVCTRL_PID1(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT1_Msk; - tmp |= PORT_EVCTRL_EVACT1(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID2_Msk; - tmp |= PORT_EVCTRL_PID2(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT2_Msk; - tmp |= PORT_EVCTRL_EVACT2(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_PID3_Msk; - tmp |= PORT_EVCTRL_PID3(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t data) -{ - uint32_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= ~PORT_EVCTRL_EVACT3_Msk; - tmp |= PORT_EVCTRL_EVACT3(data); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; - return tmp; -} - -static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, - hri_port_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; -} - -static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXE_Msk; - tmp |= PORT_PMUX_PMUXE(data); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; - return tmp; -} - -static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= ~PORT_PMUX_PMUXO_Msk; - tmp |= PORT_PMUX_PMUXO(data); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; - return tmp; -} - -static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pmux_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; -} - -static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PMUXEN; - tmp |= value << PORT_PINCFG_PMUXEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_INEN; - tmp |= value << PORT_PINCFG_INEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_PULLEN; - tmp |= value << PORT_PINCFG_PULLEN_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; - return (bool)tmp; -} - -static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint8_t tmp; - PORT_CRITICAL_SECTION_ENTER(); - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= ~PORT_PINCFG_DRVSTR; - tmp |= value << PORT_PINCFG_DRVSTR_Pos; - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_port_pincfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t data) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_port_pincfg_reg_t mask) -{ - PORT_CRITICAL_SECTION_ENTER(); - ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; - PORT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; -} - -static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, - hri_port_in_reg_t mask) -{ - return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) -{ - return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; -} - -static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, - hri_port_in_reg_t mask) -{ - uint32_t tmp; - tmp = ((Port *)hw)->Group[submodule_index].IN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Port *)hw)->Group[submodule_index].IN.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_PORT_D51_H_INCLUDED */ -#endif /* _SAMD51_PORT_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_qspi_d51.h b/atmel-samd/asf4/samd51/hri/hri_qspi_d51.h deleted file mode 100644 index 9474a03a7..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_qspi_d51.h +++ /dev/null @@ -1,2067 +0,0 @@ -/** - * \file - * - * \brief SAM QSPI - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_QSPI_COMPONENT_ -#ifndef _HRI_QSPI_D51_H_INCLUDED_ -#define _HRI_QSPI_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_QSPI_CRITICAL_SECTIONS) -#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define QSPI_CRITICAL_SECTION_ENTER() -#define QSPI_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_qspi_baud_reg_t; -typedef uint32_t hri_qspi_ctrla_reg_t; -typedef uint32_t hri_qspi_ctrlb_reg_t; -typedef uint32_t hri_qspi_instraddr_reg_t; -typedef uint32_t hri_qspi_instrctrl_reg_t; -typedef uint32_t hri_qspi_instrframe_reg_t; -typedef uint32_t hri_qspi_intenset_reg_t; -typedef uint32_t hri_qspi_intflag_reg_t; -typedef uint32_t hri_qspi_rxdata_reg_t; -typedef uint32_t hri_qspi_scrambctrl_reg_t; -typedef uint32_t hri_qspi_scrambkey_reg_t; -typedef uint32_t hri_qspi_status_reg_t; -typedef uint32_t hri_qspi_txdata_reg_t; - -static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; -} - -static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos; -} - -static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; - } -} - -static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; -} - -static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; -} - -static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos; -} - -static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; - } -} - -static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; -} - -static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; -} - -static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos; -} - -static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; - } -} - -static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; -} - -static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; -} - -static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos; -} - -static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; - } -} - -static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; -} - -static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; -} - -static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos; -} - -static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; - } -} - -static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; -} - -static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; -} - -static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos; -} - -static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; - } else { - ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; - } -} - -static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; -} - -static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) -{ - ((Qspi *)hw)->INTENSET.reg = mask; -} - -static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw) -{ - return ((Qspi *)hw)->INTENSET.reg; -} - -static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data) -{ - ((Qspi *)hw)->INTENSET.reg = data; - ((Qspi *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) -{ - ((Qspi *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; -} - -static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; -} - -static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; -} - -static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; -} - -static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; -} - -static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; -} - -static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; -} - -static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; -} - -static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; -} - -static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; -} - -static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; -} - -static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; -} - -static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; -} - -static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; -} - -static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; -} - -static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; -} - -static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw) -{ - return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; -} - -static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw) -{ - ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; -} - -static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw) -{ - return ((Qspi *)hw)->INTFLAG.reg; -} - -static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) -{ - ((Qspi *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->TXDATA.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBKEY.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp &= ~QSPI_CTRLA_ENABLE; - tmp |= value << QSPI_CTRLA_ENABLE_Pos; - ((Qspi *)hw)->CTRLA.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp &= ~QSPI_CTRLA_LASTXFER; - tmp |= value << QSPI_CTRLA_LASTXFER_Pos; - ((Qspi *)hw)->CTRLA.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLA.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw) -{ - return ((Qspi *)hw)->CTRLA.reg; -} - -static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_MODE; - tmp |= value << QSPI_CTRLB_MODE_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_LOOPEN; - tmp |= value << QSPI_CTRLB_LOOPEN_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_WDRBT; - tmp |= value << QSPI_CTRLB_WDRBT_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_SMEMREG; - tmp |= value << QSPI_CTRLB_SMEMREG_Pos; - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_CSMODE_Msk; - tmp |= QSPI_CTRLB_CSMODE(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_DATALEN_Msk; - tmp |= QSPI_CTRLB_DATALEN(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_DLYBCT_Msk; - tmp |= QSPI_CTRLB_DLYBCT(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= ~QSPI_CTRLB_DLYCS_Msk; - tmp |= QSPI_CTRLB_DLYCS(data); - ((Qspi *)hw)->CTRLB.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos; - return tmp; -} - -static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->CTRLB.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw) -{ - return ((Qspi *)hw)->CTRLB.reg; -} - -static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_CPOL; - tmp |= value << QSPI_BAUD_CPOL_Pos; - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_CPHA; - tmp |= value << QSPI_BAUD_CPHA_Pos; - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_BAUD_Msk; - tmp |= QSPI_BAUD_BAUD(data); - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos; - return tmp; -} - -static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= ~QSPI_BAUD_DLYBS_Msk; - tmp |= QSPI_BAUD_DLYBS(data); - ((Qspi *)hw)->BAUD.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos; - return tmp; -} - -static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->BAUD.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw) -{ - return ((Qspi *)hw)->BAUD.reg; -} - -static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const hw, - hri_qspi_instraddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp &= ~QSPI_INSTRADDR_ADDR_Msk; - tmp |= QSPI_INSTRADDR_ADDR(data); - ((Qspi *)hw)->INSTRADDR.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRADDR.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw) -{ - return ((Qspi *)hw)->INSTRADDR.reg; -} - -static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const hw, - hri_qspi_instrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp &= ~QSPI_INSTRCTRL_INSTR_Msk; - tmp |= QSPI_INSTRCTRL_INSTR(data); - ((Qspi *)hw)->INSTRCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const hw, - hri_qspi_instrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk; - tmp |= QSPI_INSTRCTRL_OPTCODE(data); - ((Qspi *)hw)->INSTRCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRCTRL.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw) -{ - return ((Qspi *)hw)->INSTRCTRL.reg; -} - -static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_INSTREN; - tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_ADDREN; - tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_OPTCODEEN; - tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_DATAEN; - tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_ADDRLEN; - tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_CRMODE; - tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_DDREN; - tmp |= value << QSPI_INSTRFRAME_DDREN_Pos; - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk; - tmp |= QSPI_INSTRFRAME_WIDTH(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk; - tmp |= QSPI_INSTRFRAME_OPTCODELEN(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk; - tmp |= QSPI_INSTRFRAME_TFRTYPE(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk; - tmp |= QSPI_INSTRFRAME_DUMMYLEN(data); - ((Qspi *)hw)->INSTRFRAME.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask); - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; - return tmp; -} - -static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const hw, - hri_qspi_instrframe_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->INSTRFRAME.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->INSTRFRAME.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw) -{ - return ((Qspi *)hw)->INSTRFRAME.reg; -} - -static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp &= ~QSPI_SCRAMBCTRL_ENABLE; - tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos; - ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos; - return (bool)tmp; -} - -static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - QSPI_CRITICAL_SECTION_ENTER(); - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS; - tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos; - ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg |= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const hw, - hri_qspi_scrambctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg = data; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) -{ - QSPI_CRITICAL_SECTION_ENTER(); - ((Qspi *)hw)->SCRAMBCTRL.reg ^= mask; - QSPI_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw) -{ - return ((Qspi *)hw)->SCRAMBCTRL.reg; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask) -{ - return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw) -{ - return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->RXDATA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw) -{ - return ((Qspi *)hw)->RXDATA.reg; -} - -static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw) -{ - return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos; -} - -static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw) -{ - return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos; -} - -static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Qspi *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw) -{ - return ((Qspi *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_QSPI_D51_H_INCLUDED */ -#endif /* _SAMD51_QSPI_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_ramecc_d51.h b/atmel-samd/asf4/samd51/hri/hri_ramecc_d51.h deleted file mode 100644 index 97147807d..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_ramecc_d51.h +++ /dev/null @@ -1,371 +0,0 @@ -/** - * \file - * - * \brief SAM RAMECC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_RAMECC_COMPONENT_ -#ifndef _HRI_RAMECC_D51_H_INCLUDED_ -#define _HRI_RAMECC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RAMECC_CRITICAL_SECTIONS) -#define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RAMECC_CRITICAL_SECTION_ENTER() -#define RAMECC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_ramecc_erraddr_reg_t; -typedef uint8_t hri_ramecc_dbgctrl_reg_t; -typedef uint8_t hri_ramecc_intenset_reg_t; -typedef uint8_t hri_ramecc_intflag_reg_t; -typedef uint8_t hri_ramecc_status_reg_t; - -static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; -} - -static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos; -} - -static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; - } else { - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; - } -} - -static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; -} - -static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; -} - -static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos; -} - -static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; - } else { - ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; - } -} - -static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; -} - -static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) -{ - ((Ramecc *)hw)->INTENSET.reg = mask; -} - -static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw) -{ - return ((Ramecc *)hw)->INTENSET.reg; -} - -static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data) -{ - ((Ramecc *)hw)->INTENSET.reg = data; - ((Ramecc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) -{ - ((Ramecc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; -} - -static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; -} - -static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; -} - -static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; -} - -static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; -} - -static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; -} - -static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw) -{ - return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; -} - -static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw) -{ - ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; -} - -static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) -{ - return ((Ramecc *)hw)->INTFLAG.reg; -} - -static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) -{ - ((Ramecc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos; - return (bool)tmp; -} - -static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RAMECC_CRITICAL_SECTION_ENTER(); - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp &= ~RAMECC_DBGCTRL_ECCDIS; - tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos; - ((Ramecc *)hw)->DBGCTRL.reg = tmp; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos; - return (bool)tmp; -} - -static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RAMECC_CRITICAL_SECTION_ENTER(); - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp &= ~RAMECC_DBGCTRL_ECCELOG; - tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos; - ((Ramecc *)hw)->DBGCTRL.reg = tmp; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg |= mask; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg = data; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg &= ~mask; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) -{ - RAMECC_CRITICAL_SECTION_ENTER(); - ((Ramecc *)hw)->DBGCTRL.reg ^= mask; - RAMECC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Ramecc *)hw)->DBGCTRL.reg; -} - -static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw) -{ - return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos; -} - -static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Ramecc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw) -{ - return ((Ramecc *)hw)->STATUS.reg; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const hw, - hri_ramecc_erraddr_reg_t mask) -{ - return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw) -{ - return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Ramecc *)hw)->ERRADDR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) -{ - return ((Ramecc *)hw)->ERRADDR.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RAMECC_D51_H_INCLUDED */ -#endif /* _SAMD51_RAMECC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_rstc_d51.h b/atmel-samd/asf4/samd51/hri/hri_rstc_d51.h deleted file mode 100644 index 75dde1108..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_rstc_d51.h +++ /dev/null @@ -1,151 +0,0 @@ -/** - * \file - * - * \brief SAM RSTC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_RSTC_COMPONENT_ -#ifndef _HRI_RSTC_D51_H_INCLUDED_ -#define _HRI_RSTC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) -#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RSTC_CRITICAL_SECTION_ENTER() -#define RSTC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint8_t hri_rstc_bkupexit_reg_t; -typedef uint8_t hri_rstc_rcause_reg_t; - -static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_NVM_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_NVM) >> RSTC_RCAUSE_NVM_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; -} - -static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) -{ - return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; -} - -static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rstc *)hw)->RCAUSE.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) -{ - return ((Rstc *)hw)->RCAUSE.reg; -} - -static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) -{ - return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; -} - -static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) -{ - return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; -} - -static inline bool hri_rstc_get_BKUPEXIT_HIB_bit(const void *const hw) -{ - return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_HIB) >> RSTC_BKUPEXIT_HIB_Pos; -} - -static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rstc *)hw)->BKUPEXIT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) -{ - return ((Rstc *)hw)->BKUPEXIT.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RSTC_D51_H_INCLUDED */ -#endif /* _SAMD51_RSTC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_rtc_d51.h b/atmel-samd/asf4/samd51/hri/hri_rtc_d51.h deleted file mode 100644 index 1df33141c..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_rtc_d51.h +++ /dev/null @@ -1,12310 +0,0 @@ -/** - * \file - * - * \brief SAM RTC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_RTC_COMPONENT_ -#ifndef _HRI_RTC_D51_H_INCLUDED_ -#define _HRI_RTC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_RTC_CRITICAL_SECTIONS) -#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define RTC_CRITICAL_SECTION_ENTER() -#define RTC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_rtcmode0_ctrla_reg_t; -typedef uint16_t hri_rtcmode0_ctrlb_reg_t; -typedef uint16_t hri_rtcmode0_intenset_reg_t; -typedef uint16_t hri_rtcmode0_intflag_reg_t; -typedef uint16_t hri_rtcmode1_comp_reg_t; -typedef uint16_t hri_rtcmode1_count_reg_t; -typedef uint16_t hri_rtcmode1_ctrla_reg_t; -typedef uint16_t hri_rtcmode1_ctrlb_reg_t; -typedef uint16_t hri_rtcmode1_intenset_reg_t; -typedef uint16_t hri_rtcmode1_intflag_reg_t; -typedef uint16_t hri_rtcmode1_per_reg_t; -typedef uint16_t hri_rtcmode2_ctrla_reg_t; -typedef uint16_t hri_rtcmode2_ctrlb_reg_t; -typedef uint16_t hri_rtcmode2_intenset_reg_t; -typedef uint16_t hri_rtcmode2_intflag_reg_t; -typedef uint32_t hri_rtcalarm_alarm_reg_t; -typedef uint32_t hri_rtcmode0_bkup_reg_t; -typedef uint32_t hri_rtcmode0_comp_reg_t; -typedef uint32_t hri_rtcmode0_count_reg_t; -typedef uint32_t hri_rtcmode0_evctrl_reg_t; -typedef uint32_t hri_rtcmode0_gp_reg_t; -typedef uint32_t hri_rtcmode0_syncbusy_reg_t; -typedef uint32_t hri_rtcmode0_tampctrl_reg_t; -typedef uint32_t hri_rtcmode0_tampid_reg_t; -typedef uint32_t hri_rtcmode0_timestamp_reg_t; -typedef uint32_t hri_rtcmode1_bkup_reg_t; -typedef uint32_t hri_rtcmode1_evctrl_reg_t; -typedef uint32_t hri_rtcmode1_gp_reg_t; -typedef uint32_t hri_rtcmode1_syncbusy_reg_t; -typedef uint32_t hri_rtcmode1_tampctrl_reg_t; -typedef uint32_t hri_rtcmode1_tampid_reg_t; -typedef uint32_t hri_rtcmode1_timestamp_reg_t; -typedef uint32_t hri_rtcmode2_alarm_reg_t; -typedef uint32_t hri_rtcmode2_bkup_reg_t; -typedef uint32_t hri_rtcmode2_clock_reg_t; -typedef uint32_t hri_rtcmode2_evctrl_reg_t; -typedef uint32_t hri_rtcmode2_gp_reg_t; -typedef uint32_t hri_rtcmode2_syncbusy_reg_t; -typedef uint32_t hri_rtcmode2_tampctrl_reg_t; -typedef uint32_t hri_rtcmode2_tampid_reg_t; -typedef uint32_t hri_rtcmode2_timestamp_reg_t; -typedef uint8_t hri_rtcalarm_mask_reg_t; -typedef uint8_t hri_rtcmode0_dbgctrl_reg_t; -typedef uint8_t hri_rtcmode0_freqcorr_reg_t; -typedef uint8_t hri_rtcmode1_dbgctrl_reg_t; -typedef uint8_t hri_rtcmode1_freqcorr_reg_t; -typedef uint8_t hri_rtcmode2_dbgctrl_reg_t; -typedef uint8_t hri_rtcmode2_freqcorr_reg_t; -typedef uint8_t hri_rtcmode2_mask_reg_t; - -static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) -{ - while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) -{ - return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; -} - -static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; - tmp |= RTC_MODE2_ALARM_SECOND(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; - tmp |= RTC_MODE2_ALARM_MINUTE(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; - tmp |= RTC_MODE2_ALARM_HOUR(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_DAY_Msk; - tmp |= RTC_MODE2_ALARM_DAY(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; - tmp |= RTC_MODE2_ALARM_MONTH(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; - tmp |= RTC_MODE2_ALARM_YEAR(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) -{ - return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; -} - -static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp &= ~RTC_MODE2_MASK_SEL_Msk; - tmp |= RTC_MODE2_MASK_SEL(data); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcalarm_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcalarm_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; -} - -static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; - tmp |= RTC_MODE2_ALARM_SECOND(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; - tmp |= RTC_MODE2_ALARM_MINUTE(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; - tmp |= RTC_MODE2_ALARM_HOUR(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_DAY_Msk; - tmp |= RTC_MODE2_ALARM_DAY(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; - tmp |= RTC_MODE2_ALARM_MONTH(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; - tmp |= RTC_MODE2_ALARM_YEAR(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_alarm_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; -} - -static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp &= ~RTC_MODE2_MASK_SEL_Msk; - tmp |= RTC_MODE2_MASK_SEL(data); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, - hri_rtcmode2_mask_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; -} - -static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; -} - -static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; -} - -static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; -} - -static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; -} - -static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; -} - -static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; -} - -static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; -} - -static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; -} - -static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; -} - -static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; -} - -static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; -} - -static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; -} - -static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; -} - -static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; -} - -static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; -} - -static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; - } -} - -static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; -} - -static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; -} - -static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; - } -} - -static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; -} - -static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; -} - -static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; - } -} - -static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; -} - -static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; -} - -static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; -} - -static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; - } -} - -static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; -} - -static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = mask; -} - -static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, - hri_rtcmode2_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.INTENSET.reg; -} - -static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE2.INTENSET.reg = data; - ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; -} - -static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; -} - -static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; -} - -static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; -} - -static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; -} - -static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; -} - -static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; -} - -static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; -} - -static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; -} - -static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; -} - -static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; -} - -static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; -} - -static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; -} - -static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; -} - -static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; -} - -static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; -} - -static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, - hri_rtcmode2_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.INTFLAG.reg; -} - -static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; -} - -static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_ENABLE; - tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_CLKREP; - tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; - tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_BKTRST; - tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_GPTRST; - tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; - tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; - tmp |= RTC_MODE2_CTRLA_MODE(data); - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE2_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.CTRLA.reg; -} - -static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_GP0EN; - tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_GP2EN; - tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_RTCOUT; - tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DMAEN; - tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk; - tmp |= RTC_MODE2_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk; - tmp |= RTC_MODE2_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.CTRLB.reg; -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO0; - tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO1; - tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO2; - tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO3; - tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO4; - tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO5; - tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO6; - tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_PEREO7; - tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; - tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1; - tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_OVFEO; - tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, - hri_rtcmode2_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.EVCTRL.reg; -} - -static inline void hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; - tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; - tmp &= ~RTC_DBGCTRL_DBGRUN; - tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; - ((Rtc *)hw)->MODE2.DBGCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_get_DBGCTRL_reg(const void *const hw, - hri_rtcmode2_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode2_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.DBGCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_dbgctrl_reg_t hri_rtcmode2_read_DBGCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.DBGCTRL.reg; -} - -static inline void hri_rtcmode2_set_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_FREQCORR_SIGN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_FREQCORR_SIGN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_SIGN; - tmp |= value << RTC_FREQCORR_SIGN_Pos; - ((Rtc *)hw)->MODE2.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_VALUE_bf(const void *const hw, - hri_rtcmode2_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_VALUE_Msk; - tmp |= RTC_FREQCORR_VALUE(data); - ((Rtc *)hw)->MODE2.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_VALUE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.FREQCORR.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_get_FREQCORR_reg(const void *const hw, - hri_rtcmode2_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE2.FREQCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.FREQCORR.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.FREQCORR.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode2_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.FREQCORR.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_freqcorr_reg_t hri_rtcmode2_read_FREQCORR_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.FREQCORR.reg; -} - -static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; - tmp |= RTC_MODE2_CLOCK_SECOND(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; - tmp |= RTC_MODE2_CLOCK_MINUTE(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; - tmp |= RTC_MODE2_CLOCK_HOUR(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; - tmp |= RTC_MODE2_CLOCK_DAY(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; - tmp |= RTC_MODE2_CLOCK_MONTH(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, - hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; - tmp |= RTC_MODE2_CLOCK_YEAR(data); - ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.CLOCK.reg; -} - -static inline void hri_rtcmode2_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.GP[index].reg |= RTC_GP_GP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_gp_reg_t hri_rtcmode2_get_GP_GP_bf(const void *const hw, uint8_t index, - hri_rtcmode2_gp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.GP[index].reg; - tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - tmp = ((Rtc *)hw)->MODE2.GP[index].reg; - tmp &= ~RTC_GP_GP_Msk; - tmp |= RTC_GP_GP(data); - ((Rtc *)hw)->MODE2.GP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.GP[index].reg &= ~RTC_GP_GP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - ((Rtc *)hw)->MODE2.GP[index].reg ^= RTC_GP_GP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_gp_reg_t hri_rtcmode2_read_GP_GP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.GP[index].reg; - tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.GP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_gp_reg_t hri_rtcmode2_get_GP_reg(const void *const hw, uint8_t index, - hri_rtcmode2_gp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.GP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.GP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.GP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtcmode2_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.GP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_gp_reg_t hri_rtcmode2_read_GP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE2.GP[index].reg; -} - -static inline void hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL0; - tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL1; - tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL2; - tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL3; - tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL4; - tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC0; - tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC1; - tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC2; - tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC3; - tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC4; - tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(const void *const hw, - hri_rtcmode2_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; - tmp |= RTC_TAMPCTRL_IN0ACT(data); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(const void *const hw, - hri_rtcmode2_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; - tmp |= RTC_TAMPCTRL_IN1ACT(data); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(const void *const hw, - hri_rtcmode2_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; - tmp |= RTC_TAMPCTRL_IN2ACT(data); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(const void *const hw, - hri_rtcmode2_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; - tmp |= RTC_TAMPCTRL_IN3ACT(data); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(const void *const hw, - hri_rtcmode2_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; - tmp |= RTC_TAMPCTRL_IN4ACT(data); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_TAMPCTRL_reg(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_get_TAMPCTRL_reg(const void *const hw, - hri_rtcmode2_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_TAMPCTRL_reg(const void *const hw, hri_rtcmode2_tampctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPCTRL_reg(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPCTRL_reg(const void *const hw, hri_rtcmode2_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampctrl_reg_t hri_rtcmode2_read_TAMPCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.TAMPCTRL.reg; -} - -static inline void hri_rtcmode2_set_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPID_TAMPID0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID0; - tmp |= value << RTC_TAMPID_TAMPID0_Pos; - ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPID_TAMPID1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID1; - tmp |= value << RTC_TAMPID_TAMPID1_Pos; - ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPID_TAMPID2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID2; - tmp |= value << RTC_TAMPID_TAMPID2_Pos; - ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPID_TAMPID3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID3; - tmp |= value << RTC_TAMPID_TAMPID3_Pos; - ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPID_TAMPID4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID4; - tmp |= value << RTC_TAMPID_TAMPID4_Pos; - ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg |= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode2_get_TAMPID_TAMPEVT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode2_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPEVT; - tmp |= value << RTC_TAMPID_TAMPEVT_Pos; - ((Rtc *)hw)->MODE2.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_set_TAMPID_reg(const void *const hw, hri_rtcmode2_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampid_reg_t hri_rtcmode2_get_TAMPID_reg(const void *const hw, - hri_rtcmode2_tampid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TAMPID.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_TAMPID_reg(const void *const hw, hri_rtcmode2_tampid_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_TAMPID_reg(const void *const hw, hri_rtcmode2_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_TAMPID_reg(const void *const hw, hri_rtcmode2_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.TAMPID.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_tampid_reg_t hri_rtcmode2_read_TAMPID_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.TAMPID.reg; -} - -static inline void hri_rtcmode2_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.BKUP[index].reg |= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_bkup_reg_t hri_rtcmode2_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, - hri_rtcmode2_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtcmode2_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE2.BKUP[index].reg; - tmp &= ~RTC_BKUP_BKUP_Msk; - tmp |= RTC_BKUP_BKUP(data); - ((Rtc *)hw)->MODE2.BKUP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_bkup_reg_t hri_rtcmode2_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtcmode2_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.BKUP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_bkup_reg_t hri_rtcmode2_get_BKUP_reg(const void *const hw, uint8_t index, - hri_rtcmode2_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.BKUP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode2_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.BKUP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.BKUP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode2_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode2_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE2.BKUP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode2_bkup_reg_t hri_rtcmode2_read_BKUP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE2.BKUP[index].reg; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos; -} - -static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos; -} - -static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode2_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw) -{ - hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); - return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode2_timestamp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE2.TIMESTAMP.reg; -} - -static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; -} - -static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; -} - -static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; -} - -static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; -} - -static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; -} - -static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; -} - -static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; -} - -static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; -} - -static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; -} - -static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; -} - -static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; -} - -static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; -} - -static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; -} - -static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; -} - -static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; -} - -static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; - } -} - -static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; -} - -static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; -} - -static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; - } -} - -static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; -} - -static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; -} - -static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; - } -} - -static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; -} - -static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; -} - -static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; -} - -static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; - } -} - -static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; -} - -static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = mask; -} - -static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, - hri_rtcmode0_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.INTENSET.reg; -} - -static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE0.INTENSET.reg = data; - ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; -} - -static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; -} - -static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; -} - -static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; -} - -static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; -} - -static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; -} - -static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; -} - -static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; -} - -static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; -} - -static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; -} - -static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; -} - -static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; -} - -static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, - hri_rtcmode0_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.INTFLAG.reg; -} - -static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; -} - -static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_ENABLE; - tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; - tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_BKTRST; - tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_GPTRST; - tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; - tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; - tmp |= RTC_MODE0_CTRLA_MODE(data); - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE0_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.CTRLA.reg; -} - -static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_GP0EN; - tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_GP2EN; - tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_RTCOUT; - tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DMAEN; - tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk; - tmp |= RTC_MODE0_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk; - tmp |= RTC_MODE0_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.CTRLB.reg; -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO0; - tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO1; - tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO2; - tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO3; - tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO4; - tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO5; - tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO6; - tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_PEREO7; - tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; - tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_CMPEO1; - tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_OVFEO; - tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, - hri_rtcmode0_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.EVCTRL.reg; -} - -static inline void hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp &= ~RTC_DBGCTRL_DBGRUN; - tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; - ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_get_DBGCTRL_reg(const void *const hw, - hri_rtcmode0_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode0_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_dbgctrl_reg_t hri_rtcmode0_read_DBGCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.DBGCTRL.reg; -} - -static inline void hri_rtcmode0_set_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_FREQCORR_SIGN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_FREQCORR_SIGN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_SIGN; - tmp |= value << RTC_FREQCORR_SIGN_Pos; - ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_VALUE_bf(const void *const hw, - hri_rtcmode0_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_VALUE_Msk; - tmp |= RTC_FREQCORR_VALUE(data); - ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_VALUE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_get_FREQCORR_reg(const void *const hw, - hri_rtcmode0_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode0_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_freqcorr_reg_t hri_rtcmode0_read_FREQCORR_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.FREQCORR.reg; -} - -static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, - hri_rtcmode0_count_reg_t mask) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; - tmp |= RTC_MODE0_COUNT_COUNT(data); - ((Rtc *)hw)->MODE0.COUNT.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.COUNT.reg; -} - -static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, - hri_rtcmode0_comp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp &= ~RTC_MODE0_COMP_COMP_Msk; - tmp |= RTC_MODE0_COMP_COMP(data); - ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, - hri_rtcmode0_comp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE0.COMP[index].reg; -} - -static inline void hri_rtcmode0_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_gp_reg_t hri_rtcmode0_get_GP_GP_bf(const void *const hw, uint8_t index, - hri_rtcmode0_gp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp &= ~RTC_GP_GP_Msk; - tmp |= RTC_GP_GP(data); - ((Rtc *)hw)->MODE0.GP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_gp_reg_t hri_rtcmode0_read_GP_GP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_gp_reg_t hri_rtcmode0_get_GP_reg(const void *const hw, uint8_t index, - hri_rtcmode0_gp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.GP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtcmode0_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_gp_reg_t hri_rtcmode0_read_GP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE0.GP[index].reg; -} - -static inline void hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL0; - tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL1; - tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL2; - tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL3; - tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL4; - tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC0; - tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC1; - tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC2; - tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC3; - tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC4; - tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(const void *const hw, - hri_rtcmode0_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; - tmp |= RTC_TAMPCTRL_IN0ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(const void *const hw, - hri_rtcmode0_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; - tmp |= RTC_TAMPCTRL_IN1ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(const void *const hw, - hri_rtcmode0_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; - tmp |= RTC_TAMPCTRL_IN2ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(const void *const hw, - hri_rtcmode0_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; - tmp |= RTC_TAMPCTRL_IN3ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(const void *const hw, - hri_rtcmode0_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; - tmp |= RTC_TAMPCTRL_IN4ACT(data); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_TAMPCTRL_reg(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_get_TAMPCTRL_reg(const void *const hw, - hri_rtcmode0_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_TAMPCTRL_reg(const void *const hw, hri_rtcmode0_tampctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPCTRL_reg(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPCTRL_reg(const void *const hw, hri_rtcmode0_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampctrl_reg_t hri_rtcmode0_read_TAMPCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.TAMPCTRL.reg; -} - -static inline void hri_rtcmode0_set_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPID_TAMPID0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID0; - tmp |= value << RTC_TAMPID_TAMPID0_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPID_TAMPID1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID1; - tmp |= value << RTC_TAMPID_TAMPID1_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPID_TAMPID2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID2; - tmp |= value << RTC_TAMPID_TAMPID2_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPID_TAMPID3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID3; - tmp |= value << RTC_TAMPID_TAMPID3_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPID_TAMPID4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID4; - tmp |= value << RTC_TAMPID_TAMPID4_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode0_get_TAMPID_TAMPEVT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode0_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPEVT; - tmp |= value << RTC_TAMPID_TAMPEVT_Pos; - ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_set_TAMPID_reg(const void *const hw, hri_rtcmode0_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampid_reg_t hri_rtcmode0_get_TAMPID_reg(const void *const hw, - hri_rtcmode0_tampid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_TAMPID_reg(const void *const hw, hri_rtcmode0_tampid_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_TAMPID_reg(const void *const hw, hri_rtcmode0_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_TAMPID_reg(const void *const hw, hri_rtcmode0_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.TAMPID.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_tampid_reg_t hri_rtcmode0_read_TAMPID_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.TAMPID.reg; -} - -static inline void hri_rtcmode0_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_bkup_reg_t hri_rtcmode0_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, - hri_rtcmode0_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp &= ~RTC_BKUP_BKUP_Msk; - tmp |= RTC_BKUP_BKUP(data); - ((Rtc *)hw)->MODE0.BKUP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_bkup_reg_t hri_rtcmode0_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtcmode0_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_bkup_reg_t hri_rtcmode0_get_BKUP_reg(const void *const hw, uint8_t index, - hri_rtcmode0_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode0_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode0_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode0_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode0_bkup_reg_t hri_rtcmode0_read_BKUP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE0.BKUP[index].reg; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos; -} - -static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos; -} - -static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode0_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const hw, - hri_rtcmode0_timestamp_reg_t mask) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw) -{ - hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode0_timestamp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE0.TIMESTAMP.reg; -} - -static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; -} - -static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; -} - -static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; -} - -static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; -} - -static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; -} - -static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; -} - -static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; -} - -static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; -} - -static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; -} - -static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; -} - -static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; -} - -static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; -} - -static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; -} - -static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; -} - -static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; -} - -static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; - } -} - -static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; -} - -static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; -} - -static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; -} - -static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; -} - -static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; -} - -static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; - } -} - -static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; -} - -static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; -} - -static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; - } -} - -static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; -} - -static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; -} - -static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; -} - -static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; - } else { - ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; - } -} - -static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; -} - -static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = mask; -} - -static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, - hri_rtcmode1_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.INTENSET.reg; -} - -static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) -{ - ((Rtc *)hw)->MODE1.INTENSET.reg = data; - ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; -} - -static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; -} - -static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; -} - -static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; -} - -static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; -} - -static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; -} - -static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; -} - -static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; -} - -static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; -} - -static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; -} - -static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; -} - -static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; -} - -static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; -} - -static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; -} - -static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; -} - -static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; -} - -static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; -} - -static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, - hri_rtcmode1_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.INTFLAG.reg; -} - -static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) -{ - ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; -} - -static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_ENABLE; - tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_BKTRST; - tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_GPTRST; - tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; - tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, - hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; - tmp |= RTC_MODE1_CTRLA_MODE(data); - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, - hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; - tmp |= RTC_MODE1_CTRLA_PRESCALER(data); - ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.CTRLA.reg; -} - -static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_GP0EN; - tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_GP2EN; - tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBMAJ; - tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBASYNC; - tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_RTCOUT; - tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DMAEN; - tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos; - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const hw, - hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk; - tmp |= RTC_MODE1_CTRLB_DEBF(data); - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const hw, - hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk; - tmp |= RTC_MODE1_CTRLB_ACTF(data); - ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.CTRLB.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.CTRLB.reg; -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO0; - tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO1; - tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO2; - tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO3; - tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO4; - tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO5; - tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO6; - tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_PEREO7; - tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO2; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_CMPEO3; - tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO; - tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_OVFEO; - tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI; - tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos; - ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, - hri_rtcmode1_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.EVCTRL.reg; -} - -static inline void hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; - tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; - tmp &= ~RTC_DBGCTRL_DBGRUN; - tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; - ((Rtc *)hw)->MODE1.DBGCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_get_DBGCTRL_reg(const void *const hw, - hri_rtcmode1_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_DBGCTRL_reg(const void *const hw, hri_rtcmode1_dbgctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.DBGCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_dbgctrl_reg_t hri_rtcmode1_read_DBGCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.DBGCTRL.reg; -} - -static inline void hri_rtcmode1_set_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_FREQCORR_SIGN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_FREQCORR_SIGN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_SIGN; - tmp |= value << RTC_FREQCORR_SIGN_Pos; - ((Rtc *)hw)->MODE1.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_FREQCORR_SIGN_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_SIGN; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_VALUE_bf(const void *const hw, - hri_rtcmode1_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t data) -{ - uint8_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp &= ~RTC_FREQCORR_VALUE_Msk; - tmp |= RTC_FREQCORR_VALUE(data); - ((Rtc *)hw)->MODE1.FREQCORR.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_VALUE_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.FREQCORR.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_get_FREQCORR_reg(const void *const hw, - hri_rtcmode1_freqcorr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Rtc *)hw)->MODE1.FREQCORR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.FREQCORR.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.FREQCORR.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_FREQCORR_reg(const void *const hw, hri_rtcmode1_freqcorr_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.FREQCORR.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_freqcorr_reg_t hri_rtcmode1_read_FREQCORR_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.FREQCORR.reg; -} - -static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, - hri_rtcmode1_count_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; - tmp |= RTC_MODE1_COUNT_COUNT(data); - ((Rtc *)hw)->MODE1.COUNT.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.COUNT.reg; -} - -static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp &= ~RTC_MODE1_PER_PER_Msk; - tmp |= RTC_MODE1_PER_PER(data); - ((Rtc *)hw)->MODE1.PER.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) -{ - uint16_t tmp; - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.PER.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.PER.reg; -} - -static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, - hri_rtcmode1_comp_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) -{ - uint16_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp &= ~RTC_MODE1_COMP_COMP_Msk; - tmp |= RTC_MODE1_COMP_COMP(data); - ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, - hri_rtcmode1_comp_reg_t mask) -{ - uint16_t tmp; - tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE1.COMP[index].reg; -} - -static inline void hri_rtcmode1_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.GP[index].reg |= RTC_GP_GP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_gp_reg_t hri_rtcmode1_get_GP_GP_bf(const void *const hw, uint8_t index, - hri_rtcmode1_gp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.GP[index].reg; - tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - tmp = ((Rtc *)hw)->MODE1.GP[index].reg; - tmp &= ~RTC_GP_GP_Msk; - tmp |= RTC_GP_GP(data); - ((Rtc *)hw)->MODE1.GP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.GP[index].reg &= ~RTC_GP_GP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); - ((Rtc *)hw)->MODE1.GP[index].reg ^= RTC_GP_GP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_gp_reg_t hri_rtcmode1_read_GP_GP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.GP[index].reg; - tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.GP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_gp_reg_t hri_rtcmode1_get_GP_reg(const void *const hw, uint8_t index, - hri_rtcmode1_gp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.GP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.GP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.GP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtcmode1_gp_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.GP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_gp_reg_t hri_rtcmode1_read_GP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE1.GP[index].reg; -} - -static inline void hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL0; - tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL1; - tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL2; - tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL3; - tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_TAMLVL4; - tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC0; - tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC1; - tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC2; - tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC3; - tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_DEBNC4; - tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(const void *const hw, - hri_rtcmode1_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; - tmp |= RTC_TAMPCTRL_IN0ACT(data); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(const void *const hw, - hri_rtcmode1_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; - tmp |= RTC_TAMPCTRL_IN1ACT(data); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(const void *const hw, - hri_rtcmode1_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; - tmp |= RTC_TAMPCTRL_IN2ACT(data); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(const void *const hw, - hri_rtcmode1_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; - tmp |= RTC_TAMPCTRL_IN3ACT(data); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(const void *const hw, - hri_rtcmode1_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; - tmp |= RTC_TAMPCTRL_IN4ACT(data); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_TAMPCTRL_reg(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_get_TAMPCTRL_reg(const void *const hw, - hri_rtcmode1_tampctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_TAMPCTRL_reg(const void *const hw, hri_rtcmode1_tampctrl_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPCTRL_reg(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPCTRL_reg(const void *const hw, hri_rtcmode1_tampctrl_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPCTRL.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampctrl_reg_t hri_rtcmode1_read_TAMPCTRL_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.TAMPCTRL.reg; -} - -static inline void hri_rtcmode1_set_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPID_TAMPID0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID0; - tmp |= value << RTC_TAMPID_TAMPID0_Pos; - ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPID0; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPID_TAMPID1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID1; - tmp |= value << RTC_TAMPID_TAMPID1_Pos; - ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPID1; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPID_TAMPID2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID2; - tmp |= value << RTC_TAMPID_TAMPID2_Pos; - ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPID2; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPID_TAMPID3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID3; - tmp |= value << RTC_TAMPID_TAMPID3_Pos; - ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPID3; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPID_TAMPID4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPID4; - tmp |= value << RTC_TAMPID_TAMPID4_Pos; - ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPID4; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg |= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_rtcmode1_get_TAMPID_TAMPEVT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; - return (bool)tmp; -} - -static inline void hri_rtcmode1_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp &= ~RTC_TAMPID_TAMPEVT; - tmp |= value << RTC_TAMPID_TAMPEVT_Pos; - ((Rtc *)hw)->MODE1.TAMPID.reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(const void *const hw) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_set_TAMPID_reg(const void *const hw, hri_rtcmode1_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampid_reg_t hri_rtcmode1_get_TAMPID_reg(const void *const hw, - hri_rtcmode1_tampid_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TAMPID.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_TAMPID_reg(const void *const hw, hri_rtcmode1_tampid_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_TAMPID_reg(const void *const hw, hri_rtcmode1_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_TAMPID_reg(const void *const hw, hri_rtcmode1_tampid_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.TAMPID.reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_tampid_reg_t hri_rtcmode1_read_TAMPID_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.TAMPID.reg; -} - -static inline void hri_rtcmode1_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.BKUP[index].reg |= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_bkup_reg_t hri_rtcmode1_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, - hri_rtcmode1_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t data) -{ - uint32_t tmp; - RTC_CRITICAL_SECTION_ENTER(); - tmp = ((Rtc *)hw)->MODE1.BKUP[index].reg; - tmp &= ~RTC_BKUP_BKUP_Msk; - tmp |= RTC_BKUP_BKUP(data); - ((Rtc *)hw)->MODE1.BKUP[index].reg = tmp; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_bkup_reg_t hri_rtcmode1_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.BKUP[index].reg; - tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; - return tmp; -} - -static inline void hri_rtcmode1_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.BKUP[index].reg |= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_bkup_reg_t hri_rtcmode1_get_BKUP_reg(const void *const hw, uint8_t index, - hri_rtcmode1_bkup_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.BKUP[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_rtcmode1_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t data) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.BKUP[index].reg = data; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.BKUP[index].reg &= ~mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_rtcmode1_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtcmode1_bkup_reg_t mask) -{ - RTC_CRITICAL_SECTION_ENTER(); - ((Rtc *)hw)->MODE1.BKUP[index].reg ^= mask; - RTC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_rtcmode1_bkup_reg_t hri_rtcmode1_read_BKUP_reg(const void *const hw, uint8_t index) -{ - return ((Rtc *)hw)->MODE1.BKUP[index].reg; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos; -} - -static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw) -{ - return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos; -} - -static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, - hri_rtcmode1_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const hw, - hri_rtcmode1_timestamp_reg_t mask) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw) -{ - hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); - return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const hw, - hri_rtcmode1_timestamp_reg_t mask) -{ - uint32_t tmp; - tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg; - tmp &= mask; - return tmp; -} - -static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw) -{ - return ((Rtc *)hw)->MODE1.TIMESTAMP.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_RTC_D51_H_INCLUDED */ -#endif /* _SAMD51_RTC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_sdhc_d51.h b/atmel-samd/asf4/samd51/hri/hri_sdhc_d51.h deleted file mode 100644 index 2095b6682..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_sdhc_d51.h +++ /dev/null @@ -1,9878 +0,0 @@ -/** - * \file - * - * \brief SAM SDHC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_SDHC_COMPONENT_ -#ifndef _HRI_SDHC_D51_H_INCLUDED_ -#define _HRI_SDHC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SDHC_CRITICAL_SECTIONS) -#define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SDHC_CRITICAL_SECTION_ENTER() -#define SDHC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_sdhc_acesr_reg_t; -typedef uint16_t hri_sdhc_bcr_reg_t; -typedef uint16_t hri_sdhc_bsr_reg_t; -typedef uint16_t hri_sdhc_ccr_reg_t; -typedef uint16_t hri_sdhc_cr_reg_t; -typedef uint16_t hri_sdhc_eisier_reg_t; -typedef uint16_t hri_sdhc_eister_reg_t; -typedef uint16_t hri_sdhc_eistr_reg_t; -typedef uint16_t hri_sdhc_feraces_reg_t; -typedef uint16_t hri_sdhc_fereis_reg_t; -typedef uint16_t hri_sdhc_hc2r_reg_t; -typedef uint16_t hri_sdhc_hcvr_reg_t; -typedef uint16_t hri_sdhc_nisier_reg_t; -typedef uint16_t hri_sdhc_nister_reg_t; -typedef uint16_t hri_sdhc_nistr_reg_t; -typedef uint16_t hri_sdhc_pvr_reg_t; -typedef uint16_t hri_sdhc_sisr_reg_t; -typedef uint16_t hri_sdhc_tmr_reg_t; -typedef uint32_t hri_sdhc_acr_reg_t; -typedef uint32_t hri_sdhc_arg1r_reg_t; -typedef uint32_t hri_sdhc_asar_reg_t; -typedef uint32_t hri_sdhc_bdpr_reg_t; -typedef uint32_t hri_sdhc_ca0r_reg_t; -typedef uint32_t hri_sdhc_ca1r_reg_t; -typedef uint32_t hri_sdhc_cacr_reg_t; -typedef uint32_t hri_sdhc_cc2r_reg_t; -typedef uint32_t hri_sdhc_mccar_reg_t; -typedef uint32_t hri_sdhc_psr_reg_t; -typedef uint32_t hri_sdhc_rr_reg_t; -typedef uint32_t hri_sdhc_ssar_reg_t; -typedef uint8_t hri_sdhc_aesr_reg_t; -typedef uint8_t hri_sdhc_bgcr_reg_t; -typedef uint8_t hri_sdhc_dbgr_reg_t; -typedef uint8_t hri_sdhc_hc1r_reg_t; -typedef uint8_t hri_sdhc_mc1r_reg_t; -typedef uint8_t hri_sdhc_mc2r_reg_t; -typedef uint8_t hri_sdhc_pcr_reg_t; -typedef uint8_t hri_sdhc_srr_reg_t; -typedef uint8_t hri_sdhc_tcr_reg_t; -typedef uint8_t hri_sdhc_wcr_reg_t; - -static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos; - return tmp; -} - -static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk; - tmp |= SDHC_SSAR_CMD23_ARG2(data); - ((Sdhc *)hw)->SSAR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos; - return tmp; -} - -static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos; - return tmp; -} - -static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp &= ~SDHC_SSAR_ADDR_Msk; - tmp |= SDHC_SSAR_ADDR(data); - ((Sdhc *)hw)->SSAR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos; - return tmp; -} - -static inline void hri_sdhc_set_SSAR_CMD23_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_SSAR_CMD23_reg(const void *const hw, hri_sdhc_ssar_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SSAR_CMD23_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SSAR_CMD23_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_reg(const void *const hw) -{ - return ((Sdhc *)hw)->SSAR.reg; -} - -static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->SSAR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SSAR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->SSAR.reg; -} - -static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_LEDCTRL; - tmp |= value << SDHC_HC1R_LEDCTRL_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_DW; - tmp |= value << SDHC_HC1R_DW_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_HSEN; - tmp |= value << SDHC_HC1R_HSEN_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_CARDDTL; - tmp |= value << SDHC_HC1R_CARDDTL_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_CARDDSEL; - tmp |= value << SDHC_HC1R_CARDDSEL_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_EMMC_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_EMMC_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_EMMC_DW_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_EMMC_DW) >> SDHC_HC1R_EMMC_DW_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_EMMC_DW_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_EMMC_DW; - tmp |= value << SDHC_HC1R_EMMC_DW_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_EMMC_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_EMMC_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_EMMC_DW_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_EMMC_DW; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_EMMC_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_EMMC_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC1R_EMMC_HSEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_EMMC_HSEN) >> SDHC_HC1R_EMMC_HSEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC1R_EMMC_HSEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_EMMC_HSEN; - tmp |= value << SDHC_HC1R_EMMC_HSEN_Pos; - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_EMMC_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_EMMC_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_EMMC_HSEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_DMASEL_Msk; - tmp |= SDHC_HC1R_DMASEL(data); - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC1R_EMMC_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_EMMC_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_EMMC_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_EMMC_DMASEL(mask)) >> SDHC_HC1R_EMMC_DMASEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC1R_EMMC_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= ~SDHC_HC1R_EMMC_DMASEL_Msk; - tmp |= SDHC_HC1R_EMMC_DMASEL(data); - ((Sdhc *)hw)->HC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_EMMC_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_EMMC_DMASEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_EMMC_DMASEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp = (tmp & SDHC_HC1R_EMMC_DMASEL_Msk) >> SDHC_HC1R_EMMC_DMASEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->HC1R.reg; -} - -static inline void hri_sdhc_set_HC1R_EMMC_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_EMMC_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->HC1R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_HC1R_EMMC_reg(const void *const hw, hri_sdhc_hc1r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC1R_EMMC_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC1R_EMMC_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC1R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_EMMC_reg(const void *const hw) -{ - return ((Sdhc *)hw)->HC1R.reg; -} - -static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_STPBGR; - tmp |= value << SDHC_BGCR_STPBGR_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_CONTR; - tmp |= value << SDHC_BGCR_CONTR_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_RWCTRL; - tmp |= value << SDHC_BGCR_RWCTRL_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_INTBG; - tmp |= value << SDHC_BGCR_INTBG_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_EMMC_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_EMMC_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_EMMC_STPBGR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_EMMC_STPBGR) >> SDHC_BGCR_EMMC_STPBGR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_EMMC_STPBGR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_EMMC_STPBGR; - tmp |= value << SDHC_BGCR_EMMC_STPBGR_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_EMMC_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_EMMC_STPBGR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_EMMC_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_EMMC_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_BGCR_EMMC_CONTR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp = (tmp & SDHC_BGCR_EMMC_CONTR) >> SDHC_BGCR_EMMC_CONTR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_BGCR_EMMC_CONTR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= ~SDHC_BGCR_EMMC_CONTR; - tmp |= value << SDHC_BGCR_EMMC_CONTR_Pos; - ((Sdhc *)hw)->BGCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_EMMC_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_EMMC_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_EMMC_CONTR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BGCR.reg; -} - -static inline void hri_sdhc_set_BGCR_EMMC_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_EMMC_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->BGCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BGCR_EMMC_reg(const void *const hw, hri_sdhc_bgcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BGCR_EMMC_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BGCR_EMMC_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BGCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_EMMC_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BGCR.reg; -} - -static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CMDC; - tmp |= value << SDHC_NISTR_CMDC_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_TRFC; - tmp |= value << SDHC_NISTR_TRFC_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_BLKGE; - tmp |= value << SDHC_NISTR_BLKGE_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_DMAINT; - tmp |= value << SDHC_NISTR_DMAINT_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_BWRRDY; - tmp |= value << SDHC_NISTR_BWRRDY_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_BRDRDY; - tmp |= value << SDHC_NISTR_BRDRDY_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CINS; - tmp |= value << SDHC_NISTR_CINS_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CREM; - tmp |= value << SDHC_NISTR_CREM_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_CINT; - tmp |= value << SDHC_NISTR_CINT_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_ERRINT; - tmp |= value << SDHC_NISTR_ERRINT_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_EMMC_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_EMMC_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_EMMC_CMDC) >> SDHC_NISTR_EMMC_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_EMMC_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_EMMC_CMDC; - tmp |= value << SDHC_NISTR_EMMC_CMDC_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_EMMC_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_EMMC_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_EMMC_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_EMMC_TRFC) >> SDHC_NISTR_EMMC_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_EMMC_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_EMMC_TRFC; - tmp |= value << SDHC_NISTR_EMMC_TRFC_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_EMMC_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_EMMC_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_EMMC_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_EMMC_BLKGE) >> SDHC_NISTR_EMMC_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_EMMC_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_EMMC_BLKGE; - tmp |= value << SDHC_NISTR_EMMC_BLKGE_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_EMMC_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_EMMC_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_EMMC_DMAINT) >> SDHC_NISTR_EMMC_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_EMMC_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_EMMC_DMAINT; - tmp |= value << SDHC_NISTR_EMMC_DMAINT_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_EMMC_BWRRDY) >> SDHC_NISTR_EMMC_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_EMMC_BWRRDY; - tmp |= value << SDHC_NISTR_EMMC_BWRRDY_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_EMMC_BRDRDY) >> SDHC_NISTR_EMMC_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_EMMC_BRDRDY; - tmp |= value << SDHC_NISTR_EMMC_BRDRDY_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_EMMC_BOOTAR; - tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_EMMC_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTR_EMMC_ERRINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp = (tmp & SDHC_NISTR_EMMC_ERRINT) >> SDHC_NISTR_EMMC_ERRINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTR_EMMC_ERRINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= ~SDHC_NISTR_EMMC_ERRINT; - tmp |= value << SDHC_NISTR_EMMC_ERRINT_Pos; - ((Sdhc *)hw)->NISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_ERRINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISTR.reg; -} - -static inline void hri_sdhc_set_NISTR_EMMC_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_EMMC_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISTR_EMMC_reg(const void *const hw, hri_sdhc_nistr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTR_EMMC_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTR_EMMC_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_EMMC_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISTR.reg; -} - -static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDTEO; - tmp |= value << SDHC_EISTR_CMDTEO_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDCRC; - tmp |= value << SDHC_EISTR_CMDCRC_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDEND; - tmp |= value << SDHC_EISTR_CMDEND_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CMDIDX; - tmp |= value << SDHC_EISTR_CMDIDX_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_DATTEO; - tmp |= value << SDHC_EISTR_DATTEO_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_DATCRC; - tmp |= value << SDHC_EISTR_DATCRC_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_DATEND; - tmp |= value << SDHC_EISTR_DATEND_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_CURLIM; - tmp |= value << SDHC_EISTR_CURLIM_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_ACMD; - tmp |= value << SDHC_EISTR_ACMD_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_ADMA; - tmp |= value << SDHC_EISTR_ADMA_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_CMDTEO) >> SDHC_EISTR_EMMC_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_CMDTEO; - tmp |= value << SDHC_EISTR_EMMC_CMDTEO_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_CMDCRC) >> SDHC_EISTR_EMMC_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_CMDCRC; - tmp |= value << SDHC_EISTR_EMMC_CMDCRC_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_CMDEND) >> SDHC_EISTR_EMMC_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_CMDEND; - tmp |= value << SDHC_EISTR_EMMC_CMDEND_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_CMDIDX) >> SDHC_EISTR_EMMC_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_CMDIDX; - tmp |= value << SDHC_EISTR_EMMC_CMDIDX_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_DATTEO) >> SDHC_EISTR_EMMC_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_DATTEO; - tmp |= value << SDHC_EISTR_EMMC_DATTEO_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_DATCRC) >> SDHC_EISTR_EMMC_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_DATCRC; - tmp |= value << SDHC_EISTR_EMMC_DATCRC_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_DATEND) >> SDHC_EISTR_EMMC_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_DATEND; - tmp |= value << SDHC_EISTR_EMMC_DATEND_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_CURLIM) >> SDHC_EISTR_EMMC_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_CURLIM; - tmp |= value << SDHC_EISTR_EMMC_CURLIM_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_ACMD) >> SDHC_EISTR_EMMC_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_ACMD; - tmp |= value << SDHC_EISTR_EMMC_ACMD_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_ADMA) >> SDHC_EISTR_EMMC_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_ADMA; - tmp |= value << SDHC_EISTR_EMMC_ADMA_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= ~SDHC_EISTR_EMMC_BOOTAE; - tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos; - ((Sdhc *)hw)->EISTR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISTR.reg; -} - -static inline void hri_sdhc_set_EISTR_EMMC_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_EMMC_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISTR_EMMC_reg(const void *const hw, hri_sdhc_eistr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTR_EMMC_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTR_EMMC_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_EMMC_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISTR.reg; -} - -static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CMDC; - tmp |= value << SDHC_NISTER_CMDC_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_TRFC; - tmp |= value << SDHC_NISTER_TRFC_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_BLKGE; - tmp |= value << SDHC_NISTER_BLKGE_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_DMAINT; - tmp |= value << SDHC_NISTER_DMAINT_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_BWRRDY; - tmp |= value << SDHC_NISTER_BWRRDY_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_BRDRDY; - tmp |= value << SDHC_NISTER_BRDRDY_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CINS; - tmp |= value << SDHC_NISTER_CINS_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CREM; - tmp |= value << SDHC_NISTER_CREM_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_CINT; - tmp |= value << SDHC_NISTER_CINT_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_EMMC_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_EMMC_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_EMMC_CMDC) >> SDHC_NISTER_EMMC_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_EMMC_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_EMMC_CMDC; - tmp |= value << SDHC_NISTER_EMMC_CMDC_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_EMMC_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_EMMC_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_EMMC_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_EMMC_TRFC) >> SDHC_NISTER_EMMC_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_EMMC_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_EMMC_TRFC; - tmp |= value << SDHC_NISTER_EMMC_TRFC_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_EMMC_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_EMMC_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_EMMC_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_EMMC_BLKGE) >> SDHC_NISTER_EMMC_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_EMMC_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_EMMC_BLKGE; - tmp |= value << SDHC_NISTER_EMMC_BLKGE_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_EMMC_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_EMMC_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_EMMC_DMAINT) >> SDHC_NISTER_EMMC_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_EMMC_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_EMMC_DMAINT; - tmp |= value << SDHC_NISTER_EMMC_DMAINT_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_EMMC_BWRRDY) >> SDHC_NISTER_EMMC_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_EMMC_BWRRDY; - tmp |= value << SDHC_NISTER_EMMC_BWRRDY_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_EMMC_BRDRDY) >> SDHC_NISTER_EMMC_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_EMMC_BRDRDY; - tmp |= value << SDHC_NISTER_EMMC_BRDRDY_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= ~SDHC_NISTER_EMMC_BOOTAR; - tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos; - ((Sdhc *)hw)->NISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISTER.reg; -} - -static inline void hri_sdhc_set_NISTER_EMMC_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_EMMC_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISTER_EMMC_reg(const void *const hw, hri_sdhc_nister_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISTER_EMMC_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISTER_EMMC_reg(const void *const hw, hri_sdhc_nister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISTER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_EMMC_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISTER.reg; -} - -static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDTEO; - tmp |= value << SDHC_EISTER_CMDTEO_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDCRC; - tmp |= value << SDHC_EISTER_CMDCRC_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDEND; - tmp |= value << SDHC_EISTER_CMDEND_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CMDIDX; - tmp |= value << SDHC_EISTER_CMDIDX_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_DATTEO; - tmp |= value << SDHC_EISTER_DATTEO_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_DATCRC; - tmp |= value << SDHC_EISTER_DATCRC_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_DATEND; - tmp |= value << SDHC_EISTER_DATEND_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_CURLIM; - tmp |= value << SDHC_EISTER_CURLIM_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_ACMD; - tmp |= value << SDHC_EISTER_ACMD_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_ADMA; - tmp |= value << SDHC_EISTER_ADMA_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_CMDTEO) >> SDHC_EISTER_EMMC_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_CMDTEO; - tmp |= value << SDHC_EISTER_EMMC_CMDTEO_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_CMDCRC) >> SDHC_EISTER_EMMC_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_CMDCRC; - tmp |= value << SDHC_EISTER_EMMC_CMDCRC_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_CMDEND) >> SDHC_EISTER_EMMC_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_CMDEND; - tmp |= value << SDHC_EISTER_EMMC_CMDEND_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_CMDIDX) >> SDHC_EISTER_EMMC_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_CMDIDX; - tmp |= value << SDHC_EISTER_EMMC_CMDIDX_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_DATTEO) >> SDHC_EISTER_EMMC_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_DATTEO; - tmp |= value << SDHC_EISTER_EMMC_DATTEO_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_DATCRC) >> SDHC_EISTER_EMMC_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_DATCRC; - tmp |= value << SDHC_EISTER_EMMC_DATCRC_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_DATEND) >> SDHC_EISTER_EMMC_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_DATEND; - tmp |= value << SDHC_EISTER_EMMC_DATEND_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_CURLIM) >> SDHC_EISTER_EMMC_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_CURLIM; - tmp |= value << SDHC_EISTER_EMMC_CURLIM_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_ACMD) >> SDHC_EISTER_EMMC_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_ACMD; - tmp |= value << SDHC_EISTER_EMMC_ACMD_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_ADMA) >> SDHC_EISTER_EMMC_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_ADMA; - tmp |= value << SDHC_EISTER_EMMC_ADMA_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= ~SDHC_EISTER_EMMC_BOOTAE; - tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos; - ((Sdhc *)hw)->EISTER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISTER.reg; -} - -static inline void hri_sdhc_set_EISTER_EMMC_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_EMMC_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISTER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISTER_EMMC_reg(const void *const hw, hri_sdhc_eister_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISTER_EMMC_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISTER_EMMC_reg(const void *const hw, hri_sdhc_eister_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISTER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_EMMC_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISTER.reg; -} - -static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CMDC; - tmp |= value << SDHC_NISIER_CMDC_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_TRFC; - tmp |= value << SDHC_NISIER_TRFC_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_BLKGE; - tmp |= value << SDHC_NISIER_BLKGE_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_DMAINT; - tmp |= value << SDHC_NISIER_DMAINT_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_BWRRDY; - tmp |= value << SDHC_NISIER_BWRRDY_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_BRDRDY; - tmp |= value << SDHC_NISIER_BRDRDY_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CINS; - tmp |= value << SDHC_NISIER_CINS_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CREM; - tmp |= value << SDHC_NISIER_CREM_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_CINT; - tmp |= value << SDHC_NISIER_CINT_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_EMMC_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_EMMC_CMDC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_EMMC_CMDC) >> SDHC_NISIER_EMMC_CMDC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_EMMC_CMDC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_EMMC_CMDC; - tmp |= value << SDHC_NISIER_EMMC_CMDC_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_EMMC_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_CMDC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_EMMC_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_EMMC_TRFC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_EMMC_TRFC) >> SDHC_NISIER_EMMC_TRFC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_EMMC_TRFC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_EMMC_TRFC; - tmp |= value << SDHC_NISIER_EMMC_TRFC_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_EMMC_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_TRFC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_EMMC_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_EMMC_BLKGE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_EMMC_BLKGE) >> SDHC_NISIER_EMMC_BLKGE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_EMMC_BLKGE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_EMMC_BLKGE; - tmp |= value << SDHC_NISIER_EMMC_BLKGE_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BLKGE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_EMMC_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_EMMC_DMAINT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_EMMC_DMAINT) >> SDHC_NISIER_EMMC_DMAINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_EMMC_DMAINT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_EMMC_DMAINT; - tmp |= value << SDHC_NISIER_EMMC_DMAINT_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_DMAINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_EMMC_BWRRDY) >> SDHC_NISIER_EMMC_BWRRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_EMMC_BWRRDY; - tmp |= value << SDHC_NISIER_EMMC_BWRRDY_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BWRRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_EMMC_BRDRDY) >> SDHC_NISIER_EMMC_BRDRDY_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_EMMC_BRDRDY; - tmp |= value << SDHC_NISIER_EMMC_BRDRDY_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BRDRDY; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= ~SDHC_NISIER_EMMC_BOOTAR; - tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos; - ((Sdhc *)hw)->NISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISIER.reg; -} - -static inline void hri_sdhc_set_NISIER_EMMC_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_EMMC_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->NISIER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_NISIER_EMMC_reg(const void *const hw, hri_sdhc_nisier_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_NISIER_EMMC_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_NISIER_EMMC_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->NISIER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_EMMC_reg(const void *const hw) -{ - return ((Sdhc *)hw)->NISIER.reg; -} - -static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDTEO; - tmp |= value << SDHC_EISIER_CMDTEO_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDCRC; - tmp |= value << SDHC_EISIER_CMDCRC_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDEND; - tmp |= value << SDHC_EISIER_CMDEND_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CMDIDX; - tmp |= value << SDHC_EISIER_CMDIDX_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_DATTEO; - tmp |= value << SDHC_EISIER_DATTEO_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_DATCRC; - tmp |= value << SDHC_EISIER_DATCRC_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_DATEND; - tmp |= value << SDHC_EISIER_DATEND_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_CURLIM; - tmp |= value << SDHC_EISIER_CURLIM_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_ACMD; - tmp |= value << SDHC_EISIER_ACMD_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_ADMA; - tmp |= value << SDHC_EISIER_ADMA_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_CMDTEO) >> SDHC_EISIER_EMMC_CMDTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_CMDTEO; - tmp |= value << SDHC_EISIER_EMMC_CMDTEO_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_CMDTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_CMDCRC) >> SDHC_EISIER_EMMC_CMDCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_CMDCRC; - tmp |= value << SDHC_EISIER_EMMC_CMDCRC_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_CMDCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_CMDEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_CMDEND) >> SDHC_EISIER_EMMC_CMDEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_CMDEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_CMDEND; - tmp |= value << SDHC_EISIER_EMMC_CMDEND_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_CMDEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_CMDIDX) >> SDHC_EISIER_EMMC_CMDIDX_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_CMDIDX; - tmp |= value << SDHC_EISIER_EMMC_CMDIDX_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_CMDIDX; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_DATTEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_DATTEO) >> SDHC_EISIER_EMMC_DATTEO_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_DATTEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_DATTEO; - tmp |= value << SDHC_EISIER_EMMC_DATTEO_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_DATTEO; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_DATCRC_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_DATCRC) >> SDHC_EISIER_EMMC_DATCRC_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_DATCRC_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_DATCRC; - tmp |= value << SDHC_EISIER_EMMC_DATCRC_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_DATCRC; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_DATEND_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_DATEND) >> SDHC_EISIER_EMMC_DATEND_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_DATEND_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_DATEND; - tmp |= value << SDHC_EISIER_EMMC_DATEND_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_DATEND; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_CURLIM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_CURLIM) >> SDHC_EISIER_EMMC_CURLIM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_CURLIM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_CURLIM; - tmp |= value << SDHC_EISIER_EMMC_CURLIM_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_CURLIM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_ACMD_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_ACMD) >> SDHC_EISIER_EMMC_ACMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_ACMD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_ACMD; - tmp |= value << SDHC_EISIER_EMMC_ACMD_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_ACMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_ADMA_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_ADMA) >> SDHC_EISIER_EMMC_ADMA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_ADMA_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_ADMA; - tmp |= value << SDHC_EISIER_EMMC_ADMA_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_ADMA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= ~SDHC_EISIER_EMMC_BOOTAE; - tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos; - ((Sdhc *)hw)->EISIER.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISIER.reg; -} - -static inline void hri_sdhc_set_EISIER_EMMC_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_EMMC_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->EISIER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_EISIER_EMMC_reg(const void *const hw, hri_sdhc_eisier_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_EISIER_EMMC_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_EISIER_EMMC_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->EISIER.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_EMMC_reg(const void *const hw) -{ - return ((Sdhc *)hw)->EISIER.reg; -} - -static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_VS18EN; - tmp |= value << SDHC_HC2R_VS18EN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_EXTUN; - tmp |= value << SDHC_HC2R_EXTUN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_SLCKSEL; - tmp |= value << SDHC_HC2R_SLCKSEL_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_ASINTEN; - tmp |= value << SDHC_HC2R_ASINTEN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_PVALEN; - tmp |= value << SDHC_HC2R_PVALEN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_EMMC_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_EMMC_EXTUN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EMMC_EXTUN) >> SDHC_HC2R_EMMC_EXTUN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_EMMC_EXTUN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_EMMC_EXTUN; - tmp |= value << SDHC_HC2R_EMMC_EXTUN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_EXTUN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EMMC_SLCKSEL) >> SDHC_HC2R_EMMC_SLCKSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_EMMC_SLCKSEL; - tmp |= value << SDHC_HC2R_EMMC_SLCKSEL_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_SLCKSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_EMMC_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_HC2R_EMMC_PVALEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EMMC_PVALEN) >> SDHC_HC2R_EMMC_PVALEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_HC2R_EMMC_PVALEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_EMMC_PVALEN; - tmp |= value << SDHC_HC2R_EMMC_PVALEN_Pos; - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_PVALEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_UHSMS_Msk; - tmp |= SDHC_HC2R_UHSMS(data); - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_DRVSEL_Msk; - tmp |= SDHC_HC2R_DRVSEL(data); - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk; - tmp |= SDHC_HC2R_EMMC_HS200EN(data); - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EMMC_DRVSEL(mask)) >> SDHC_HC2R_EMMC_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= ~SDHC_HC2R_EMMC_DRVSEL_Msk; - tmp |= SDHC_HC2R_EMMC_DRVSEL(data); - ((Sdhc *)hw)->HC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp = (tmp & SDHC_HC2R_EMMC_DRVSEL_Msk) >> SDHC_HC2R_EMMC_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->HC2R.reg; -} - -static inline void hri_sdhc_set_HC2R_EMMC_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HC2R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_HC2R_EMMC_reg(const void *const hw, hri_sdhc_hc2r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_HC2R_EMMC_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_HC2R_EMMC_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->HC2R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_reg(const void *const hw) -{ - return ((Sdhc *)hw)->HC2R.reg; -} - -static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->FERACES.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->FEREIS.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC2R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BSR.reg; - tmp &= ~SDHC_BSR_BLOCKSIZE_Msk; - tmp |= SDHC_BSR_BLOCKSIZE(data); - ((Sdhc *)hw)->BSR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BSR.reg; - tmp &= ~SDHC_BSR_BOUNDARY_Msk; - tmp |= SDHC_BSR_BOUNDARY(data); - ((Sdhc *)hw)->BSR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BSR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BSR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BSR.reg; -} - -static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BCR.reg; - tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BCR.reg; - tmp &= ~SDHC_BCR_BCNT_Msk; - tmp |= SDHC_BCR_BCNT(data); - ((Sdhc *)hw)->BCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BCR.reg; - tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->BCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BCR.reg; -} - -static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos; - return tmp; -} - -static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp &= ~SDHC_ARG1R_ARG_Msk; - tmp |= SDHC_ARG1R_ARG(data); - ((Sdhc *)hw)->ARG1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos; - return tmp; -} - -static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ARG1R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ARG1R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->ARG1R.reg; -} - -static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_DMAEN; - tmp |= value << SDHC_TMR_DMAEN_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_BCEN; - tmp |= value << SDHC_TMR_BCEN_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_DTDSEL; - tmp |= value << SDHC_TMR_DTDSEL_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_MSBSEL; - tmp |= value << SDHC_TMR_MSBSEL_Pos; - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos; - return tmp; -} - -static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= ~SDHC_TMR_ACMDEN_Msk; - tmp |= SDHC_TMR_ACMDEN(data); - ((Sdhc *)hw)->TMR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos; - return tmp; -} - -static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->TMR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TMR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->TMR.reg; -} - -static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDCCEN; - tmp |= value << SDHC_CR_CMDCCEN_Pos; - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDICEN; - tmp |= value << SDHC_CR_CMDICEN_Pos; - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_DPSEL; - tmp |= value << SDHC_CR_DPSEL_Pos; - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_RESPTYP_Msk; - tmp |= SDHC_CR_RESPTYP(data); - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDTYP_Msk; - tmp |= SDHC_CR_CMDTYP(data); - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= ~SDHC_CR_CMDIDX_Msk; - tmp |= SDHC_CR_CMDIDX(data); - ((Sdhc *)hw)->CR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CR.reg; -} - -static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos; - return tmp; -} - -static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp &= ~SDHC_BDPR_BUFDATA_Msk; - tmp |= SDHC_BDPR_BUFDATA(data); - ((Sdhc *)hw)->BDPR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos; - return tmp; -} - -static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->BDPR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->BDPR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->BDPR.reg; -} - -static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PCR.reg; - tmp &= ~SDHC_PCR_SDBPWR; - tmp |= value << SDHC_PCR_SDBPWR_Pos; - ((Sdhc *)hw)->PCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PCR.reg; - tmp &= ~SDHC_PCR_SDBVSEL_Msk; - tmp |= SDHC_PCR_SDBVSEL(data); - ((Sdhc *)hw)->PCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->PCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->PCR.reg; -} - -static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= ~SDHC_WCR_WKENCINT; - tmp |= value << SDHC_WCR_WKENCINT_Pos; - ((Sdhc *)hw)->WCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= ~SDHC_WCR_WKENCINS; - tmp |= value << SDHC_WCR_WKENCINS_Pos; - ((Sdhc *)hw)->WCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= ~SDHC_WCR_WKENCREM; - tmp |= value << SDHC_WCR_WKENCREM_Pos; - ((Sdhc *)hw)->WCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->WCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->WCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->WCR.reg; -} - -static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_INTCLKEN; - tmp |= value << SDHC_CCR_INTCLKEN_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_INTCLKS; - tmp |= value << SDHC_CCR_INTCLKS_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_SDCLKEN; - tmp |= value << SDHC_CCR_SDCLKEN_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_CLKGSEL; - tmp |= value << SDHC_CCR_CLKGSEL_Pos; - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_USDCLKFSEL_Msk; - tmp |= SDHC_CCR_USDCLKFSEL(data); - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= ~SDHC_CCR_SDCLKFSEL_Msk; - tmp |= SDHC_CCR_SDCLKFSEL(data); - ((Sdhc *)hw)->CCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->CCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CCR.reg; -} - -static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->TCR.reg; - tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->TCR.reg; - tmp &= ~SDHC_TCR_DTCVAL_Msk; - tmp |= SDHC_TCR_DTCVAL(data); - ((Sdhc *)hw)->TCR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->TCR.reg; - tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->TCR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->TCR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->TCR.reg; -} - -static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= ~SDHC_SRR_SWRSTALL; - tmp |= value << SDHC_SRR_SWRSTALL_Pos; - ((Sdhc *)hw)->SRR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= ~SDHC_SRR_SWRSTCMD; - tmp |= value << SDHC_SRR_SWRSTCMD_Pos; - ((Sdhc *)hw)->SRR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= ~SDHC_SRR_SWRSTDAT; - tmp |= value << SDHC_SRR_SWRSTDAT_Pos; - ((Sdhc *)hw)->SRR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->SRR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->SRR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->SRR.reg; -} - -static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index, - hri_sdhc_asar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos; - return tmp; -} - -static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp &= ~SDHC_ASAR_ADMASA_Msk; - tmp |= SDHC_ASAR_ADMASA(data); - ((Sdhc *)hw)->ASAR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos; - return tmp; -} - -static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ASAR[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ASAR[index].reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index) -{ - return ((Sdhc *)hw)->ASAR[index].reg; -} - -static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= ~SDHC_PVR_CLKGSEL; - tmp |= value << SDHC_PVR_CLKGSEL_Pos; - ((Sdhc *)hw)->PVR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, - hri_sdhc_pvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= ~SDHC_PVR_SDCLKFSEL_Msk; - tmp |= SDHC_PVR_SDCLKFSEL(data); - ((Sdhc *)hw)->PVR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index, - hri_sdhc_pvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) -{ - uint16_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= ~SDHC_PVR_DRVSEL_Msk; - tmp |= SDHC_PVR_DRVSEL(data); - ((Sdhc *)hw)->PVR[index].reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos; - return tmp; -} - -static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->PVR[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->PVR[index].reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index) -{ - return ((Sdhc *)hw)->PVR[index].reg; -} - -static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_DDR; - tmp |= value << SDHC_MC1R_DDR_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_OPD; - tmp |= value << SDHC_MC1R_OPD_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_BOOTA; - tmp |= value << SDHC_MC1R_BOOTA_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_RSTN; - tmp |= value << SDHC_MC1R_RSTN_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_FCD; - tmp |= value << SDHC_MC1R_FCD_Pos; - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= ~SDHC_MC1R_CMDTYP_Msk; - tmp |= SDHC_MC1R_CMDTYP(data); - ((Sdhc *)hw)->MC1R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos; - return tmp; -} - -static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->MC1R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->MC1R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->MC1R.reg; -} - -static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ACR.reg; - tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos; - return tmp; -} - -static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->ACR.reg; - tmp &= ~SDHC_ACR_BMAX_Msk; - tmp |= SDHC_ACR_BMAX(data); - ((Sdhc *)hw)->ACR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ACR.reg; - tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos; - return tmp; -} - -static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->ACR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->ACR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->ACR.reg; -} - -static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CC2R.reg; - tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CC2R.reg; - tmp &= ~SDHC_CC2R_FSDCLKD; - tmp |= value << SDHC_CC2R_FSDCLKD_Pos; - ((Sdhc *)hw)->CC2R.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CC2R.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CC2R.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CC2R.reg; -} - -static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CACR.reg; - tmp &= ~SDHC_CACR_CAPWREN; - tmp |= value << SDHC_CACR_CAPWREN_Pos; - ((Sdhc *)hw)->CACR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos; - return tmp; -} - -static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data) -{ - uint32_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->CACR.reg; - tmp &= ~SDHC_CACR_KEY_Msk; - tmp |= SDHC_CACR_KEY(data); - ((Sdhc *)hw)->CACR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask); - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos; - return tmp; -} - -static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CACR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->CACR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CACR.reg; -} - -static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->DBGR.reg; - tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos; - return (bool)tmp; -} - -static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SDHC_CRITICAL_SECTION_ENTER(); - tmp = ((Sdhc *)hw)->DBGR.reg; - tmp &= ~SDHC_DBGR_NIDBG; - tmp |= value << SDHC_DBGR_NIDBG_Pos; - ((Sdhc *)hw)->DBGR.reg = tmp; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg |= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->DBGR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg = data; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg &= ~mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) -{ - SDHC_CRITICAL_SECTION_ENTER(); - ((Sdhc *)hw)->DBGR.reg ^= mask; - SDHC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->DBGR.reg; -} - -static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) -{ - return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos; -} - -static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index) -{ - return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos; -} - -static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->RR[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index) -{ - return ((Sdhc *)hw)->RR[index].reg; -} - -static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos; -} - -static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos; -} - -static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos; -} - -static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos; -} - -static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos; -} - -static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos; -} - -static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos; -} - -static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos; -} - -static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos; -} - -static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos; -} - -static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos; -} - -static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos; -} - -static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw) -{ - return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->PSR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->PSR.reg; -} - -static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos; -} - -static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos; -} - -static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw) -{ - return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos; -} - -static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->ACESR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->ACESR.reg; -} - -static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos; -} - -static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos; -} - -static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CA0R.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CA0R.reg; -} - -static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos; -} - -static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw) -{ - return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->CA1R.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw) -{ - return ((Sdhc *)hw)->CA1R.reg; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw) -{ - return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sdhc *)hw)->MCCAR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->MCCAR.reg; -} - -static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw) -{ - return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask) -{ - return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw) -{ - return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sdhc *)hw)->AESR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->AESR.reg; -} - -static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw) -{ - return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos; -} - -static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->SISR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->SISR.reg; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw) -{ - return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sdhc *)hw)->HCVR.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw) -{ - return ((Sdhc *)hw)->HCVR.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SDHC_D51_H_INCLUDED */ -#endif /* _SAMD51_SDHC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_sercom_d51.h b/atmel-samd/asf4/samd51/hri/hri_sercom_d51.h deleted file mode 100644 index 9e09d23f3..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_sercom_d51.h +++ /dev/null @@ -1,8591 +0,0 @@ -/** - * \file - * - * \brief SAM SERCOM - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_SERCOM_COMPONENT_ -#ifndef _HRI_SERCOM_D51_H_INCLUDED_ -#define _HRI_SERCOM_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) -#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SERCOM_CRITICAL_SECTION_ENTER() -#define SERCOM_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_sercomi2cm_status_reg_t; -typedef uint16_t hri_sercomi2cs_length_reg_t; -typedef uint16_t hri_sercomi2cs_status_reg_t; -typedef uint16_t hri_sercomspi_length_reg_t; -typedef uint16_t hri_sercomspi_status_reg_t; -typedef uint16_t hri_sercomusart_baud_reg_t; -typedef uint16_t hri_sercomusart_length_reg_t; -typedef uint16_t hri_sercomusart_status_reg_t; -typedef uint32_t hri_sercomi2cm_addr_reg_t; -typedef uint32_t hri_sercomi2cm_baud_reg_t; -typedef uint32_t hri_sercomi2cm_ctrla_reg_t; -typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; -typedef uint32_t hri_sercomi2cm_ctrlc_reg_t; -typedef uint32_t hri_sercomi2cm_data_reg_t; -typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; -typedef uint32_t hri_sercomi2cs_addr_reg_t; -typedef uint32_t hri_sercomi2cs_ctrla_reg_t; -typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; -typedef uint32_t hri_sercomi2cs_ctrlc_reg_t; -typedef uint32_t hri_sercomi2cs_data_reg_t; -typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; -typedef uint32_t hri_sercomspi_addr_reg_t; -typedef uint32_t hri_sercomspi_ctrla_reg_t; -typedef uint32_t hri_sercomspi_ctrlb_reg_t; -typedef uint32_t hri_sercomspi_ctrlc_reg_t; -typedef uint32_t hri_sercomspi_data_reg_t; -typedef uint32_t hri_sercomspi_syncbusy_reg_t; -typedef uint32_t hri_sercomusart_ctrla_reg_t; -typedef uint32_t hri_sercomusart_ctrlb_reg_t; -typedef uint32_t hri_sercomusart_ctrlc_reg_t; -typedef uint32_t hri_sercomusart_data_reg_t; -typedef uint32_t hri_sercomusart_syncbusy_reg_t; -typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; -typedef uint8_t hri_sercomi2cm_intenset_reg_t; -typedef uint8_t hri_sercomi2cm_intflag_reg_t; -typedef uint8_t hri_sercomi2cs_intenset_reg_t; -typedef uint8_t hri_sercomi2cs_intflag_reg_t; -typedef uint8_t hri_sercomspi_baud_reg_t; -typedef uint8_t hri_sercomspi_dbgctrl_reg_t; -typedef uint8_t hri_sercomspi_intenset_reg_t; -typedef uint8_t hri_sercomspi_intflag_reg_t; -typedef uint8_t hri_sercomusart_dbgctrl_reg_t; -typedef uint8_t hri_sercomusart_intenset_reg_t; -typedef uint8_t hri_sercomusart_intflag_reg_t; -typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; -typedef uint8_t hri_sercomusart_rxpl_reg_t; - -static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) -{ - while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) -{ - return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; -} - -static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; -} - -static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; -} - -static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; - } -} - -static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; -} - -static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; -} - -static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; -} - -static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; - } -} - -static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; -} - -static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; -} - -static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; -} - -static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; - } -} - -static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; -} - -static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; -} - -static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; -} - -static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; - } -} - -static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; -} - -static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; -} - -static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; - } else { - ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; - } -} - -static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; -} - -static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = mask; -} - -static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, - hri_sercomspi_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.INTENSET.reg; -} - -static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) -{ - ((Sercom *)hw)->SPI.INTENSET.reg = data; - ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; -} - -static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTENCLR.reg = mask; -} - -static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; -} - -static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; -} - -static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; -} - -static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; -} - -static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; -} - -static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; -} - -static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; -} - -static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; -} - -static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; -} - -static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; -} - -static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, - hri_sercomspi_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.INTFLAG.reg; -} - -static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) -{ - ((Sercom *)hw)->SPI.INTFLAG.reg = mask; -} - -static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_ENABLE; - tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_IBON; - tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_CPHA; - tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_CPOL; - tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DORD; - tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; - tmp |= SERCOM_SPI_CTRLA_MODE(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; - tmp |= SERCOM_SPI_CTRLA_DOPO(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; - tmp |= SERCOM_SPI_CTRLA_DIPO(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; - tmp |= SERCOM_SPI_CTRLA_FORM(data); - ((Sercom *)hw)->SPI.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); - ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, - hri_sercomspi_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.CTRLA.reg; -} - -static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; - tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_SSDE; - tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_MSSEN; - tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_RXEN; - tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; - tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; - tmp |= SERCOM_SPI_CTRLB_AMODE(data); - ((Sercom *)hw)->SPI.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, - hri_sercomspi_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.CTRLB.reg; -} - -static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp &= ~SERCOM_SPI_CTRLC_DATA32B; - tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos; - ((Sercom *)hw)->SPI.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const hw, - hri_sercomspi_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk; - tmp |= SERCOM_SPI_CTRLC_ICSPACE(data); - ((Sercom *)hw)->SPI.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const hw, - hri_sercomspi_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.CTRLC.reg; -} - -static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomspi_baud_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; - tmp |= SERCOM_SPI_BAUD_BAUD(data); - ((Sercom *)hw)->SPI.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.BAUD.reg; -} - -static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp &= ~SERCOM_SPI_LENGTH_LENEN; - tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos; - ((Sercom *)hw)->SPI.LENGTH.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const hw, - hri_sercomspi_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk; - tmp |= SERCOM_SPI_LENGTH_LEN(data); - ((Sercom *)hw)->SPI.LENGTH.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const hw, - hri_sercomspi_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.LENGTH.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.LENGTH.reg; -} - -static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; - tmp |= SERCOM_SPI_ADDR_ADDR(data); - ((Sercom *)hw)->SPI.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, - hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; - tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); - ((Sercom *)hw)->SPI.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.ADDR.reg; -} - -static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.DATA.reg; -} - -static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, - hri_sercomspi_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.DBGCTRL.reg; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, - hri_sercomspi_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.SYNCBUSY.reg; -} - -static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; -} - -static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos; -} - -static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, - hri_sercomspi_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->SPI.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->SPI.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->SPI.STATUS.reg; -} - -static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; -} - -static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; -} - -static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; -} - -static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; -} - -static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; -} - -static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; - } else { - ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; - } -} - -static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; -} - -static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = mask; -} - -static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, - hri_sercomi2cm_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.INTENSET.reg; -} - -static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) -{ - ((Sercom *)hw)->I2CM.INTENSET.reg = data; - ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; -} - -static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; -} - -static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; -} - -static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; -} - -static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; -} - -static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; -} - -static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, - hri_sercomi2cm_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.INTFLAG.reg; -} - -static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) -{ - ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; -} - -static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_BUSERR; - tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; - tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_RXNACK; - tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; - tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; - tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; - tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; - tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_LENERR; - tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, - hri_sercomi2cm_status_reg_t mask) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; -} - -static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; -} - -static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; - tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); - ((Sercom *)hw)->I2CM.STATUS.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, - hri_sercomi2cm_status_reg_t mask) -{ - uint16_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg |= mask; -} - -static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - return ((Sercom *)hw)->I2CM.STATUS.reg; -} - -static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg = data; -} - -static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; -} - -static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; - tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; - tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; - tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; - tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; - tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; - tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; - tmp |= SERCOM_I2CM_CTRLA_MODE(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; - tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; - tmp |= SERCOM_I2CM_CTRLA_SPEED(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; - tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); - ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, - hri_sercomi2cm_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.CTRLA.reg; -} - -static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_SMEN; - tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_QCEN; - tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; - tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, - hri_sercomi2cm_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; - tmp |= SERCOM_I2CM_CTRLB_CMD(data); - ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, - hri_sercomi2cm_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.CTRLB.reg; -} - -static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; - tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; - tmp &= ~SERCOM_I2CM_CTRLC_DATA32B; - tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos; - ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const hw, - hri_sercomi2cm_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.CTRLC.reg; -} - -static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; - tmp |= SERCOM_I2CM_BAUD_BAUD(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; - tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; - tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; - tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); - ((Sercom *)hw)->I2CM.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, - hri_sercomi2cm_baud_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.BAUD.reg; -} - -static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_LENEN; - tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_HS; - tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; - tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; - tmp |= SERCOM_I2CM_ADDR_ADDR(data); - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; - tmp |= SERCOM_I2CM_ADDR_LEN(data); - ((Sercom *)hw)->I2CM.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, - hri_sercomi2cm_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.ADDR.reg; -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); - tmp = ((Sercom *)hw)->I2CM.DATA.reg; - tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; - tmp |= SERCOM_I2CM_DATA_DATA(data); - ((Sercom *)hw)->I2CM.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.DATA.reg; -} - -static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, - hri_sercomi2cm_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.DBGCTRL.reg; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; -} - -static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, - hri_sercomi2cm_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; -} - -static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD(mask)) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRAC_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_FRAC_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_BAUD_Msk) >> SERCOM_USART_BAUD_FRAC_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; - tmp |= SERCOM_USART_BAUD_FRAC_FP(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD(mask)) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRACFP_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_FRACFP_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_BAUD_Msk) >> SERCOM_USART_BAUD_FRACFP_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; - tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_USARTFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD(mask)) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= ~SERCOM_USART_BAUD_USARTFP_BAUD_Msk; - tmp |= SERCOM_USART_BAUD_USARTFP_BAUD(data); - ((Sercom *)hw)->USART.BAUD.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_USARTFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_USARTFP_BAUD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp = (tmp & SERCOM_USART_BAUD_USARTFP_BAUD_Msk) >> SERCOM_USART_BAUD_USARTFP_BAUD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.BAUD.reg; -} - -static inline void hri_sercomusart_set_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_reg(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRAC_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.BAUD.reg; -} - -static inline void hri_sercomusart_set_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_reg(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_FRACFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.BAUD.reg; -} - -static inline void hri_sercomusart_set_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_reg(const void *const hw, - hri_sercomusart_baud_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.BAUD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_BAUD_USARTFP_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.BAUD.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.BAUD.reg; -} - -static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; -} - -static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; -} - -static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; - } -} - -static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; -} - -static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; -} - -static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; - } -} - -static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; -} - -static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; -} - -static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; -} - -static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; -} - -static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; -} - -static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; -} - -static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; -} - -static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; - } -} - -static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; -} - -static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; -} - -static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; -} - -static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; - } -} - -static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; -} - -static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; -} - -static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; - } else { - ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; - } -} - -static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; -} - -static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) -{ - ((Sercom *)hw)->USART.INTENSET.reg = mask; -} - -static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, - hri_sercomusart_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.INTENSET.reg; -} - -static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) -{ - ((Sercom *)hw)->USART.INTENSET.reg = data; - ((Sercom *)hw)->USART.INTENCLR.reg = ~data; -} - -static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) -{ - ((Sercom *)hw)->USART.INTENCLR.reg = mask; -} - -static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; -} - -static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; -} - -static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; -} - -static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; -} - -static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; -} - -static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; -} - -static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; -} - -static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; -} - -static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; -} - -static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; -} - -static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; -} - -static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; -} - -static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, - hri_sercomusart_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.INTFLAG.reg; -} - -static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) -{ - ((Sercom *)hw)->USART.INTFLAG.reg = mask; -} - -static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_ENABLE; - tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_IBON; - tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_TXINV; - tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RXINV; - tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_CMODE; - tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_CPOL; - tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_DORD; - tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; - tmp |= SERCOM_USART_CTRLA_MODE(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; - tmp |= SERCOM_USART_CTRLA_SAMPR(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; - tmp |= SERCOM_USART_CTRLA_TXPO(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; - tmp |= SERCOM_USART_CTRLA_RXPO(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; - tmp |= SERCOM_USART_CTRLA_SAMPA(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; - tmp |= SERCOM_USART_CTRLA_FORM(data); - ((Sercom *)hw)->USART.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); - ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, - hri_sercomusart_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.CTRLA.reg; -} - -static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_SBMODE; - tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_COLDEN; - tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_SFDE; - tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_ENC; - tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_PMODE; - tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_TXEN; - tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_RXEN; - tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; - tmp |= SERCOM_USART_CTRLB_CHSIZE(data); - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk; - tmp |= SERCOM_USART_CTRLB_LINCMD(data); - ((Sercom *)hw)->USART.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, - hri_sercomusart_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLB.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.CTRLB.reg; -} - -static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_INACK; - tmp |= value << SERCOM_USART_CTRLC_INACK_Pos; - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_DSNACK; - tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos; - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; - tmp |= SERCOM_USART_CTRLC_GTIME(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk; - tmp |= SERCOM_USART_CTRLC_BRKLEN(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk; - tmp |= SERCOM_USART_CTRLC_HDRDLY(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk; - tmp |= SERCOM_USART_CTRLC_MAXITER(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk; - tmp |= SERCOM_USART_CTRLC_DATA32B(data); - ((Sercom *)hw)->USART.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, - hri_sercomusart_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.CTRLC.reg; -} - -static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, - hri_sercomusart_rxpl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; - tmp |= SERCOM_USART_RXPL_RXPL(data); - ((Sercom *)hw)->USART.RXPL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, - hri_sercomusart_rxpl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXPL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.RXPL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.RXPL.reg; -} - -static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const hw, - hri_sercomusart_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp &= ~SERCOM_USART_LENGTH_LEN_Msk; - tmp |= SERCOM_USART_LENGTH_LEN(data); - ((Sercom *)hw)->USART.LENGTH.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const hw, - hri_sercomusart_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk; - tmp |= SERCOM_USART_LENGTH_LENEN(data); - ((Sercom *)hw)->USART.LENGTH.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos; - return tmp; -} - -static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const hw, - hri_sercomusart_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.LENGTH.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.LENGTH.reg; -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.DATA.reg; - tmp &= ~SERCOM_USART_DATA_DATA_Msk; - tmp |= SERCOM_USART_DATA_DATA(data); - ((Sercom *)hw)->USART.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.DATA.reg; -} - -static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; - return (bool)tmp; -} - -static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) -{ - uint8_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; - tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; - ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, - hri_sercomusart_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.DBGCTRL.reg; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos; -} - -static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, - hri_sercomusart_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.SYNCBUSY.reg; -} - -static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const hw, - hri_sercomusart_rxerrcnt_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->USART.RXERRCNT.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.RXERRCNT.reg; -} - -static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw) -{ - return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos; -} - -static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, - hri_sercomusart_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->USART.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->USART.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->USART.STATUS.reg; -} - -static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; -} - -static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; -} - -static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; -} - -static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; -} - -static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; -} - -static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; -} - -static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; -} - -static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; -} - -static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; - } else { - ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; - } -} - -static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; -} - -static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = mask; -} - -static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, - hri_sercomi2cs_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.INTENSET.reg; -} - -static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) -{ - ((Sercom *)hw)->I2CS.INTENSET.reg = data; - ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; -} - -static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; -} - -static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; -} - -static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; -} - -static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; -} - -static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; -} - -static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; -} - -static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; -} - -static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, - hri_sercomi2cs_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.INTFLAG.reg; -} - -static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) -{ - ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; -} - -static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; - tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; - tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; - tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; - tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; - tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; - tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; - tmp |= SERCOM_I2CS_CTRLA_MODE(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; - tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; - tmp |= SERCOM_I2CS_CTRLA_SPEED(data); - ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, - hri_sercomi2cs_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.CTRLA.reg; -} - -static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_SMEN; - tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_GCMD; - tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; - tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; - tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; - tmp |= SERCOM_I2CS_CTRLB_AMODE(data); - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; - tmp |= SERCOM_I2CS_CTRLB_CMD(data); - ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, - hri_sercomi2cs_ctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.CTRLB.reg; -} - -static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp &= ~SERCOM_I2CS_CTRLC_DATA32B; - tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos; - ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const hw, - hri_sercomi2cs_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk; - tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data); - ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const hw, - hri_sercomi2cs_ctrlc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.CTRLC.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.CTRLC.reg; -} - -static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp &= ~SERCOM_I2CS_LENGTH_LENEN; - tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos; - ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const hw, - hri_sercomi2cs_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data) -{ - uint16_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk; - tmp |= SERCOM_I2CS_LENGTH_LEN(data); - ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const hw, - hri_sercomi2cs_length_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.LENGTH.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.LENGTH.reg; -} - -static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_GENCEN; - tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; - return (bool)tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; - tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; - tmp |= SERCOM_I2CS_ADDR_ADDR(data); - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; - tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); - ((Sercom *)hw)->I2CS.ADDR.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg |= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, - hri_sercomi2cs_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.ADDR.reg; -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; - return tmp; -} - -static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) -{ - uint32_t tmp; - SERCOM_CRITICAL_SECTION_ENTER(); - tmp = ((Sercom *)hw)->I2CS.DATA.reg; - tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; - tmp |= SERCOM_I2CS_DATA_DATA(data); - ((Sercom *)hw)->I2CS.DATA.reg = tmp; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.DATA.reg; -} - -static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.DATA.reg = data; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos; -} - -static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, - hri_sercomi2cs_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; -} - -static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw) -{ - return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos; -} - -static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, - hri_sercomi2cs_status_reg_t mask) -{ - uint16_t tmp; - tmp = ((Sercom *)hw)->I2CS.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) -{ - SERCOM_CRITICAL_SECTION_ENTER(); - ((Sercom *)hw)->I2CS.STATUS.reg = mask; - SERCOM_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) -{ - return ((Sercom *)hw)->I2CS.STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SERCOM_D51_H_INCLUDED */ -#endif /* _SAMD51_SERCOM_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_supc_d51.h b/atmel-samd/asf4/samd51/hri/hri_supc_d51.h deleted file mode 100644 index 90797c85b..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_supc_d51.h +++ /dev/null @@ -1,2311 +0,0 @@ -/** - * \file - * - * \brief SAM SUPC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_SUPC_COMPONENT_ -#ifndef _HRI_SUPC_D51_H_INCLUDED_ -#define _HRI_SUPC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) -#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define SUPC_CRITICAL_SECTION_ENTER() -#define SUPC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_supc_bbps_reg_t; -typedef uint32_t hri_supc_bkin_reg_t; -typedef uint32_t hri_supc_bkout_reg_t; -typedef uint32_t hri_supc_bod12_reg_t; -typedef uint32_t hri_supc_bod33_reg_t; -typedef uint32_t hri_supc_intenset_reg_t; -typedef uint32_t hri_supc_intflag_reg_t; -typedef uint32_t hri_supc_status_reg_t; -typedef uint32_t hri_supc_vref_reg_t; -typedef uint32_t hri_supc_vreg_reg_t; - -static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; -} - -static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; -} - -static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; - } -} - -static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; -} - -static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; -} - -static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; -} - -static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; - } -} - -static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; -} - -static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; -} - -static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; -} - -static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; - } -} - -static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; -} - -static inline void hri_supc_set_INTEN_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; -} - -static inline bool hri_supc_get_INTEN_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12RDY) >> SUPC_INTENSET_BOD12RDY_Pos; -} - -static inline void hri_supc_write_INTEN_BOD12RDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12RDY; - } -} - -static inline void hri_supc_clear_INTEN_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12RDY; -} - -static inline void hri_supc_set_INTEN_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; -} - -static inline bool hri_supc_get_INTEN_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD12DET) >> SUPC_INTENSET_BOD12DET_Pos; -} - -static inline void hri_supc_write_INTEN_BOD12DET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD12DET; - } -} - -static inline void hri_supc_clear_INTEN_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD12DET; -} - -static inline void hri_supc_set_INTEN_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; -} - -static inline bool hri_supc_get_INTEN_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B12SRDY) >> SUPC_INTENSET_B12SRDY_Pos; -} - -static inline void hri_supc_write_INTEN_B12SRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B12SRDY; - } -} - -static inline void hri_supc_clear_INTEN_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B12SRDY; -} - -static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; -} - -static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; -} - -static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; - } -} - -static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; -} - -static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; -} - -static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; -} - -static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; - } else { - ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; - } -} - -static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; -} - -static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - ((Supc *)hw)->INTENSET.reg = mask; -} - -static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) -{ - return ((Supc *)hw)->INTENSET.reg; -} - -static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) -{ - ((Supc *)hw)->INTENSET.reg = data; - ((Supc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) -{ - ((Supc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; -} - -static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; -} - -static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; -} - -static inline bool hri_supc_get_INTFLAG_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; -} - -static inline bool hri_supc_get_INTFLAG_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; -} - -static inline void hri_supc_clear_INTFLAG_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; -} - -static inline bool hri_supc_get_INTFLAG_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; -} - -static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; -} - -static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; -} - -static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; -} - -static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; -} - -static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; -} - -static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; -} - -static inline bool hri_supc_get_interrupt_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12RDY) >> SUPC_INTFLAG_BOD12RDY_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD12RDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12RDY; -} - -static inline bool hri_supc_get_interrupt_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD12DET) >> SUPC_INTFLAG_BOD12DET_Pos; -} - -static inline void hri_supc_clear_interrupt_BOD12DET_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD12DET; -} - -static inline bool hri_supc_get_interrupt_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B12SRDY) >> SUPC_INTFLAG_B12SRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_B12SRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B12SRDY; -} - -static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; -} - -static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; -} - -static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; -} - -static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) -{ - ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; -} - -static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) -{ - return ((Supc *)hw)->INTFLAG.reg; -} - -static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) -{ - ((Supc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_ENABLE; - tmp |= value << SUPC_BOD33_ENABLE_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_STDBYCFG; - tmp |= value << SUPC_BOD33_STDBYCFG_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_RUNSTDBY; - tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_RUNHIB; - tmp |= value << SUPC_BOD33_RUNHIB_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_RUNBKUP; - tmp |= value << SUPC_BOD33_RUNBKUP_Pos; - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_ACTION_Msk; - tmp |= SUPC_BOD33_ACTION(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_HYST_Msk; - tmp |= SUPC_BOD33_HYST(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_PSEL_Msk; - tmp |= SUPC_BOD33_PSEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_LEVEL_Msk; - tmp |= SUPC_BOD33_LEVEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= ~SUPC_BOD33_VBATLEVEL_Msk; - tmp |= SUPC_BOD33_VBATLEVEL(data); - ((Supc *)hw)->BOD33.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD33.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD33.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) -{ - return ((Supc *)hw)->BOD33.reg; -} - -static inline void hri_supc_set_BOD12_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ENABLE) >> SUPC_BOD12_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_ENABLE; - tmp |= value << SUPC_BOD12_ENABLE_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_HYST_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_HYST) >> SUPC_BOD12_HYST_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_HYST_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_HYST; - tmp |= value << SUPC_BOD12_HYST_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_HYST_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_HYST; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_STDBYCFG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_STDBYCFG) >> SUPC_BOD12_STDBYCFG_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_STDBYCFG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_STDBYCFG; - tmp |= value << SUPC_BOD12_STDBYCFG_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_STDBYCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_STDBYCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_RUNSTDBY) >> SUPC_BOD12_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_RUNSTDBY; - tmp |= value << SUPC_BOD12_RUNSTDBY_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BOD12_ACTCFG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ACTCFG) >> SUPC_BOD12_ACTCFG_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BOD12_ACTCFG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_ACTCFG; - tmp |= value << SUPC_BOD12_ACTCFG_Pos; - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_ACTCFG_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTCFG; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ACTION(mask)) >> SUPC_BOD12_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_ACTION_Msk; - tmp |= SUPC_BOD12_ACTION(data); - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_ACTION_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_ACTION(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_ACTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_ACTION_Msk) >> SUPC_BOD12_ACTION_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_PSEL(mask)) >> SUPC_BOD12_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_PSEL_Msk; - tmp |= SUPC_BOD12_PSEL(data); - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_PSEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_PSEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_PSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_PSEL_Msk) >> SUPC_BOD12_PSEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= SUPC_BOD12_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_LEVEL(mask)) >> SUPC_BOD12_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_write_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= ~SUPC_BOD12_LEVEL_Msk; - tmp |= SUPC_BOD12_LEVEL(data); - ((Supc *)hw)->BOD12.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~SUPC_BOD12_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_LEVEL_bf(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= SUPC_BOD12_LEVEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_LEVEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp = (tmp & SUPC_BOD12_LEVEL_Msk) >> SUPC_BOD12_LEVEL_Pos; - return tmp; -} - -static inline void hri_supc_set_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_get_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BOD12.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BOD12_reg(const void *const hw, hri_supc_bod12_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BOD12.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bod12_reg_t hri_supc_read_BOD12_reg(const void *const hw) -{ - return ((Supc *)hw)->BOD12.reg; -} - -static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_ENABLE; - tmp |= value << SUPC_VREG_ENABLE_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_SEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_SEL; - tmp |= value << SUPC_VREG_SEL_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_RUNBKUP; - tmp |= value << SUPC_VREG_RUNBKUP_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_VSEN; - tmp |= value << SUPC_VREG_VSEN_Pos; - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; - return tmp; -} - -static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREG.reg; - tmp &= ~SUPC_VREG_VSPER_Msk; - tmp |= SUPC_VREG_VSPER(data); - ((Supc *)hw)->VREG.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; - return tmp; -} - -static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREG.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) -{ - return ((Supc *)hw)->VREG.reg; -} - -static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_TSEN; - tmp |= value << SUPC_VREF_TSEN_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_VREFOE; - tmp |= value << SUPC_VREF_VREFOE_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_TSSEL; - tmp |= value << SUPC_VREF_TSSEL_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_RUNSTDBY; - tmp |= value << SUPC_VREF_RUNSTDBY_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_ONDEMAND; - tmp |= value << SUPC_VREF_ONDEMAND_Pos; - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; - return tmp; -} - -static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->VREF.reg; - tmp &= ~SUPC_VREF_SEL_Msk; - tmp |= SUPC_VREF_SEL(data); - ((Supc *)hw)->VREF.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; - return tmp; -} - -static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->VREF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->VREF.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) -{ - return ((Supc *)hw)->VREF.reg; -} - -static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= ~SUPC_BBPS_CONF; - tmp |= value << SUPC_BBPS_CONF_Pos; - ((Supc *)hw)->BBPS.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; - return (bool)tmp; -} - -static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= ~SUPC_BBPS_WAKEEN; - tmp |= value << SUPC_BBPS_WAKEEN_Pos; - ((Supc *)hw)->BBPS.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BBPS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BBPS.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) -{ - return ((Supc *)hw)->BBPS.reg; -} - -static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_EN_Msk; - tmp |= SUPC_BKOUT_EN(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_CLR_Msk; - tmp |= SUPC_BKOUT_CLR(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_SET_Msk; - tmp |= SUPC_BKOUT_SET(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; - return tmp; -} - -static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) -{ - uint32_t tmp; - SUPC_CRITICAL_SECTION_ENTER(); - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= ~SUPC_BKOUT_RTCTGL_Msk; - tmp |= SUPC_BKOUT_RTCTGL(data); - ((Supc *)hw)->BKOUT.reg = tmp; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; - return tmp; -} - -static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg |= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKOUT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg = data; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg &= ~mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) -{ - SUPC_CRITICAL_SECTION_ENTER(); - ((Supc *)hw)->BKOUT.reg ^= mask; - SUPC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) -{ - return ((Supc *)hw)->BKOUT.reg; -} - -static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; -} - -static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; -} - -static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; -} - -static inline bool hri_supc_get_STATUS_BOD12RDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12RDY) >> SUPC_STATUS_BOD12RDY_Pos; -} - -static inline bool hri_supc_get_STATUS_BOD12DET_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD12DET) >> SUPC_STATUS_BOD12DET_Pos; -} - -static inline bool hri_supc_get_STATUS_B12SRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B12SRDY) >> SUPC_STATUS_B12SRDY_Pos; -} - -static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; -} - -static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) -{ - return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; -} - -static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) -{ - return ((Supc *)hw)->STATUS.reg; -} - -static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) -{ - return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; -} - -static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) -{ - return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; -} - -static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) -{ - uint32_t tmp; - tmp = ((Supc *)hw)->BKIN.reg; - tmp &= mask; - return tmp; -} - -static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) -{ - return ((Supc *)hw)->BKIN.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_SUPC_D51_H_INCLUDED */ -#endif /* _SAMD51_SUPC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_tal_d51.h b/atmel-samd/asf4/samd51/hri/hri_tal_d51.h deleted file mode 100644 index cacb98a2d..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_tal_d51.h +++ /dev/null @@ -1,10867 +0,0 @@ -/** - * \file - * - * \brief SAM TAL - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_TAL_COMPONENT_ -#ifndef _HRI_TAL_D51_H_INCLUDED_ -#define _HRI_TAL_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TAL_CRITICAL_SECTIONS) -#define TAL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TAL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TAL_CRITICAL_SECTION_ENTER() -#define TAL_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_tal_brkstatus_reg_t; -typedef uint16_t hri_tal_evctrl_reg_t; -typedef uint16_t hri_tal_irqmon_reg_t; -typedef uint32_t hri_tal_cpuirqs_reg_t; -typedef uint32_t hri_tal_dmacpusel0_reg_t; -typedef uint32_t hri_tal_dmacpusel1_reg_t; -typedef uint32_t hri_tal_eiccpusel0_reg_t; -typedef uint32_t hri_tal_evcpusel0_reg_t; -typedef uint32_t hri_tal_intcpusel0_reg_t; -typedef uint32_t hri_tal_intcpusel1_reg_t; -typedef uint32_t hri_tal_intcpusel2_reg_t; -typedef uint32_t hri_tal_intcpusel3_reg_t; -typedef uint32_t hri_tal_intcpusel4_reg_t; -typedef uint32_t hri_tal_intcpusel5_reg_t; -typedef uint32_t hri_tal_intcpusel6_reg_t; -typedef uint32_t hri_tal_intcpusel7_reg_t; -typedef uint32_t hri_tal_intcpusel8_reg_t; -typedef uint32_t hri_tal_irqtrig_reg_t; -typedef uint32_t hri_tal_sflag_reg_t; -typedef uint32_t hri_tal_smask_reg_t; -typedef uint32_t hri_talcpuirqs_cpuirqs_reg_t; -typedef uint32_t hri_talsmasks_smask_reg_t; -typedef uint8_t hri_tal_ctictrla_reg_t; -typedef uint8_t hri_tal_ctimask_reg_t; -typedef uint8_t hri_tal_ctrla_reg_t; -typedef uint8_t hri_tal_extctrl_reg_t; -typedef uint8_t hri_tal_globmask_reg_t; -typedef uint8_t hri_tal_halt_reg_t; -typedef uint8_t hri_tal_intenset_reg_t; -typedef uint8_t hri_tal_intflag_reg_t; -typedef uint8_t hri_tal_intstatus_reg_t; -typedef uint8_t hri_tal_restart_reg_t; -typedef uint8_t hri_tal_sflagclrr_reg_t; -typedef uint8_t hri_talctis_ctictrla_reg_t; -typedef uint8_t hri_talctis_ctimask_reg_t; - -static inline void hri_talsmasks_set_SMASK_IPS0_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS0_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS0) >> TAL_SMASK_IPS0_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS0_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS0; - tmp |= value << TAL_SMASK_IPS0_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS0_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS0_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS1_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS1_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS1) >> TAL_SMASK_IPS1_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS1_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS1; - tmp |= value << TAL_SMASK_IPS1_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS1_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS1_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS2_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS2; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS2_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS2) >> TAL_SMASK_IPS2_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS2_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS2; - tmp |= value << TAL_SMASK_IPS2_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS2_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS2; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS2_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS2; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS3_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS3; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS3_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS3) >> TAL_SMASK_IPS3_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS3_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS3; - tmp |= value << TAL_SMASK_IPS3_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS3_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS3; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS3_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS3; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS4_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS4; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS4_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS4) >> TAL_SMASK_IPS4_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS4_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS4; - tmp |= value << TAL_SMASK_IPS4_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS4_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS4; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS4_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS4; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS5_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS5; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS5_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS5) >> TAL_SMASK_IPS5_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS5_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS5; - tmp |= value << TAL_SMASK_IPS5_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS5_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS5; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS5_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS5; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS6_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS6; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS6_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS6) >> TAL_SMASK_IPS6_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS6_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS6; - tmp |= value << TAL_SMASK_IPS6_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS6_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS6; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS6_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS6; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS7_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS7; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS7_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS7) >> TAL_SMASK_IPS7_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS7_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS7; - tmp |= value << TAL_SMASK_IPS7_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS7_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS7; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS7_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS7; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS8_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS8; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS8_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS8) >> TAL_SMASK_IPS8_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS8_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS8; - tmp |= value << TAL_SMASK_IPS8_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS8_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS8; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS8_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS8; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS9_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS9; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS9_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS9) >> TAL_SMASK_IPS9_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS9_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS9; - tmp |= value << TAL_SMASK_IPS9_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS9_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS9; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS9_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS9; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS10_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS10; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS10_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS10) >> TAL_SMASK_IPS10_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS10_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS10; - tmp |= value << TAL_SMASK_IPS10_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS10_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS10; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS10_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS10; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS11_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS11; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS11_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS11) >> TAL_SMASK_IPS11_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS11_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS11; - tmp |= value << TAL_SMASK_IPS11_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS11_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS11; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS11_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS11; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS12_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS12; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS12_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS12) >> TAL_SMASK_IPS12_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS12_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS12; - tmp |= value << TAL_SMASK_IPS12_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS12_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS12; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS12_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS12; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS13_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS13; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS13_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS13) >> TAL_SMASK_IPS13_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS13_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS13; - tmp |= value << TAL_SMASK_IPS13_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS13_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS13; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS13_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS13; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS14_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS14; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS14_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS14) >> TAL_SMASK_IPS14_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS14_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS14; - tmp |= value << TAL_SMASK_IPS14_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS14_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS14; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS14_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS14; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS15_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS15; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS15_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS15) >> TAL_SMASK_IPS15_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS15_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS15; - tmp |= value << TAL_SMASK_IPS15_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS15_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS15; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS15_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS15; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS16_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS16; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS16_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS16) >> TAL_SMASK_IPS16_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS16_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS16; - tmp |= value << TAL_SMASK_IPS16_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS16_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS16; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS16_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS16; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS17_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS17; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS17_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS17) >> TAL_SMASK_IPS17_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS17_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS17; - tmp |= value << TAL_SMASK_IPS17_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS17_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS17; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS17_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS17; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS18_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS18; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS18_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS18) >> TAL_SMASK_IPS18_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS18_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS18; - tmp |= value << TAL_SMASK_IPS18_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS18_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS18; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS18_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS18; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS19_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS19; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS19_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS19) >> TAL_SMASK_IPS19_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS19_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS19; - tmp |= value << TAL_SMASK_IPS19_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS19_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS19; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS19_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS19; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS20_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS20; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS20_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS20) >> TAL_SMASK_IPS20_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS20_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS20; - tmp |= value << TAL_SMASK_IPS20_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS20_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS20; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS20_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS20; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS21_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS21; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS21_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS21) >> TAL_SMASK_IPS21_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS21_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS21; - tmp |= value << TAL_SMASK_IPS21_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS21_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS21; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS21_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS21; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS22_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS22; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS22_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS22) >> TAL_SMASK_IPS22_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS22_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS22; - tmp |= value << TAL_SMASK_IPS22_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS22_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS22; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS22_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS22; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS23_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS23; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS23_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS23) >> TAL_SMASK_IPS23_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS23_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS23; - tmp |= value << TAL_SMASK_IPS23_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS23_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS23; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS23_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS23; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS24_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS24; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS24_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS24) >> TAL_SMASK_IPS24_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS24_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS24; - tmp |= value << TAL_SMASK_IPS24_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS24_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS24; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS24_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS24; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS25_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS25; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS25_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS25) >> TAL_SMASK_IPS25_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS25_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS25; - tmp |= value << TAL_SMASK_IPS25_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS25_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS25; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS25_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS25; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS26_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS26; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS26_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS26) >> TAL_SMASK_IPS26_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS26_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS26; - tmp |= value << TAL_SMASK_IPS26_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS26_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS26; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS26_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS26; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS27_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS27; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS27_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS27) >> TAL_SMASK_IPS27_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS27_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS27; - tmp |= value << TAL_SMASK_IPS27_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS27_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS27; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS27_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS27; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS28_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS28; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS28_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS28) >> TAL_SMASK_IPS28_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS28_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS28; - tmp |= value << TAL_SMASK_IPS28_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS28_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS28; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS28_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS28; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS29_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS29; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS29_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS29) >> TAL_SMASK_IPS29_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS29_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS29; - tmp |= value << TAL_SMASK_IPS29_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS29_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS29; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS29_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS29; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS30_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS30; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS30_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS30) >> TAL_SMASK_IPS30_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS30_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS30; - tmp |= value << TAL_SMASK_IPS30_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS30_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS30; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS30_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS30; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_IPS31_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= TAL_SMASK_IPS31; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talsmasks_get_SMASK_IPS31_bit(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS31) >> TAL_SMASK_IPS31_Pos; - return (bool)tmp; -} - -static inline void hri_talsmasks_write_SMASK_IPS31_bit(const void *const hw, uint8_t index, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS31; - tmp |= value << TAL_SMASK_IPS31_Pos; - ((TalSmasks *)hw)->SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_IPS31_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~TAL_SMASK_IPS31; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_IPS31_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= TAL_SMASK_IPS31; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_set_SMASK_reg(const void *const hw, uint8_t index, hri_tal_smask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_smask_reg_t hri_talsmasks_get_SMASK_reg(const void *const hw, uint8_t index, - hri_tal_smask_reg_t mask) -{ - uint32_t tmp; - tmp = ((TalSmasks *)hw)->SMASK[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_talsmasks_write_SMASK_reg(const void *const hw, uint8_t index, hri_tal_smask_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_clear_SMASK_reg(const void *const hw, uint8_t index, hri_tal_smask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talsmasks_toggle_SMASK_reg(const void *const hw, uint8_t index, hri_tal_smask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalSmasks *)hw)->SMASK[index].reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_smask_reg_t hri_talsmasks_read_SMASK_reg(const void *const hw, uint8_t index) -{ - return ((TalSmasks *)hw)->SMASK[index].reg; -} - -static inline void hri_tal_set_SMASK_IPS0_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS0_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS0) >> TAL_SMASK_IPS0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS0_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS0; - tmp |= value << TAL_SMASK_IPS0_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS0_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS0_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS1_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS1_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS1) >> TAL_SMASK_IPS1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS1_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS1; - tmp |= value << TAL_SMASK_IPS1_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS1_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS1_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS2_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS2; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS2_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS2) >> TAL_SMASK_IPS2_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS2_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS2; - tmp |= value << TAL_SMASK_IPS2_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS2_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS2; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS2_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS2; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS3_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS3; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS3_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS3) >> TAL_SMASK_IPS3_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS3_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS3; - tmp |= value << TAL_SMASK_IPS3_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS3_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS3; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS3_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS3; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS4_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS4; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS4_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS4) >> TAL_SMASK_IPS4_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS4_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS4; - tmp |= value << TAL_SMASK_IPS4_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS4_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS4; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS4_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS4; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS5_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS5; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS5_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS5) >> TAL_SMASK_IPS5_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS5_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS5; - tmp |= value << TAL_SMASK_IPS5_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS5_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS5; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS5_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS5; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS6_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS6; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS6_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS6) >> TAL_SMASK_IPS6_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS6_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS6; - tmp |= value << TAL_SMASK_IPS6_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS6_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS6; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS6_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS6; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS7_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS7; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS7_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS7) >> TAL_SMASK_IPS7_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS7_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS7; - tmp |= value << TAL_SMASK_IPS7_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS7_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS7; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS7_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS7; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS8_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS8; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS8_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS8) >> TAL_SMASK_IPS8_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS8_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS8; - tmp |= value << TAL_SMASK_IPS8_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS8_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS8; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS8_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS8; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS9_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS9; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS9_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS9) >> TAL_SMASK_IPS9_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS9_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS9; - tmp |= value << TAL_SMASK_IPS9_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS9_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS9; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS9_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS9; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS10_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS10; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS10_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS10) >> TAL_SMASK_IPS10_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS10_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS10; - tmp |= value << TAL_SMASK_IPS10_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS10_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS10; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS10_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS10; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS11_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS11; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS11_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS11) >> TAL_SMASK_IPS11_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS11_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS11; - tmp |= value << TAL_SMASK_IPS11_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS11_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS11; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS11_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS11; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS12_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS12; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS12_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS12) >> TAL_SMASK_IPS12_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS12_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS12; - tmp |= value << TAL_SMASK_IPS12_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS12_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS12; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS12_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS12; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS13_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS13; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS13_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS13) >> TAL_SMASK_IPS13_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS13_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS13; - tmp |= value << TAL_SMASK_IPS13_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS13_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS13; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS13_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS13; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS14_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS14; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS14_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS14) >> TAL_SMASK_IPS14_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS14_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS14; - tmp |= value << TAL_SMASK_IPS14_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS14_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS14; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS14_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS14; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS15_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS15; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS15_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS15) >> TAL_SMASK_IPS15_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS15_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS15; - tmp |= value << TAL_SMASK_IPS15_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS15_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS15; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS15_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS15; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS16_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS16; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS16_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS16) >> TAL_SMASK_IPS16_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS16_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS16; - tmp |= value << TAL_SMASK_IPS16_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS16_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS16; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS16_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS16; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS17_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS17; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS17_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS17) >> TAL_SMASK_IPS17_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS17_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS17; - tmp |= value << TAL_SMASK_IPS17_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS17_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS17; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS17_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS17; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS18_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS18; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS18_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS18) >> TAL_SMASK_IPS18_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS18_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS18; - tmp |= value << TAL_SMASK_IPS18_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS18_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS18; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS18_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS18; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS19_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS19; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS19_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS19) >> TAL_SMASK_IPS19_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS19_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS19; - tmp |= value << TAL_SMASK_IPS19_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS19_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS19; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS19_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS19; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS20_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS20; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS20_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS20) >> TAL_SMASK_IPS20_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS20_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS20; - tmp |= value << TAL_SMASK_IPS20_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS20_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS20; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS20_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS20; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS21_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS21; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS21_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS21) >> TAL_SMASK_IPS21_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS21_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS21; - tmp |= value << TAL_SMASK_IPS21_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS21_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS21; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS21_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS21; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS22_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS22; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS22_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS22) >> TAL_SMASK_IPS22_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS22_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS22; - tmp |= value << TAL_SMASK_IPS22_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS22_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS22; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS22_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS22; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS23_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS23; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS23_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS23) >> TAL_SMASK_IPS23_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS23_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS23; - tmp |= value << TAL_SMASK_IPS23_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS23_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS23; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS23_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS23; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS24_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS24; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS24_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS24) >> TAL_SMASK_IPS24_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS24_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS24; - tmp |= value << TAL_SMASK_IPS24_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS24_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS24; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS24_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS24; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS25_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS25; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS25_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS25) >> TAL_SMASK_IPS25_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS25_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS25; - tmp |= value << TAL_SMASK_IPS25_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS25_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS25; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS25_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS25; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS26_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS26; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS26_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS26) >> TAL_SMASK_IPS26_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS26_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS26; - tmp |= value << TAL_SMASK_IPS26_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS26_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS26; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS26_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS26; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS27_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS27; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS27_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS27) >> TAL_SMASK_IPS27_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS27_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS27; - tmp |= value << TAL_SMASK_IPS27_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS27_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS27; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS27_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS27; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS28_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS28; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS28_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS28) >> TAL_SMASK_IPS28_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS28_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS28; - tmp |= value << TAL_SMASK_IPS28_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS28_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS28; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS28_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS28; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS29_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS29; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS29_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS29) >> TAL_SMASK_IPS29_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS29_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS29; - tmp |= value << TAL_SMASK_IPS29_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS29_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS29; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS29_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS29; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS30_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS30; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS30_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS30) >> TAL_SMASK_IPS30_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS30_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS30; - tmp |= value << TAL_SMASK_IPS30_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS30_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS30; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS30_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS30; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_IPS31_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= TAL_SMASK_IPS31; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SMASK_IPS31_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp = (tmp & TAL_SMASK_IPS31) >> TAL_SMASK_IPS31_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SMASK_IPS31_bit(const void *const hw, uint8_t submodule_index, uint8_t index, - bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= ~TAL_SMASK_IPS31; - tmp |= value << TAL_SMASK_IPS31_Pos; - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_IPS31_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~TAL_SMASK_IPS31; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_IPS31_bit(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= TAL_SMASK_IPS31; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_tal_smask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_smask_reg_t hri_tal_get_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_tal_smask_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_tal_smask_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_tal_smask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index, - hri_tal_smask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_smask_reg_t hri_tal_read_SMASK_reg(const void *const hw, uint8_t submodule_index, uint8_t index) -{ - return ((Tal *)hw)->Smasks[submodule_index].SMASK[index].reg; -} - -static inline void hri_tal_set_INTEN_BRK_bit(const void *const hw) -{ - ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_BRK; -} - -static inline bool hri_tal_get_INTEN_BRK_bit(const void *const hw) -{ - return (((Tal *)hw)->INTENSET.reg & TAL_INTENSET_BRK) >> TAL_INTENSET_BRK_Pos; -} - -static inline void hri_tal_write_INTEN_BRK_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_BRK; - } else { - ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_BRK; - } -} - -static inline void hri_tal_clear_INTEN_BRK_bit(const void *const hw) -{ - ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_BRK; -} - -static inline void hri_tal_set_INTEN_IPS0_bit(const void *const hw) -{ - ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_IPS0; -} - -static inline bool hri_tal_get_INTEN_IPS0_bit(const void *const hw) -{ - return (((Tal *)hw)->INTENSET.reg & TAL_INTENSET_IPS0) >> TAL_INTENSET_IPS0_Pos; -} - -static inline void hri_tal_write_INTEN_IPS0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_IPS0; - } else { - ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_IPS0; - } -} - -static inline void hri_tal_clear_INTEN_IPS0_bit(const void *const hw) -{ - ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_IPS0; -} - -static inline void hri_tal_set_INTEN_IPS1_bit(const void *const hw) -{ - ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_IPS1; -} - -static inline bool hri_tal_get_INTEN_IPS1_bit(const void *const hw) -{ - return (((Tal *)hw)->INTENSET.reg & TAL_INTENSET_IPS1) >> TAL_INTENSET_IPS1_Pos; -} - -static inline void hri_tal_write_INTEN_IPS1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_IPS1; - } else { - ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_IPS1; - } -} - -static inline void hri_tal_clear_INTEN_IPS1_bit(const void *const hw) -{ - ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_IPS1; -} - -static inline void hri_tal_set_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t mask) -{ - ((Tal *)hw)->INTENSET.reg = mask; -} - -static inline hri_tal_intenset_reg_t hri_tal_get_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tal_intenset_reg_t hri_tal_read_INTEN_reg(const void *const hw) -{ - return ((Tal *)hw)->INTENSET.reg; -} - -static inline void hri_tal_write_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t data) -{ - ((Tal *)hw)->INTENSET.reg = data; - ((Tal *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_tal_clear_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t mask) -{ - ((Tal *)hw)->INTENCLR.reg = mask; -} - -static inline void hri_tal_set_SFLAG_IPS0_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS0; -} - -static inline bool hri_tal_get_SFLAG_IPS0_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS0) >> TAL_SFLAG_IPS0_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS0_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS0; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS0; - } -} - -static inline void hri_tal_clear_SFLAG_IPS0_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS0; -} - -static inline void hri_tal_set_SFLAG_IPS1_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS1; -} - -static inline bool hri_tal_get_SFLAG_IPS1_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS1) >> TAL_SFLAG_IPS1_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS1_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS1; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS1; - } -} - -static inline void hri_tal_clear_SFLAG_IPS1_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS1; -} - -static inline void hri_tal_set_SFLAG_IPS2_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS2; -} - -static inline bool hri_tal_get_SFLAG_IPS2_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS2) >> TAL_SFLAG_IPS2_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS2_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS2; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS2; - } -} - -static inline void hri_tal_clear_SFLAG_IPS2_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS2; -} - -static inline void hri_tal_set_SFLAG_IPS3_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS3; -} - -static inline bool hri_tal_get_SFLAG_IPS3_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS3) >> TAL_SFLAG_IPS3_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS3_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS3; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS3; - } -} - -static inline void hri_tal_clear_SFLAG_IPS3_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS3; -} - -static inline void hri_tal_set_SFLAG_IPS4_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS4; -} - -static inline bool hri_tal_get_SFLAG_IPS4_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS4) >> TAL_SFLAG_IPS4_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS4_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS4; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS4; - } -} - -static inline void hri_tal_clear_SFLAG_IPS4_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS4; -} - -static inline void hri_tal_set_SFLAG_IPS5_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS5; -} - -static inline bool hri_tal_get_SFLAG_IPS5_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS5) >> TAL_SFLAG_IPS5_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS5_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS5; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS5; - } -} - -static inline void hri_tal_clear_SFLAG_IPS5_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS5; -} - -static inline void hri_tal_set_SFLAG_IPS6_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS6; -} - -static inline bool hri_tal_get_SFLAG_IPS6_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS6) >> TAL_SFLAG_IPS6_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS6_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS6; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS6; - } -} - -static inline void hri_tal_clear_SFLAG_IPS6_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS6; -} - -static inline void hri_tal_set_SFLAG_IPS7_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS7; -} - -static inline bool hri_tal_get_SFLAG_IPS7_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS7) >> TAL_SFLAG_IPS7_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS7_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS7; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS7; - } -} - -static inline void hri_tal_clear_SFLAG_IPS7_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS7; -} - -static inline void hri_tal_set_SFLAG_IPS8_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS8; -} - -static inline bool hri_tal_get_SFLAG_IPS8_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS8) >> TAL_SFLAG_IPS8_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS8_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS8; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS8; - } -} - -static inline void hri_tal_clear_SFLAG_IPS8_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS8; -} - -static inline void hri_tal_set_SFLAG_IPS9_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS9; -} - -static inline bool hri_tal_get_SFLAG_IPS9_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS9) >> TAL_SFLAG_IPS9_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS9_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS9; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS9; - } -} - -static inline void hri_tal_clear_SFLAG_IPS9_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS9; -} - -static inline void hri_tal_set_SFLAG_IPS10_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS10; -} - -static inline bool hri_tal_get_SFLAG_IPS10_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS10) >> TAL_SFLAG_IPS10_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS10_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS10; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS10; - } -} - -static inline void hri_tal_clear_SFLAG_IPS10_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS10; -} - -static inline void hri_tal_set_SFLAG_IPS11_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS11; -} - -static inline bool hri_tal_get_SFLAG_IPS11_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS11) >> TAL_SFLAG_IPS11_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS11_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS11; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS11; - } -} - -static inline void hri_tal_clear_SFLAG_IPS11_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS11; -} - -static inline void hri_tal_set_SFLAG_IPS12_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS12; -} - -static inline bool hri_tal_get_SFLAG_IPS12_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS12) >> TAL_SFLAG_IPS12_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS12_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS12; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS12; - } -} - -static inline void hri_tal_clear_SFLAG_IPS12_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS12; -} - -static inline void hri_tal_set_SFLAG_IPS13_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS13; -} - -static inline bool hri_tal_get_SFLAG_IPS13_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS13) >> TAL_SFLAG_IPS13_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS13_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS13; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS13; - } -} - -static inline void hri_tal_clear_SFLAG_IPS13_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS13; -} - -static inline void hri_tal_set_SFLAG_IPS14_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS14; -} - -static inline bool hri_tal_get_SFLAG_IPS14_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS14) >> TAL_SFLAG_IPS14_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS14_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS14; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS14; - } -} - -static inline void hri_tal_clear_SFLAG_IPS14_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS14; -} - -static inline void hri_tal_set_SFLAG_IPS15_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS15; -} - -static inline bool hri_tal_get_SFLAG_IPS15_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS15) >> TAL_SFLAG_IPS15_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS15_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS15; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS15; - } -} - -static inline void hri_tal_clear_SFLAG_IPS15_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS15; -} - -static inline void hri_tal_set_SFLAG_IPS16_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS16; -} - -static inline bool hri_tal_get_SFLAG_IPS16_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS16) >> TAL_SFLAG_IPS16_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS16_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS16; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS16; - } -} - -static inline void hri_tal_clear_SFLAG_IPS16_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS16; -} - -static inline void hri_tal_set_SFLAG_IPS17_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS17; -} - -static inline bool hri_tal_get_SFLAG_IPS17_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS17) >> TAL_SFLAG_IPS17_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS17_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS17; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS17; - } -} - -static inline void hri_tal_clear_SFLAG_IPS17_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS17; -} - -static inline void hri_tal_set_SFLAG_IPS18_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS18; -} - -static inline bool hri_tal_get_SFLAG_IPS18_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS18) >> TAL_SFLAG_IPS18_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS18_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS18; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS18; - } -} - -static inline void hri_tal_clear_SFLAG_IPS18_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS18; -} - -static inline void hri_tal_set_SFLAG_IPS19_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS19; -} - -static inline bool hri_tal_get_SFLAG_IPS19_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS19) >> TAL_SFLAG_IPS19_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS19_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS19; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS19; - } -} - -static inline void hri_tal_clear_SFLAG_IPS19_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS19; -} - -static inline void hri_tal_set_SFLAG_IPS20_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS20; -} - -static inline bool hri_tal_get_SFLAG_IPS20_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS20) >> TAL_SFLAG_IPS20_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS20_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS20; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS20; - } -} - -static inline void hri_tal_clear_SFLAG_IPS20_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS20; -} - -static inline void hri_tal_set_SFLAG_IPS21_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS21; -} - -static inline bool hri_tal_get_SFLAG_IPS21_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS21) >> TAL_SFLAG_IPS21_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS21_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS21; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS21; - } -} - -static inline void hri_tal_clear_SFLAG_IPS21_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS21; -} - -static inline void hri_tal_set_SFLAG_IPS22_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS22; -} - -static inline bool hri_tal_get_SFLAG_IPS22_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS22) >> TAL_SFLAG_IPS22_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS22_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS22; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS22; - } -} - -static inline void hri_tal_clear_SFLAG_IPS22_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS22; -} - -static inline void hri_tal_set_SFLAG_IPS23_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS23; -} - -static inline bool hri_tal_get_SFLAG_IPS23_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS23) >> TAL_SFLAG_IPS23_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS23_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS23; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS23; - } -} - -static inline void hri_tal_clear_SFLAG_IPS23_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS23; -} - -static inline void hri_tal_set_SFLAG_IPS24_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS24; -} - -static inline bool hri_tal_get_SFLAG_IPS24_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS24) >> TAL_SFLAG_IPS24_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS24_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS24; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS24; - } -} - -static inline void hri_tal_clear_SFLAG_IPS24_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS24; -} - -static inline void hri_tal_set_SFLAG_IPS25_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS25; -} - -static inline bool hri_tal_get_SFLAG_IPS25_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS25) >> TAL_SFLAG_IPS25_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS25_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS25; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS25; - } -} - -static inline void hri_tal_clear_SFLAG_IPS25_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS25; -} - -static inline void hri_tal_set_SFLAG_IPS26_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS26; -} - -static inline bool hri_tal_get_SFLAG_IPS26_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS26) >> TAL_SFLAG_IPS26_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS26_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS26; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS26; - } -} - -static inline void hri_tal_clear_SFLAG_IPS26_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS26; -} - -static inline void hri_tal_set_SFLAG_IPS27_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS27; -} - -static inline bool hri_tal_get_SFLAG_IPS27_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS27) >> TAL_SFLAG_IPS27_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS27_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS27; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS27; - } -} - -static inline void hri_tal_clear_SFLAG_IPS27_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS27; -} - -static inline void hri_tal_set_SFLAG_IPS28_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS28; -} - -static inline bool hri_tal_get_SFLAG_IPS28_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS28) >> TAL_SFLAG_IPS28_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS28_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS28; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS28; - } -} - -static inline void hri_tal_clear_SFLAG_IPS28_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS28; -} - -static inline void hri_tal_set_SFLAG_IPS29_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS29; -} - -static inline bool hri_tal_get_SFLAG_IPS29_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS29) >> TAL_SFLAG_IPS29_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS29_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS29; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS29; - } -} - -static inline void hri_tal_clear_SFLAG_IPS29_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS29; -} - -static inline void hri_tal_set_SFLAG_IPS30_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS30; -} - -static inline bool hri_tal_get_SFLAG_IPS30_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS30) >> TAL_SFLAG_IPS30_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS30_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS30; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS30; - } -} - -static inline void hri_tal_clear_SFLAG_IPS30_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS30; -} - -static inline void hri_tal_set_SFLAG_IPS31_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS31; -} - -static inline bool hri_tal_get_SFLAG_IPS31_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->SFLAG[index].reg & TAL_SFLAG_IPS31) >> TAL_SFLAG_IPS31_Pos; -} - -static inline void hri_tal_write_SFLAG_IPS31_bit(const void *const hw, uint8_t index, bool value) -{ - if (value == 0x0) { - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS31; - } else { - ((Tal *)hw)->SFLAGSET[index].reg = TAL_SFLAG_IPS31; - } -} - -static inline void hri_tal_clear_SFLAG_IPS31_bit(const void *const hw, uint8_t index) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = TAL_SFLAG_IPS31; -} - -static inline void hri_tal_set_SFLAG_reg(const void *const hw, uint8_t index, hri_tal_sflag_reg_t mask) -{ - ((Tal *)hw)->SFLAGSET[index].reg = mask; -} - -static inline hri_tal_sflag_reg_t hri_tal_get_SFLAG_reg(const void *const hw, uint8_t index, hri_tal_sflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->SFLAG[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_tal_sflag_reg_t hri_tal_read_SFLAG_reg(const void *const hw, uint8_t index) -{ - return ((Tal *)hw)->SFLAG[index].reg; -} - -static inline void hri_tal_write_SFLAG_reg(const void *const hw, uint8_t index, hri_tal_sflag_reg_t data) -{ - ((Tal *)hw)->SFLAGSET[index].reg = data; - ((Tal *)hw)->SFLAGCLR[index].reg = ~data; -} - -static inline void hri_tal_clear_SFLAG_reg(const void *const hw, uint8_t index, hri_tal_sflag_reg_t mask) -{ - ((Tal *)hw)->SFLAGCLR[index].reg = mask; -} - -static inline bool hri_tal_get_INTFLAG_BRK_bit(const void *const hw) -{ - return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_BRK) >> TAL_INTFLAG_BRK_Pos; -} - -static inline void hri_tal_clear_INTFLAG_BRK_bit(const void *const hw) -{ - ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_BRK; -} - -static inline bool hri_tal_get_INTFLAG_IPS0_bit(const void *const hw) -{ - return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_IPS0) >> TAL_INTFLAG_IPS0_Pos; -} - -static inline void hri_tal_clear_INTFLAG_IPS0_bit(const void *const hw) -{ - ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_IPS0; -} - -static inline bool hri_tal_get_INTFLAG_IPS1_bit(const void *const hw) -{ - return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_IPS1) >> TAL_INTFLAG_IPS1_Pos; -} - -static inline void hri_tal_clear_INTFLAG_IPS1_bit(const void *const hw) -{ - ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_IPS1; -} - -static inline bool hri_tal_get_interrupt_BRK_bit(const void *const hw) -{ - return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_BRK) >> TAL_INTFLAG_BRK_Pos; -} - -static inline void hri_tal_clear_interrupt_BRK_bit(const void *const hw) -{ - ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_BRK; -} - -static inline bool hri_tal_get_interrupt_IPS0_bit(const void *const hw) -{ - return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_IPS0) >> TAL_INTFLAG_IPS0_Pos; -} - -static inline void hri_tal_clear_interrupt_IPS0_bit(const void *const hw) -{ - ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_IPS0; -} - -static inline bool hri_tal_get_interrupt_IPS1_bit(const void *const hw) -{ - return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_IPS1) >> TAL_INTFLAG_IPS1_Pos; -} - -static inline void hri_tal_clear_interrupt_IPS1_bit(const void *const hw) -{ - ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_IPS1; -} - -static inline hri_tal_intflag_reg_t hri_tal_get_INTFLAG_reg(const void *const hw, hri_tal_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tal_intflag_reg_t hri_tal_read_INTFLAG_reg(const void *const hw) -{ - return ((Tal *)hw)->INTFLAG.reg; -} - -static inline void hri_tal_clear_INTFLAG_reg(const void *const hw, hri_tal_intflag_reg_t mask) -{ - ((Tal *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_tal_write_HALT_reg(const void *const hw, hri_tal_halt_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->HALT.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_write_RESTART_reg(const void *const hw, hri_tal_restart_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->RESTART.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_CTRLA_SWRST_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->CTRLA.reg |= TAL_CTRLA_SWRST; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->CTRLA.reg; - tmp = (tmp & TAL_CTRLA_SWRST) >> TAL_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_tal_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->CTRLA.reg |= TAL_CTRLA_ENABLE; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->CTRLA.reg; - tmp = (tmp & TAL_CTRLA_ENABLE) >> TAL_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->CTRLA.reg; - tmp &= ~TAL_CTRLA_ENABLE; - tmp |= value << TAL_CTRLA_ENABLE_Pos; - ((Tal *)hw)->CTRLA.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->CTRLA.reg &= ~TAL_CTRLA_ENABLE; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->CTRLA.reg ^= TAL_CTRLA_ENABLE; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->CTRLA.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctrla_reg_t hri_tal_get_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->CTRLA.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->CTRLA.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->CTRLA.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctrla_reg_t hri_tal_read_CTRLA_reg(const void *const hw) -{ - return ((Tal *)hw)->CTRLA.reg; -} - -static inline void hri_tal_set_EXTCTRL_ENABLE_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EXTCTRL.reg |= TAL_EXTCTRL_ENABLE; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EXTCTRL_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->EXTCTRL.reg; - tmp = (tmp & TAL_EXTCTRL_ENABLE) >> TAL_EXTCTRL_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EXTCTRL_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EXTCTRL.reg; - tmp &= ~TAL_EXTCTRL_ENABLE; - tmp |= value << TAL_EXTCTRL_ENABLE_Pos; - ((Tal *)hw)->EXTCTRL.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EXTCTRL_ENABLE_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EXTCTRL.reg &= ~TAL_EXTCTRL_ENABLE; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EXTCTRL_ENABLE_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EXTCTRL.reg ^= TAL_EXTCTRL_ENABLE; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EXTCTRL_INV_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EXTCTRL.reg |= TAL_EXTCTRL_INV; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EXTCTRL_INV_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->EXTCTRL.reg; - tmp = (tmp & TAL_EXTCTRL_INV) >> TAL_EXTCTRL_INV_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EXTCTRL_INV_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EXTCTRL.reg; - tmp &= ~TAL_EXTCTRL_INV; - tmp |= value << TAL_EXTCTRL_INV_Pos; - ((Tal *)hw)->EXTCTRL.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EXTCTRL_INV_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EXTCTRL.reg &= ~TAL_EXTCTRL_INV; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EXTCTRL_INV_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EXTCTRL.reg ^= TAL_EXTCTRL_INV; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EXTCTRL.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_extctrl_reg_t hri_tal_get_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->EXTCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EXTCTRL.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EXTCTRL.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EXTCTRL.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_extctrl_reg_t hri_tal_read_EXTCTRL_reg(const void *const hw) -{ - return ((Tal *)hw)->EXTCTRL.reg; -} - -static inline void hri_tal_set_EVCTRL_BRKEI_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg |= TAL_EVCTRL_BRKEI; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCTRL_BRKEI_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tal *)hw)->EVCTRL.reg; - tmp = (tmp & TAL_EVCTRL_BRKEI) >> TAL_EVCTRL_BRKEI_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCTRL_BRKEI_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCTRL.reg; - tmp &= ~TAL_EVCTRL_BRKEI; - tmp |= value << TAL_EVCTRL_BRKEI_Pos; - ((Tal *)hw)->EVCTRL.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCTRL_BRKEI_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg &= ~TAL_EVCTRL_BRKEI; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCTRL_BRKEI_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg ^= TAL_EVCTRL_BRKEI; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCTRL_BRKEO_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg |= TAL_EVCTRL_BRKEO; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCTRL_BRKEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tal *)hw)->EVCTRL.reg; - tmp = (tmp & TAL_EVCTRL_BRKEO) >> TAL_EVCTRL_BRKEO_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCTRL_BRKEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCTRL.reg; - tmp &= ~TAL_EVCTRL_BRKEO; - tmp |= value << TAL_EVCTRL_BRKEO_Pos; - ((Tal *)hw)->EVCTRL.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCTRL_BRKEO_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg &= ~TAL_EVCTRL_BRKEO; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCTRL_BRKEO_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg ^= TAL_EVCTRL_BRKEO; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCTRL_IRQMONEO0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg |= TAL_EVCTRL_IRQMONEO0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCTRL_IRQMONEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tal *)hw)->EVCTRL.reg; - tmp = (tmp & TAL_EVCTRL_IRQMONEO0) >> TAL_EVCTRL_IRQMONEO0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCTRL_IRQMONEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCTRL.reg; - tmp &= ~TAL_EVCTRL_IRQMONEO0; - tmp |= value << TAL_EVCTRL_IRQMONEO0_Pos; - ((Tal *)hw)->EVCTRL.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCTRL_IRQMONEO0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg &= ~TAL_EVCTRL_IRQMONEO0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCTRL_IRQMONEO0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg ^= TAL_EVCTRL_IRQMONEO0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_evctrl_reg_t hri_tal_get_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tal *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCTRL.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_evctrl_reg_t hri_tal_read_EVCTRL_reg(const void *const hw) -{ - return ((Tal *)hw)->EVCTRL.reg; -} - -static inline void hri_tal_set_GLOBMASK_CPU0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_CPU0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_GLOBMASK_CPU0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->GLOBMASK.reg; - tmp = (tmp & TAL_GLOBMASK_CPU0) >> TAL_GLOBMASK_CPU0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_GLOBMASK_CPU0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->GLOBMASK.reg; - tmp &= ~TAL_GLOBMASK_CPU0; - tmp |= value << TAL_GLOBMASK_CPU0_Pos; - ((Tal *)hw)->GLOBMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_GLOBMASK_CPU0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_CPU0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_GLOBMASK_CPU0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_CPU0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_GLOBMASK_CPU1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_CPU1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_GLOBMASK_CPU1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->GLOBMASK.reg; - tmp = (tmp & TAL_GLOBMASK_CPU1) >> TAL_GLOBMASK_CPU1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_GLOBMASK_CPU1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->GLOBMASK.reg; - tmp &= ~TAL_GLOBMASK_CPU1; - tmp |= value << TAL_GLOBMASK_CPU1_Pos; - ((Tal *)hw)->GLOBMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_GLOBMASK_CPU1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_CPU1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_GLOBMASK_CPU1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_CPU1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_GLOBMASK_EVBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_EVBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_GLOBMASK_EVBRK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->GLOBMASK.reg; - tmp = (tmp & TAL_GLOBMASK_EVBRK) >> TAL_GLOBMASK_EVBRK_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_GLOBMASK_EVBRK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->GLOBMASK.reg; - tmp &= ~TAL_GLOBMASK_EVBRK; - tmp |= value << TAL_GLOBMASK_EVBRK_Pos; - ((Tal *)hw)->GLOBMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_GLOBMASK_EVBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_EVBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_GLOBMASK_EVBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_EVBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_GLOBMASK_EXTBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_EXTBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_GLOBMASK_EXTBRK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->GLOBMASK.reg; - tmp = (tmp & TAL_GLOBMASK_EXTBRK) >> TAL_GLOBMASK_EXTBRK_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_GLOBMASK_EXTBRK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->GLOBMASK.reg; - tmp &= ~TAL_GLOBMASK_EXTBRK; - tmp |= value << TAL_GLOBMASK_EXTBRK_Pos; - ((Tal *)hw)->GLOBMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_GLOBMASK_EXTBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_EXTBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_GLOBMASK_EXTBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_EXTBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_globmask_reg_t hri_tal_get_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->GLOBMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->GLOBMASK.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_globmask_reg_t hri_tal_read_GLOBMASK_reg(const void *const hw) -{ - return ((Tal *)hw)->GLOBMASK.reg; -} - -static inline void hri_tal_set_DMACPUSEL0_CH0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH0_Msk) >> TAL_DMACPUSEL0_CH0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH0_Msk; - tmp |= value << TAL_DMACPUSEL0_CH0_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH1_Msk) >> TAL_DMACPUSEL0_CH1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH1_Msk; - tmp |= value << TAL_DMACPUSEL0_CH1_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH2_Msk) >> TAL_DMACPUSEL0_CH2_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH2_Msk; - tmp |= value << TAL_DMACPUSEL0_CH2_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH3_Msk) >> TAL_DMACPUSEL0_CH3_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH3_Msk; - tmp |= value << TAL_DMACPUSEL0_CH3_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH4_Msk) >> TAL_DMACPUSEL0_CH4_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH4_Msk; - tmp |= value << TAL_DMACPUSEL0_CH4_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH5_Msk) >> TAL_DMACPUSEL0_CH5_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH5_Msk; - tmp |= value << TAL_DMACPUSEL0_CH5_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH6_Msk) >> TAL_DMACPUSEL0_CH6_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH6_Msk; - tmp |= value << TAL_DMACPUSEL0_CH6_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH7_Msk) >> TAL_DMACPUSEL0_CH7_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH7_Msk; - tmp |= value << TAL_DMACPUSEL0_CH7_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH8_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH8_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH8_Msk) >> TAL_DMACPUSEL0_CH8_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH8_Msk; - tmp |= value << TAL_DMACPUSEL0_CH8_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH8_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH8_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH8_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH8_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH9_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH9_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH9_Msk) >> TAL_DMACPUSEL0_CH9_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH9_Msk; - tmp |= value << TAL_DMACPUSEL0_CH9_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH9_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH9_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH9_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH9_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH10_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH10_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH10_Msk) >> TAL_DMACPUSEL0_CH10_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH10_Msk; - tmp |= value << TAL_DMACPUSEL0_CH10_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH10_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH10_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH10_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH10_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH11_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH11_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH11_Msk) >> TAL_DMACPUSEL0_CH11_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH11_Msk; - tmp |= value << TAL_DMACPUSEL0_CH11_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH11_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH11_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH11_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH11_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH12_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH12_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH12_Msk) >> TAL_DMACPUSEL0_CH12_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH12_Msk; - tmp |= value << TAL_DMACPUSEL0_CH12_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH12_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH12_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH12_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH12_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH13_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH13_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH13_Msk) >> TAL_DMACPUSEL0_CH13_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH13_Msk; - tmp |= value << TAL_DMACPUSEL0_CH13_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH13_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH13_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH13_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH13_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH14_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH14_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH14_Msk) >> TAL_DMACPUSEL0_CH14_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH14_Msk; - tmp |= value << TAL_DMACPUSEL0_CH14_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH14_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH14_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH14_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH14_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_CH15_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH15_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL0_CH15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp = (tmp & TAL_DMACPUSEL0_CH15_Msk) >> TAL_DMACPUSEL0_CH15_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_CH15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= ~TAL_DMACPUSEL0_CH15_Msk; - tmp |= value << TAL_DMACPUSEL0_CH15_Pos; - ((Tal *)hw)->DMACPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_CH15_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH15_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_CH15_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH15_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_dmacpusel0_reg_t hri_tal_get_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL0.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_dmacpusel0_reg_t hri_tal_read_DMACPUSEL0_reg(const void *const hw) -{ - return ((Tal *)hw)->DMACPUSEL0.reg; -} - -static inline void hri_tal_set_DMACPUSEL1_CH16_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH16_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH16_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH16_Msk) >> TAL_DMACPUSEL1_CH16_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH16_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH16_Msk; - tmp |= value << TAL_DMACPUSEL1_CH16_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH16_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH16_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH16_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH16_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH17_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH17_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH17_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH17_Msk) >> TAL_DMACPUSEL1_CH17_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH17_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH17_Msk; - tmp |= value << TAL_DMACPUSEL1_CH17_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH17_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH17_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH17_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH17_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH18_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH18_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH18_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH18_Msk) >> TAL_DMACPUSEL1_CH18_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH18_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH18_Msk; - tmp |= value << TAL_DMACPUSEL1_CH18_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH18_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH18_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH18_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH18_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH19_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH19_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH19_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH19_Msk) >> TAL_DMACPUSEL1_CH19_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH19_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH19_Msk; - tmp |= value << TAL_DMACPUSEL1_CH19_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH19_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH19_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH19_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH19_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH20_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH20_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH20_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH20_Msk) >> TAL_DMACPUSEL1_CH20_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH20_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH20_Msk; - tmp |= value << TAL_DMACPUSEL1_CH20_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH20_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH20_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH20_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH20_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH21_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH21_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH21_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH21_Msk) >> TAL_DMACPUSEL1_CH21_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH21_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH21_Msk; - tmp |= value << TAL_DMACPUSEL1_CH21_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH21_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH21_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH21_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH21_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH22_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH22_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH22_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH22_Msk) >> TAL_DMACPUSEL1_CH22_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH22_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH22_Msk; - tmp |= value << TAL_DMACPUSEL1_CH22_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH22_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH22_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH22_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH22_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH23_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH23_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH23_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH23_Msk) >> TAL_DMACPUSEL1_CH23_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH23_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH23_Msk; - tmp |= value << TAL_DMACPUSEL1_CH23_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH23_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH23_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH23_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH23_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH24_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH24_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH24_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH24_Msk) >> TAL_DMACPUSEL1_CH24_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH24_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH24_Msk; - tmp |= value << TAL_DMACPUSEL1_CH24_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH24_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH24_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH24_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH24_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH25_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH25_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH25_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH25_Msk) >> TAL_DMACPUSEL1_CH25_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH25_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH25_Msk; - tmp |= value << TAL_DMACPUSEL1_CH25_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH25_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH25_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH25_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH25_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH26_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH26_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH26_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH26_Msk) >> TAL_DMACPUSEL1_CH26_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH26_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH26_Msk; - tmp |= value << TAL_DMACPUSEL1_CH26_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH26_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH26_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH26_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH26_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH27_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH27_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH27_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH27_Msk) >> TAL_DMACPUSEL1_CH27_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH27_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH27_Msk; - tmp |= value << TAL_DMACPUSEL1_CH27_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH27_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH27_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH27_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH27_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH28_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH28_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH28_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH28_Msk) >> TAL_DMACPUSEL1_CH28_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH28_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH28_Msk; - tmp |= value << TAL_DMACPUSEL1_CH28_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH28_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH28_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH28_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH28_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH29_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH29_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH29_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH29_Msk) >> TAL_DMACPUSEL1_CH29_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH29_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH29_Msk; - tmp |= value << TAL_DMACPUSEL1_CH29_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH29_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH29_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH29_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH29_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH30_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH30_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH30_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH30_Msk) >> TAL_DMACPUSEL1_CH30_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH30_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH30_Msk; - tmp |= value << TAL_DMACPUSEL1_CH30_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH30_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH30_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH30_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH30_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_CH31_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= TAL_DMACPUSEL1_CH31_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_DMACPUSEL1_CH31_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp = (tmp & TAL_DMACPUSEL1_CH31_Msk) >> TAL_DMACPUSEL1_CH31_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_CH31_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= ~TAL_DMACPUSEL1_CH31_Msk; - tmp |= value << TAL_DMACPUSEL1_CH31_Pos; - ((Tal *)hw)->DMACPUSEL1.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_CH31_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~TAL_DMACPUSEL1_CH31_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_CH31_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= TAL_DMACPUSEL1_CH31_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_DMACPUSEL1_reg(const void *const hw, hri_tal_dmacpusel1_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_dmacpusel1_reg_t hri_tal_get_DMACPUSEL1_reg(const void *const hw, hri_tal_dmacpusel1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->DMACPUSEL1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_DMACPUSEL1_reg(const void *const hw, hri_tal_dmacpusel1_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_DMACPUSEL1_reg(const void *const hw, hri_tal_dmacpusel1_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_DMACPUSEL1_reg(const void *const hw, hri_tal_dmacpusel1_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->DMACPUSEL1.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_dmacpusel1_reg_t hri_tal_read_DMACPUSEL1_reg(const void *const hw) -{ - return ((Tal *)hw)->DMACPUSEL1.reg; -} - -static inline void hri_tal_set_EVCPUSEL0_CH0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH0_Msk) >> TAL_EVCPUSEL0_CH0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH0_Msk; - tmp |= value << TAL_EVCPUSEL0_CH0_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_CH1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH1_Msk) >> TAL_EVCPUSEL0_CH1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH1_Msk; - tmp |= value << TAL_EVCPUSEL0_CH1_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_CH2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH2_Msk) >> TAL_EVCPUSEL0_CH2_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH2_Msk; - tmp |= value << TAL_EVCPUSEL0_CH2_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_CH3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH3_Msk) >> TAL_EVCPUSEL0_CH3_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH3_Msk; - tmp |= value << TAL_EVCPUSEL0_CH3_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_CH4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH4_Msk) >> TAL_EVCPUSEL0_CH4_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH4_Msk; - tmp |= value << TAL_EVCPUSEL0_CH4_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_CH5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH5_Msk) >> TAL_EVCPUSEL0_CH5_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH5_Msk; - tmp |= value << TAL_EVCPUSEL0_CH5_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_CH6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH6_Msk) >> TAL_EVCPUSEL0_CH6_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH6_Msk; - tmp |= value << TAL_EVCPUSEL0_CH6_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_CH7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH7_Msk) >> TAL_EVCPUSEL0_CH7_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH7_Msk; - tmp |= value << TAL_EVCPUSEL0_CH7_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_CH8_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH8_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH8_Msk) >> TAL_EVCPUSEL0_CH8_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH8_Msk; - tmp |= value << TAL_EVCPUSEL0_CH8_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH8_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH8_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH8_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH8_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_CH9_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH9_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH9_Msk) >> TAL_EVCPUSEL0_CH9_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH9_Msk; - tmp |= value << TAL_EVCPUSEL0_CH9_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH9_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH9_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH9_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH9_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_CH10_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH10_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH10_Msk) >> TAL_EVCPUSEL0_CH10_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH10_Msk; - tmp |= value << TAL_EVCPUSEL0_CH10_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH10_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH10_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH10_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH10_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_CH11_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH11_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EVCPUSEL0_CH11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp = (tmp & TAL_EVCPUSEL0_CH11_Msk) >> TAL_EVCPUSEL0_CH11_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_CH11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= ~TAL_EVCPUSEL0_CH11_Msk; - tmp |= value << TAL_EVCPUSEL0_CH11_Pos; - ((Tal *)hw)->EVCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_CH11_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH11_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_CH11_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH11_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_evcpusel0_reg_t hri_tal_get_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EVCPUSEL0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EVCPUSEL0.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_evcpusel0_reg_t hri_tal_read_EVCPUSEL0_reg(const void *const hw) -{ - return ((Tal *)hw)->EVCPUSEL0.reg; -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT0_Msk) >> TAL_EICCPUSEL0_EXTINT0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT0_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT0_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT1_Msk) >> TAL_EICCPUSEL0_EXTINT1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT1_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT1_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT2_Msk) >> TAL_EICCPUSEL0_EXTINT2_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT2_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT2_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT3_Msk) >> TAL_EICCPUSEL0_EXTINT3_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT3_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT3_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT4_Msk) >> TAL_EICCPUSEL0_EXTINT4_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT4_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT4_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT5_Msk) >> TAL_EICCPUSEL0_EXTINT5_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT5_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT5_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT6_Msk) >> TAL_EICCPUSEL0_EXTINT6_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT6_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT6_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT7_Msk) >> TAL_EICCPUSEL0_EXTINT7_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT7_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT7_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT8_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT8_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT8_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT8_Msk) >> TAL_EICCPUSEL0_EXTINT8_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT8_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT8_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT8_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT8_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT8_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT8_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT8_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT9_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT9_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT9_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT9_Msk) >> TAL_EICCPUSEL0_EXTINT9_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT9_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT9_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT9_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT9_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT9_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT9_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT9_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT10_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT10_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT10_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT10_Msk) >> TAL_EICCPUSEL0_EXTINT10_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT10_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT10_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT10_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT10_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT10_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT10_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT10_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT11_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT11_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT11_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT11_Msk) >> TAL_EICCPUSEL0_EXTINT11_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT11_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT11_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT11_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT11_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT11_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT11_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT11_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT12_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT12_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT12_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT12_Msk) >> TAL_EICCPUSEL0_EXTINT12_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT12_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT12_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT12_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT12_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT12_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT12_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT12_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT13_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT13_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT13_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT13_Msk) >> TAL_EICCPUSEL0_EXTINT13_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT13_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT13_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT13_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT13_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT13_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT13_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT13_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT14_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT14_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT14_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT14_Msk) >> TAL_EICCPUSEL0_EXTINT14_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT14_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT14_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT14_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT14_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT14_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT14_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT14_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_EXTINT15_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT15_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_EICCPUSEL0_EXTINT15_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp = (tmp & TAL_EICCPUSEL0_EXTINT15_Msk) >> TAL_EICCPUSEL0_EXTINT15_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_EXTINT15_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= ~TAL_EICCPUSEL0_EXTINT15_Msk; - tmp |= value << TAL_EICCPUSEL0_EXTINT15_Pos; - ((Tal *)hw)->EICCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_EXTINT15_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT15_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_EXTINT15_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT15_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_eiccpusel0_reg_t hri_tal_get_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->EICCPUSEL0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->EICCPUSEL0.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_eiccpusel0_reg_t hri_tal_read_EICCPUSEL0_reg(const void *const hw) -{ - return ((Tal *)hw)->EICCPUSEL0.reg; -} - -static inline void hri_tal_set_INTCPUSEL0_PAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_PAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_PAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_PAC_Msk) >> TAL_INTCPUSEL0_PAC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_PAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_PAC_Msk; - tmp |= value << TAL_INTCPUSEL0_PAC_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_PAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_PAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_PAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_PAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_PM_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_PM_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_PM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_PM_Msk) >> TAL_INTCPUSEL0_PM_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_PM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_PM_Msk; - tmp |= value << TAL_INTCPUSEL0_PM_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_PM_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_PM_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_PM_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_PM_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_MCLK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_MCLK_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_MCLK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_MCLK_Msk) >> TAL_INTCPUSEL0_MCLK_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_MCLK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_MCLK_Msk; - tmp |= value << TAL_INTCPUSEL0_MCLK_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_MCLK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_MCLK_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_MCLK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_MCLK_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_OSCCTRL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_OSCCTRL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_OSCCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_OSCCTRL_Msk) >> TAL_INTCPUSEL0_OSCCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_OSCCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_OSCCTRL_Msk; - tmp |= value << TAL_INTCPUSEL0_OSCCTRL_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_OSCCTRL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_OSCCTRL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_OSCCTRL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_OSCCTRL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_OSC32KCTRL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_OSC32KCTRL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_OSC32KCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_OSC32KCTRL_Msk) >> TAL_INTCPUSEL0_OSC32KCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_OSC32KCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_OSC32KCTRL_Msk; - tmp |= value << TAL_INTCPUSEL0_OSC32KCTRL_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_OSC32KCTRL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_OSC32KCTRL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_OSC32KCTRL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_OSC32KCTRL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_SUPC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SUPC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_SUPC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_SUPC_Msk) >> TAL_INTCPUSEL0_SUPC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_SUPC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_SUPC_Msk; - tmp |= value << TAL_INTCPUSEL0_SUPC_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_SUPC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SUPC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_SUPC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SUPC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_WDT_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_WDT_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_WDT_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_WDT_Msk) >> TAL_INTCPUSEL0_WDT_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_WDT_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_WDT_Msk; - tmp |= value << TAL_INTCPUSEL0_WDT_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_WDT_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_WDT_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_WDT_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_WDT_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_RTC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_RTC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_RTC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_RTC_Msk) >> TAL_INTCPUSEL0_RTC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_RTC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_RTC_Msk; - tmp |= value << TAL_INTCPUSEL0_RTC_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_RTC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_RTC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_RTC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_RTC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_EIC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_EIC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_EIC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_EIC_Msk) >> TAL_INTCPUSEL0_EIC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_EIC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_EIC_Msk; - tmp |= value << TAL_INTCPUSEL0_EIC_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_EIC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_EIC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_EIC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_EIC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_FREQM_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_FREQM_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_FREQM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_FREQM_Msk) >> TAL_INTCPUSEL0_FREQM_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_FREQM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_FREQM_Msk; - tmp |= value << TAL_INTCPUSEL0_FREQM_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_FREQM_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_FREQM_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_FREQM_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_FREQM_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_SERCOM0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SERCOM0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_SERCOM0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_SERCOM0_Msk) >> TAL_INTCPUSEL0_SERCOM0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_SERCOM0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_SERCOM0_Msk; - tmp |= value << TAL_INTCPUSEL0_SERCOM0_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_SERCOM0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SERCOM0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_SERCOM0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SERCOM0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_SERCOM1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SERCOM1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_SERCOM1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_SERCOM1_Msk) >> TAL_INTCPUSEL0_SERCOM1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_SERCOM1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_SERCOM1_Msk; - tmp |= value << TAL_INTCPUSEL0_SERCOM1_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_SERCOM1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SERCOM1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_SERCOM1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SERCOM1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_TC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_TC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_TC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_TC0_Msk) >> TAL_INTCPUSEL0_TC0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_TC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_TC0_Msk; - tmp |= value << TAL_INTCPUSEL0_TC0_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_TC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_TC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_TC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_TC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_TC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_TC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL0_TC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp = (tmp & TAL_INTCPUSEL0_TC1_Msk) >> TAL_INTCPUSEL0_TC1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_TC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= ~TAL_INTCPUSEL0_TC1_Msk; - tmp |= value << TAL_INTCPUSEL0_TC1_Pos; - ((Tal *)hw)->INTCPUSEL0.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_TC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_TC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_TC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_TC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel0_reg_t hri_tal_get_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL0.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL0.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel0_reg_t hri_tal_read_INTCPUSEL0_reg(const void *const hw) -{ - return ((Tal *)hw)->INTCPUSEL0.reg; -} - -static inline void hri_tal_set_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL1.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel1_reg_t hri_tal_get_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL1.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL1.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL1.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL1.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel1_reg_t hri_tal_read_INTCPUSEL1_reg(const void *const hw) -{ - return ((Tal *)hw)->INTCPUSEL1.reg; -} - -static inline void hri_tal_set_INTCPUSEL2_USB_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_USB_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_USB_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_USB_Msk) >> TAL_INTCPUSEL2_USB_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_USB_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_USB_Msk; - tmp |= value << TAL_INTCPUSEL2_USB_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_USB_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_USB_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_USB_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_USB_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_NVMCTRL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_NVMCTRL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_NVMCTRL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_NVMCTRL_Msk) >> TAL_INTCPUSEL2_NVMCTRL_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_NVMCTRL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_NVMCTRL_Msk; - tmp |= value << TAL_INTCPUSEL2_NVMCTRL_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_NVMCTRL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_NVMCTRL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_NVMCTRL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_NVMCTRL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_DMAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_DMAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_DMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_DMAC_Msk) >> TAL_INTCPUSEL2_DMAC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_DMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_DMAC_Msk; - tmp |= value << TAL_INTCPUSEL2_DMAC_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_DMAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_DMAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_DMAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_DMAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_EVSYS_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_EVSYS_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_EVSYS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_EVSYS_Msk) >> TAL_INTCPUSEL2_EVSYS_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_EVSYS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_EVSYS_Msk; - tmp |= value << TAL_INTCPUSEL2_EVSYS_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_EVSYS_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_EVSYS_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_EVSYS_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_EVSYS_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_PICOP_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_PICOP_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_PICOP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_PICOP_Msk) >> TAL_INTCPUSEL2_PICOP_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_PICOP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_PICOP_Msk; - tmp |= value << TAL_INTCPUSEL2_PICOP_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_PICOP_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_PICOP_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_PICOP_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_PICOP_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_SERCOM2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_SERCOM2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_SERCOM2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_SERCOM2_Msk) >> TAL_INTCPUSEL2_SERCOM2_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_SERCOM2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_SERCOM2_Msk; - tmp |= value << TAL_INTCPUSEL2_SERCOM2_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_SERCOM2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_SERCOM2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_SERCOM2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_SERCOM2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_SERCOM3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_SERCOM3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_SERCOM3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_SERCOM3_Msk) >> TAL_INTCPUSEL2_SERCOM3_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_SERCOM3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_SERCOM3_Msk; - tmp |= value << TAL_INTCPUSEL2_SERCOM3_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_SERCOM3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_SERCOM3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_SERCOM3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_SERCOM3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_TCC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_TCC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_TCC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_TCC0_Msk) >> TAL_INTCPUSEL2_TCC0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_TCC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_TCC0_Msk; - tmp |= value << TAL_INTCPUSEL2_TCC0_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_TCC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_TCC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_TCC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_TCC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_TCC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_TCC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_TCC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_TCC1_Msk) >> TAL_INTCPUSEL2_TCC1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_TCC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_TCC1_Msk; - tmp |= value << TAL_INTCPUSEL2_TCC1_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_TCC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_TCC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_TCC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_TCC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_TC2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_TC2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_TC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_TC2_Msk) >> TAL_INTCPUSEL2_TC2_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_TC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_TC2_Msk; - tmp |= value << TAL_INTCPUSEL2_TC2_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_TC2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_TC2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_TC2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_TC2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_TC3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_TC3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_TC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_TC3_Msk) >> TAL_INTCPUSEL2_TC3_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_TC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_TC3_Msk; - tmp |= value << TAL_INTCPUSEL2_TC3_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_TC3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_TC3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_TC3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_TC3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_TAL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= TAL_INTCPUSEL2_TAL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL2_TAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp = (tmp & TAL_INTCPUSEL2_TAL_Msk) >> TAL_INTCPUSEL2_TAL_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_TAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= ~TAL_INTCPUSEL2_TAL_Msk; - tmp |= value << TAL_INTCPUSEL2_TAL_Pos; - ((Tal *)hw)->INTCPUSEL2.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_TAL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~TAL_INTCPUSEL2_TAL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_TAL_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= TAL_INTCPUSEL2_TAL_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL2_reg(const void *const hw, hri_tal_intcpusel2_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel2_reg_t hri_tal_get_INTCPUSEL2_reg(const void *const hw, hri_tal_intcpusel2_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL2.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_INTCPUSEL2_reg(const void *const hw, hri_tal_intcpusel2_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL2_reg(const void *const hw, hri_tal_intcpusel2_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL2_reg(const void *const hw, hri_tal_intcpusel2_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL2.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel2_reg_t hri_tal_read_INTCPUSEL2_reg(const void *const hw) -{ - return ((Tal *)hw)->INTCPUSEL2.reg; -} - -static inline void hri_tal_set_INTCPUSEL3_RAMECC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL3.reg |= TAL_INTCPUSEL3_RAMECC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL3_RAMECC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL3.reg; - tmp = (tmp & TAL_INTCPUSEL3_RAMECC_Msk) >> TAL_INTCPUSEL3_RAMECC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL3_RAMECC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL3.reg; - tmp &= ~TAL_INTCPUSEL3_RAMECC_Msk; - tmp |= value << TAL_INTCPUSEL3_RAMECC_Pos; - ((Tal *)hw)->INTCPUSEL3.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL3_RAMECC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL3.reg &= ~TAL_INTCPUSEL3_RAMECC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL3_RAMECC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL3.reg ^= TAL_INTCPUSEL3_RAMECC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL3_reg(const void *const hw, hri_tal_intcpusel3_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL3.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel3_reg_t hri_tal_get_INTCPUSEL3_reg(const void *const hw, hri_tal_intcpusel3_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL3.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_INTCPUSEL3_reg(const void *const hw, hri_tal_intcpusel3_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL3.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL3_reg(const void *const hw, hri_tal_intcpusel3_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL3.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL3_reg(const void *const hw, hri_tal_intcpusel3_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL3.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel3_reg_t hri_tal_read_INTCPUSEL3_reg(const void *const hw) -{ - return ((Tal *)hw)->INTCPUSEL3.reg; -} - -static inline void hri_tal_set_INTCPUSEL4_CAN0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_CAN0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_CAN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_CAN0_Msk) >> TAL_INTCPUSEL4_CAN0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_CAN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_CAN0_Msk; - tmp |= value << TAL_INTCPUSEL4_CAN0_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_CAN0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_CAN0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_CAN0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_CAN0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_CAN1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_CAN1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_CAN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_CAN1_Msk) >> TAL_INTCPUSEL4_CAN1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_CAN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_CAN1_Msk; - tmp |= value << TAL_INTCPUSEL4_CAN1_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_CAN1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_CAN1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_CAN1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_CAN1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_GMAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_GMAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_GMAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_GMAC_Msk) >> TAL_INTCPUSEL4_GMAC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_GMAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_GMAC_Msk; - tmp |= value << TAL_INTCPUSEL4_GMAC_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_GMAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_GMAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_GMAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_GMAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_TCC2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_TCC2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_TCC2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_TCC2_Msk) >> TAL_INTCPUSEL4_TCC2_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_TCC2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_TCC2_Msk; - tmp |= value << TAL_INTCPUSEL4_TCC2_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_TCC2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_TCC2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_TCC2_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_TCC2_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_TCC3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_TCC3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_TCC3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_TCC3_Msk) >> TAL_INTCPUSEL4_TCC3_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_TCC3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_TCC3_Msk; - tmp |= value << TAL_INTCPUSEL4_TCC3_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_TCC3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_TCC3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_TCC3_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_TCC3_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_TC4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_TC4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_TC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_TC4_Msk) >> TAL_INTCPUSEL4_TC4_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_TC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_TC4_Msk; - tmp |= value << TAL_INTCPUSEL4_TC4_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_TC4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_TC4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_TC4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_TC4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_TC5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_TC5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_TC5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_TC5_Msk) >> TAL_INTCPUSEL4_TC5_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_TC5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_TC5_Msk; - tmp |= value << TAL_INTCPUSEL4_TC5_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_TC5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_TC5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_TC5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_TC5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_PDEC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_PDEC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_PDEC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_PDEC_Msk) >> TAL_INTCPUSEL4_PDEC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_PDEC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_PDEC_Msk; - tmp |= value << TAL_INTCPUSEL4_PDEC_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_PDEC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_PDEC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_PDEC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_PDEC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_AC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_AC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_AC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_AC_Msk) >> TAL_INTCPUSEL4_AC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_AC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_AC_Msk; - tmp |= value << TAL_INTCPUSEL4_AC_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_AC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_AC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_AC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_AC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_AES_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_AES_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_AES_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_AES_Msk) >> TAL_INTCPUSEL4_AES_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_AES_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_AES_Msk; - tmp |= value << TAL_INTCPUSEL4_AES_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_AES_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_AES_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_AES_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_AES_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_TRNG_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_TRNG_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_TRNG_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_TRNG_Msk) >> TAL_INTCPUSEL4_TRNG_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_TRNG_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_TRNG_Msk; - tmp |= value << TAL_INTCPUSEL4_TRNG_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_TRNG_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_TRNG_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_TRNG_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_TRNG_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_ICM_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_ICM_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_ICM_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_ICM_Msk) >> TAL_INTCPUSEL4_ICM_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_ICM_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_ICM_Msk; - tmp |= value << TAL_INTCPUSEL4_ICM_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_ICM_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_ICM_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_ICM_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_ICM_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_PUKCC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_PUKCC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_PUKCC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_PUKCC_Msk) >> TAL_INTCPUSEL4_PUKCC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_PUKCC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_PUKCC_Msk; - tmp |= value << TAL_INTCPUSEL4_PUKCC_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_PUKCC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_PUKCC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_PUKCC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_PUKCC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_QSPI_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= TAL_INTCPUSEL4_QSPI_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL4_QSPI_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp = (tmp & TAL_INTCPUSEL4_QSPI_Msk) >> TAL_INTCPUSEL4_QSPI_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_QSPI_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= ~TAL_INTCPUSEL4_QSPI_Msk; - tmp |= value << TAL_INTCPUSEL4_QSPI_Pos; - ((Tal *)hw)->INTCPUSEL4.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_QSPI_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~TAL_INTCPUSEL4_QSPI_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_QSPI_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= TAL_INTCPUSEL4_QSPI_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL4_reg(const void *const hw, hri_tal_intcpusel4_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel4_reg_t hri_tal_get_INTCPUSEL4_reg(const void *const hw, hri_tal_intcpusel4_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL4.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_INTCPUSEL4_reg(const void *const hw, hri_tal_intcpusel4_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL4_reg(const void *const hw, hri_tal_intcpusel4_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL4_reg(const void *const hw, hri_tal_intcpusel4_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL4.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel4_reg_t hri_tal_read_INTCPUSEL4_reg(const void *const hw) -{ - return ((Tal *)hw)->INTCPUSEL4.reg; -} - -static inline void hri_tal_set_INTCPUSEL5_reg(const void *const hw, hri_tal_intcpusel5_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL5.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel5_reg_t hri_tal_get_INTCPUSEL5_reg(const void *const hw, hri_tal_intcpusel5_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL5.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_INTCPUSEL5_reg(const void *const hw, hri_tal_intcpusel5_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL5.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL5_reg(const void *const hw, hri_tal_intcpusel5_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL5.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL5_reg(const void *const hw, hri_tal_intcpusel5_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL5.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel5_reg_t hri_tal_read_INTCPUSEL5_reg(const void *const hw) -{ - return ((Tal *)hw)->INTCPUSEL5.reg; -} - -static inline void hri_tal_set_INTCPUSEL6_SERCOM4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_SERCOM4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_SERCOM4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_SERCOM4_Msk) >> TAL_INTCPUSEL6_SERCOM4_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_SERCOM4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_SERCOM4_Msk; - tmp |= value << TAL_INTCPUSEL6_SERCOM4_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_SERCOM4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_SERCOM4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_SERCOM4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_SERCOM4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_SERCOM5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_SERCOM5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_SERCOM5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_SERCOM5_Msk) >> TAL_INTCPUSEL6_SERCOM5_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_SERCOM5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_SERCOM5_Msk; - tmp |= value << TAL_INTCPUSEL6_SERCOM5_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_SERCOM5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_SERCOM5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_SERCOM5_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_SERCOM5_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_SERCOM6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_SERCOM6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_SERCOM6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_SERCOM6_Msk) >> TAL_INTCPUSEL6_SERCOM6_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_SERCOM6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_SERCOM6_Msk; - tmp |= value << TAL_INTCPUSEL6_SERCOM6_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_SERCOM6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_SERCOM6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_SERCOM6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_SERCOM6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_SERCOM7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_SERCOM7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_SERCOM7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_SERCOM7_Msk) >> TAL_INTCPUSEL6_SERCOM7_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_SERCOM7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_SERCOM7_Msk; - tmp |= value << TAL_INTCPUSEL6_SERCOM7_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_SERCOM7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_SERCOM7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_SERCOM7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_SERCOM7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_TCC4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_TCC4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_TCC4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_TCC4_Msk) >> TAL_INTCPUSEL6_TCC4_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_TCC4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_TCC4_Msk; - tmp |= value << TAL_INTCPUSEL6_TCC4_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_TCC4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_TCC4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_TCC4_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_TCC4_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_TC6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_TC6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_TC6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_TC6_Msk) >> TAL_INTCPUSEL6_TC6_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_TC6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_TC6_Msk; - tmp |= value << TAL_INTCPUSEL6_TC6_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_TC6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_TC6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_TC6_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_TC6_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_TC7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_TC7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_TC7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_TC7_Msk) >> TAL_INTCPUSEL6_TC7_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_TC7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_TC7_Msk; - tmp |= value << TAL_INTCPUSEL6_TC7_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_TC7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_TC7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_TC7_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_TC7_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_ADC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_ADC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_ADC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_ADC0_Msk) >> TAL_INTCPUSEL6_ADC0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_ADC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_ADC0_Msk; - tmp |= value << TAL_INTCPUSEL6_ADC0_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_ADC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_ADC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_ADC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_ADC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_ADC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_ADC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_ADC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_ADC1_Msk) >> TAL_INTCPUSEL6_ADC1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_ADC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_ADC1_Msk; - tmp |= value << TAL_INTCPUSEL6_ADC1_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_ADC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_ADC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_ADC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_ADC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_DAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_DAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_DAC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_DAC_Msk) >> TAL_INTCPUSEL6_DAC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_DAC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_DAC_Msk; - tmp |= value << TAL_INTCPUSEL6_DAC_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_DAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_DAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_DAC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_DAC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_I2S_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_I2S_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_I2S_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_I2S_Msk) >> TAL_INTCPUSEL6_I2S_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_I2S_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_I2S_Msk; - tmp |= value << TAL_INTCPUSEL6_I2S_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_I2S_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_I2S_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_I2S_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_I2S_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_PCC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= TAL_INTCPUSEL6_PCC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL6_PCC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp = (tmp & TAL_INTCPUSEL6_PCC_Msk) >> TAL_INTCPUSEL6_PCC_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_PCC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= ~TAL_INTCPUSEL6_PCC_Msk; - tmp |= value << TAL_INTCPUSEL6_PCC_Pos; - ((Tal *)hw)->INTCPUSEL6.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_PCC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~TAL_INTCPUSEL6_PCC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_PCC_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= TAL_INTCPUSEL6_PCC_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL6_reg(const void *const hw, hri_tal_intcpusel6_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel6_reg_t hri_tal_get_INTCPUSEL6_reg(const void *const hw, hri_tal_intcpusel6_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL6.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_INTCPUSEL6_reg(const void *const hw, hri_tal_intcpusel6_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL6_reg(const void *const hw, hri_tal_intcpusel6_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL6_reg(const void *const hw, hri_tal_intcpusel6_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL6.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel6_reg_t hri_tal_read_INTCPUSEL6_reg(const void *const hw) -{ - return ((Tal *)hw)->INTCPUSEL6.reg; -} - -static inline void hri_tal_set_INTCPUSEL7_reg(const void *const hw, hri_tal_intcpusel7_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL7.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel7_reg_t hri_tal_get_INTCPUSEL7_reg(const void *const hw, hri_tal_intcpusel7_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL7.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_INTCPUSEL7_reg(const void *const hw, hri_tal_intcpusel7_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL7.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL7_reg(const void *const hw, hri_tal_intcpusel7_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL7.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL7_reg(const void *const hw, hri_tal_intcpusel7_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL7.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel7_reg_t hri_tal_read_INTCPUSEL7_reg(const void *const hw) -{ - return ((Tal *)hw)->INTCPUSEL7.reg; -} - -static inline void hri_tal_set_INTCPUSEL8_SDHC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL8.reg |= TAL_INTCPUSEL8_SDHC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL8_SDHC0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL8.reg; - tmp = (tmp & TAL_INTCPUSEL8_SDHC0_Msk) >> TAL_INTCPUSEL8_SDHC0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL8_SDHC0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL8.reg; - tmp &= ~TAL_INTCPUSEL8_SDHC0_Msk; - tmp |= value << TAL_INTCPUSEL8_SDHC0_Pos; - ((Tal *)hw)->INTCPUSEL8.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL8_SDHC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL8.reg &= ~TAL_INTCPUSEL8_SDHC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL8_SDHC0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL8.reg ^= TAL_INTCPUSEL8_SDHC0_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL8_SDHC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL8.reg |= TAL_INTCPUSEL8_SDHC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_INTCPUSEL8_SDHC1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL8.reg; - tmp = (tmp & TAL_INTCPUSEL8_SDHC1_Msk) >> TAL_INTCPUSEL8_SDHC1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_INTCPUSEL8_SDHC1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->INTCPUSEL8.reg; - tmp &= ~TAL_INTCPUSEL8_SDHC1_Msk; - tmp |= value << TAL_INTCPUSEL8_SDHC1_Pos; - ((Tal *)hw)->INTCPUSEL8.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL8_SDHC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL8.reg &= ~TAL_INTCPUSEL8_SDHC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL8_SDHC1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL8.reg ^= TAL_INTCPUSEL8_SDHC1_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_INTCPUSEL8_reg(const void *const hw, hri_tal_intcpusel8_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL8.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel8_reg_t hri_tal_get_INTCPUSEL8_reg(const void *const hw, hri_tal_intcpusel8_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->INTCPUSEL8.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_INTCPUSEL8_reg(const void *const hw, hri_tal_intcpusel8_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL8.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_INTCPUSEL8_reg(const void *const hw, hri_tal_intcpusel8_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL8.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_INTCPUSEL8_reg(const void *const hw, hri_tal_intcpusel8_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->INTCPUSEL8.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_intcpusel8_reg_t hri_tal_read_INTCPUSEL8_reg(const void *const hw) -{ - return ((Tal *)hw)->INTCPUSEL8.reg; -} - -static inline void hri_tal_set_IRQTRIG_ENABLE_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg |= TAL_IRQTRIG_ENABLE; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_IRQTRIG_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->IRQTRIG.reg; - tmp = (tmp & TAL_IRQTRIG_ENABLE) >> TAL_IRQTRIG_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_IRQTRIG_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->IRQTRIG.reg; - tmp &= ~TAL_IRQTRIG_ENABLE; - tmp |= value << TAL_IRQTRIG_ENABLE_Pos; - ((Tal *)hw)->IRQTRIG.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_IRQTRIG_ENABLE_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg &= ~TAL_IRQTRIG_ENABLE; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_IRQTRIG_ENABLE_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg ^= TAL_IRQTRIG_ENABLE; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg |= TAL_IRQTRIG_IRQNUM(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_irqtrig_reg_t hri_tal_get_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->IRQTRIG.reg; - tmp = (tmp & TAL_IRQTRIG_IRQNUM(mask)) >> TAL_IRQTRIG_IRQNUM_Pos; - return tmp; -} - -static inline void hri_tal_write_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t data) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->IRQTRIG.reg; - tmp &= ~TAL_IRQTRIG_IRQNUM_Msk; - tmp |= TAL_IRQTRIG_IRQNUM(data); - ((Tal *)hw)->IRQTRIG.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg &= ~TAL_IRQTRIG_IRQNUM(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg ^= TAL_IRQTRIG_IRQNUM(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_irqtrig_reg_t hri_tal_read_IRQTRIG_IRQNUM_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->IRQTRIG.reg; - tmp = (tmp & TAL_IRQTRIG_IRQNUM_Msk) >> TAL_IRQTRIG_IRQNUM_Pos; - return tmp; -} - -static inline void hri_tal_set_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg |= TAL_IRQTRIG_OVERRIDE(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_irqtrig_reg_t hri_tal_get_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->IRQTRIG.reg; - tmp = (tmp & TAL_IRQTRIG_OVERRIDE(mask)) >> TAL_IRQTRIG_OVERRIDE_Pos; - return tmp; -} - -static inline void hri_tal_write_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t data) -{ - uint32_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->IRQTRIG.reg; - tmp &= ~TAL_IRQTRIG_OVERRIDE_Msk; - tmp |= TAL_IRQTRIG_OVERRIDE(data); - ((Tal *)hw)->IRQTRIG.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg &= ~TAL_IRQTRIG_OVERRIDE(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg ^= TAL_IRQTRIG_OVERRIDE(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_irqtrig_reg_t hri_tal_read_IRQTRIG_OVERRIDE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->IRQTRIG.reg; - tmp = (tmp & TAL_IRQTRIG_OVERRIDE_Msk) >> TAL_IRQTRIG_OVERRIDE_Pos; - return tmp; -} - -static inline void hri_tal_set_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_irqtrig_reg_t hri_tal_get_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->IRQTRIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQTRIG.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_irqtrig_reg_t hri_tal_read_IRQTRIG_reg(const void *const hw) -{ - return ((Tal *)hw)->IRQTRIG.reg; -} - -static inline void hri_tal_set_IRQMON_EXTEND_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg |= TAL_IRQMON_EXTEND; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_IRQMON_EXTEND_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Tal *)hw)->IRQMON[index].reg; - tmp = (tmp & TAL_IRQMON_EXTEND) >> TAL_IRQMON_EXTEND_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_IRQMON_EXTEND_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->IRQMON[index].reg; - tmp &= ~TAL_IRQMON_EXTEND; - tmp |= value << TAL_IRQMON_EXTEND_Pos; - ((Tal *)hw)->IRQMON[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_IRQMON_EXTEND_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg &= ~TAL_IRQMON_EXTEND; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_IRQMON_EXTEND_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg ^= TAL_IRQMON_EXTEND; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_IRQMON_DROP_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg |= TAL_IRQMON_DROP; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_IRQMON_DROP_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Tal *)hw)->IRQMON[index].reg; - tmp = (tmp & TAL_IRQMON_DROP) >> TAL_IRQMON_DROP_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_IRQMON_DROP_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->IRQMON[index].reg; - tmp &= ~TAL_IRQMON_DROP; - tmp |= value << TAL_IRQMON_DROP_Pos; - ((Tal *)hw)->IRQMON[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_IRQMON_DROP_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg &= ~TAL_IRQMON_DROP; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_IRQMON_DROP_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg ^= TAL_IRQMON_DROP; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_IRQMON_CPUID_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg |= TAL_IRQMON_CPUID_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_IRQMON_CPUID_bit(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Tal *)hw)->IRQMON[index].reg; - tmp = (tmp & TAL_IRQMON_CPUID_Msk) >> TAL_IRQMON_CPUID_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_IRQMON_CPUID_bit(const void *const hw, uint8_t index, bool value) -{ - uint16_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->IRQMON[index].reg; - tmp &= ~TAL_IRQMON_CPUID_Msk; - tmp |= value << TAL_IRQMON_CPUID_Pos; - ((Tal *)hw)->IRQMON[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_IRQMON_CPUID_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg &= ~TAL_IRQMON_CPUID_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_IRQMON_CPUID_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg ^= TAL_IRQMON_CPUID_Msk; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg |= TAL_IRQMON_IRQNUM(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_irqmon_reg_t hri_tal_get_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index, - hri_tal_irqmon_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tal *)hw)->IRQMON[index].reg; - tmp = (tmp & TAL_IRQMON_IRQNUM(mask)) >> TAL_IRQMON_IRQNUM_Pos; - return tmp; -} - -static inline void hri_tal_write_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t data) -{ - uint16_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->IRQMON[index].reg; - tmp &= ~TAL_IRQMON_IRQNUM_Msk; - tmp |= TAL_IRQMON_IRQNUM(data); - ((Tal *)hw)->IRQMON[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg &= ~TAL_IRQMON_IRQNUM(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg ^= TAL_IRQMON_IRQNUM(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_irqmon_reg_t hri_tal_read_IRQMON_IRQNUM_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Tal *)hw)->IRQMON[index].reg; - tmp = (tmp & TAL_IRQMON_IRQNUM_Msk) >> TAL_IRQMON_IRQNUM_Pos; - return tmp; -} - -static inline void hri_tal_set_IRQMON_reg(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_irqmon_reg_t hri_tal_get_IRQMON_reg(const void *const hw, uint8_t index, - hri_tal_irqmon_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tal *)hw)->IRQMON[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_IRQMON_reg(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_IRQMON_reg(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_IRQMON_reg(const void *const hw, uint8_t index, hri_tal_irqmon_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->IRQMON[index].reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_irqmon_reg_t hri_tal_read_IRQMON_reg(const void *const hw, uint8_t index) -{ - return ((Tal *)hw)->IRQMON[index].reg; -} - -static inline void hri_tal_set_SFLAGCLRR_IPS_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->SFLAGCLRR[index].reg |= TAL_SFLAGCLRR_IPS; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_SFLAGCLRR_IPS_bit(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->SFLAGCLRR[index].reg; - tmp = (tmp & TAL_SFLAGCLRR_IPS) >> TAL_SFLAGCLRR_IPS_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_SFLAGCLRR_IPS_bit(const void *const hw, uint8_t index, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->SFLAGCLRR[index].reg; - tmp &= ~TAL_SFLAGCLRR_IPS; - tmp |= value << TAL_SFLAGCLRR_IPS_Pos; - ((Tal *)hw)->SFLAGCLRR[index].reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SFLAGCLRR_IPS_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->SFLAGCLRR[index].reg &= ~TAL_SFLAGCLRR_IPS; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SFLAGCLRR_IPS_bit(const void *const hw, uint8_t index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->SFLAGCLRR[index].reg ^= TAL_SFLAGCLRR_IPS; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_SFLAGCLRR_reg(const void *const hw, uint8_t index, hri_tal_sflagclrr_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->SFLAGCLRR[index].reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_sflagclrr_reg_t hri_tal_get_SFLAGCLRR_reg(const void *const hw, uint8_t index, - hri_tal_sflagclrr_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->SFLAGCLRR[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_SFLAGCLRR_reg(const void *const hw, uint8_t index, hri_tal_sflagclrr_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->SFLAGCLRR[index].reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_SFLAGCLRR_reg(const void *const hw, uint8_t index, hri_tal_sflagclrr_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->SFLAGCLRR[index].reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_SFLAGCLRR_reg(const void *const hw, uint8_t index, hri_tal_sflagclrr_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->SFLAGCLRR[index].reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_sflagclrr_reg_t hri_tal_read_SFLAGCLRR_reg(const void *const hw, uint8_t index) -{ - return ((Tal *)hw)->SFLAGCLRR[index].reg; -} - -static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_CPU0_bf(const void *const hw, hri_tal_brkstatus_reg_t mask) -{ - return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_CPU0(mask)) >> TAL_BRKSTATUS_CPU0_Pos; -} - -static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_CPU0_bf(const void *const hw) -{ - return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_CPU0_Msk) >> TAL_BRKSTATUS_CPU0_Pos; -} - -static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_CPU1_bf(const void *const hw, hri_tal_brkstatus_reg_t mask) -{ - return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_CPU1(mask)) >> TAL_BRKSTATUS_CPU1_Pos; -} - -static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_CPU1_bf(const void *const hw) -{ - return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_CPU1_Msk) >> TAL_BRKSTATUS_CPU1_Pos; -} - -static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_EVBRK_bf(const void *const hw, hri_tal_brkstatus_reg_t mask) -{ - return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EVBRK(mask)) >> TAL_BRKSTATUS_EVBRK_Pos; -} - -static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_EVBRK_bf(const void *const hw) -{ - return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EVBRK_Msk) >> TAL_BRKSTATUS_EVBRK_Pos; -} - -static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_EXTBRK_bf(const void *const hw, - hri_tal_brkstatus_reg_t mask) -{ - return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EXTBRK(mask)) >> TAL_BRKSTATUS_EXTBRK_Pos; -} - -static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_EXTBRK_bf(const void *const hw) -{ - return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EXTBRK_Msk) >> TAL_BRKSTATUS_EXTBRK_Pos; -} - -static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_reg(const void *const hw, hri_tal_brkstatus_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tal *)hw)->BRKSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_reg(const void *const hw) -{ - return ((Tal *)hw)->BRKSTATUS.reg; -} - -static inline bool hri_tal_get_INTSTATUS_IRQ0_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ0) >> TAL_INTSTATUS_IRQ0_Pos; -} - -static inline bool hri_tal_get_INTSTATUS_IRQ1_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ1) >> TAL_INTSTATUS_IRQ1_Pos; -} - -static inline bool hri_tal_get_INTSTATUS_IRQ2_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ2) >> TAL_INTSTATUS_IRQ2_Pos; -} - -static inline bool hri_tal_get_INTSTATUS_IRQ3_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ3) >> TAL_INTSTATUS_IRQ3_Pos; -} - -static inline bool hri_tal_get_INTSTATUS_IRQ4_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ4) >> TAL_INTSTATUS_IRQ4_Pos; -} - -static inline bool hri_tal_get_INTSTATUS_IRQ5_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ5) >> TAL_INTSTATUS_IRQ5_Pos; -} - -static inline bool hri_tal_get_INTSTATUS_IRQ6_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ6) >> TAL_INTSTATUS_IRQ6_Pos; -} - -static inline bool hri_tal_get_INTSTATUS_IRQ7_bit(const void *const hw, uint8_t index) -{ - return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ7) >> TAL_INTSTATUS_IRQ7_Pos; -} - -static inline hri_tal_intstatus_reg_t hri_tal_get_INTSTATUS_reg(const void *const hw, uint8_t index, - hri_tal_intstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->INTSTATUS[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_tal_intstatus_reg_t hri_tal_read_INTSTATUS_reg(const void *const hw, uint8_t index) -{ - return ((Tal *)hw)->INTSTATUS[index].reg; -} - -static inline hri_tal_cpuirqs_reg_t hri_talcpuirqs_get_CPUIRQS_CPUIRQS_bf(const void *const hw, uint8_t index, - hri_tal_cpuirqs_reg_t mask) -{ - return (((TalCpuirqs *)hw)->CPUIRQS[index].reg & TAL_CPUIRQS_CPUIRQS(mask)) >> TAL_CPUIRQS_CPUIRQS_Pos; -} - -static inline hri_tal_cpuirqs_reg_t hri_talcpuirqs_read_CPUIRQS_CPUIRQS_bf(const void *const hw, uint8_t index) -{ - return (((TalCpuirqs *)hw)->CPUIRQS[index].reg & TAL_CPUIRQS_CPUIRQS_Msk) >> TAL_CPUIRQS_CPUIRQS_Pos; -} - -static inline hri_tal_cpuirqs_reg_t hri_talcpuirqs_get_CPUIRQS_reg(const void *const hw, uint8_t index, - hri_tal_cpuirqs_reg_t mask) -{ - uint32_t tmp; - tmp = ((TalCpuirqs *)hw)->CPUIRQS[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_tal_cpuirqs_reg_t hri_talcpuirqs_read_CPUIRQS_reg(const void *const hw, uint8_t index) -{ - return ((TalCpuirqs *)hw)->CPUIRQS[index].reg; -} - -static inline hri_tal_cpuirqs_reg_t hri_tal_get_CPUIRQS_CPUIRQS_bf(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_tal_cpuirqs_reg_t mask) -{ - return (((Tal *)hw)->Cpuirqs[submodule_index].CPUIRQS[index].reg & TAL_CPUIRQS_CPUIRQS(mask)) - >> TAL_CPUIRQS_CPUIRQS_Pos; -} - -static inline hri_tal_cpuirqs_reg_t hri_tal_read_CPUIRQS_CPUIRQS_bf(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - return (((Tal *)hw)->Cpuirqs[submodule_index].CPUIRQS[index].reg & TAL_CPUIRQS_CPUIRQS_Msk) - >> TAL_CPUIRQS_CPUIRQS_Pos; -} - -static inline hri_tal_cpuirqs_reg_t hri_tal_get_CPUIRQS_reg(const void *const hw, uint8_t submodule_index, - uint8_t index, hri_tal_cpuirqs_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tal *)hw)->Cpuirqs[submodule_index].CPUIRQS[index].reg; - tmp &= mask; - return tmp; -} - -static inline hri_tal_cpuirqs_reg_t hri_tal_read_CPUIRQS_reg(const void *const hw, uint8_t submodule_index, - uint8_t index) -{ - return ((Tal *)hw)->Cpuirqs[submodule_index].CPUIRQS[index].reg; -} - -static inline void hri_talctis_set_CTICTRLA_RESTART_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg |= TAL_CTICTRLA_RESTART; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talctis_get_CTICTRLA_RESTART_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((TalCtis *)hw)->CTICTRLA.reg; - tmp = (tmp & TAL_CTICTRLA_RESTART) >> TAL_CTICTRLA_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_talctis_write_CTICTRLA_RESTART_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalCtis *)hw)->CTICTRLA.reg; - tmp &= ~TAL_CTICTRLA_RESTART; - tmp |= value << TAL_CTICTRLA_RESTART_Pos; - ((TalCtis *)hw)->CTICTRLA.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_clear_CTICTRLA_RESTART_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg &= ~TAL_CTICTRLA_RESTART; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_toggle_CTICTRLA_RESTART_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg ^= TAL_CTICTRLA_RESTART; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_set_CTICTRLA_IPS_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg |= TAL_CTICTRLA_IPS; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talctis_get_CTICTRLA_IPS_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((TalCtis *)hw)->CTICTRLA.reg; - tmp = (tmp & TAL_CTICTRLA_IPS) >> TAL_CTICTRLA_IPS_Pos; - return (bool)tmp; -} - -static inline void hri_talctis_write_CTICTRLA_IPS_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalCtis *)hw)->CTICTRLA.reg; - tmp &= ~TAL_CTICTRLA_IPS; - tmp |= value << TAL_CTICTRLA_IPS_Pos; - ((TalCtis *)hw)->CTICTRLA.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_clear_CTICTRLA_IPS_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg &= ~TAL_CTICTRLA_IPS; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_toggle_CTICTRLA_IPS_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg ^= TAL_CTICTRLA_IPS; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_set_CTICTRLA_BRK_bf(const void *const hw, hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg |= TAL_CTICTRLA_BRK(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctictrla_reg_t hri_talctis_get_CTICTRLA_BRK_bf(const void *const hw, hri_tal_ctictrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((TalCtis *)hw)->CTICTRLA.reg; - tmp = (tmp & TAL_CTICTRLA_BRK(mask)) >> TAL_CTICTRLA_BRK_Pos; - return tmp; -} - -static inline void hri_talctis_write_CTICTRLA_BRK_bf(const void *const hw, hri_tal_ctictrla_reg_t data) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalCtis *)hw)->CTICTRLA.reg; - tmp &= ~TAL_CTICTRLA_BRK_Msk; - tmp |= TAL_CTICTRLA_BRK(data); - ((TalCtis *)hw)->CTICTRLA.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_clear_CTICTRLA_BRK_bf(const void *const hw, hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg &= ~TAL_CTICTRLA_BRK(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_toggle_CTICTRLA_BRK_bf(const void *const hw, hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg ^= TAL_CTICTRLA_BRK(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctictrla_reg_t hri_talctis_read_CTICTRLA_BRK_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((TalCtis *)hw)->CTICTRLA.reg; - tmp = (tmp & TAL_CTICTRLA_BRK_Msk) >> TAL_CTICTRLA_BRK_Pos; - return tmp; -} - -static inline void hri_talctis_set_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctictrla_reg_t hri_talctis_get_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((TalCtis *)hw)->CTICTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_talctis_write_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_clear_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_toggle_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTICTRLA.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctictrla_reg_t hri_talctis_read_CTICTRLA_reg(const void *const hw) -{ - return ((TalCtis *)hw)->CTICTRLA.reg; -} - -static inline void hri_talctis_set_CTIMASK_CPU0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_CPU0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talctis_get_CTIMASK_CPU0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((TalCtis *)hw)->CTIMASK.reg; - tmp = (tmp & TAL_CTIMASK_CPU0) >> TAL_CTIMASK_CPU0_Pos; - return (bool)tmp; -} - -static inline void hri_talctis_write_CTIMASK_CPU0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalCtis *)hw)->CTIMASK.reg; - tmp &= ~TAL_CTIMASK_CPU0; - tmp |= value << TAL_CTIMASK_CPU0_Pos; - ((TalCtis *)hw)->CTIMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_clear_CTIMASK_CPU0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_CPU0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_toggle_CTIMASK_CPU0_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_CPU0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_set_CTIMASK_CPU1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_CPU1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talctis_get_CTIMASK_CPU1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((TalCtis *)hw)->CTIMASK.reg; - tmp = (tmp & TAL_CTIMASK_CPU1) >> TAL_CTIMASK_CPU1_Pos; - return (bool)tmp; -} - -static inline void hri_talctis_write_CTIMASK_CPU1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalCtis *)hw)->CTIMASK.reg; - tmp &= ~TAL_CTIMASK_CPU1; - tmp |= value << TAL_CTIMASK_CPU1_Pos; - ((TalCtis *)hw)->CTIMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_clear_CTIMASK_CPU1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_CPU1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_toggle_CTIMASK_CPU1_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_CPU1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_set_CTIMASK_EVBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_EVBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talctis_get_CTIMASK_EVBRK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((TalCtis *)hw)->CTIMASK.reg; - tmp = (tmp & TAL_CTIMASK_EVBRK) >> TAL_CTIMASK_EVBRK_Pos; - return (bool)tmp; -} - -static inline void hri_talctis_write_CTIMASK_EVBRK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalCtis *)hw)->CTIMASK.reg; - tmp &= ~TAL_CTIMASK_EVBRK; - tmp |= value << TAL_CTIMASK_EVBRK_Pos; - ((TalCtis *)hw)->CTIMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_clear_CTIMASK_EVBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_EVBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_toggle_CTIMASK_EVBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_EVBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_set_CTIMASK_EXTBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_EXTBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_talctis_get_CTIMASK_EXTBRK_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((TalCtis *)hw)->CTIMASK.reg; - tmp = (tmp & TAL_CTIMASK_EXTBRK) >> TAL_CTIMASK_EXTBRK_Pos; - return (bool)tmp; -} - -static inline void hri_talctis_write_CTIMASK_EXTBRK_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((TalCtis *)hw)->CTIMASK.reg; - tmp &= ~TAL_CTIMASK_EXTBRK; - tmp |= value << TAL_CTIMASK_EXTBRK_Pos; - ((TalCtis *)hw)->CTIMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_clear_CTIMASK_EXTBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_EXTBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_toggle_CTIMASK_EXTBRK_bit(const void *const hw) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_EXTBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_set_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctimask_reg_t hri_talctis_get_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask) -{ - uint8_t tmp; - tmp = ((TalCtis *)hw)->CTIMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_talctis_write_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_clear_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_talctis_toggle_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((TalCtis *)hw)->CTIMASK.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctimask_reg_t hri_talctis_read_CTIMASK_reg(const void *const hw) -{ - return ((TalCtis *)hw)->CTIMASK.reg; -} - -static inline void hri_tal_set_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg |= TAL_CTICTRLA_RESTART; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; - tmp = (tmp & TAL_CTICTRLA_RESTART) >> TAL_CTICTRLA_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; - tmp &= ~TAL_CTICTRLA_RESTART; - tmp |= value << TAL_CTICTRLA_RESTART_Pos; - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg &= ~TAL_CTICTRLA_RESTART; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg ^= TAL_CTICTRLA_RESTART; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_CTICTRLA_IPS_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg |= TAL_CTICTRLA_IPS; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_CTICTRLA_IPS_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; - tmp = (tmp & TAL_CTICTRLA_IPS) >> TAL_CTICTRLA_IPS_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_CTICTRLA_IPS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; - tmp &= ~TAL_CTICTRLA_IPS; - tmp |= value << TAL_CTICTRLA_IPS_Pos; - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_CTICTRLA_IPS_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg &= ~TAL_CTICTRLA_IPS; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_CTICTRLA_IPS_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg ^= TAL_CTICTRLA_IPS; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index, - hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg |= TAL_CTICTRLA_BRK(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctictrla_reg_t hri_tal_get_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index, - hri_tal_ctictrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; - tmp = (tmp & TAL_CTICTRLA_BRK(mask)) >> TAL_CTICTRLA_BRK_Pos; - return tmp; -} - -static inline void hri_tal_write_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index, - hri_tal_ctictrla_reg_t data) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; - tmp &= ~TAL_CTICTRLA_BRK_Msk; - tmp |= TAL_CTICTRLA_BRK(data); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index, - hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg &= ~TAL_CTICTRLA_BRK(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index, - hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg ^= TAL_CTICTRLA_BRK(mask); - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctictrla_reg_t hri_tal_read_CTICTRLA_BRK_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; - tmp = (tmp & TAL_CTICTRLA_BRK_Msk) >> TAL_CTICTRLA_BRK_Pos; - return tmp; -} - -static inline void hri_tal_set_CTICTRLA_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctictrla_reg_t hri_tal_get_CTICTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_tal_ctictrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_CTICTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_tal_ctictrla_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_CTICTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_CTICTRLA_reg(const void *const hw, uint8_t submodule_index, - hri_tal_ctictrla_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctictrla_reg_t hri_tal_read_CTICTRLA_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg; -} - -static inline void hri_tal_set_CTIMASK_CPU0_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_CPU0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_CTIMASK_CPU0_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; - tmp = (tmp & TAL_CTIMASK_CPU0) >> TAL_CTIMASK_CPU0_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_CTIMASK_CPU0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; - tmp &= ~TAL_CTIMASK_CPU0; - tmp |= value << TAL_CTIMASK_CPU0_Pos; - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_CTIMASK_CPU0_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_CPU0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_CTIMASK_CPU0_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_CPU0; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_CTIMASK_CPU1_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_CPU1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_CTIMASK_CPU1_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; - tmp = (tmp & TAL_CTIMASK_CPU1) >> TAL_CTIMASK_CPU1_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_CTIMASK_CPU1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; - tmp &= ~TAL_CTIMASK_CPU1; - tmp |= value << TAL_CTIMASK_CPU1_Pos; - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_CTIMASK_CPU1_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_CPU1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_CTIMASK_CPU1_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_CPU1; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_EVBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; - tmp = (tmp & TAL_CTIMASK_EVBRK) >> TAL_CTIMASK_EVBRK_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; - tmp &= ~TAL_CTIMASK_EVBRK; - tmp |= value << TAL_CTIMASK_EVBRK_Pos; - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_EVBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_EVBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_EXTBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tal_get_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; - tmp = (tmp & TAL_CTIMASK_EXTBRK) >> TAL_CTIMASK_EXTBRK_Pos; - return (bool)tmp; -} - -static inline void hri_tal_write_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - TAL_CRITICAL_SECTION_ENTER(); - tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; - tmp &= ~TAL_CTIMASK_EXTBRK; - tmp |= value << TAL_CTIMASK_EXTBRK_Pos; - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_EXTBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_EXTBRK; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_set_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctimask_reg_t hri_tal_get_CTIMASK_reg(const void *const hw, uint8_t submodule_index, - hri_tal_ctimask_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tal_write_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t data) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = data; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_clear_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tal_toggle_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t mask) -{ - TAL_CRITICAL_SECTION_ENTER(); - ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= mask; - TAL_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tal_ctimask_reg_t hri_tal_read_CTIMASK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TAL_D51_H_INCLUDED */ -#endif /* _SAMD51_TAL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_tc_d51.h b/atmel-samd/asf4/samd51/hri/hri_tc_d51.h deleted file mode 100644 index 481295858..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_tc_d51.h +++ /dev/null @@ -1,2861 +0,0 @@ -/** - * \file - * - * \brief SAM TC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_TC_COMPONENT_ -#ifndef _HRI_TC_D51_H_INCLUDED_ -#define _HRI_TC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TC_CRITICAL_SECTIONS) -#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TC_CRITICAL_SECTION_ENTER() -#define TC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_tc_cc16_reg_t; -typedef uint16_t hri_tc_ccbuf16_reg_t; -typedef uint16_t hri_tc_count16_reg_t; -typedef uint16_t hri_tc_evctrl_reg_t; -typedef uint32_t hri_tc_cc32_reg_t; -typedef uint32_t hri_tc_ccbuf32_reg_t; -typedef uint32_t hri_tc_count32_reg_t; -typedef uint32_t hri_tc_ctrla_reg_t; -typedef uint32_t hri_tc_syncbusy_reg_t; -typedef uint8_t hri_tc_cc8_reg_t; -typedef uint8_t hri_tc_ccbuf8_reg_t; -typedef uint8_t hri_tc_count8_reg_t; -typedef uint8_t hri_tc_ctrlbset_reg_t; -typedef uint8_t hri_tc_dbgctrl_reg_t; -typedef uint8_t hri_tc_drvctrl_reg_t; -typedef uint8_t hri_tc_intenset_reg_t; -typedef uint8_t hri_tc_intflag_reg_t; -typedef uint8_t hri_tc_per_reg_t; -typedef uint8_t hri_tc_perbuf_reg_t; -typedef uint8_t hri_tc_status_reg_t; -typedef uint8_t hri_tc_wave_reg_t; - -static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) -{ - while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) -{ - return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; -} - -static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; - tmp |= TC_COUNT16_COUNT_COUNT(data); - ((Tc *)hw)->COUNT16.COUNT.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count16_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tc_count16_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tc_count16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count16_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT16.COUNT.reg; -} - -static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp &= ~TC_COUNT16_CC_CC_Msk; - tmp |= TC_COUNT16_CC_CC(data); - ((Tc *)hw)->COUNT16.CC[index].reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc16_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc16_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) -{ - return ((Tc *)hw)->COUNT16.CC[index].reg; -} - -static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf16_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tc_ccbuf16_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT16_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf16_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf16_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tc_ccbuf16_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf16_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf16_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - return ((Tc *)hw)->COUNT16.CCBUF[index].reg; -} - -static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; - tmp |= TC_COUNT32_COUNT_COUNT(data); - ((Tc *)hw)->COUNT32.COUNT.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count32_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tc_count32_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tc_count32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count32_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT32.COUNT.reg; -} - -static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp &= ~TC_COUNT32_CC_CC_Msk; - tmp |= TC_COUNT32_CC_CC(data); - ((Tc *)hw)->COUNT32.CC[index].reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc32_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc32_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) -{ - return ((Tc *)hw)->COUNT32.CC[index].reg; -} - -static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf32_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tc_ccbuf32_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT32_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf32_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf32_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tc_ccbuf32_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf32_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf32_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - return ((Tc *)hw)->COUNT32.CCBUF[index].reg; -} - -static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR; -} - -static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; -} - -static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR; - } else { - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_DIR; - } -} - -static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_DIR; -} - -static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_LUPD; -} - -static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_LUPD; - } else { - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_LUPD; - } -} - -static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_LUPD; -} - -static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; -} - -static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; -} - -static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; - } else { - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; - } -} - -static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; -} - -static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; - tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; - tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = TC_CTRLBSET_CMD(data); - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); -} - -static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); -} - -static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = mask; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.CTRLBSET.reg; -} - -static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) -{ - ((Tc *)hw)->COUNT8.CTRLBSET.reg = data; - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = ~data; -} - -static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.CTRLBCLR.reg = mask; -} - -static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF; -} - -static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; -} - -static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF; - } else { - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_OVF; - } -} - -static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_OVF; -} - -static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR; -} - -static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; -} - -static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR; - } else { - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_ERR; - } -} - -static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_ERR; -} - -static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0; -} - -static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; -} - -static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0; - } else { - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC0; - } -} - -static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC0; -} - -static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1; -} - -static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; -} - -static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1; - } else { - ((Tc *)hw)->COUNT8.INTENSET.reg = TC_INTENSET_MC1; - } -} - -static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTENCLR.reg = TC_INTENSET_MC1; -} - -static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = mask; -} - -static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.INTENSET.reg; -} - -static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) -{ - ((Tc *)hw)->COUNT8.INTENSET.reg = data; - ((Tc *)hw)->COUNT8.INTENCLR.reg = ~data; -} - -static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) -{ - ((Tc *)hw)->COUNT8.INTENCLR.reg = mask; -} - -static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; -} - -static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; -} - -static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; -} - -static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; -} - -static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; -} - -static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0; -} - -static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; -} - -static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1; -} - -static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; -} - -static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_OVF; -} - -static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; -} - -static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_ERR; -} - -static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; -} - -static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC0; -} - -static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; -} - -static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = TC_INTFLAG_MC1; -} - -static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.INTFLAG.reg; -} - -static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) -{ - ((Tc *)hw)->COUNT8.INTFLAG.reg = mask; -} - -static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_SWRST; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ENABLE; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_ENABLE; - tmp |= value << TC_CTRLA_ENABLE_Pos; - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ENABLE; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ENABLE; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_RUNSTDBY; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_RUNSTDBY; - tmp |= value << TC_CTRLA_RUNSTDBY_Pos; - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ONDEMAND; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_ONDEMAND; - tmp |= value << TC_CTRLA_ONDEMAND_Pos; - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ONDEMAND; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_ALOCK; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_ALOCK; - tmp |= value << TC_CTRLA_ALOCK_Pos; - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_ALOCK; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_ALOCK; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_CAPTEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTEN0; - tmp |= value << TC_CTRLA_CAPTEN0_Pos; - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_CAPTEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_CAPTEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTEN1; - tmp |= value << TC_CTRLA_CAPTEN1_Pos; - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_CAPTEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_COPEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_COPEN0; - tmp |= value << TC_CTRLA_COPEN0_Pos; - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_COPEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_COPEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_COPEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_COPEN1; - tmp |= value << TC_CTRLA_COPEN1_Pos; - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_COPEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_COPEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_MODE(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_MODE_Msk; - tmp |= TC_CTRLA_MODE(data); - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_MODE(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_MODE(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_PRESCSYNC_Msk; - tmp |= TC_CTRLA_PRESCSYNC(data); - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_PRESCALER_Msk; - tmp |= TC_CTRLA_PRESCALER(data); - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTMODE0_Msk; - tmp |= TC_CTRLA_CAPTMODE0(data); - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos; - return tmp; -} - -static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data) -{ - uint32_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= ~TC_CTRLA_CAPTMODE1_Msk; - tmp |= TC_CTRLA_CAPTMODE1(data); - ((Tc *)hw)->COUNT8.CTRLA.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos; - return tmp; -} - -static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CTRLA.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.CTRLA.reg; -} - -static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_TCINV; - tmp |= value << TC_EVCTRL_TCINV_Pos; - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCINV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_TCEI; - tmp |= value << TC_EVCTRL_TCEI_Pos; - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_TCEI; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_OVFEO; - tmp |= value << TC_EVCTRL_OVFEO_Pos; - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_OVFEO; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_MCEO0; - tmp |= value << TC_EVCTRL_MCEO0_Pos; - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_MCEO1; - tmp |= value << TC_EVCTRL_MCEO1_Pos; - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_MCEO1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) -{ - uint16_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= ~TC_EVCTRL_EVACT_Msk; - tmp |= TC_EVCTRL_EVACT(data); - ((Tc *)hw)->COUNT8.EVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; - return tmp; -} - -static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tc *)hw)->COUNT8.EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.EVCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.EVCTRL.reg; -} - -static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.WAVE.reg |= TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.WAVE.reg; - tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.WAVE.reg; - tmp &= ~TC_WAVE_WAVEGEN_Msk; - tmp |= TC_WAVE_WAVEGEN(data); - ((Tc *)hw)->COUNT8.WAVE.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.WAVE.reg; - tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.WAVE.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.WAVE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.WAVE.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.WAVE.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.WAVE.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.WAVE.reg; -} - -static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg; - tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg; - tmp &= ~TC_DRVCTRL_INVEN0; - tmp |= value << TC_DRVCTRL_INVEN0_Pos; - ((Tc *)hw)->COUNT8.DRVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg; - tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg; - tmp &= ~TC_DRVCTRL_INVEN1; - tmp |= value << TC_DRVCTRL_INVEN1_Pos; - ((Tc *)hw)->COUNT8.DRVCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DRVCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.DRVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DRVCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DRVCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DRVCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.DRVCTRL.reg; -} - -static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; - tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; - tmp &= ~TC_DBGCTRL_DBGRUN; - tmp |= value << TC_DBGCTRL_DBGRUN_Pos; - ((Tc *)hw)->COUNT8.DBGCTRL.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.DBGCTRL.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.DBGCTRL.reg; -} - -static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; - tmp |= TC_COUNT8_COUNT_COUNT(data); - ((Tc *)hw)->COUNT8.COUNT.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count8_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tc_count8_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tc_count8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_count8_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.COUNT.reg; -} - -static inline void hri_tc_set_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_per_reg_t hri_tc_get_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; - return tmp; -} - -static inline void hri_tc_write_PER_PER_bf(const void *const hw, hri_tc_per_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp &= ~TC_COUNT8_PER_PER_Msk; - tmp |= TC_COUNT8_PER_PER(data); - ((Tc *)hw)->COUNT8.PER.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_PER_PER_bf(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_per_reg_t hri_tc_read_PER_PER_bf(const void *const hw) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; - return tmp; -} - -static inline void hri_tc_set_PER_reg(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_per_reg_t hri_tc_get_PER_reg(const void *const hw, hri_tc_per_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_PER_reg(const void *const hw, hri_tc_per_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_PER_reg(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_PER_reg(const void *const hw, hri_tc_per_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PER.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_per_reg_t hri_tc_read_PER_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.PER.reg; -} - -static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp &= ~TC_COUNT8_CC_CC_Msk; - tmp |= TC_COUNT8_CC_CC(data); - ((Tc *)hw)->COUNT8.CC[index].reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; - return tmp; -} - -static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc8_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tc_cc8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_cc8_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) -{ - return ((Tc *)hw)->COUNT8.CC[index].reg; -} - -static inline void hri_tc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_perbuf_reg_t hri_tc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; - tmp |= TC_COUNT8_PERBUF_PERBUF(data); - ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tc_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_perbuf_reg_t hri_tc_read_PERBUF_PERBUF_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tc_set_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_perbuf_reg_t hri_tc_get_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_write_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_clear_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tc_toggle_PERBUF_reg(const void *const hw, hri_tc_perbuf_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_perbuf_reg_t hri_tc_read_PERBUF_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.PERBUF.reg; -} - -static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf8_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tc_ccbuf8_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t data) -{ - uint8_t tmp; - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; - tmp |= TC_COUNT8_CCBUF_CCBUF(data); - ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf8_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf8_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, - hri_tc_ccbuf8_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t data) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tc_ccbuf8_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_ccbuf8_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - return ((Tc *)hw)->COUNT8.CCBUF[index].reg; -} - -static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Tc *)hw)->COUNT8.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; -} - -static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tc *)hw)->COUNT8.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.SYNCBUSY.reg; -} - -static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; -} - -static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_STOP; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; -} - -static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_SLAVE; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; -} - -static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_PERBUFV; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; -} - -static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_CCBUFV0; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) -{ - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - return (((Tc *)hw)->COUNT8.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; -} - -static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) -{ - TC_CRITICAL_SECTION_ENTER(); - hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); - ((Tc *)hw)->COUNT8.STATUS.reg = TC_STATUS_CCBUFV1; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tc *)hw)->COUNT8.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) -{ - TC_CRITICAL_SECTION_ENTER(); - ((Tc *)hw)->COUNT8.STATUS.reg = mask; - TC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) -{ - return ((Tc *)hw)->COUNT8.STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TC_D51_H_INCLUDED */ -#endif /* _SAMD51_TC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_tcc_d51.h b/atmel-samd/asf4/samd51/hri/hri_tcc_d51.h deleted file mode 100644 index 8a2472887..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_tcc_d51.h +++ /dev/null @@ -1,10329 +0,0 @@ -/** - * \file - * - * \brief SAM TCC - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_TCC_COMPONENT_ -#ifndef _HRI_TCC_D51_H_INCLUDED_ -#define _HRI_TCC_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TCC_CRITICAL_SECTIONS) -#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TCC_CRITICAL_SECTION_ENTER() -#define TCC_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_tcc_patt_reg_t; -typedef uint16_t hri_tcc_pattbuf_reg_t; -typedef uint32_t hri_tcc_cc_reg_t; -typedef uint32_t hri_tcc_ccbuf_reg_t; -typedef uint32_t hri_tcc_count_reg_t; -typedef uint32_t hri_tcc_ctrla_reg_t; -typedef uint32_t hri_tcc_drvctrl_reg_t; -typedef uint32_t hri_tcc_evctrl_reg_t; -typedef uint32_t hri_tcc_fctrla_reg_t; -typedef uint32_t hri_tcc_fctrlb_reg_t; -typedef uint32_t hri_tcc_intenset_reg_t; -typedef uint32_t hri_tcc_intflag_reg_t; -typedef uint32_t hri_tcc_per_reg_t; -typedef uint32_t hri_tcc_perbuf_reg_t; -typedef uint32_t hri_tcc_status_reg_t; -typedef uint32_t hri_tcc_syncbusy_reg_t; -typedef uint32_t hri_tcc_wave_reg_t; -typedef uint32_t hri_tcc_wexctrl_reg_t; -typedef uint8_t hri_tcc_ctrlbset_reg_t; -typedef uint8_t hri_tcc_dbgctrl_reg_t; - -static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) -{ - while (((Tcc *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) -{ - return ((Tcc *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH4_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH4_COUNT(mask)) >> TCC_COUNT_DITH4_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_DITH4_COUNT_Msk; - tmp |= TCC_COUNT_DITH4_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH4_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH4_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH4_COUNT_Msk) >> TCC_COUNT_DITH4_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH5_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH5_COUNT(mask)) >> TCC_COUNT_DITH5_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_DITH5_COUNT_Msk; - tmp |= TCC_COUNT_DITH5_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH5_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH5_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH5_COUNT_Msk) >> TCC_COUNT_DITH5_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH6_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH6_COUNT(mask)) >> TCC_COUNT_DITH6_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_DITH6_COUNT_Msk; - tmp |= TCC_COUNT_DITH6_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH6_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH6_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_DITH6_COUNT_Msk) >> TCC_COUNT_DITH6_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= ~TCC_COUNT_COUNT_Msk; - tmp |= TCC_COUNT_COUNT(data); - ((Tcc *)hw)->COUNT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; - return tmp; -} - -static inline void hri_tcc_set_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_reg(const void *const hw) -{ - return ((Tcc *)hw)->COUNT.reg; -} - -static inline void hri_tcc_set_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_reg(const void *const hw) -{ - return ((Tcc *)hw)->COUNT.reg; -} - -static inline void hri_tcc_set_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_reg(const void *const hw) -{ - return ((Tcc *)hw)->COUNT.reg; -} - -static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->COUNT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->COUNT.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) -{ - return ((Tcc *)hw)->COUNT.reg; -} - -static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH4_DITHER_Msk; - tmp |= TCC_PER_DITH4_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_PER(mask)) >> TCC_PER_DITH4_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH4_PER_Msk; - tmp |= TCC_PER_DITH4_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH4_PER_Msk) >> TCC_PER_DITH4_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH5_DITHER_Msk; - tmp |= TCC_PER_DITH5_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_PER(mask)) >> TCC_PER_DITH5_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH5_PER_Msk; - tmp |= TCC_PER_DITH5_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH5_PER_Msk) >> TCC_PER_DITH5_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH6_DITHER_Msk; - tmp |= TCC_PER_DITH6_DITHER(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_PER(mask)) >> TCC_PER_DITH6_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_DITH6_PER_Msk; - tmp |= TCC_PER_DITH6_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_DITH6_PER_Msk) >> TCC_PER_DITH6_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PER.reg; - tmp &= ~TCC_PER_PER_Msk; - tmp |= TCC_PER_PER(data); - ((Tcc *)hw)->PER.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; - return tmp; -} - -static inline void hri_tcc_set_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_reg(const void *const hw) -{ - return ((Tcc *)hw)->PER.reg; -} - -static inline void hri_tcc_set_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_reg(const void *const hw) -{ - return ((Tcc *)hw)->PER.reg; -} - -static inline void hri_tcc_set_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_reg(const void *const hw) -{ - return ((Tcc *)hw)->PER.reg; -} - -static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PER.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PER.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) -{ - return ((Tcc *)hw)->PER.reg; -} - -static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH4_DITHER_Msk; - tmp |= TCC_CC_DITH4_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_CC(mask)) >> TCC_CC_DITH4_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH4_CC_Msk; - tmp |= TCC_CC_DITH4_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH4_CC_Msk) >> TCC_CC_DITH4_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH5_DITHER_Msk; - tmp |= TCC_CC_DITH5_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_CC(mask)) >> TCC_CC_DITH5_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH5_CC_Msk; - tmp |= TCC_CC_DITH5_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH5_CC_Msk) >> TCC_CC_DITH5_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, - hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH6_DITHER_Msk; - tmp |= TCC_CC_DITH6_DITHER(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_CC(mask)) >> TCC_CC_DITH6_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_DITH6_CC_Msk; - tmp |= TCC_CC_DITH6_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_DITH6_CC_Msk) >> TCC_CC_DITH6_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= ~TCC_CC_CC_Msk; - tmp |= TCC_CC_CC(data); - ((Tcc *)hw)->CC[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CC[index].reg; -} - -static inline void hri_tcc_set_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CC[index].reg; -} - -static inline void hri_tcc_set_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CC[index].reg; -} - -static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CC[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CC[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CC[index].reg; -} - -static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH4_PERBUF(mask)) >> TCC_PERBUF_DITH4_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH4_PERBUF_Msk; - tmp |= TCC_PERBUF_DITH4_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH4_PERBUF_Msk) >> TCC_PERBUF_DITH4_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH5_PERBUF(mask)) >> TCC_PERBUF_DITH5_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH5_PERBUF_Msk; - tmp |= TCC_PERBUF_DITH5_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH5_PERBUF_Msk) >> TCC_PERBUF_DITH5_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, - hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; - tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH6_PERBUF(mask)) >> TCC_PERBUF_DITH6_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_DITH6_PERBUF_Msk; - tmp |= TCC_PERBUF_DITH6_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_DITH6_PERBUF_Msk) >> TCC_PERBUF_DITH6_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= ~TCC_PERBUF_PERBUF_Msk; - tmp |= TCC_PERBUF_PERBUF(data); - ((Tcc *)hw)->PERBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_reg(const void *const hw) -{ - return ((Tcc *)hw)->PERBUF.reg; -} - -static inline void hri_tcc_set_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_reg(const void *const hw) -{ - return ((Tcc *)hw)->PERBUF.reg; -} - -static inline void hri_tcc_set_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_reg(const void *const hw) -{ - return ((Tcc *)hw)->PERBUF.reg; -} - -static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->PERBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PERBUF.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) -{ - return ((Tcc *)hw)->PERBUF.reg; -} - -static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH4_CCBUF(mask)) >> TCC_CCBUF_DITH4_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH4_CCBUF_Msk; - tmp |= TCC_CCBUF_DITH4_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH4_CCBUF_Msk) >> TCC_CCBUF_DITH4_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH5_CCBUF(mask)) >> TCC_CCBUF_DITH5_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH5_CCBUF_Msk; - tmp |= TCC_CCBUF_DITH5_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH5_CCBUF_Msk) >> TCC_CCBUF_DITH5_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; - tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH6_CCBUF(mask)) >> TCC_CCBUF_DITH6_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_DITH6_CCBUF_Msk; - tmp |= TCC_CCBUF_DITH6_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_DITH6_CCBUF_Msk) >> TCC_CCBUF_DITH6_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= ~TCC_CCBUF_CCBUF_Msk; - tmp |= TCC_CCBUF_CCBUF(data); - ((Tcc *)hw)->CCBUF[index].reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; - return tmp; -} - -static inline void hri_tcc_set_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_reg(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CCBUF[index].reg; -} - -static inline void hri_tcc_set_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_reg(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CCBUF[index].reg; -} - -static inline void hri_tcc_set_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_reg(const void *const hw, uint8_t index, - hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CCBUF[index].reg; -} - -static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CCBUF[index].reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CCBUF[index].reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) -{ - return ((Tcc *)hw)->CCBUF[index].reg; -} - -static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; -} - -static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; -} - -static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; - } -} - -static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; -} - -static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; -} - -static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; -} - -static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; - } -} - -static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; -} - -static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; -} - -static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) -{ - return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; -} - -static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; - } else { - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; - } -} - -static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; -} - -static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); - ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); -} - -static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); -} - -static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); - ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); -} - -static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); -} - -static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBSET.reg = mask; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->CTRLBSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) -{ - return ((Tcc *)hw)->CTRLBSET.reg; -} - -static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) -{ - ((Tcc *)hw)->CTRLBSET.reg = data; - ((Tcc *)hw)->CTRLBCLR.reg = ~data; -} - -static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) -{ - ((Tcc *)hw)->CTRLBCLR.reg = mask; -} - -static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; -} - -static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; -} - -static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; - } -} - -static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; -} - -static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; -} - -static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; -} - -static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; - } -} - -static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; -} - -static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; -} - -static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; -} - -static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; - } -} - -static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; -} - -static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; -} - -static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; -} - -static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; - } -} - -static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; -} - -static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; -} - -static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; -} - -static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; - } -} - -static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; -} - -static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; -} - -static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; -} - -static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; - } -} - -static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; -} - -static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; -} - -static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; - } -} - -static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; -} - -static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; -} - -static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; - } -} - -static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; -} - -static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; -} - -static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; - } -} - -static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; -} - -static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; -} - -static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; -} - -static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; - } -} - -static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; -} - -static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; -} - -static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; -} - -static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; - } -} - -static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; -} - -static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; -} - -static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; -} - -static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; - } -} - -static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; -} - -static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; -} - -static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; -} - -static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; - } -} - -static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; -} - -static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; -} - -static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; -} - -static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; - } -} - -static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; -} - -static inline void hri_tcc_set_INTEN_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; -} - -static inline bool hri_tcc_get_INTEN_MC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC4) >> TCC_INTENSET_MC4_Pos; -} - -static inline void hri_tcc_write_INTEN_MC4_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; - } -} - -static inline void hri_tcc_clear_INTEN_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; -} - -static inline void hri_tcc_set_INTEN_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; -} - -static inline bool hri_tcc_get_INTEN_MC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC5) >> TCC_INTENSET_MC5_Pos; -} - -static inline void hri_tcc_write_INTEN_MC5_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; - } else { - ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; - } -} - -static inline void hri_tcc_clear_INTEN_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; -} - -static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - ((Tcc *)hw)->INTENSET.reg = mask; -} - -static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) -{ - return ((Tcc *)hw)->INTENSET.reg; -} - -static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) -{ - ((Tcc *)hw)->INTENSET.reg = data; - ((Tcc *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) -{ - ((Tcc *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; -} - -static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; -} - -static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; -} - -static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; -} - -static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; -} - -static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; -} - -static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; -} - -static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; -} - -static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; -} - -static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; -} - -static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; -} - -static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; -} - -static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; -} - -static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; -} - -static inline bool hri_tcc_get_INTFLAG_MC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; -} - -static inline bool hri_tcc_get_INTFLAG_MC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; -} - -static inline void hri_tcc_clear_INTFLAG_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; -} - -static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; -} - -static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; -} - -static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; -} - -static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; -} - -static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; -} - -static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; -} - -static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; -} - -static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; -} - -static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; -} - -static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; -} - -static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; -} - -static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; -} - -static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; -} - -static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; -} - -static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; -} - -static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; -} - -static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; -} - -static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; -} - -static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; -} - -static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; -} - -static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; -} - -static inline bool hri_tcc_get_interrupt_MC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC4_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; -} - -static inline bool hri_tcc_get_interrupt_MC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; -} - -static inline void hri_tcc_clear_interrupt_MC5_bit(const void *const hw) -{ - ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; -} - -static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) -{ - return ((Tcc *)hw)->INTFLAG.reg; -} - -static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) -{ - ((Tcc *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint32_t tmp; - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_ENABLE; - tmp |= value << TCC_CTRLA_ENABLE_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_RUNSTDBY; - tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_ALOCK; - tmp |= value << TCC_CTRLA_ALOCK_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_MSYNC; - tmp |= value << TCC_CTRLA_MSYNC_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_DMAOS; - tmp |= value << TCC_CTRLA_DMAOS_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN0; - tmp |= value << TCC_CTRLA_CPTEN0_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN1; - tmp |= value << TCC_CTRLA_CPTEN1_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN2; - tmp |= value << TCC_CTRLA_CPTEN2_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN3; - tmp |= value << TCC_CTRLA_CPTEN3_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN4) >> TCC_CTRLA_CPTEN4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN4; - tmp |= value << TCC_CTRLA_CPTEN4_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_CPTEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_CTRLA_CPTEN5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_CPTEN5) >> TCC_CTRLA_CPTEN5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_CTRLA_CPTEN5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_CPTEN5; - tmp |= value << TCC_CTRLA_CPTEN5_Pos; - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_CPTEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_CPTEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_RESOLUTION_Msk; - tmp |= TCC_CTRLA_RESOLUTION(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_PRESCALER_Msk; - tmp |= TCC_CTRLA_PRESCALER(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; - tmp |= TCC_CTRLA_PRESCSYNC(data); - ((Tcc *)hw)->CTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; - return tmp; -} - -static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->CTRLA.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) -{ - return ((Tcc *)hw)->CTRLA.reg; -} - -static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_KEEP; - tmp |= value << TCC_FCTRLA_KEEP_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_QUAL; - tmp |= value << TCC_FCTRLA_QUAL_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_RESTART; - tmp |= value << TCC_FCTRLA_RESTART_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANKPRESC; - tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_SRC_Msk; - tmp |= TCC_FCTRLA_SRC(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANK_Msk; - tmp |= TCC_FCTRLA_BLANK(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_HALT_Msk; - tmp |= TCC_FCTRLA_HALT(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_CHSEL_Msk; - tmp |= TCC_FCTRLA_CHSEL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_CAPTURE_Msk; - tmp |= TCC_FCTRLA_CAPTURE(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; - tmp |= TCC_FCTRLA_BLANKVAL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; - tmp |= TCC_FCTRLA_FILTERVAL(data); - ((Tcc *)hw)->FCTRLA.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLA.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) -{ - return ((Tcc *)hw)->FCTRLA.reg; -} - -static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_KEEP; - tmp |= value << TCC_FCTRLB_KEEP_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_QUAL; - tmp |= value << TCC_FCTRLB_QUAL_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_RESTART; - tmp |= value << TCC_FCTRLB_RESTART_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANKPRESC; - tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_SRC_Msk; - tmp |= TCC_FCTRLB_SRC(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANK_Msk; - tmp |= TCC_FCTRLB_BLANK(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_HALT_Msk; - tmp |= TCC_FCTRLB_HALT(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_CHSEL_Msk; - tmp |= TCC_FCTRLB_CHSEL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_CAPTURE_Msk; - tmp |= TCC_FCTRLB_CAPTURE(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; - tmp |= TCC_FCTRLB_BLANKVAL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; - tmp |= TCC_FCTRLB_FILTERVAL(data); - ((Tcc *)hw)->FCTRLB.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; - return tmp; -} - -static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->FCTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->FCTRLB.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) -{ - return ((Tcc *)hw)->FCTRLB.reg; -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN0; - tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN1; - tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN2; - tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTIEN3; - tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_OTMX_Msk; - tmp |= TCC_WEXCTRL_OTMX(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTLS_Msk; - tmp |= TCC_WEXCTRL_DTLS(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= ~TCC_WEXCTRL_DTHS_Msk; - tmp |= TCC_WEXCTRL_DTHS(data); - ((Tcc *)hw)->WEXCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; - return tmp; -} - -static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WEXCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WEXCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->WEXCTRL.reg; -} - -static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE0; - tmp |= value << TCC_DRVCTRL_NRE0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE1; - tmp |= value << TCC_DRVCTRL_NRE1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE2; - tmp |= value << TCC_DRVCTRL_NRE2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE3; - tmp |= value << TCC_DRVCTRL_NRE3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE4; - tmp |= value << TCC_DRVCTRL_NRE4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE5; - tmp |= value << TCC_DRVCTRL_NRE5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE6; - tmp |= value << TCC_DRVCTRL_NRE6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRE7; - tmp |= value << TCC_DRVCTRL_NRE7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV0; - tmp |= value << TCC_DRVCTRL_NRV0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV1; - tmp |= value << TCC_DRVCTRL_NRV1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV2; - tmp |= value << TCC_DRVCTRL_NRV2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV3; - tmp |= value << TCC_DRVCTRL_NRV3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV4; - tmp |= value << TCC_DRVCTRL_NRV4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV5; - tmp |= value << TCC_DRVCTRL_NRV5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV6; - tmp |= value << TCC_DRVCTRL_NRV6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_NRV7; - tmp |= value << TCC_DRVCTRL_NRV7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN0; - tmp |= value << TCC_DRVCTRL_INVEN0_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN1; - tmp |= value << TCC_DRVCTRL_INVEN1_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN2; - tmp |= value << TCC_DRVCTRL_INVEN2_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN3; - tmp |= value << TCC_DRVCTRL_INVEN3_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN4; - tmp |= value << TCC_DRVCTRL_INVEN4_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN5; - tmp |= value << TCC_DRVCTRL_INVEN5_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN6; - tmp |= value << TCC_DRVCTRL_INVEN6_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_INVEN7; - tmp |= value << TCC_DRVCTRL_INVEN7_Pos; - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; - tmp |= TCC_DRVCTRL_FILTERVAL0(data); - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; - return tmp; -} - -static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; - tmp |= TCC_DRVCTRL_FILTERVAL1(data); - ((Tcc *)hw)->DRVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; - return tmp; -} - -static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->DRVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DRVCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->DRVCTRL.reg; -} - -static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= ~TCC_DBGCTRL_DBGRUN; - tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; - ((Tcc *)hw)->DBGCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= ~TCC_DBGCTRL_FDDBD; - tmp |= value << TCC_DBGCTRL_FDDBD_Pos; - ((Tcc *)hw)->DBGCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Tcc *)hw)->DBGCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->DBGCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->DBGCTRL.reg; -} - -static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_OVFEO; - tmp |= value << TCC_EVCTRL_OVFEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TRGEO; - tmp |= value << TCC_EVCTRL_TRGEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_CNTEO; - tmp |= value << TCC_EVCTRL_CNTEO_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCINV0; - tmp |= value << TCC_EVCTRL_TCINV0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCINV1; - tmp |= value << TCC_EVCTRL_TCINV1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCEI0; - tmp |= value << TCC_EVCTRL_TCEI0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_TCEI1; - tmp |= value << TCC_EVCTRL_TCEI1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI0; - tmp |= value << TCC_EVCTRL_MCEI0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI1; - tmp |= value << TCC_EVCTRL_MCEI1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI2; - tmp |= value << TCC_EVCTRL_MCEI2_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI3; - tmp |= value << TCC_EVCTRL_MCEI3_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI4) >> TCC_EVCTRL_MCEI4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI4; - tmp |= value << TCC_EVCTRL_MCEI4_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEI5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEI5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEI5) >> TCC_EVCTRL_MCEI5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEI5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEI5; - tmp |= value << TCC_EVCTRL_MCEI5_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEI5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEI5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO0; - tmp |= value << TCC_EVCTRL_MCEO0_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO1; - tmp |= value << TCC_EVCTRL_MCEO1_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO2; - tmp |= value << TCC_EVCTRL_MCEO2_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO3; - tmp |= value << TCC_EVCTRL_MCEO3_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO4) >> TCC_EVCTRL_MCEO4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO4; - tmp |= value << TCC_EVCTRL_MCEO4_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_MCEO5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_EVCTRL_MCEO5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_MCEO5) >> TCC_EVCTRL_MCEO5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_EVCTRL_MCEO5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_MCEO5; - tmp |= value << TCC_EVCTRL_MCEO5_Pos; - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_MCEO5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_MCEO5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_EVACT0_Msk; - tmp |= TCC_EVCTRL_EVACT0(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_EVACT1_Msk; - tmp |= TCC_EVCTRL_EVACT1(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= ~TCC_EVCTRL_CNTSEL_Msk; - tmp |= TCC_EVCTRL_CNTSEL(data); - ((Tcc *)hw)->EVCTRL.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; - return tmp; -} - -static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->EVCTRL.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) -{ - return ((Tcc *)hw)->EVCTRL.reg; -} - -static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE0; - tmp |= value << TCC_PATT_PGE0_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE1; - tmp |= value << TCC_PATT_PGE1_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE2; - tmp |= value << TCC_PATT_PGE2_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE3; - tmp |= value << TCC_PATT_PGE3_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE4; - tmp |= value << TCC_PATT_PGE4_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE5; - tmp |= value << TCC_PATT_PGE5_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE6; - tmp |= value << TCC_PATT_PGE6_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGE7; - tmp |= value << TCC_PATT_PGE7_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV0; - tmp |= value << TCC_PATT_PGV0_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV1; - tmp |= value << TCC_PATT_PGV1_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV2; - tmp |= value << TCC_PATT_PGV2_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV3; - tmp |= value << TCC_PATT_PGV3_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV4; - tmp |= value << TCC_PATT_PGV4_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV5; - tmp |= value << TCC_PATT_PGV5_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV6; - tmp |= value << TCC_PATT_PGV6_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= ~TCC_PATT_PGV7; - tmp |= value << TCC_PATT_PGV7_Pos; - ((Tcc *)hw)->PATT.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATT.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATT.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) -{ - return ((Tcc *)hw)->PATT.reg; -} - -static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CIPEREN; - tmp |= value << TCC_WAVE_CIPEREN_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN0; - tmp |= value << TCC_WAVE_CICCEN0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN1; - tmp |= value << TCC_WAVE_CICCEN1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN2; - tmp |= value << TCC_WAVE_CICCEN2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_CICCEN3; - tmp |= value << TCC_WAVE_CICCEN3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL0; - tmp |= value << TCC_WAVE_POL0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL1; - tmp |= value << TCC_WAVE_POL1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL2; - tmp |= value << TCC_WAVE_POL2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL3; - tmp |= value << TCC_WAVE_POL3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL4_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL4) >> TCC_WAVE_POL4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL4_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL4; - tmp |= value << TCC_WAVE_POL4_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_POL5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_POL5_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_POL5) >> TCC_WAVE_POL5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_POL5_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_POL5; - tmp |= value << TCC_WAVE_POL5_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_POL5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_POL5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP0; - tmp |= value << TCC_WAVE_SWAP0_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP1; - tmp |= value << TCC_WAVE_SWAP1_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP2; - tmp |= value << TCC_WAVE_SWAP2_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_SWAP3; - tmp |= value << TCC_WAVE_SWAP3_Pos; - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_WAVEGEN_Msk; - tmp |= TCC_WAVE_WAVEGEN(data); - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; - return tmp; -} - -static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) -{ - uint32_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= ~TCC_WAVE_RAMP_Msk; - tmp |= TCC_WAVE_RAMP(data); - ((Tcc *)hw)->WAVE.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); - ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; - return tmp; -} - -static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->WAVE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->WAVE.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) -{ - return ((Tcc *)hw)->WAVE.reg; -} - -static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB0; - tmp |= value << TCC_PATTBUF_PGEB0_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB1; - tmp |= value << TCC_PATTBUF_PGEB1_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB2; - tmp |= value << TCC_PATTBUF_PGEB2_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB3; - tmp |= value << TCC_PATTBUF_PGEB3_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB4; - tmp |= value << TCC_PATTBUF_PGEB4_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB5; - tmp |= value << TCC_PATTBUF_PGEB5_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB6; - tmp |= value << TCC_PATTBUF_PGEB6_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGEB7; - tmp |= value << TCC_PATTBUF_PGEB7_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB0; - tmp |= value << TCC_PATTBUF_PGVB0_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB1; - tmp |= value << TCC_PATTBUF_PGVB1_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB2; - tmp |= value << TCC_PATTBUF_PGVB2_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB3; - tmp |= value << TCC_PATTBUF_PGVB3_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB4; - tmp |= value << TCC_PATTBUF_PGVB4_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB5; - tmp |= value << TCC_PATTBUF_PGVB5_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB6; - tmp |= value << TCC_PATTBUF_PGVB6_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; - return (bool)tmp; -} - -static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) -{ - uint16_t tmp; - TCC_CRITICAL_SECTION_ENTER(); - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= ~TCC_PATTBUF_PGVB7; - tmp |= value << TCC_PATTBUF_PGVB7_Pos; - ((Tcc *)hw)->PATTBUF.reg = tmp; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg |= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - uint16_t tmp; - tmp = ((Tcc *)hw)->PATTBUF.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg = data; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg &= ~mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->PATTBUF.reg ^= mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) -{ - return ((Tcc *)hw)->PATTBUF.reg; -} - -static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC4_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC4) >> TCC_SYNCBUSY_CC4_Pos; -} - -static inline bool hri_tcc_get_SYNCBUSY_CC5_bit(const void *const hw) -{ - return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC5) >> TCC_SYNCBUSY_CC5_Pos; -} - -static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Tcc *)hw)->SYNCBUSY.reg; -} - -static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; -} - -static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; -} - -static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; -} - -static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; -} - -static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; -} - -static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; -} - -static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; -} - -static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; -} - -static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV4_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV4) >> TCC_STATUS_CCBUFV4_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CCBUFV5_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV5) >> TCC_STATUS_CCBUFV5_Pos; -} - -static inline void hri_tcc_clear_STATUS_CCBUFV5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP4_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP4) >> TCC_STATUS_CMP4_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP4_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP4; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_tcc_get_STATUS_CMP5_bit(const void *const hw) -{ - return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP5) >> TCC_STATUS_CMP5_Pos; -} - -static inline void hri_tcc_clear_STATUS_CMP5_bit(const void *const hw) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP5; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) -{ - uint32_t tmp; - tmp = ((Tcc *)hw)->STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) -{ - TCC_CRITICAL_SECTION_ENTER(); - ((Tcc *)hw)->STATUS.reg = mask; - TCC_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) -{ - return ((Tcc *)hw)->STATUS.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TCC_D51_H_INCLUDED */ -#endif /* _SAMD51_TCC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_trng_d51.h b/atmel-samd/asf4/samd51/hri/hri_trng_d51.h deleted file mode 100644 index 070e4c1ec..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_trng_d51.h +++ /dev/null @@ -1,389 +0,0 @@ -/** - * \file - * - * \brief SAM TRNG - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_TRNG_COMPONENT_ -#ifndef _HRI_TRNG_D51_H_INCLUDED_ -#define _HRI_TRNG_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) -#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define TRNG_CRITICAL_SECTION_ENTER() -#define TRNG_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_trng_data_reg_t; -typedef uint8_t hri_trng_ctrla_reg_t; -typedef uint8_t hri_trng_evctrl_reg_t; -typedef uint8_t hri_trng_intenset_reg_t; -typedef uint8_t hri_trng_intflag_reg_t; - -static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; -} - -static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; -} - -static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; - } else { - ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; - } -} - -static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; -} - -static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - ((Trng *)hw)->INTENSET.reg = mask; -} - -static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) -{ - return ((Trng *)hw)->INTENSET.reg; -} - -static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) -{ - ((Trng *)hw)->INTENSET.reg = data; - ((Trng *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) -{ - ((Trng *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; -} - -static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; -} - -static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) -{ - return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; -} - -static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) -{ - ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; -} - -static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) -{ - return ((Trng *)hw)->INTFLAG.reg; -} - -static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) -{ - ((Trng *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= ~TRNG_CTRLA_ENABLE; - tmp |= value << TRNG_CTRLA_ENABLE_Pos; - ((Trng *)hw)->CTRLA.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= ~TRNG_CTRLA_RUNSTDBY; - tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; - ((Trng *)hw)->CTRLA.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg |= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg = data; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg &= ~mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->CTRLA.reg ^= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) -{ - return ((Trng *)hw)->CTRLA.reg; -} - -static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; - return (bool)tmp; -} - -static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) -{ - uint8_t tmp; - TRNG_CRITICAL_SECTION_ENTER(); - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp &= ~TRNG_EVCTRL_DATARDYEO; - tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; - ((Trng *)hw)->EVCTRL.reg = tmp; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg |= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Trng *)hw)->EVCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg = data; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg &= ~mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) -{ - TRNG_CRITICAL_SECTION_ENTER(); - ((Trng *)hw)->EVCTRL.reg ^= mask; - TRNG_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) -{ - return ((Trng *)hw)->EVCTRL.reg; -} - -static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) -{ - return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; -} - -static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) -{ - return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; -} - -static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) -{ - uint32_t tmp; - tmp = ((Trng *)hw)->DATA.reg; - tmp &= mask; - return tmp; -} - -static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) -{ - return ((Trng *)hw)->DATA.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_TRNG_D51_H_INCLUDED */ -#endif /* _SAMD51_TRNG_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_usb_d51.h b/atmel-samd/asf4/samd51/hri/hri_usb_d51.h deleted file mode 100644 index 5a3047d22..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_usb_d51.h +++ /dev/null @@ -1,9851 +0,0 @@ -/** - * \file - * - * \brief SAM USB - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_USB_COMPONENT_ -#ifndef _HRI_USB_D51_H_INCLUDED_ -#define _HRI_USB_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_USB_CRITICAL_SECTIONS) -#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define USB_CRITICAL_SECTION_ENTER() -#define USB_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; -typedef uint16_t hri_usbdesc_bank_extreg_reg_t; -typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; -typedef uint16_t hri_usbdevice_ctrlb_reg_t; -typedef uint16_t hri_usbdevice_descriptor_extreg_reg_t; -typedef uint16_t hri_usbdevice_epintsmry_reg_t; -typedef uint16_t hri_usbdevice_fnum_reg_t; -typedef uint16_t hri_usbdevice_intenset_reg_t; -typedef uint16_t hri_usbdevice_intflag_reg_t; -typedef uint16_t hri_usbdevice_padcal_reg_t; -typedef uint16_t hri_usbhost_ctrlb_reg_t; -typedef uint16_t hri_usbhost_descriptor_ctrl_pipe_reg_t; -typedef uint16_t hri_usbhost_descriptor_extreg_reg_t; -typedef uint16_t hri_usbhost_descriptor_status_pipe_reg_t; -typedef uint16_t hri_usbhost_fnum_reg_t; -typedef uint16_t hri_usbhost_intenset_reg_t; -typedef uint16_t hri_usbhost_intflag_reg_t; -typedef uint16_t hri_usbhost_padcal_reg_t; -typedef uint16_t hri_usbhost_pintsmry_reg_t; -typedef uint32_t hri_usbdesc_bank_addr_reg_t; -typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; -typedef uint32_t hri_usbdevice_descadd_reg_t; -typedef uint32_t hri_usbdevice_descriptor_addr_reg_t; -typedef uint32_t hri_usbdevice_descriptor_pcksize_reg_t; -typedef uint32_t hri_usbhost_descadd_reg_t; -typedef uint32_t hri_usbhost_descriptor_addr_reg_t; -typedef uint32_t hri_usbhost_descriptor_pcksize_reg_t; -typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; -typedef uint8_t hri_usbdevice_ctrla_reg_t; -typedef uint8_t hri_usbdevice_dadd_reg_t; -typedef uint8_t hri_usbdevice_descriptor_status_bk_reg_t; -typedef uint8_t hri_usbdevice_epcfg_reg_t; -typedef uint8_t hri_usbdevice_epintenset_reg_t; -typedef uint8_t hri_usbdevice_epintflag_reg_t; -typedef uint8_t hri_usbdevice_epstatus_reg_t; -typedef uint8_t hri_usbdevice_fsmstatus_reg_t; -typedef uint8_t hri_usbdevice_qosctrl_reg_t; -typedef uint8_t hri_usbdevice_status_reg_t; -typedef uint8_t hri_usbdevice_syncbusy_reg_t; -typedef uint8_t hri_usbendpoint_epcfg_reg_t; -typedef uint8_t hri_usbendpoint_epintenset_reg_t; -typedef uint8_t hri_usbendpoint_epintflag_reg_t; -typedef uint8_t hri_usbendpoint_epstatus_reg_t; -typedef uint8_t hri_usbhost_binterval_reg_t; -typedef uint8_t hri_usbhost_ctrla_reg_t; -typedef uint8_t hri_usbhost_descriptor_status_bk_reg_t; -typedef uint8_t hri_usbhost_flenhigh_reg_t; -typedef uint8_t hri_usbhost_fsmstatus_reg_t; -typedef uint8_t hri_usbhost_hsofc_reg_t; -typedef uint8_t hri_usbhost_pcfg_reg_t; -typedef uint8_t hri_usbhost_pintenset_reg_t; -typedef uint8_t hri_usbhost_pintflag_reg_t; -typedef uint8_t hri_usbhost_pstatus_reg_t; -typedef uint8_t hri_usbhost_qosctrl_reg_t; -typedef uint8_t hri_usbhost_status_reg_t; -typedef uint8_t hri_usbhost_syncbusy_reg_t; -typedef uint8_t hri_usbpipe_binterval_reg_t; -typedef uint8_t hri_usbpipe_pcfg_reg_t; -typedef uint8_t hri_usbpipe_pintenset_reg_t; -typedef uint8_t hri_usbpipe_pintflag_reg_t; -typedef uint8_t hri_usbpipe_pstatus_reg_t; - -static inline void hri_usbdevice_wait_for_sync(const void *const hw, hri_usbdevice_syncbusy_reg_t reg) -{ - while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_usbdevice_is_syncing(const void *const hw, hri_usbdevice_syncbusy_reg_t reg) -{ - return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; -} - -static inline void hri_usbhost_wait_for_sync(const void *const hw, hri_usbhost_syncbusy_reg_t reg) -{ - while (((Usb *)hw)->HOST.SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_usbhost_is_syncing(const void *const hw, hri_usbhost_syncbusy_reg_t reg) -{ - return ((Usb *)hw)->HOST.SYNCBUSY.reg & reg; -} - -static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) - >> USB_HOST_PSTATUS_DTGL_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) - >> USB_HOST_PSTATUS_CURBK_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) - >> USB_HOST_PSTATUS_PFREEZE_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) - >> USB_HOST_PSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) - >> USB_HOST_PSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; - } -} - -static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; -} - -static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; -} - -static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t data) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; -} - -static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pstatus_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; -} - -static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) - >> USB_HOST_PINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) - >> USB_HOST_PINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) - >> USB_HOST_PINTENSET_TRFAIL_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; -} - -static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) - >> USB_HOST_PINTENSET_PERR_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; - } -} - -static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; -} - -static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) - >> USB_HOST_PINTENSET_TXSTP_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; - } -} - -static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; -} - -static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) - >> USB_HOST_PINTENSET_STALL_Pos; -} - -static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; - } else { - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; - } -} - -static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; -} - -static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; -} - -static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; -} - -static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t data) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; -} - -static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintenset_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; -} - -static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pintflag_reg_t mask) -{ - ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; -} - -static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; - return (bool)tmp; -} - -static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_BK; - tmp |= value << USB_HOST_PCFG_BK_Pos; - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; - tmp |= USB_HOST_PCFG_PTOKEN(data); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTYPE_Msk; - tmp |= USB_HOST_PCFG_PTYPE(data); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; -} - -static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; - tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbpipe_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; -} - -static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) - >> USB_HOST_PSTATUS_DTGL_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; - } -} - -static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; -} - -static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) - >> USB_HOST_PSTATUS_CURBK_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; - } -} - -static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; -} - -static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) - >> USB_HOST_PSTATUS_PFREEZE_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; - } -} - -static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; -} - -static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) - >> USB_HOST_PSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; - } -} - -static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; -} - -static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) - >> USB_HOST_PSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; - } -} - -static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; -} - -static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; -} - -static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; -} - -static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t data) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pstatus_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; -} - -static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) - >> USB_HOST_PINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; -} - -static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) - >> USB_HOST_PINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; -} - -static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) - >> USB_HOST_PINTENSET_TRFAIL_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; - } -} - -static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; -} - -static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; -} - -static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) - >> USB_HOST_PINTENSET_PERR_Pos; -} - -static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; - } -} - -static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; -} - -static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) - >> USB_HOST_PINTENSET_TXSTP_Pos; -} - -static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; - } -} - -static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; -} - -static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; -} - -static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) - >> USB_HOST_PINTENSET_STALL_Pos; -} - -static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; - } else { - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; - } -} - -static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; -} - -static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; -} - -static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; -} - -static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t data) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintenset_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) - >> USB_HOST_PINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; -} - -static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) - >> USB_HOST_PINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; -} - -static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) - >> USB_HOST_PINTFLAG_TRFAIL_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; -} - -static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) - >> USB_HOST_PINTFLAG_PERR_Pos; -} - -static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; -} - -static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) - >> USB_HOST_PINTFLAG_TXSTP_Pos; -} - -static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; -} - -static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) - >> USB_HOST_PINTFLAG_STALL_Pos; -} - -static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; -} - -static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; -} - -static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pintflag_reg_t mask) -{ - ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; -} - -static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_BK; - tmp |= value << USB_HOST_PCFG_BK_Pos; - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; - tmp |= USB_HOST_PCFG_PTOKEN(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= ~USB_HOST_PCFG_PTYPE_Msk; - tmp |= USB_HOST_PCFG_PTYPE(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_pcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; -} - -static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; - tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; - return tmp; -} - -static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_binterval_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; -} - -static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; -} - -static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; -} - -static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; - } -} - -static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; -} - -static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; -} - -static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; -} - -static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; - } -} - -static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; -} - -static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; -} - -static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; -} - -static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; - } -} - -static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; -} - -static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; -} - -static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; -} - -static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; - } -} - -static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; -} - -static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; -} - -static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; -} - -static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; - } -} - -static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; -} - -static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; -} - -static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; -} - -static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; - } -} - -static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; -} - -static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; -} - -static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; -} - -static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; - } -} - -static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; -} - -static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; -} - -static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; -} - -static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; - } else { - ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; - } -} - -static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; -} - -static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) -{ - ((Usb *)hw)->HOST.INTENSET.reg = mask; -} - -static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, - hri_usbhost_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.INTENSET.reg; -} - -static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) -{ - ((Usb *)hw)->HOST.INTENSET.reg = data; - ((Usb *)hw)->HOST.INTENCLR.reg = ~data; -} - -static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) -{ - ((Usb *)hw)->HOST.INTENCLR.reg = mask; -} - -static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; -} - -static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; -} - -static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; -} - -static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; -} - -static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; -} - -static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; -} - -static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; -} - -static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; -} - -static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; -} - -static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; -} - -static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; -} - -static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; -} - -static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; -} - -static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; -} - -static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; -} - -static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; -} - -static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; -} - -static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; -} - -static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; -} - -static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; -} - -static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, - hri_usbhost_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.INTFLAG.reg; -} - -static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) -{ - ((Usb *)hw)->HOST.INTFLAG.reg = mask; -} - -static inline void hri_usbhost_set_CTRLA_SWRST_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_set_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_ENABLE; - tmp |= value << USB_CTRLA_ENABLE_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_RUNSTDBY; - tmp |= value << USB_CTRLA_RUNSTDBY_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLA_MODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLA_MODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= ~USB_CTRLA_MODE; - tmp |= value << USB_CTRLA_MODE_Pos; - ((Usb *)hw)->HOST.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbhost_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrla_reg_t hri_usbhost_get_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLA_reg(const void *const hw, hri_usbhost_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLA.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrla_reg_t hri_usbhost_read_CTRLA_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.CTRLA.reg; -} - -static inline void hri_usbhost_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_CQOS_bf(const void *const hw, - hri_usbhost_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usbhost_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_CQOS_Msk; - tmp |= USB_QOSCTRL_CQOS(data); - ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_CQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usbhost_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_DQOS_bf(const void *const hw, - hri_usbhost_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usbhost_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_DQOS_Msk; - tmp |= USB_QOSCTRL_DQOS(data); - ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_DQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usbhost_set_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_get_QOSCTRL_reg(const void *const hw, - hri_usbhost_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_QOSCTRL_reg(const void *const hw, hri_usbhost_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_qosctrl_reg_t hri_usbhost_read_QOSCTRL_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.QOSCTRL.reg; -} - -static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_RESUME; - tmp |= value << USB_HOST_CTRLB_RESUME_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_AUTORESUME; - tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_TSTJ; - tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_TSTK; - tmp |= value << USB_HOST_CTRLB_TSTK_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_SOFE; - tmp |= value << USB_HOST_CTRLB_SOFE_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_BUSRESET; - tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_VBUSOK; - tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_L1RESUME; - tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, - hri_usbhost_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; - tmp |= USB_HOST_CTRLB_SPDCONF(data); - ((Usb *)hw)->HOST.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.CTRLB.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.CTRLB.reg; -} - -static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; - return (bool)tmp; -} - -static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= ~USB_HOST_HSOFC_FLENCE; - tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; - ((Usb *)hw)->HOST.HSOFC.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; - return tmp; -} - -static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= ~USB_HOST_HSOFC_FLENC_Msk; - tmp |= USB_HOST_HSOFC_FLENC(data); - ((Usb *)hw)->HOST.HSOFC.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; - return tmp; -} - -static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.HSOFC.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.HSOFC.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.HSOFC.reg; -} - -static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= ~USB_HOST_FNUM_MFNUM_Msk; - tmp |= USB_HOST_FNUM_MFNUM(data); - ((Usb *)hw)->HOST.FNUM.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= ~USB_HOST_FNUM_FNUM_Msk; - tmp |= USB_HOST_FNUM_FNUM(data); - ((Usb *)hw)->HOST.FNUM.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; - return tmp; -} - -static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.FNUM.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.FNUM.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FNUM.reg; -} - -static inline void hri_usbhost_set_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descadd_reg_t hri_usbhost_get_DESCADD_DESCADD_bf(const void *const hw, - hri_usbhost_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usbhost_write_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp &= ~USB_DESCADD_DESCADD_Msk; - tmp |= USB_DESCADD_DESCADD(data); - ((Usb *)hw)->HOST.DESCADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descadd_reg_t hri_usbhost_read_DESCADD_DESCADD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usbhost_set_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descadd_reg_t hri_usbhost_get_DESCADD_reg(const void *const hw, - hri_usbhost_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->HOST.DESCADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_DESCADD_reg(const void *const hw, hri_usbhost_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.DESCADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descadd_reg_t hri_usbhost_read_DESCADD_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.DESCADD.reg; -} - -static inline void hri_usbhost_set_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRANSP_bf(const void *const hw, - hri_usbhost_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSP_Msk; - tmp |= USB_PADCAL_TRANSP(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRANSP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRANSN_bf(const void *const hw, - hri_usbhost_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSN_Msk; - tmp |= USB_PADCAL_TRANSN(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRANSN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_TRIM_bf(const void *const hw, - hri_usbhost_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usbhost_write_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= ~USB_PADCAL_TRIM_Msk; - tmp |= USB_PADCAL_TRIM(data); - ((Usb *)hw)->HOST.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_TRIM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usbhost_set_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_get_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PADCAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_write_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_clear_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhost_toggle_PADCAL_reg(const void *const hw, hri_usbhost_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.PADCAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_padcal_reg_t hri_usbhost_read_PADCAL_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.PADCAL.reg; -} - -static inline bool hri_usbhost_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_usbhost_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_usbhost_syncbusy_reg_t hri_usbhost_get_SYNCBUSY_reg(const void *const hw, - hri_usbhost_syncbusy_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_syncbusy_reg_t hri_usbhost_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.SYNCBUSY.reg; -} - -static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, - hri_usbhost_fsmstatus_reg_t mask) -{ - return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_get_FSMSTATUS_reg(const void *const hw, - hri_usbhost_fsmstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_fsmstatus_reg_t hri_usbhost_read_FSMSTATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FSMSTATUS.reg; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, - hri_usbhost_flenhigh_reg_t mask) -{ - return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, - hri_usbhost_flenhigh_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.FLENHIGH.reg; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; -} - -static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) -{ - return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; -} - -static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, - hri_usbhost_pintsmry_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.PINTSMRY.reg; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, - hri_usbhost_status_reg_t mask) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; -} - -static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, - hri_usbhost_status_reg_t mask) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; -} - -static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; -} - -static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->HOST.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->HOST.STATUS.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->HOST.STATUS.reg; -} - -static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; - tmp |= USB_DEVICE_ADDR_ADDR(data); - ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->ADDR.reg; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_SIZE(data); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; - tmp |= USB_DEVICE_EXTREG_SUBPID(data); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; - tmp |= USB_DEVICE_EXTREG_VARIABLE(data); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->EXTREG.reg; -} - -static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) -{ - return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) - >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t -hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, - hri_usbdesc_bank_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) -{ - return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; -} - -static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_addr_reg_t -hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; - tmp |= USB_DEVICE_ADDR_ADDR(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_addr_reg_t -hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void -hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void -hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void -hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg - ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; - tmp |= USB_DEVICE_PCKSIZE_SIZE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t -hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; - tmp |= USB_DEVICE_EXTREG_SUBPID(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t -hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; - tmp |= USB_DEVICE_EXTREG_VARIABLE(data); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t -hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t -hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; -} - -static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) - >> USB_DEVICE_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) - >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_status_bk_reg_t -hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_descriptor_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descriptor_status_bk_reg_t -hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; -} - -static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; -} - -static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; -} - -static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; - } -} - -static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; -} - -static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; -} - -static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; -} - -static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; - } -} - -static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; -} - -static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; -} - -static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; -} - -static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; - } -} - -static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; -} - -static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; -} - -static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; -} - -static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; - } -} - -static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; -} - -static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; -} - -static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; -} - -static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; - } -} - -static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; -} - -static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; -} - -static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; -} - -static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; - } -} - -static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; -} - -static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; -} - -static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; -} - -static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; - } -} - -static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; -} - -static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; -} - -static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; -} - -static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; - } -} - -static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; -} - -static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; -} - -static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; -} - -static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; - } -} - -static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; -} - -static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; -} - -static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; - } else { - ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; - } -} - -static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; -} - -static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = mask; -} - -static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, - hri_usbdevice_intenset_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.INTENSET.reg; -} - -static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) -{ - ((Usb *)hw)->DEVICE.INTENSET.reg = data; - ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; -} - -static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; -} - -static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; -} - -static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; -} - -static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; -} - -static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; -} - -static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; -} - -static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; -} - -static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; -} - -static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; -} - -static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; -} - -static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; -} - -static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; -} - -static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; -} - -static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; -} - -static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; -} - -static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; -} - -static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; -} - -static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; -} - -static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; -} - -static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; -} - -static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, - hri_usbdevice_intflag_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.INTFLAG.reg; -} - -static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) -{ - ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; -} - -static inline void hri_usbdevice_set_CTRLA_SWRST_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_SWRST; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLA_SWRST_bit(const void *const hw) -{ - uint8_t tmp; - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_set_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= ~USB_CTRLA_ENABLE; - tmp |= value << USB_CTRLA_ENABLE_Pos; - ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_ENABLE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= ~USB_CTRLA_RUNSTDBY; - tmp |= value << USB_CTRLA_RUNSTDBY_Pos; - ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg |= USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLA_MODE_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLA_MODE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= ~USB_CTRLA_MODE; - tmp |= value << USB_CTRLA_MODE_Pos; - ((Usb *)hw)->DEVICE.CTRLA.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLA_MODE_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - hri_usbdevice_wait_for_sync(hw, USB_SYNCBUSY_MASK); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= USB_CTRLA_MODE; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrla_reg_t hri_usbdevice_get_CTRLA_reg(const void *const hw, - hri_usbdevice_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLA_reg(const void *const hw, hri_usbdevice_ctrla_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLA.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrla_reg_t hri_usbdevice_read_CTRLA_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.CTRLA.reg; -} - -static inline void hri_usbdevice_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_CQOS_bf(const void *const hw, - hri_usbdevice_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_CQOS_Msk; - tmp |= USB_QOSCTRL_CQOS(data); - ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_CQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_DQOS_bf(const void *const hw, - hri_usbdevice_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp &= ~USB_QOSCTRL_DQOS_Msk; - tmp |= USB_QOSCTRL_DQOS(data); - ((Usb *)hw)->DEVICE.QOSCTRL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_DQOS_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_get_QOSCTRL_reg(const void *const hw, - hri_usbdevice_qosctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.QOSCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_QOSCTRL_reg(const void *const hw, hri_usbdevice_qosctrl_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.QOSCTRL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_qosctrl_reg_t hri_usbdevice_read_QOSCTRL_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.QOSCTRL.reg; -} - -static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_DETACH; - tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_UPRSM; - tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_NREPLY; - tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTJ; - tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTK; - tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; - tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_OPMODE2; - tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_GNAK; - tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; - tmp |= USB_DEVICE_CTRLB_SPDCONF(data); - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; - tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); - ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, - hri_usbdevice_ctrlb_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.CTRLB.reg; -} - -static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= ~USB_DEVICE_DADD_ADDEN; - tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; - ((Usb *)hw)->DEVICE.DADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, - hri_usbdevice_dadd_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= ~USB_DEVICE_DADD_DADD_Msk; - tmp |= USB_DEVICE_DADD_DADD(data); - ((Usb *)hw)->DEVICE.DADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.DADD.reg; -} - -static inline void hri_usbdevice_set_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg |= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descadd_reg_t hri_usbdevice_get_DESCADD_DESCADD_bf(const void *const hw, - hri_usbdevice_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp &= ~USB_DESCADD_DESCADD_Msk; - tmp |= USB_DESCADD_DESCADD(data); - ((Usb *)hw)->DEVICE.DESCADD.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descadd_reg_t hri_usbdevice_read_DESCADD_DESCADD_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descadd_reg_t hri_usbdevice_get_DESCADD_reg(const void *const hw, - hri_usbdevice_descadd_reg_t mask) -{ - uint32_t tmp; - tmp = ((Usb *)hw)->DEVICE.DESCADD.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_DESCADD_reg(const void *const hw, hri_usbdevice_descadd_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DESCADD.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_descadd_reg_t hri_usbdevice_read_DESCADD_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.DESCADD.reg; -} - -static inline void hri_usbdevice_set_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRANSP_bf(const void *const hw, - hri_usbdevice_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSP_Msk; - tmp |= USB_PADCAL_TRANSP(data); - ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRANSP_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRANSN_bf(const void *const hw, - hri_usbdevice_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= ~USB_PADCAL_TRANSN_Msk; - tmp |= USB_PADCAL_TRANSN(data); - ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRANSN_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_TRIM_bf(const void *const hw, - hri_usbdevice_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= ~USB_PADCAL_TRIM_Msk; - tmp |= USB_PADCAL_TRIM(data); - ((Usb *)hw)->DEVICE.PADCAL.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= USB_PADCAL_TRIM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_TRIM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_get_PADCAL_reg(const void *const hw, - hri_usbdevice_padcal_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.PADCAL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_PADCAL_reg(const void *const hw, hri_usbdevice_padcal_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.PADCAL.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_padcal_reg_t hri_usbdevice_read_PADCAL_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.PADCAL.reg; -} - -static inline bool hri_usbdevice_get_SYNCBUSY_SWRST_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; -} - -static inline bool hri_usbdevice_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; -} - -static inline hri_usbdevice_syncbusy_reg_t hri_usbdevice_get_SYNCBUSY_reg(const void *const hw, - hri_usbdevice_syncbusy_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_syncbusy_reg_t hri_usbdevice_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.SYNCBUSY.reg; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, - hri_usbdevice_status_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.STATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.STATUS.reg; -} - -static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, - hri_usbdevice_fsmstatus_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; -} - -static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_get_FSMSTATUS_reg(const void *const hw, - hri_usbdevice_fsmstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.FSMSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_fsmstatus_reg_t hri_usbdevice_read_FSMSTATUS_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.FSMSTATUS.reg; -} - -static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, - hri_usbdevice_fnum_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, - hri_usbdevice_fnum_reg_t mask) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.FNUM.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.FNUM.reg; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; -} - -static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) -{ - return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; -} - -static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, - hri_usbdevice_epintsmry_reg_t mask) -{ - uint16_t tmp; - tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) -{ - return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; -} - -static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) - >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) - >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) - >> USB_DEVICE_EPSTATUS_CURBK_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) - >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) - >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) - >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) - >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } -} - -static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; -} - -static inline hri_usbendpoint_epstatus_reg_t -hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; -} - -static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t data) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; -} - -static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epstatus_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) - >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) - >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) - >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) - >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) - >> USB_DEVICE_EPINTENSET_RXSTP_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) - >> USB_DEVICE_EPINTENSET_STALL0_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) - >> USB_DEVICE_EPINTENSET_STALL1_Pos; -} - -static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; - } else { - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; - } -} - -static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; -} - -static inline hri_usbendpoint_epintenset_reg_t -hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; -} - -static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t data) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; -} - -static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintenset_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline hri_usbendpoint_epintflag_reg_t -hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; -} - -static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epintflag_reg_t mask) -{ - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; -} - -static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; - return (bool)tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_NYETDIS; - tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t -hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t -hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbendpoint_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; -} - -static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) - >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; -} - -static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) - >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; -} - -static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) - >> USB_DEVICE_EPSTATUS_CURBK_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; -} - -static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) - >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; -} - -static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) - >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; -} - -static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) - >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; -} - -static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) - >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; -} - -static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; - } -} - -static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; -} - -static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; -} - -static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; -} - -static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t data) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epstatus_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; -} - -static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) - >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; -} - -static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) - >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; -} - -static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) - >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; -} - -static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) - >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; -} - -static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) - >> USB_DEVICE_EPINTENSET_RXSTP_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; -} - -static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) - >> USB_DEVICE_EPINTENSET_STALL0_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; -} - -static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) - >> USB_DEVICE_EPINTENSET_STALL1_Pos; -} - -static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - if (value == 0x0) { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; - } else { - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; - } -} - -static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; -} - -static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; -} - -static inline hri_usbdevice_epintenset_reg_t -hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; -} - -static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t data) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; -} - -static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintenset_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) - >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; -} - -static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) - >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; -} - -static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) - >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; -} - -static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) - >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; -} - -static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) - >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; -} - -static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) - >> USB_DEVICE_EPINTFLAG_STALL0_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; -} - -static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) - >> USB_DEVICE_EPINTFLAG_STALL1_Pos; -} - -static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; -} - -static inline hri_usbdevice_epintflag_reg_t -hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; -} - -static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epintflag_reg_t mask) -{ - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; -} - -static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; - return (bool)tmp; -} - -static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_NYETDIS; - tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t -hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t -hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - uint8_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; - tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, - uint8_t submodule_index) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; - return tmp; -} - -static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - uint8_t tmp; - tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, - hri_usbdevice_epcfg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) -{ - return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; -} - -static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp &= ~USB_HOST_ADDR_ADDR_Msk; - tmp |= USB_HOST_ADDR_ADDR(data); - ((UsbHostDescBank *)hw)->ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, - hri_usbdesc_bank_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->ADDR.reg; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t -hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_SIZE(data); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, - hri_usbdesc_bank_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->PCKSIZE.reg; -} - -static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; - tmp |= USB_HOST_EXTREG_SUBPID(data); - ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t -hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; - tmp |= USB_HOST_EXTREG_VARIABLE(data); - ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, - hri_usbdesc_bank_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->EXTREG.reg; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; - tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; - tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; - tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, - hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t -hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; -} - -static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t -hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->STATUS_BK.reg; -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) - >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) - >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t -hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, - hri_usbdesc_bank_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) -{ - return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline hri_usbdesc_bank_status_pipe_reg_t -hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, - hri_usbdesc_bank_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) -{ - return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; -} - -static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_addr_reg_t -hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp &= ~USB_HOST_ADDR_ADDR_Msk; - tmp |= USB_HOST_ADDR_ADDR(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_addr_reg_t -hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_addr_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - return (bool)tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, - bool value) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; - tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, - uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t data) -{ - uint32_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; - tmp |= USB_HOST_PCKSIZE_SIZE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, - uint8_t submodule_index) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t -hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - uint32_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_pcksize_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; - tmp |= USB_HOST_EXTREG_SUBPID(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, - uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; - tmp |= USB_HOST_EXTREG_VARIABLE(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, - uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t -hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_extreg_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; - tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; - tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t data) -{ - uint16_t tmp; - USB_CRITICAL_SECTION_ENTER(); - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; - tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; - return tmp; -} - -static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t -hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t data) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_ctrl_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; -} - -static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) - >> USB_HOST_STATUS_BK_CRCERR_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) - >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_status_bk_reg_t -hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_bk_reg_t mask) -{ - uint8_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_bk_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, - uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) - >> USB_HOST_STATUS_PIPE_DTGLER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) - >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) - >> USB_HOST_STATUS_PIPE_PIDER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) - >> USB_HOST_STATUS_PIPE_TOUTER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) - >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_status_pipe_reg_t -hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_pipe_reg_t mask) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_status_pipe_reg_t -hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) -{ - return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) - >> USB_HOST_STATUS_PIPE_ERCNT_Pos; -} - -static inline hri_usbhost_descriptor_status_pipe_reg_t -hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_pipe_reg_t mask) -{ - uint16_t tmp; - tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, - hri_usbhost_descriptor_status_pipe_reg_t mask) -{ - USB_CRITICAL_SECTION_ENTER(); - ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; - USB_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_usbhost_descriptor_status_pipe_reg_t -hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) -{ - return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_USB_D51_H_INCLUDED */ -#endif /* _SAMD51_USB_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/hri/hri_wdt_d51.h b/atmel-samd/asf4/samd51/hri/hri_wdt_d51.h deleted file mode 100644 index f711c59c3..000000000 --- a/atmel-samd/asf4/samd51/hri/hri_wdt_d51.h +++ /dev/null @@ -1,619 +0,0 @@ -/** - * \file - * - * \brief SAM WDT - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - */ - -#ifdef _SAMD51_WDT_COMPONENT_ -#ifndef _HRI_WDT_D51_H_INCLUDED_ -#define _HRI_WDT_D51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#if defined(ENABLE_WDT_CRITICAL_SECTIONS) -#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() -#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() -#else -#define WDT_CRITICAL_SECTION_ENTER() -#define WDT_CRITICAL_SECTION_LEAVE() -#endif - -typedef uint32_t hri_wdt_syncbusy_reg_t; -typedef uint8_t hri_wdt_clear_reg_t; -typedef uint8_t hri_wdt_config_reg_t; -typedef uint8_t hri_wdt_ctrla_reg_t; -typedef uint8_t hri_wdt_ewctrl_reg_t; -typedef uint8_t hri_wdt_intenset_reg_t; -typedef uint8_t hri_wdt_intflag_reg_t; - -static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) -{ - while (((Wdt *)hw)->SYNCBUSY.reg & reg) { - }; -} - -static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) -{ - return ((Wdt *)hw)->SYNCBUSY.reg & reg; -} - -static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; -} - -static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; -} - -static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) -{ - if (value == 0x0) { - ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; - } else { - ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; - } -} - -static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; -} - -static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - ((Wdt *)hw)->INTENSET.reg = mask; -} - -static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->INTENSET.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) -{ - return ((Wdt *)hw)->INTENSET.reg; -} - -static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) -{ - ((Wdt *)hw)->INTENSET.reg = data; - ((Wdt *)hw)->INTENCLR.reg = ~data; -} - -static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) -{ - ((Wdt *)hw)->INTENCLR.reg = mask; -} - -static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; -} - -static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; -} - -static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) -{ - return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; -} - -static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) -{ - ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; -} - -static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->INTFLAG.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) -{ - return ((Wdt *)hw)->INTFLAG.reg; -} - -static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) -{ - ((Wdt *)hw)->INTFLAG.reg = mask; -} - -static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CLEAR.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_ENABLE; - tmp |= value << WDT_CTRLA_ENABLE_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_WEN; - tmp |= value << WDT_CTRLA_WEN_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) -{ - uint8_t tmp; - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; - return (bool)tmp; -} - -static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= ~WDT_CTRLA_ALWAYSON; - tmp |= value << WDT_CTRLA_ALWAYSON_Pos; - ((Wdt *)hw)->CTRLA.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) -{ - WDT_CRITICAL_SECTION_ENTER(); - hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); - ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CTRLA.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CTRLA.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) -{ - return ((Wdt *)hw)->CTRLA.reg; -} - -static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= ~WDT_CONFIG_PER_Msk; - tmp |= WDT_CONFIG_PER(data); - ((Wdt *)hw)->CONFIG.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; - return tmp; -} - -static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= ~WDT_CONFIG_WINDOW_Msk; - tmp |= WDT_CONFIG_WINDOW(data); - ((Wdt *)hw)->CONFIG.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; - return tmp; -} - -static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->CONFIG.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->CONFIG.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) -{ - return ((Wdt *)hw)->CONFIG.reg; -} - -static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; - return tmp; -} - -static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) -{ - uint8_t tmp; - WDT_CRITICAL_SECTION_ENTER(); - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; - tmp |= WDT_EWCTRL_EWOFFSET(data); - ((Wdt *)hw)->EWCTRL.reg = tmp; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; - return tmp; -} - -static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg |= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - uint8_t tmp; - tmp = ((Wdt *)hw)->EWCTRL.reg; - tmp &= mask; - return tmp; -} - -static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg = data; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg &= ~mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) -{ - WDT_CRITICAL_SECTION_ENTER(); - ((Wdt *)hw)->EWCTRL.reg ^= mask; - WDT_CRITICAL_SECTION_LEAVE(); -} - -static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) -{ - return ((Wdt *)hw)->EWCTRL.reg; -} - -static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; -} - -static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) -{ - return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; -} - -static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) -{ - uint32_t tmp; - tmp = ((Wdt *)hw)->SYNCBUSY.reg; - tmp &= mask; - return tmp; -} - -static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) -{ - return ((Wdt *)hw)->SYNCBUSY.reg; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _HRI_WDT_D51_H_INCLUDED */ -#endif /* _SAMD51_WDT_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component-version.h b/atmel-samd/asf4/samd51/include/component-version.h deleted file mode 100644 index 80801fc12..000000000 --- a/atmel-samd/asf4/samd51/include/component-version.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * \file - * - * \brief Component version header file - * - * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _COMPONENT_VERSION_H_INCLUDED -#define _COMPONENT_VERSION_H_INCLUDED - -#define COMPONENT_VERSION_MAJOR 1 -#define COMPONENT_VERSION_MINOR 0 - -// -// The COMPONENT_VERSION define is composed of the major and the minor version number. -// -// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. -// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION -// is at least 8 digits long. -// -#define COMPONENT_VERSION 00010000 - -// -// The build number does not refer to the component, but to the build number -// of the device pack that provides the component. -// -#define BUILD_NUMBER 70 - -// -// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. -// -#define COMPONENT_VERSION_STRING "1.0" - -// -// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. -// -// The COMPONENT_DATE_STRING is written out using the following strftime pattern. -// -// "%Y-%m-%d %H:%M:%S" -// -// -#define COMPONENT_DATE_STRING "2017-08-09 09:59:41" - -#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ - diff --git a/atmel-samd/asf4/samd51/include/component/ac.h b/atmel-samd/asf4/samd51/include/component/ac.h deleted file mode 100644 index 24623d00a..000000000 --- a/atmel-samd/asf4/samd51/include/component/ac.h +++ /dev/null @@ -1,598 +0,0 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_AC_COMPONENT_ -#define _SAMD51_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_AC Analog Comparators */ -/*@{*/ - -#define AC_U2501 -#define REV_AC 0x100 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ - uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ -#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ -#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ -#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) -#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) -#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ -#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) -#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) -#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ -#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ - -#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ -#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) -#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ - uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :1; /*!< bit: 27 Reserved */ - uint32_t OUT:2; /*!< bit: 28..29 Output */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ -#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) -#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ -#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) -#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ -#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */ -#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */ -#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ - uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ - uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :3; /*!< bit: 0.. 2 Reserved */ - uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} AC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ -#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ - -#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ -#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) -#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ -#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) -#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ -#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) -#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) -#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) -#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ - -/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */ - uint16_t :14; /*!< bit: 2..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} AC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */ -#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */ - -#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */ -#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) -#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) -#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ - __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ - RoReg8 Reserved1[0x1]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ - RoReg8 Reserved2[0x2]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved3[0x8]; - __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ - __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_AC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/adc.h b/atmel-samd/asf4/samd51/include/component/adc.h deleted file mode 100644 index 33c38ae3f..000000000 --- a/atmel-samd/asf4/samd51/include/component/adc.h +++ /dev/null @@ -1,871 +0,0 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_ADC_COMPONENT_ -#define _SAMD51_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2500 -#define REV_ADC 0x100 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t :1; /*!< bit: 2 Reserved */ - uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */ - uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :4; /*!< bit: 11..14 Reserved */ - uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */ -#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) -#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ -#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ -#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ -#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */ -#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ -#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) -#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */ -#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) -#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */ -#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */ -#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */ -#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */ -#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */ -#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */ -#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */ -#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */ -#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */ -#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos) -#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ - uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ - uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ - uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ -#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) -#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ -#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ -#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) -#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */ -#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint16_t :2; /*!< bit: 5.. 6 Reserved */ - uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */ - uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint16_t :2; /*!< bit: 13..14 Reserved */ - uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */ -#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */ -#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */ -#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) -#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */ - uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ - uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ -#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) -#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */ -#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) -#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */ -#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos) -#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ -#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) -#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ -#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */ -#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) -#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */ -#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */ -#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ -#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */ -#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos) -#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */ -#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */ -#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ -#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ -#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) -#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ -#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ -#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ -#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ -#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ -#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ -#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ -#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ -#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */ -#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */ - -#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */ -#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) -#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */ -#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) -#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) -#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */ - -/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ - uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */ - uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */ - uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */ - uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */ - uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */ - uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */ - uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */ - uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */ - uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ -#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ - -#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ -#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) -#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ -#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) -#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */ -#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) -#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */ -#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) -#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */ -#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) -#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */ -#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) -#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */ -#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) -#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */ -#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) -#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */ -#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) -#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */ -#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) -#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */ -#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) -#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */ -#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) -#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */ - -/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */ -#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */ - -#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */ -#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) -#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) -#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */ - -/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ - uint32_t CTRLB:1; /*!< bit: 1 Control B */ - uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ - uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ - uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ - uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ - uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ - uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ - uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ - uint32_t :22; /*!< bit: 9..30 Reserved */ - uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */ -#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */ - -#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */ -#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) -#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */ -#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) -#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */ -#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) -#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */ -#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) -#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */ -#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) -#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */ -#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) -#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */ -#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) -#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */ -#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) -#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */ -#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) -#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */ -#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) -#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */ - -/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ - uint32_t CTRLB:1; /*!< bit: 1 Control B */ - uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ - uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ - uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ - uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ - uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ - uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ - uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ - uint32_t :22; /*!< bit: 9..30 Reserved */ - uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQSTAT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */ -#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */ - -#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */ -#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) -#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */ -#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) -#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */ -#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) -#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */ -#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) -#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */ -#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) -#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */ -#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) -#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */ -#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) -#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */ -#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) -#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */ -#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) -#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */ -#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) -#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */ -#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ -#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */ -#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */ - -#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */ -#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) -#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) -#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ -#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) -#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) -#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */ -#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) -#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) -#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ -#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) -#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) -#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */ - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */ - RoReg8 Reserved1[0x1]; - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */ - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */ - RoReg8 Reserved2[0x17]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */ - __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */ - __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */ - __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */ - __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */ - RoReg8 Reserved3[0x2]; - __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */ - RoReg8 Reserved4[0x2]; - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_ADC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/aes.h b/atmel-samd/asf4/samd51/include/component/aes.h deleted file mode 100644 index 5a74eac28..000000000 --- a/atmel-samd/asf4/samd51/include/component/aes.h +++ /dev/null @@ -1,375 +0,0 @@ -/** - * \file - * - * \brief Component description for AES - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_AES_COMPONENT_ -#define _SAMD51_AES_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AES */ -/* ========================================================================== */ -/** \addtogroup SAMD51_AES Advanced Encryption Standard */ -/*@{*/ - -#define AES_U2238 -#define REV_AES 0x220 - -/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ - uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */ - uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */ - uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */ - uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */ - uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */ - uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */ - uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AES_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ -#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ - -#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ -#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) -#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ -#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) -#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ -#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) -#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */ -#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */ -#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */ -#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */ -#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */ -#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */ -#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */ -#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */ -#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) -#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */ -#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) -#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */ -#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */ -#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */ -#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */ -#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */ -#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */ -#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */ -#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */ -#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */ -#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */ -#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */ -#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ -#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */ -#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) -#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) -#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ - -/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */ - uint8_t NEWMSG:1; /*!< bit: 1 New message */ - uint8_t EOM:1; /*!< bit: 2 End of message */ - uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ -#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ - -#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */ -#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) -#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ -#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) -#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ -#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) -#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ -#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) -#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ - -/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ -#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */ -#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */ -#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) -#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ - -/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ -#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ - -#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */ -#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) -#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */ -#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) -#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ - -/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ -#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ - -#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ -#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) -#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ -#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) -#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ - -/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DATABUFPTR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ -#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ - -#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ -#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) -#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) -#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ - -/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ -#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ - -#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ -#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) -#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ - -/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_KEYWORD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ -#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ -#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ - -/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ -#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ -#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ - -/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INTVECTV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ -#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ -#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ - -/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_HASHKEY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ -#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ -#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ - -/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_GHASH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ -#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ -#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ - -/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_CIPLEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ -#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ -#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ - -/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_RANDSEED_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ -#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ -#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ - -/** \brief AES hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ - __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ - __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ - __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ - __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ - __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */ - RoReg8 Reserved1[0x2]; - __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ - RoReg8 Reserved2[0xC]; - __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ - __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ - RoReg8 Reserved3[0x10]; - __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ - __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ - RoReg8 Reserved4[0x4]; - __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ - __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ -} Aes; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_AES_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/can.h b/atmel-samd/asf4/samd51/include/component/can.h deleted file mode 100644 index 9d6754998..000000000 --- a/atmel-samd/asf4/samd51/include/component/can.h +++ /dev/null @@ -1,3207 +0,0 @@ -/** - * \file - * - * \brief Component description for CAN - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_CAN_COMPONENT_ -#define _SAMD51_CAN_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CAN */ -/* ========================================================================== */ -/** \addtogroup SAMD51_CAN Control Area Network */ -/*@{*/ - -#define CAN_U2003 -#define REV_CAN 0x321 - -/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :20; /*!< bit: 0..19 Reserved */ - uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */ - uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */ - uint32_t REL:4; /*!< bit: 28..31 Core Release */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_CREL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */ -#define CAN_CREL_RESETVALUE 0x32100000u /**< \brief (CAN_CREL reset_value) Core Release */ - -#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */ -#define CAN_CREL_SUBSTEP_Msk (0xFu << CAN_CREL_SUBSTEP_Pos) -#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos)) -#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */ -#define CAN_CREL_STEP_Msk (0xFu << CAN_CREL_STEP_Pos) -#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos)) -#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */ -#define CAN_CREL_REL_Msk (0xFu << CAN_CREL_REL_Pos) -#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos)) -#define CAN_CREL_MASK 0xFFF00000u /**< \brief (CAN_CREL) MASK Register */ - -/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ENDN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */ -#define CAN_ENDN_RESETVALUE 0x87654321u /**< \brief (CAN_ENDN reset_value) Endian */ - -#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */ -#define CAN_ENDN_ETV_Msk (0xFFFFFFFFu << CAN_ENDN_ETV_Pos) -#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos)) -#define CAN_ENDN_MASK 0xFFFFFFFFu /**< \brief (CAN_ENDN) MASK Register */ - -/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_MRCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */ -#define CAN_MRCFG_RESETVALUE 0x00000002u /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */ - -#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */ -#define CAN_MRCFG_QOS_Msk (0x3u << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos)) -#define CAN_MRCFG_QOS_DISABLE_Val 0x0u /**< \brief (CAN_MRCFG) Background (no sensitive operation) */ -#define CAN_MRCFG_QOS_LOW_Val 0x1u /**< \brief (CAN_MRCFG) Sensitive Bandwidth */ -#define CAN_MRCFG_QOS_MEDIUM_Val 0x2u /**< \brief (CAN_MRCFG) Sensitive Latency */ -#define CAN_MRCFG_QOS_HIGH_Val 0x3u /**< \brief (CAN_MRCFG) Critical Latency */ -#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) -#define CAN_MRCFG_MASK 0x00000003u /**< \brief (CAN_MRCFG) MASK Register */ - -/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */ - uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */ - uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */ - uint32_t :2; /*!< bit: 21..22 Reserved */ - uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_DBTP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */ -#define CAN_DBTP_RESETVALUE 0x00000A33u /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */ - -#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */ -#define CAN_DBTP_DSJW_Msk (0xFu << CAN_DBTP_DSJW_Pos) -#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos)) -#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */ -#define CAN_DBTP_DTSEG2_Msk (0xFu << CAN_DBTP_DTSEG2_Pos) -#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos)) -#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */ -#define CAN_DBTP_DTSEG1_Msk (0x1Fu << CAN_DBTP_DTSEG1_Pos) -#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos)) -#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */ -#define CAN_DBTP_DBRP_Msk (0x1Fu << CAN_DBTP_DBRP_Pos) -#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos)) -#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */ -#define CAN_DBTP_TDC (0x1u << CAN_DBTP_TDC_Pos) -#define CAN_DBTP_MASK 0x009F1FFFu /**< \brief (CAN_DBTP) MASK Register */ - -/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */ - uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */ - uint32_t RX:1; /*!< bit: 7 Receive Pin */ - uint32_t :24; /*!< bit: 8..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TEST_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */ -#define CAN_TEST_RESETVALUE 0x00000000u /**< \brief (CAN_TEST reset_value) Test */ - -#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */ -#define CAN_TEST_LBCK (0x1u << CAN_TEST_LBCK_Pos) -#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */ -#define CAN_TEST_TX_Msk (0x3u << CAN_TEST_TX_Pos) -#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos)) -#define CAN_TEST_TX_CORE_Val 0x0u /**< \brief (CAN_TEST) TX controlled by CAN core */ -#define CAN_TEST_TX_SAMPLE_Val 0x1u /**< \brief (CAN_TEST) TX monitoring sample point */ -#define CAN_TEST_TX_DOMINANT_Val 0x2u /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */ -#define CAN_TEST_TX_RECESSIVE_Val 0x3u /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */ -#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) -#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */ -#define CAN_TEST_RX (0x1u << CAN_TEST_RX_Pos) -#define CAN_TEST_MASK 0x000000F0u /**< \brief (CAN_TEST) MASK Register */ - -/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */ - uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RWD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */ -#define CAN_RWD_RESETVALUE 0x00000000u /**< \brief (CAN_RWD reset_value) RAM Watchdog */ - -#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */ -#define CAN_RWD_WDC_Msk (0xFFu << CAN_RWD_WDC_Pos) -#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos)) -#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */ -#define CAN_RWD_WDV_Msk (0xFFu << CAN_RWD_WDV_Pos) -#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos)) -#define CAN_RWD_MASK 0x0000FFFFu /**< \brief (CAN_RWD) MASK Register */ - -/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INIT:1; /*!< bit: 0 Initialization */ - uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */ - uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */ - uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */ - uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */ - uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */ - uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */ - uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */ - uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */ - uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */ - uint32_t :2; /*!< bit: 10..11 Reserved */ - uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */ - uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */ - uint32_t TXP:1; /*!< bit: 14 Transmit Pause */ - uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_CCCR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */ -#define CAN_CCCR_RESETVALUE 0x00000001u /**< \brief (CAN_CCCR reset_value) CC Control */ - -#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */ -#define CAN_CCCR_INIT (0x1u << CAN_CCCR_INIT_Pos) -#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */ -#define CAN_CCCR_CCE (0x1u << CAN_CCCR_CCE_Pos) -#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */ -#define CAN_CCCR_ASM (0x1u << CAN_CCCR_ASM_Pos) -#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */ -#define CAN_CCCR_CSA (0x1u << CAN_CCCR_CSA_Pos) -#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */ -#define CAN_CCCR_CSR (0x1u << CAN_CCCR_CSR_Pos) -#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */ -#define CAN_CCCR_MON (0x1u << CAN_CCCR_MON_Pos) -#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */ -#define CAN_CCCR_DAR (0x1u << CAN_CCCR_DAR_Pos) -#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */ -#define CAN_CCCR_TEST (0x1u << CAN_CCCR_TEST_Pos) -#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */ -#define CAN_CCCR_FDOE (0x1u << CAN_CCCR_FDOE_Pos) -#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */ -#define CAN_CCCR_BRSE (0x1u << CAN_CCCR_BRSE_Pos) -#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */ -#define CAN_CCCR_PXHD (0x1u << CAN_CCCR_PXHD_Pos) -#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */ -#define CAN_CCCR_EFBI (0x1u << CAN_CCCR_EFBI_Pos) -#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */ -#define CAN_CCCR_TXP (0x1u << CAN_CCCR_TXP_Pos) -#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */ -#define CAN_CCCR_NISO (0x1u << CAN_CCCR_NISO_Pos) -#define CAN_CCCR_MASK 0x0000F3FFu /**< \brief (CAN_CCCR) MASK Register */ - -/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */ - uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */ - uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_NBTP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */ -#define CAN_NBTP_RESETVALUE 0x06000A03u /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */ - -#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */ -#define CAN_NBTP_NTSEG2_Msk (0x7Fu << CAN_NBTP_NTSEG2_Pos) -#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos)) -#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */ -#define CAN_NBTP_NTSEG1_Msk (0xFFu << CAN_NBTP_NTSEG1_Pos) -#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos)) -#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */ -#define CAN_NBTP_NBRP_Msk (0x1FFu << CAN_NBTP_NBRP_Pos) -#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos)) -#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */ -#define CAN_NBTP_NSJW_Msk (0x7Fu << CAN_NBTP_NSJW_Pos) -#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos)) -#define CAN_NBTP_MASK 0xFFFFFF7Fu /**< \brief (CAN_NBTP) MASK Register */ - -/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */ - uint32_t :14; /*!< bit: 2..15 Reserved */ - uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TSCC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */ -#define CAN_TSCC_RESETVALUE 0x00000000u /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */ - -#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */ -#define CAN_TSCC_TSS_Msk (0x3u << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos)) -#define CAN_TSCC_TSS_ZERO_Val 0x0u /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */ -#define CAN_TSCC_TSS_INC_Val 0x1u /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */ -#define CAN_TSCC_TSS_EXT_Val 0x2u /**< \brief (CAN_TSCC) External timestamp counter value used */ -#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) -#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */ -#define CAN_TSCC_TCP_Msk (0xFu << CAN_TSCC_TCP_Pos) -#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos)) -#define CAN_TSCC_MASK 0x000F0003u /**< \brief (CAN_TSCC) MASK Register */ - -/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TSCV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */ -#define CAN_TSCV_RESETVALUE 0x00000000u /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */ - -#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */ -#define CAN_TSCV_TSC_Msk (0xFFFFu << CAN_TSCV_TSC_Pos) -#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos)) -#define CAN_TSCV_MASK 0x0000FFFFu /**< \brief (CAN_TSCV) MASK Register */ - -/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */ - uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */ - uint32_t :13; /*!< bit: 3..15 Reserved */ - uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TOCC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */ -#define CAN_TOCC_RESETVALUE 0xFFFF0000u /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */ - -#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */ -#define CAN_TOCC_ETOC (0x1u << CAN_TOCC_ETOC_Pos) -#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */ -#define CAN_TOCC_TOS_Msk (0x3u << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos)) -#define CAN_TOCC_TOS_CONT_Val 0x0u /**< \brief (CAN_TOCC) Continuout operation */ -#define CAN_TOCC_TOS_TXEF_Val 0x1u /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */ -#define CAN_TOCC_TOS_RXF0_Val 0x2u /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ -#define CAN_TOCC_TOS_RXF1_Val 0x3u /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ -#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) -#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */ -#define CAN_TOCC_TOP_Msk (0xFFFFu << CAN_TOCC_TOP_Pos) -#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos)) -#define CAN_TOCC_MASK 0xFFFF0007u /**< \brief (CAN_TOCC) MASK Register */ - -/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TOCV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */ -#define CAN_TOCV_RESETVALUE 0x0000FFFFu /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */ - -#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */ -#define CAN_TOCV_TOC_Msk (0xFFFFu << CAN_TOCV_TOC_Pos) -#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos)) -#define CAN_TOCV_MASK 0x0000FFFFu /**< \brief (CAN_TOCV) MASK Register */ - -/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */ - uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */ - uint32_t RP:1; /*!< bit: 15 Receive Error Passive */ - uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ECR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */ -#define CAN_ECR_RESETVALUE 0x00000000u /**< \brief (CAN_ECR reset_value) Error Counter */ - -#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */ -#define CAN_ECR_TEC_Msk (0xFFu << CAN_ECR_TEC_Pos) -#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos)) -#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */ -#define CAN_ECR_REC_Msk (0x7Fu << CAN_ECR_REC_Pos) -#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos)) -#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */ -#define CAN_ECR_RP (0x1u << CAN_ECR_RP_Pos) -#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */ -#define CAN_ECR_CEL_Msk (0xFFu << CAN_ECR_CEL_Pos) -#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos)) -#define CAN_ECR_MASK 0x00FFFFFFu /**< \brief (CAN_ECR) MASK Register */ - -/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */ - uint32_t ACT:2; /*!< bit: 3.. 4 Activity */ - uint32_t EP:1; /*!< bit: 5 Error Passive */ - uint32_t EW:1; /*!< bit: 6 Warning Status */ - uint32_t BO:1; /*!< bit: 7 Bus_Off Status */ - uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */ - uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */ - uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */ - uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */ - uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_PSR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */ -#define CAN_PSR_RESETVALUE 0x00000707u /**< \brief (CAN_PSR reset_value) Protocol Status */ - -#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */ -#define CAN_PSR_LEC_Msk (0x7u << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos)) -#define CAN_PSR_LEC_NONE_Val 0x0u /**< \brief (CAN_PSR) No Error */ -#define CAN_PSR_LEC_STUFF_Val 0x1u /**< \brief (CAN_PSR) Stuff Error */ -#define CAN_PSR_LEC_FORM_Val 0x2u /**< \brief (CAN_PSR) Form Error */ -#define CAN_PSR_LEC_ACK_Val 0x3u /**< \brief (CAN_PSR) Ack Error */ -#define CAN_PSR_LEC_BIT1_Val 0x4u /**< \brief (CAN_PSR) Bit1 Error */ -#define CAN_PSR_LEC_BIT0_Val 0x5u /**< \brief (CAN_PSR) Bit0 Error */ -#define CAN_PSR_LEC_CRC_Val 0x6u /**< \brief (CAN_PSR) CRC Error */ -#define CAN_PSR_LEC_NC_Val 0x7u /**< \brief (CAN_PSR) No Change */ -#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) -#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */ -#define CAN_PSR_ACT_Msk (0x3u << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos)) -#define CAN_PSR_ACT_SYNC_Val 0x0u /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */ -#define CAN_PSR_ACT_IDLE_Val 0x1u /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */ -#define CAN_PSR_ACT_RX_Val 0x2u /**< \brief (CAN_PSR) Node is operating as receiver */ -#define CAN_PSR_ACT_TX_Val 0x3u /**< \brief (CAN_PSR) Node is operating as transmitter */ -#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) -#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */ -#define CAN_PSR_EP (0x1u << CAN_PSR_EP_Pos) -#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */ -#define CAN_PSR_EW (0x1u << CAN_PSR_EW_Pos) -#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */ -#define CAN_PSR_BO (0x1u << CAN_PSR_BO_Pos) -#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */ -#define CAN_PSR_DLEC_Msk (0x7u << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos)) -#define CAN_PSR_DLEC_NONE_Val 0x0u /**< \brief (CAN_PSR) No Error */ -#define CAN_PSR_DLEC_STUFF_Val 0x1u /**< \brief (CAN_PSR) Stuff Error */ -#define CAN_PSR_DLEC_FORM_Val 0x2u /**< \brief (CAN_PSR) Form Error */ -#define CAN_PSR_DLEC_ACK_Val 0x3u /**< \brief (CAN_PSR) Ack Error */ -#define CAN_PSR_DLEC_BIT1_Val 0x4u /**< \brief (CAN_PSR) Bit1 Error */ -#define CAN_PSR_DLEC_BIT0_Val 0x5u /**< \brief (CAN_PSR) Bit0 Error */ -#define CAN_PSR_DLEC_CRC_Val 0x6u /**< \brief (CAN_PSR) CRC Error */ -#define CAN_PSR_DLEC_NC_Val 0x7u /**< \brief (CAN_PSR) No Change */ -#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) -#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */ -#define CAN_PSR_RESI (0x1u << CAN_PSR_RESI_Pos) -#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */ -#define CAN_PSR_RBRS (0x1u << CAN_PSR_RBRS_Pos) -#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */ -#define CAN_PSR_RFDF (0x1u << CAN_PSR_RFDF_Pos) -#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */ -#define CAN_PSR_PXE (0x1u << CAN_PSR_PXE_Pos) -#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */ -#define CAN_PSR_TDCV_Msk (0x7Fu << CAN_PSR_TDCV_Pos) -#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos)) -#define CAN_PSR_MASK 0x007F7FFFu /**< \brief (CAN_PSR) MASK Register */ - -/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */ - uint32_t :17; /*!< bit: 15..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TDCR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */ -#define CAN_TDCR_RESETVALUE 0x00000000u /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */ - -#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */ -#define CAN_TDCR_TDCF_Msk (0x7Fu << CAN_TDCR_TDCF_Pos) -#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos)) -#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */ -#define CAN_TDCR_TDCO_Msk (0x7Fu << CAN_TDCR_TDCO_Pos) -#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos)) -#define CAN_TDCR_MASK 0x00007F7Fu /**< \brief (CAN_TDCR) MASK Register */ - -/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */ - uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */ - uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */ - uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */ - uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */ - uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */ - uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */ - uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */ - uint32_t HPM:1; /*!< bit: 8 High Priority Message */ - uint32_t TC:1; /*!< bit: 9 Timestamp Completed */ - uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */ - uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */ - uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */ - uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */ - uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */ - uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */ - uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */ - uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */ - uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */ - uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */ - uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */ - uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */ - uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */ - uint32_t EP:1; /*!< bit: 23 Error Passive */ - uint32_t EW:1; /*!< bit: 24 Warning Status */ - uint32_t BO:1; /*!< bit: 25 Bus_Off Status */ - uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */ - uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */ - uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */ - uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_IR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */ -#define CAN_IR_RESETVALUE 0x00000000u /**< \brief (CAN_IR reset_value) Interrupt */ - -#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */ -#define CAN_IR_RF0N (0x1u << CAN_IR_RF0N_Pos) -#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */ -#define CAN_IR_RF0W (0x1u << CAN_IR_RF0W_Pos) -#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */ -#define CAN_IR_RF0F (0x1u << CAN_IR_RF0F_Pos) -#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */ -#define CAN_IR_RF0L (0x1u << CAN_IR_RF0L_Pos) -#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */ -#define CAN_IR_RF1N (0x1u << CAN_IR_RF1N_Pos) -#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */ -#define CAN_IR_RF1W (0x1u << CAN_IR_RF1W_Pos) -#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */ -#define CAN_IR_RF1F (0x1u << CAN_IR_RF1F_Pos) -#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */ -#define CAN_IR_RF1L (0x1u << CAN_IR_RF1L_Pos) -#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */ -#define CAN_IR_HPM (0x1u << CAN_IR_HPM_Pos) -#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */ -#define CAN_IR_TC (0x1u << CAN_IR_TC_Pos) -#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */ -#define CAN_IR_TCF (0x1u << CAN_IR_TCF_Pos) -#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */ -#define CAN_IR_TFE (0x1u << CAN_IR_TFE_Pos) -#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */ -#define CAN_IR_TEFN (0x1u << CAN_IR_TEFN_Pos) -#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */ -#define CAN_IR_TEFW (0x1u << CAN_IR_TEFW_Pos) -#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */ -#define CAN_IR_TEFF (0x1u << CAN_IR_TEFF_Pos) -#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */ -#define CAN_IR_TEFL (0x1u << CAN_IR_TEFL_Pos) -#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */ -#define CAN_IR_TSW (0x1u << CAN_IR_TSW_Pos) -#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */ -#define CAN_IR_MRAF (0x1u << CAN_IR_MRAF_Pos) -#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */ -#define CAN_IR_TOO (0x1u << CAN_IR_TOO_Pos) -#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */ -#define CAN_IR_DRX (0x1u << CAN_IR_DRX_Pos) -#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */ -#define CAN_IR_BEC (0x1u << CAN_IR_BEC_Pos) -#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */ -#define CAN_IR_BEU (0x1u << CAN_IR_BEU_Pos) -#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */ -#define CAN_IR_ELO (0x1u << CAN_IR_ELO_Pos) -#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */ -#define CAN_IR_EP (0x1u << CAN_IR_EP_Pos) -#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */ -#define CAN_IR_EW (0x1u << CAN_IR_EW_Pos) -#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */ -#define CAN_IR_BO (0x1u << CAN_IR_BO_Pos) -#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */ -#define CAN_IR_WDI (0x1u << CAN_IR_WDI_Pos) -#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */ -#define CAN_IR_PEA (0x1u << CAN_IR_PEA_Pos) -#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */ -#define CAN_IR_PED (0x1u << CAN_IR_PED_Pos) -#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */ -#define CAN_IR_ARA (0x1u << CAN_IR_ARA_Pos) -#define CAN_IR_MASK 0x3FFFFFFFu /**< \brief (CAN_IR) MASK Register */ - -/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */ - uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */ - uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */ - uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */ - uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */ - uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */ - uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */ - uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */ - uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */ - uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */ - uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */ - uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */ - uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */ - uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */ - uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */ - uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */ - uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */ - uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */ - uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */ - uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */ - uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */ - uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */ - uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */ - uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */ - uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */ - uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */ - uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */ - uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */ - uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */ - uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_IE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */ -#define CAN_IE_RESETVALUE 0x00000000u /**< \brief (CAN_IE reset_value) Interrupt Enable */ - -#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */ -#define CAN_IE_RF0NE (0x1u << CAN_IE_RF0NE_Pos) -#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */ -#define CAN_IE_RF0WE (0x1u << CAN_IE_RF0WE_Pos) -#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */ -#define CAN_IE_RF0FE (0x1u << CAN_IE_RF0FE_Pos) -#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */ -#define CAN_IE_RF0LE (0x1u << CAN_IE_RF0LE_Pos) -#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */ -#define CAN_IE_RF1NE (0x1u << CAN_IE_RF1NE_Pos) -#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */ -#define CAN_IE_RF1WE (0x1u << CAN_IE_RF1WE_Pos) -#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */ -#define CAN_IE_RF1FE (0x1u << CAN_IE_RF1FE_Pos) -#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */ -#define CAN_IE_RF1LE (0x1u << CAN_IE_RF1LE_Pos) -#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */ -#define CAN_IE_HPME (0x1u << CAN_IE_HPME_Pos) -#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */ -#define CAN_IE_TCE (0x1u << CAN_IE_TCE_Pos) -#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */ -#define CAN_IE_TCFE (0x1u << CAN_IE_TCFE_Pos) -#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */ -#define CAN_IE_TFEE (0x1u << CAN_IE_TFEE_Pos) -#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */ -#define CAN_IE_TEFNE (0x1u << CAN_IE_TEFNE_Pos) -#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ -#define CAN_IE_TEFWE (0x1u << CAN_IE_TEFWE_Pos) -#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */ -#define CAN_IE_TEFFE (0x1u << CAN_IE_TEFFE_Pos) -#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */ -#define CAN_IE_TEFLE (0x1u << CAN_IE_TEFLE_Pos) -#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */ -#define CAN_IE_TSWE (0x1u << CAN_IE_TSWE_Pos) -#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */ -#define CAN_IE_MRAFE (0x1u << CAN_IE_MRAFE_Pos) -#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */ -#define CAN_IE_TOOE (0x1u << CAN_IE_TOOE_Pos) -#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */ -#define CAN_IE_DRXE (0x1u << CAN_IE_DRXE_Pos) -#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */ -#define CAN_IE_BECE (0x1u << CAN_IE_BECE_Pos) -#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */ -#define CAN_IE_BEUE (0x1u << CAN_IE_BEUE_Pos) -#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */ -#define CAN_IE_ELOE (0x1u << CAN_IE_ELOE_Pos) -#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */ -#define CAN_IE_EPE (0x1u << CAN_IE_EPE_Pos) -#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */ -#define CAN_IE_EWE (0x1u << CAN_IE_EWE_Pos) -#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */ -#define CAN_IE_BOE (0x1u << CAN_IE_BOE_Pos) -#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */ -#define CAN_IE_WDIE (0x1u << CAN_IE_WDIE_Pos) -#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */ -#define CAN_IE_PEAE (0x1u << CAN_IE_PEAE_Pos) -#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */ -#define CAN_IE_PEDE (0x1u << CAN_IE_PEDE_Pos) -#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */ -#define CAN_IE_ARAE (0x1u << CAN_IE_ARAE_Pos) -#define CAN_IE_MASK 0x3FFFFFFFu /**< \brief (CAN_IE) MASK Register */ - -/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */ - uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */ - uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */ - uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */ - uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */ - uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */ - uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */ - uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */ - uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */ - uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */ - uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */ - uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */ - uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */ - uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */ - uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */ - uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */ - uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */ - uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */ - uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */ - uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */ - uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */ - uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */ - uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */ - uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */ - uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */ - uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */ - uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */ - uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */ - uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */ - uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ILS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */ -#define CAN_ILS_RESETVALUE 0x00000000u /**< \brief (CAN_ILS reset_value) Interrupt Line Select */ - -#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */ -#define CAN_ILS_RF0NL (0x1u << CAN_ILS_RF0NL_Pos) -#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */ -#define CAN_ILS_RF0WL (0x1u << CAN_ILS_RF0WL_Pos) -#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */ -#define CAN_ILS_RF0FL (0x1u << CAN_ILS_RF0FL_Pos) -#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */ -#define CAN_ILS_RF0LL (0x1u << CAN_ILS_RF0LL_Pos) -#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */ -#define CAN_ILS_RF1NL (0x1u << CAN_ILS_RF1NL_Pos) -#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */ -#define CAN_ILS_RF1WL (0x1u << CAN_ILS_RF1WL_Pos) -#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */ -#define CAN_ILS_RF1FL (0x1u << CAN_ILS_RF1FL_Pos) -#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */ -#define CAN_ILS_RF1LL (0x1u << CAN_ILS_RF1LL_Pos) -#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */ -#define CAN_ILS_HPML (0x1u << CAN_ILS_HPML_Pos) -#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */ -#define CAN_ILS_TCL (0x1u << CAN_ILS_TCL_Pos) -#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */ -#define CAN_ILS_TCFL (0x1u << CAN_ILS_TCFL_Pos) -#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */ -#define CAN_ILS_TFEL (0x1u << CAN_ILS_TFEL_Pos) -#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */ -#define CAN_ILS_TEFNL (0x1u << CAN_ILS_TEFNL_Pos) -#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ -#define CAN_ILS_TEFWL (0x1u << CAN_ILS_TEFWL_Pos) -#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */ -#define CAN_ILS_TEFFL (0x1u << CAN_ILS_TEFFL_Pos) -#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */ -#define CAN_ILS_TEFLL (0x1u << CAN_ILS_TEFLL_Pos) -#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */ -#define CAN_ILS_TSWL (0x1u << CAN_ILS_TSWL_Pos) -#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */ -#define CAN_ILS_MRAFL (0x1u << CAN_ILS_MRAFL_Pos) -#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */ -#define CAN_ILS_TOOL (0x1u << CAN_ILS_TOOL_Pos) -#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */ -#define CAN_ILS_DRXL (0x1u << CAN_ILS_DRXL_Pos) -#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */ -#define CAN_ILS_BECL (0x1u << CAN_ILS_BECL_Pos) -#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */ -#define CAN_ILS_BEUL (0x1u << CAN_ILS_BEUL_Pos) -#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */ -#define CAN_ILS_ELOL (0x1u << CAN_ILS_ELOL_Pos) -#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */ -#define CAN_ILS_EPL (0x1u << CAN_ILS_EPL_Pos) -#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */ -#define CAN_ILS_EWL (0x1u << CAN_ILS_EWL_Pos) -#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */ -#define CAN_ILS_BOL (0x1u << CAN_ILS_BOL_Pos) -#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */ -#define CAN_ILS_WDIL (0x1u << CAN_ILS_WDIL_Pos) -#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */ -#define CAN_ILS_PEAL (0x1u << CAN_ILS_PEAL_Pos) -#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */ -#define CAN_ILS_PEDL (0x1u << CAN_ILS_PEDL_Pos) -#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */ -#define CAN_ILS_ARAL (0x1u << CAN_ILS_ARAL_Pos) -#define CAN_ILS_MASK 0x3FFFFFFFu /**< \brief (CAN_ILS) MASK Register */ - -/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */ - uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_ILE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */ -#define CAN_ILE_RESETVALUE 0x00000000u /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */ - -#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */ -#define CAN_ILE_EINT0 (0x1u << CAN_ILE_EINT0_Pos) -#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */ -#define CAN_ILE_EINT1 (0x1u << CAN_ILE_EINT1_Pos) -#define CAN_ILE_MASK 0x00000003u /**< \brief (CAN_ILE) MASK Register */ - -/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */ - uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */ - uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */ - uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_GFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */ -#define CAN_GFC_RESETVALUE 0x00000000u /**< \brief (CAN_GFC reset_value) Global Filter Configuration */ - -#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */ -#define CAN_GFC_RRFE (0x1u << CAN_GFC_RRFE_Pos) -#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */ -#define CAN_GFC_RRFS (0x1u << CAN_GFC_RRFS_Pos) -#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */ -#define CAN_GFC_ANFE_Msk (0x3u << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos)) -#define CAN_GFC_ANFE_RXF0_Val 0x0u /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ -#define CAN_GFC_ANFE_RXF1_Val 0x1u /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ -#define CAN_GFC_ANFE_REJECT_Val 0x2u /**< \brief (CAN_GFC) Reject */ -#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) -#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */ -#define CAN_GFC_ANFS_Msk (0x3u << CAN_GFC_ANFS_Pos) -#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos)) -#define CAN_GFC_ANFS_RXF0_Val 0x0u /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ -#define CAN_GFC_ANFS_RXF1_Val 0x1u /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ -#define CAN_GFC_ANFS_REJECT_Val 0x2u /**< \brief (CAN_GFC) Reject */ -#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) -#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) -#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) -#define CAN_GFC_MASK 0x0000003Fu /**< \brief (CAN_GFC) MASK Register */ - -/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */ - uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */ - uint32_t :8; /*!< bit: 24..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_SIDFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */ -#define CAN_SIDFC_RESETVALUE 0x00000000u /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */ - -#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */ -#define CAN_SIDFC_FLSSA_Msk (0xFFFFu << CAN_SIDFC_FLSSA_Pos) -#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos)) -#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */ -#define CAN_SIDFC_LSS_Msk (0xFFu << CAN_SIDFC_LSS_Pos) -#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos)) -#define CAN_SIDFC_MASK 0x00FFFFFFu /**< \brief (CAN_SIDFC) MASK Register */ - -/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */ - uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */ - uint32_t :9; /*!< bit: 23..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */ -#define CAN_XIDFC_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */ - -#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */ -#define CAN_XIDFC_FLESA_Msk (0xFFFFu << CAN_XIDFC_FLESA_Pos) -#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos)) -#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */ -#define CAN_XIDFC_LSE_Msk (0x7Fu << CAN_XIDFC_LSE_Pos) -#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos)) -#define CAN_XIDFC_MASK 0x007FFFFFu /**< \brief (CAN_XIDFC) MASK Register */ - -/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */ - uint32_t :3; /*!< bit: 29..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDAM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */ -#define CAN_XIDAM_RESETVALUE 0x1FFFFFFFu /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */ - -#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */ -#define CAN_XIDAM_EIDM_Msk (0x1FFFFFFFu << CAN_XIDAM_EIDM_Pos) -#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos)) -#define CAN_XIDAM_MASK 0x1FFFFFFFu /**< \brief (CAN_XIDAM) MASK Register */ - -/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */ - uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */ - uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */ - uint32_t FLST:1; /*!< bit: 15 Filter List */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_HPMS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */ -#define CAN_HPMS_RESETVALUE 0x00000000u /**< \brief (CAN_HPMS reset_value) High Priority Message Status */ - -#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */ -#define CAN_HPMS_BIDX_Msk (0x3Fu << CAN_HPMS_BIDX_Pos) -#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos)) -#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */ -#define CAN_HPMS_MSI_Msk (0x3u << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos)) -#define CAN_HPMS_MSI_NONE_Val 0x0u /**< \brief (CAN_HPMS) No FIFO selected */ -#define CAN_HPMS_MSI_LOST_Val 0x1u /**< \brief (CAN_HPMS) FIFO message lost */ -#define CAN_HPMS_MSI_FIFO0_Val 0x2u /**< \brief (CAN_HPMS) Message stored in FIFO 0 */ -#define CAN_HPMS_MSI_FIFO1_Val 0x3u /**< \brief (CAN_HPMS) Message stored in FIFO 1 */ -#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) -#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */ -#define CAN_HPMS_FIDX_Msk (0x7Fu << CAN_HPMS_FIDX_Pos) -#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos)) -#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */ -#define CAN_HPMS_FLST (0x1u << CAN_HPMS_FLST_Pos) -#define CAN_HPMS_MASK 0x0000FFFFu /**< \brief (CAN_HPMS) MASK Register */ - -/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ND0:1; /*!< bit: 0 New Data 0 */ - uint32_t ND1:1; /*!< bit: 1 New Data 1 */ - uint32_t ND2:1; /*!< bit: 2 New Data 2 */ - uint32_t ND3:1; /*!< bit: 3 New Data 3 */ - uint32_t ND4:1; /*!< bit: 4 New Data 4 */ - uint32_t ND5:1; /*!< bit: 5 New Data 5 */ - uint32_t ND6:1; /*!< bit: 6 New Data 6 */ - uint32_t ND7:1; /*!< bit: 7 New Data 7 */ - uint32_t ND8:1; /*!< bit: 8 New Data 8 */ - uint32_t ND9:1; /*!< bit: 9 New Data 9 */ - uint32_t ND10:1; /*!< bit: 10 New Data 10 */ - uint32_t ND11:1; /*!< bit: 11 New Data 11 */ - uint32_t ND12:1; /*!< bit: 12 New Data 12 */ - uint32_t ND13:1; /*!< bit: 13 New Data 13 */ - uint32_t ND14:1; /*!< bit: 14 New Data 14 */ - uint32_t ND15:1; /*!< bit: 15 New Data 15 */ - uint32_t ND16:1; /*!< bit: 16 New Data 16 */ - uint32_t ND17:1; /*!< bit: 17 New Data 17 */ - uint32_t ND18:1; /*!< bit: 18 New Data 18 */ - uint32_t ND19:1; /*!< bit: 19 New Data 19 */ - uint32_t ND20:1; /*!< bit: 20 New Data 20 */ - uint32_t ND21:1; /*!< bit: 21 New Data 21 */ - uint32_t ND22:1; /*!< bit: 22 New Data 22 */ - uint32_t ND23:1; /*!< bit: 23 New Data 23 */ - uint32_t ND24:1; /*!< bit: 24 New Data 24 */ - uint32_t ND25:1; /*!< bit: 25 New Data 25 */ - uint32_t ND26:1; /*!< bit: 26 New Data 26 */ - uint32_t ND27:1; /*!< bit: 27 New Data 27 */ - uint32_t ND28:1; /*!< bit: 28 New Data 28 */ - uint32_t ND29:1; /*!< bit: 29 New Data 29 */ - uint32_t ND30:1; /*!< bit: 30 New Data 30 */ - uint32_t ND31:1; /*!< bit: 31 New Data 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_NDAT1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */ -#define CAN_NDAT1_RESETVALUE 0x00000000u /**< \brief (CAN_NDAT1 reset_value) New Data 1 */ - -#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */ -#define CAN_NDAT1_ND0 (0x1u << CAN_NDAT1_ND0_Pos) -#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */ -#define CAN_NDAT1_ND1 (0x1u << CAN_NDAT1_ND1_Pos) -#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */ -#define CAN_NDAT1_ND2 (0x1u << CAN_NDAT1_ND2_Pos) -#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */ -#define CAN_NDAT1_ND3 (0x1u << CAN_NDAT1_ND3_Pos) -#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */ -#define CAN_NDAT1_ND4 (0x1u << CAN_NDAT1_ND4_Pos) -#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */ -#define CAN_NDAT1_ND5 (0x1u << CAN_NDAT1_ND5_Pos) -#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */ -#define CAN_NDAT1_ND6 (0x1u << CAN_NDAT1_ND6_Pos) -#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */ -#define CAN_NDAT1_ND7 (0x1u << CAN_NDAT1_ND7_Pos) -#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */ -#define CAN_NDAT1_ND8 (0x1u << CAN_NDAT1_ND8_Pos) -#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */ -#define CAN_NDAT1_ND9 (0x1u << CAN_NDAT1_ND9_Pos) -#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */ -#define CAN_NDAT1_ND10 (0x1u << CAN_NDAT1_ND10_Pos) -#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */ -#define CAN_NDAT1_ND11 (0x1u << CAN_NDAT1_ND11_Pos) -#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */ -#define CAN_NDAT1_ND12 (0x1u << CAN_NDAT1_ND12_Pos) -#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */ -#define CAN_NDAT1_ND13 (0x1u << CAN_NDAT1_ND13_Pos) -#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */ -#define CAN_NDAT1_ND14 (0x1u << CAN_NDAT1_ND14_Pos) -#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */ -#define CAN_NDAT1_ND15 (0x1u << CAN_NDAT1_ND15_Pos) -#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */ -#define CAN_NDAT1_ND16 (0x1u << CAN_NDAT1_ND16_Pos) -#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */ -#define CAN_NDAT1_ND17 (0x1u << CAN_NDAT1_ND17_Pos) -#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */ -#define CAN_NDAT1_ND18 (0x1u << CAN_NDAT1_ND18_Pos) -#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */ -#define CAN_NDAT1_ND19 (0x1u << CAN_NDAT1_ND19_Pos) -#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */ -#define CAN_NDAT1_ND20 (0x1u << CAN_NDAT1_ND20_Pos) -#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */ -#define CAN_NDAT1_ND21 (0x1u << CAN_NDAT1_ND21_Pos) -#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */ -#define CAN_NDAT1_ND22 (0x1u << CAN_NDAT1_ND22_Pos) -#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */ -#define CAN_NDAT1_ND23 (0x1u << CAN_NDAT1_ND23_Pos) -#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */ -#define CAN_NDAT1_ND24 (0x1u << CAN_NDAT1_ND24_Pos) -#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */ -#define CAN_NDAT1_ND25 (0x1u << CAN_NDAT1_ND25_Pos) -#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */ -#define CAN_NDAT1_ND26 (0x1u << CAN_NDAT1_ND26_Pos) -#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */ -#define CAN_NDAT1_ND27 (0x1u << CAN_NDAT1_ND27_Pos) -#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */ -#define CAN_NDAT1_ND28 (0x1u << CAN_NDAT1_ND28_Pos) -#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */ -#define CAN_NDAT1_ND29 (0x1u << CAN_NDAT1_ND29_Pos) -#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */ -#define CAN_NDAT1_ND30 (0x1u << CAN_NDAT1_ND30_Pos) -#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */ -#define CAN_NDAT1_ND31 (0x1u << CAN_NDAT1_ND31_Pos) -#define CAN_NDAT1_MASK 0xFFFFFFFFu /**< \brief (CAN_NDAT1) MASK Register */ - -/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ND32:1; /*!< bit: 0 New Data 32 */ - uint32_t ND33:1; /*!< bit: 1 New Data 33 */ - uint32_t ND34:1; /*!< bit: 2 New Data 34 */ - uint32_t ND35:1; /*!< bit: 3 New Data 35 */ - uint32_t ND36:1; /*!< bit: 4 New Data 36 */ - uint32_t ND37:1; /*!< bit: 5 New Data 37 */ - uint32_t ND38:1; /*!< bit: 6 New Data 38 */ - uint32_t ND39:1; /*!< bit: 7 New Data 39 */ - uint32_t ND40:1; /*!< bit: 8 New Data 40 */ - uint32_t ND41:1; /*!< bit: 9 New Data 41 */ - uint32_t ND42:1; /*!< bit: 10 New Data 42 */ - uint32_t ND43:1; /*!< bit: 11 New Data 43 */ - uint32_t ND44:1; /*!< bit: 12 New Data 44 */ - uint32_t ND45:1; /*!< bit: 13 New Data 45 */ - uint32_t ND46:1; /*!< bit: 14 New Data 46 */ - uint32_t ND47:1; /*!< bit: 15 New Data 47 */ - uint32_t ND48:1; /*!< bit: 16 New Data 48 */ - uint32_t ND49:1; /*!< bit: 17 New Data 49 */ - uint32_t ND50:1; /*!< bit: 18 New Data 50 */ - uint32_t ND51:1; /*!< bit: 19 New Data 51 */ - uint32_t ND52:1; /*!< bit: 20 New Data 52 */ - uint32_t ND53:1; /*!< bit: 21 New Data 53 */ - uint32_t ND54:1; /*!< bit: 22 New Data 54 */ - uint32_t ND55:1; /*!< bit: 23 New Data 55 */ - uint32_t ND56:1; /*!< bit: 24 New Data 56 */ - uint32_t ND57:1; /*!< bit: 25 New Data 57 */ - uint32_t ND58:1; /*!< bit: 26 New Data 58 */ - uint32_t ND59:1; /*!< bit: 27 New Data 59 */ - uint32_t ND60:1; /*!< bit: 28 New Data 60 */ - uint32_t ND61:1; /*!< bit: 29 New Data 61 */ - uint32_t ND62:1; /*!< bit: 30 New Data 62 */ - uint32_t ND63:1; /*!< bit: 31 New Data 63 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_NDAT2_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */ -#define CAN_NDAT2_RESETVALUE 0x00000000u /**< \brief (CAN_NDAT2 reset_value) New Data 2 */ - -#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */ -#define CAN_NDAT2_ND32 (0x1u << CAN_NDAT2_ND32_Pos) -#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */ -#define CAN_NDAT2_ND33 (0x1u << CAN_NDAT2_ND33_Pos) -#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */ -#define CAN_NDAT2_ND34 (0x1u << CAN_NDAT2_ND34_Pos) -#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */ -#define CAN_NDAT2_ND35 (0x1u << CAN_NDAT2_ND35_Pos) -#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */ -#define CAN_NDAT2_ND36 (0x1u << CAN_NDAT2_ND36_Pos) -#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */ -#define CAN_NDAT2_ND37 (0x1u << CAN_NDAT2_ND37_Pos) -#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */ -#define CAN_NDAT2_ND38 (0x1u << CAN_NDAT2_ND38_Pos) -#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */ -#define CAN_NDAT2_ND39 (0x1u << CAN_NDAT2_ND39_Pos) -#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */ -#define CAN_NDAT2_ND40 (0x1u << CAN_NDAT2_ND40_Pos) -#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */ -#define CAN_NDAT2_ND41 (0x1u << CAN_NDAT2_ND41_Pos) -#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */ -#define CAN_NDAT2_ND42 (0x1u << CAN_NDAT2_ND42_Pos) -#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */ -#define CAN_NDAT2_ND43 (0x1u << CAN_NDAT2_ND43_Pos) -#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */ -#define CAN_NDAT2_ND44 (0x1u << CAN_NDAT2_ND44_Pos) -#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */ -#define CAN_NDAT2_ND45 (0x1u << CAN_NDAT2_ND45_Pos) -#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */ -#define CAN_NDAT2_ND46 (0x1u << CAN_NDAT2_ND46_Pos) -#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */ -#define CAN_NDAT2_ND47 (0x1u << CAN_NDAT2_ND47_Pos) -#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */ -#define CAN_NDAT2_ND48 (0x1u << CAN_NDAT2_ND48_Pos) -#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */ -#define CAN_NDAT2_ND49 (0x1u << CAN_NDAT2_ND49_Pos) -#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */ -#define CAN_NDAT2_ND50 (0x1u << CAN_NDAT2_ND50_Pos) -#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */ -#define CAN_NDAT2_ND51 (0x1u << CAN_NDAT2_ND51_Pos) -#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */ -#define CAN_NDAT2_ND52 (0x1u << CAN_NDAT2_ND52_Pos) -#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */ -#define CAN_NDAT2_ND53 (0x1u << CAN_NDAT2_ND53_Pos) -#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */ -#define CAN_NDAT2_ND54 (0x1u << CAN_NDAT2_ND54_Pos) -#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */ -#define CAN_NDAT2_ND55 (0x1u << CAN_NDAT2_ND55_Pos) -#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */ -#define CAN_NDAT2_ND56 (0x1u << CAN_NDAT2_ND56_Pos) -#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */ -#define CAN_NDAT2_ND57 (0x1u << CAN_NDAT2_ND57_Pos) -#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */ -#define CAN_NDAT2_ND58 (0x1u << CAN_NDAT2_ND58_Pos) -#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */ -#define CAN_NDAT2_ND59 (0x1u << CAN_NDAT2_ND59_Pos) -#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */ -#define CAN_NDAT2_ND60 (0x1u << CAN_NDAT2_ND60_Pos) -#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */ -#define CAN_NDAT2_ND61 (0x1u << CAN_NDAT2_ND61_Pos) -#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */ -#define CAN_NDAT2_ND62 (0x1u << CAN_NDAT2_ND62_Pos) -#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */ -#define CAN_NDAT2_ND63 (0x1u << CAN_NDAT2_ND63_Pos) -#define CAN_NDAT2_MASK 0xFFFFFFFFu /**< \brief (CAN_NDAT2) MASK Register */ - -/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */ - uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */ - uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0C_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */ -#define CAN_RXF0C_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */ - -#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */ -#define CAN_RXF0C_F0SA_Msk (0xFFFFu << CAN_RXF0C_F0SA_Pos) -#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos)) -#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */ -#define CAN_RXF0C_F0S_Msk (0x7Fu << CAN_RXF0C_F0S_Pos) -#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos)) -#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */ -#define CAN_RXF0C_F0WM_Msk (0x7Fu << CAN_RXF0C_F0WM_Pos) -#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos)) -#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */ -#define CAN_RXF0C_F0OM (0x1u << CAN_RXF0C_F0OM_Pos) -#define CAN_RXF0C_MASK 0xFF7FFFFFu /**< \brief (CAN_RXF0C) MASK Register */ - -/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */ - uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0S_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */ -#define CAN_RXF0S_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */ - -#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */ -#define CAN_RXF0S_F0FL_Msk (0x7Fu << CAN_RXF0S_F0FL_Pos) -#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos)) -#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */ -#define CAN_RXF0S_F0GI_Msk (0x3Fu << CAN_RXF0S_F0GI_Pos) -#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos)) -#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */ -#define CAN_RXF0S_F0PI_Msk (0x3Fu << CAN_RXF0S_F0PI_Pos) -#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos)) -#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */ -#define CAN_RXF0S_F0F (0x1u << CAN_RXF0S_F0F_Pos) -#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */ -#define CAN_RXF0S_RF0L (0x1u << CAN_RXF0S_RF0L_Pos) -#define CAN_RXF0S_MASK 0x033F3F7Fu /**< \brief (CAN_RXF0S) MASK Register */ - -/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0A_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */ -#define CAN_RXF0A_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */ - -#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */ -#define CAN_RXF0A_F0AI_Msk (0x3Fu << CAN_RXF0A_F0AI_Pos) -#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos)) -#define CAN_RXF0A_MASK 0x0000003Fu /**< \brief (CAN_RXF0A) MASK Register */ - -/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */ - uint32_t :16; /*!< bit: 16..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */ -#define CAN_RXBC_RESETVALUE 0x00000000u /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */ - -#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */ -#define CAN_RXBC_RBSA_Msk (0xFFFFu << CAN_RXBC_RBSA_Pos) -#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos)) -#define CAN_RXBC_MASK 0x0000FFFFu /**< \brief (CAN_RXBC) MASK Register */ - -/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */ - uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */ - uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1C_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */ -#define CAN_RXF1C_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */ - -#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */ -#define CAN_RXF1C_F1SA_Msk (0xFFFFu << CAN_RXF1C_F1SA_Pos) -#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos)) -#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */ -#define CAN_RXF1C_F1S_Msk (0x7Fu << CAN_RXF1C_F1S_Pos) -#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos)) -#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */ -#define CAN_RXF1C_F1WM_Msk (0x7Fu << CAN_RXF1C_F1WM_Pos) -#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos)) -#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */ -#define CAN_RXF1C_F1OM (0x1u << CAN_RXF1C_F1OM_Pos) -#define CAN_RXF1C_MASK 0xFF7FFFFFu /**< \brief (CAN_RXF1C) MASK Register */ - -/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */ - uint32_t :2; /*!< bit: 14..15 Reserved */ - uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */ - uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */ - uint32_t :4; /*!< bit: 26..29 Reserved */ - uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1S_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */ -#define CAN_RXF1S_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */ - -#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */ -#define CAN_RXF1S_F1FL_Msk (0x7Fu << CAN_RXF1S_F1FL_Pos) -#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos)) -#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */ -#define CAN_RXF1S_F1GI_Msk (0x3Fu << CAN_RXF1S_F1GI_Pos) -#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos)) -#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */ -#define CAN_RXF1S_F1PI_Msk (0x3Fu << CAN_RXF1S_F1PI_Pos) -#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos)) -#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */ -#define CAN_RXF1S_F1F (0x1u << CAN_RXF1S_F1F_Pos) -#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */ -#define CAN_RXF1S_RF1L (0x1u << CAN_RXF1S_RF1L_Pos) -#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */ -#define CAN_RXF1S_DMS_Msk (0x3u << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos)) -#define CAN_RXF1S_DMS_IDLE_Val 0x0u /**< \brief (CAN_RXF1S) Idle state */ -#define CAN_RXF1S_DMS_DBGA_Val 0x1u /**< \brief (CAN_RXF1S) Debug message A received */ -#define CAN_RXF1S_DMS_DBGB_Val 0x2u /**< \brief (CAN_RXF1S) Debug message A/B received */ -#define CAN_RXF1S_DMS_DBGC_Val 0x3u /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */ -#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) -#define CAN_RXF1S_MASK 0xC33F3F7Fu /**< \brief (CAN_RXF1S) MASK Register */ - -/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1A_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */ -#define CAN_RXF1A_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */ - -#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */ -#define CAN_RXF1A_F1AI_Msk (0x3Fu << CAN_RXF1A_F1AI_Pos) -#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos)) -#define CAN_RXF1A_MASK 0x0000003Fu /**< \brief (CAN_RXF1A) MASK Register */ - -/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */ - uint32_t :21; /*!< bit: 11..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXESC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */ -#define CAN_RXESC_RESETVALUE 0x00000000u /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */ - -#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */ -#define CAN_RXESC_F0DS_Msk (0x7u << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos)) -#define CAN_RXESC_F0DS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_F0DS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_F0DS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_F0DS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_F0DS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_F0DS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_F0DS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_F0DS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) -#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */ -#define CAN_RXESC_F1DS_Msk (0x7u << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos)) -#define CAN_RXESC_F1DS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_F1DS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_F1DS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_F1DS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_F1DS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_F1DS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_F1DS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_F1DS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) -#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */ -#define CAN_RXESC_RBDS_Msk (0x7u << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos)) -#define CAN_RXESC_RBDS_DATA8_Val 0x0u /**< \brief (CAN_RXESC) 8 byte data field */ -#define CAN_RXESC_RBDS_DATA12_Val 0x1u /**< \brief (CAN_RXESC) 12 byte data field */ -#define CAN_RXESC_RBDS_DATA16_Val 0x2u /**< \brief (CAN_RXESC) 16 byte data field */ -#define CAN_RXESC_RBDS_DATA20_Val 0x3u /**< \brief (CAN_RXESC) 20 byte data field */ -#define CAN_RXESC_RBDS_DATA24_Val 0x4u /**< \brief (CAN_RXESC) 24 byte data field */ -#define CAN_RXESC_RBDS_DATA32_Val 0x5u /**< \brief (CAN_RXESC) 32 byte data field */ -#define CAN_RXESC_RBDS_DATA48_Val 0x6u /**< \brief (CAN_RXESC) 48 byte data field */ -#define CAN_RXESC_RBDS_DATA64_Val 0x7u /**< \brief (CAN_RXESC) 64 byte data field */ -#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) -#define CAN_RXESC_MASK 0x00000777u /**< \brief (CAN_RXESC) MASK Register */ - -/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */ - uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */ - uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */ - uint32_t :1; /*!< bit: 31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */ -#define CAN_TXBC_RESETVALUE 0x00000000u /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */ - -#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */ -#define CAN_TXBC_TBSA_Msk (0xFFFFu << CAN_TXBC_TBSA_Pos) -#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos)) -#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */ -#define CAN_TXBC_NDTB_Msk (0x3Fu << CAN_TXBC_NDTB_Pos) -#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos)) -#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */ -#define CAN_TXBC_TFQS_Msk (0x3Fu << CAN_TXBC_TFQS_Pos) -#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos)) -#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */ -#define CAN_TXBC_TFQM (0x1u << CAN_TXBC_TFQM_Pos) -#define CAN_TXBC_MASK 0x7F3FFFFFu /**< \brief (CAN_TXBC) MASK Register */ - -/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */ - uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */ - uint32_t :10; /*!< bit: 22..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXFQS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */ -#define CAN_TXFQS_RESETVALUE 0x00000000u /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */ - -#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */ -#define CAN_TXFQS_TFFL_Msk (0x3Fu << CAN_TXFQS_TFFL_Pos) -#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos)) -#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */ -#define CAN_TXFQS_TFGI_Msk (0x1Fu << CAN_TXFQS_TFGI_Pos) -#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos)) -#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */ -#define CAN_TXFQS_TFQPI_Msk (0x1Fu << CAN_TXFQS_TFQPI_Pos) -#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos)) -#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */ -#define CAN_TXFQS_TFQF (0x1u << CAN_TXFQS_TFQF_Pos) -#define CAN_TXFQS_MASK 0x003F1F3Fu /**< \brief (CAN_TXFQS) MASK Register */ - -/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */ - uint32_t :29; /*!< bit: 3..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXESC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */ -#define CAN_TXESC_RESETVALUE 0x00000000u /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */ - -#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */ -#define CAN_TXESC_TBDS_Msk (0x7u << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos)) -#define CAN_TXESC_TBDS_DATA8_Val 0x0u /**< \brief (CAN_TXESC) 8 byte data field */ -#define CAN_TXESC_TBDS_DATA12_Val 0x1u /**< \brief (CAN_TXESC) 12 byte data field */ -#define CAN_TXESC_TBDS_DATA16_Val 0x2u /**< \brief (CAN_TXESC) 16 byte data field */ -#define CAN_TXESC_TBDS_DATA20_Val 0x3u /**< \brief (CAN_TXESC) 20 byte data field */ -#define CAN_TXESC_TBDS_DATA24_Val 0x4u /**< \brief (CAN_TXESC) 24 byte data field */ -#define CAN_TXESC_TBDS_DATA32_Val 0x5u /**< \brief (CAN_TXESC) 32 byte data field */ -#define CAN_TXESC_TBDS_DATA48_Val 0x6u /**< \brief (CAN_TXESC) 48 byte data field */ -#define CAN_TXESC_TBDS_DATA64_Val 0x7u /**< \brief (CAN_TXESC) 64 byte data field */ -#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) -#define CAN_TXESC_MASK 0x00000007u /**< \brief (CAN_TXESC) MASK Register */ - -/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */ - uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */ - uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */ - uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */ - uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */ - uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */ - uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */ - uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */ - uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */ - uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */ - uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */ - uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */ - uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */ - uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */ - uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */ - uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */ - uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */ - uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */ - uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */ - uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */ - uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */ - uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */ - uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */ - uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */ - uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */ - uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */ - uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */ - uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */ - uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */ - uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */ - uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */ - uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBRP_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */ -#define CAN_TXBRP_RESETVALUE 0x00000000u /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */ - -#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */ -#define CAN_TXBRP_TRP0 (0x1u << CAN_TXBRP_TRP0_Pos) -#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */ -#define CAN_TXBRP_TRP1 (0x1u << CAN_TXBRP_TRP1_Pos) -#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */ -#define CAN_TXBRP_TRP2 (0x1u << CAN_TXBRP_TRP2_Pos) -#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */ -#define CAN_TXBRP_TRP3 (0x1u << CAN_TXBRP_TRP3_Pos) -#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */ -#define CAN_TXBRP_TRP4 (0x1u << CAN_TXBRP_TRP4_Pos) -#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */ -#define CAN_TXBRP_TRP5 (0x1u << CAN_TXBRP_TRP5_Pos) -#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */ -#define CAN_TXBRP_TRP6 (0x1u << CAN_TXBRP_TRP6_Pos) -#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */ -#define CAN_TXBRP_TRP7 (0x1u << CAN_TXBRP_TRP7_Pos) -#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */ -#define CAN_TXBRP_TRP8 (0x1u << CAN_TXBRP_TRP8_Pos) -#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */ -#define CAN_TXBRP_TRP9 (0x1u << CAN_TXBRP_TRP9_Pos) -#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */ -#define CAN_TXBRP_TRP10 (0x1u << CAN_TXBRP_TRP10_Pos) -#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */ -#define CAN_TXBRP_TRP11 (0x1u << CAN_TXBRP_TRP11_Pos) -#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */ -#define CAN_TXBRP_TRP12 (0x1u << CAN_TXBRP_TRP12_Pos) -#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */ -#define CAN_TXBRP_TRP13 (0x1u << CAN_TXBRP_TRP13_Pos) -#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */ -#define CAN_TXBRP_TRP14 (0x1u << CAN_TXBRP_TRP14_Pos) -#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */ -#define CAN_TXBRP_TRP15 (0x1u << CAN_TXBRP_TRP15_Pos) -#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */ -#define CAN_TXBRP_TRP16 (0x1u << CAN_TXBRP_TRP16_Pos) -#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */ -#define CAN_TXBRP_TRP17 (0x1u << CAN_TXBRP_TRP17_Pos) -#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */ -#define CAN_TXBRP_TRP18 (0x1u << CAN_TXBRP_TRP18_Pos) -#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */ -#define CAN_TXBRP_TRP19 (0x1u << CAN_TXBRP_TRP19_Pos) -#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */ -#define CAN_TXBRP_TRP20 (0x1u << CAN_TXBRP_TRP20_Pos) -#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */ -#define CAN_TXBRP_TRP21 (0x1u << CAN_TXBRP_TRP21_Pos) -#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */ -#define CAN_TXBRP_TRP22 (0x1u << CAN_TXBRP_TRP22_Pos) -#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */ -#define CAN_TXBRP_TRP23 (0x1u << CAN_TXBRP_TRP23_Pos) -#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */ -#define CAN_TXBRP_TRP24 (0x1u << CAN_TXBRP_TRP24_Pos) -#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */ -#define CAN_TXBRP_TRP25 (0x1u << CAN_TXBRP_TRP25_Pos) -#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */ -#define CAN_TXBRP_TRP26 (0x1u << CAN_TXBRP_TRP26_Pos) -#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */ -#define CAN_TXBRP_TRP27 (0x1u << CAN_TXBRP_TRP27_Pos) -#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */ -#define CAN_TXBRP_TRP28 (0x1u << CAN_TXBRP_TRP28_Pos) -#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */ -#define CAN_TXBRP_TRP29 (0x1u << CAN_TXBRP_TRP29_Pos) -#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */ -#define CAN_TXBRP_TRP30 (0x1u << CAN_TXBRP_TRP30_Pos) -#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */ -#define CAN_TXBRP_TRP31 (0x1u << CAN_TXBRP_TRP31_Pos) -#define CAN_TXBRP_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBRP) MASK Register */ - -/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t AR0:1; /*!< bit: 0 Add Request 0 */ - uint32_t AR1:1; /*!< bit: 1 Add Request 1 */ - uint32_t AR2:1; /*!< bit: 2 Add Request 2 */ - uint32_t AR3:1; /*!< bit: 3 Add Request 3 */ - uint32_t AR4:1; /*!< bit: 4 Add Request 4 */ - uint32_t AR5:1; /*!< bit: 5 Add Request 5 */ - uint32_t AR6:1; /*!< bit: 6 Add Request 6 */ - uint32_t AR7:1; /*!< bit: 7 Add Request 7 */ - uint32_t AR8:1; /*!< bit: 8 Add Request 8 */ - uint32_t AR9:1; /*!< bit: 9 Add Request 9 */ - uint32_t AR10:1; /*!< bit: 10 Add Request 10 */ - uint32_t AR11:1; /*!< bit: 11 Add Request 11 */ - uint32_t AR12:1; /*!< bit: 12 Add Request 12 */ - uint32_t AR13:1; /*!< bit: 13 Add Request 13 */ - uint32_t AR14:1; /*!< bit: 14 Add Request 14 */ - uint32_t AR15:1; /*!< bit: 15 Add Request 15 */ - uint32_t AR16:1; /*!< bit: 16 Add Request 16 */ - uint32_t AR17:1; /*!< bit: 17 Add Request 17 */ - uint32_t AR18:1; /*!< bit: 18 Add Request 18 */ - uint32_t AR19:1; /*!< bit: 19 Add Request 19 */ - uint32_t AR20:1; /*!< bit: 20 Add Request 20 */ - uint32_t AR21:1; /*!< bit: 21 Add Request 21 */ - uint32_t AR22:1; /*!< bit: 22 Add Request 22 */ - uint32_t AR23:1; /*!< bit: 23 Add Request 23 */ - uint32_t AR24:1; /*!< bit: 24 Add Request 24 */ - uint32_t AR25:1; /*!< bit: 25 Add Request 25 */ - uint32_t AR26:1; /*!< bit: 26 Add Request 26 */ - uint32_t AR27:1; /*!< bit: 27 Add Request 27 */ - uint32_t AR28:1; /*!< bit: 28 Add Request 28 */ - uint32_t AR29:1; /*!< bit: 29 Add Request 29 */ - uint32_t AR30:1; /*!< bit: 30 Add Request 30 */ - uint32_t AR31:1; /*!< bit: 31 Add Request 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBAR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */ -#define CAN_TXBAR_RESETVALUE 0x00000000u /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */ - -#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */ -#define CAN_TXBAR_AR0 (0x1u << CAN_TXBAR_AR0_Pos) -#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */ -#define CAN_TXBAR_AR1 (0x1u << CAN_TXBAR_AR1_Pos) -#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */ -#define CAN_TXBAR_AR2 (0x1u << CAN_TXBAR_AR2_Pos) -#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */ -#define CAN_TXBAR_AR3 (0x1u << CAN_TXBAR_AR3_Pos) -#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */ -#define CAN_TXBAR_AR4 (0x1u << CAN_TXBAR_AR4_Pos) -#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */ -#define CAN_TXBAR_AR5 (0x1u << CAN_TXBAR_AR5_Pos) -#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */ -#define CAN_TXBAR_AR6 (0x1u << CAN_TXBAR_AR6_Pos) -#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */ -#define CAN_TXBAR_AR7 (0x1u << CAN_TXBAR_AR7_Pos) -#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */ -#define CAN_TXBAR_AR8 (0x1u << CAN_TXBAR_AR8_Pos) -#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */ -#define CAN_TXBAR_AR9 (0x1u << CAN_TXBAR_AR9_Pos) -#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */ -#define CAN_TXBAR_AR10 (0x1u << CAN_TXBAR_AR10_Pos) -#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */ -#define CAN_TXBAR_AR11 (0x1u << CAN_TXBAR_AR11_Pos) -#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */ -#define CAN_TXBAR_AR12 (0x1u << CAN_TXBAR_AR12_Pos) -#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */ -#define CAN_TXBAR_AR13 (0x1u << CAN_TXBAR_AR13_Pos) -#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */ -#define CAN_TXBAR_AR14 (0x1u << CAN_TXBAR_AR14_Pos) -#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */ -#define CAN_TXBAR_AR15 (0x1u << CAN_TXBAR_AR15_Pos) -#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */ -#define CAN_TXBAR_AR16 (0x1u << CAN_TXBAR_AR16_Pos) -#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */ -#define CAN_TXBAR_AR17 (0x1u << CAN_TXBAR_AR17_Pos) -#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */ -#define CAN_TXBAR_AR18 (0x1u << CAN_TXBAR_AR18_Pos) -#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */ -#define CAN_TXBAR_AR19 (0x1u << CAN_TXBAR_AR19_Pos) -#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */ -#define CAN_TXBAR_AR20 (0x1u << CAN_TXBAR_AR20_Pos) -#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */ -#define CAN_TXBAR_AR21 (0x1u << CAN_TXBAR_AR21_Pos) -#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */ -#define CAN_TXBAR_AR22 (0x1u << CAN_TXBAR_AR22_Pos) -#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */ -#define CAN_TXBAR_AR23 (0x1u << CAN_TXBAR_AR23_Pos) -#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */ -#define CAN_TXBAR_AR24 (0x1u << CAN_TXBAR_AR24_Pos) -#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */ -#define CAN_TXBAR_AR25 (0x1u << CAN_TXBAR_AR25_Pos) -#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */ -#define CAN_TXBAR_AR26 (0x1u << CAN_TXBAR_AR26_Pos) -#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */ -#define CAN_TXBAR_AR27 (0x1u << CAN_TXBAR_AR27_Pos) -#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */ -#define CAN_TXBAR_AR28 (0x1u << CAN_TXBAR_AR28_Pos) -#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */ -#define CAN_TXBAR_AR29 (0x1u << CAN_TXBAR_AR29_Pos) -#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */ -#define CAN_TXBAR_AR30 (0x1u << CAN_TXBAR_AR30_Pos) -#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */ -#define CAN_TXBAR_AR31 (0x1u << CAN_TXBAR_AR31_Pos) -#define CAN_TXBAR_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBAR) MASK Register */ - -/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */ - uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */ - uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */ - uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */ - uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */ - uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */ - uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */ - uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */ - uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */ - uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */ - uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */ - uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */ - uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */ - uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */ - uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */ - uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */ - uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */ - uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */ - uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */ - uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */ - uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */ - uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */ - uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */ - uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */ - uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */ - uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */ - uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */ - uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */ - uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */ - uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */ - uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */ - uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBCR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */ -#define CAN_TXBCR_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */ - -#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */ -#define CAN_TXBCR_CR0 (0x1u << CAN_TXBCR_CR0_Pos) -#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */ -#define CAN_TXBCR_CR1 (0x1u << CAN_TXBCR_CR1_Pos) -#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */ -#define CAN_TXBCR_CR2 (0x1u << CAN_TXBCR_CR2_Pos) -#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */ -#define CAN_TXBCR_CR3 (0x1u << CAN_TXBCR_CR3_Pos) -#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */ -#define CAN_TXBCR_CR4 (0x1u << CAN_TXBCR_CR4_Pos) -#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */ -#define CAN_TXBCR_CR5 (0x1u << CAN_TXBCR_CR5_Pos) -#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */ -#define CAN_TXBCR_CR6 (0x1u << CAN_TXBCR_CR6_Pos) -#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */ -#define CAN_TXBCR_CR7 (0x1u << CAN_TXBCR_CR7_Pos) -#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */ -#define CAN_TXBCR_CR8 (0x1u << CAN_TXBCR_CR8_Pos) -#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */ -#define CAN_TXBCR_CR9 (0x1u << CAN_TXBCR_CR9_Pos) -#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */ -#define CAN_TXBCR_CR10 (0x1u << CAN_TXBCR_CR10_Pos) -#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */ -#define CAN_TXBCR_CR11 (0x1u << CAN_TXBCR_CR11_Pos) -#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */ -#define CAN_TXBCR_CR12 (0x1u << CAN_TXBCR_CR12_Pos) -#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */ -#define CAN_TXBCR_CR13 (0x1u << CAN_TXBCR_CR13_Pos) -#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */ -#define CAN_TXBCR_CR14 (0x1u << CAN_TXBCR_CR14_Pos) -#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */ -#define CAN_TXBCR_CR15 (0x1u << CAN_TXBCR_CR15_Pos) -#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */ -#define CAN_TXBCR_CR16 (0x1u << CAN_TXBCR_CR16_Pos) -#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */ -#define CAN_TXBCR_CR17 (0x1u << CAN_TXBCR_CR17_Pos) -#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */ -#define CAN_TXBCR_CR18 (0x1u << CAN_TXBCR_CR18_Pos) -#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */ -#define CAN_TXBCR_CR19 (0x1u << CAN_TXBCR_CR19_Pos) -#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */ -#define CAN_TXBCR_CR20 (0x1u << CAN_TXBCR_CR20_Pos) -#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */ -#define CAN_TXBCR_CR21 (0x1u << CAN_TXBCR_CR21_Pos) -#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */ -#define CAN_TXBCR_CR22 (0x1u << CAN_TXBCR_CR22_Pos) -#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */ -#define CAN_TXBCR_CR23 (0x1u << CAN_TXBCR_CR23_Pos) -#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */ -#define CAN_TXBCR_CR24 (0x1u << CAN_TXBCR_CR24_Pos) -#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */ -#define CAN_TXBCR_CR25 (0x1u << CAN_TXBCR_CR25_Pos) -#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */ -#define CAN_TXBCR_CR26 (0x1u << CAN_TXBCR_CR26_Pos) -#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */ -#define CAN_TXBCR_CR27 (0x1u << CAN_TXBCR_CR27_Pos) -#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */ -#define CAN_TXBCR_CR28 (0x1u << CAN_TXBCR_CR28_Pos) -#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */ -#define CAN_TXBCR_CR29 (0x1u << CAN_TXBCR_CR29_Pos) -#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */ -#define CAN_TXBCR_CR30 (0x1u << CAN_TXBCR_CR30_Pos) -#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */ -#define CAN_TXBCR_CR31 (0x1u << CAN_TXBCR_CR31_Pos) -#define CAN_TXBCR_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCR) MASK Register */ - -/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */ - uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */ - uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */ - uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */ - uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */ - uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */ - uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */ - uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */ - uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */ - uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */ - uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */ - uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */ - uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */ - uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */ - uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */ - uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */ - uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */ - uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */ - uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */ - uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */ - uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */ - uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */ - uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */ - uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */ - uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */ - uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */ - uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */ - uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */ - uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */ - uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */ - uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */ - uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBTO_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */ -#define CAN_TXBTO_RESETVALUE 0x00000000u /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */ - -#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */ -#define CAN_TXBTO_TO0 (0x1u << CAN_TXBTO_TO0_Pos) -#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */ -#define CAN_TXBTO_TO1 (0x1u << CAN_TXBTO_TO1_Pos) -#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */ -#define CAN_TXBTO_TO2 (0x1u << CAN_TXBTO_TO2_Pos) -#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */ -#define CAN_TXBTO_TO3 (0x1u << CAN_TXBTO_TO3_Pos) -#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */ -#define CAN_TXBTO_TO4 (0x1u << CAN_TXBTO_TO4_Pos) -#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */ -#define CAN_TXBTO_TO5 (0x1u << CAN_TXBTO_TO5_Pos) -#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */ -#define CAN_TXBTO_TO6 (0x1u << CAN_TXBTO_TO6_Pos) -#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */ -#define CAN_TXBTO_TO7 (0x1u << CAN_TXBTO_TO7_Pos) -#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */ -#define CAN_TXBTO_TO8 (0x1u << CAN_TXBTO_TO8_Pos) -#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */ -#define CAN_TXBTO_TO9 (0x1u << CAN_TXBTO_TO9_Pos) -#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */ -#define CAN_TXBTO_TO10 (0x1u << CAN_TXBTO_TO10_Pos) -#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */ -#define CAN_TXBTO_TO11 (0x1u << CAN_TXBTO_TO11_Pos) -#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */ -#define CAN_TXBTO_TO12 (0x1u << CAN_TXBTO_TO12_Pos) -#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */ -#define CAN_TXBTO_TO13 (0x1u << CAN_TXBTO_TO13_Pos) -#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */ -#define CAN_TXBTO_TO14 (0x1u << CAN_TXBTO_TO14_Pos) -#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */ -#define CAN_TXBTO_TO15 (0x1u << CAN_TXBTO_TO15_Pos) -#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */ -#define CAN_TXBTO_TO16 (0x1u << CAN_TXBTO_TO16_Pos) -#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */ -#define CAN_TXBTO_TO17 (0x1u << CAN_TXBTO_TO17_Pos) -#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */ -#define CAN_TXBTO_TO18 (0x1u << CAN_TXBTO_TO18_Pos) -#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */ -#define CAN_TXBTO_TO19 (0x1u << CAN_TXBTO_TO19_Pos) -#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */ -#define CAN_TXBTO_TO20 (0x1u << CAN_TXBTO_TO20_Pos) -#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */ -#define CAN_TXBTO_TO21 (0x1u << CAN_TXBTO_TO21_Pos) -#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */ -#define CAN_TXBTO_TO22 (0x1u << CAN_TXBTO_TO22_Pos) -#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */ -#define CAN_TXBTO_TO23 (0x1u << CAN_TXBTO_TO23_Pos) -#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */ -#define CAN_TXBTO_TO24 (0x1u << CAN_TXBTO_TO24_Pos) -#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */ -#define CAN_TXBTO_TO25 (0x1u << CAN_TXBTO_TO25_Pos) -#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */ -#define CAN_TXBTO_TO26 (0x1u << CAN_TXBTO_TO26_Pos) -#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */ -#define CAN_TXBTO_TO27 (0x1u << CAN_TXBTO_TO27_Pos) -#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */ -#define CAN_TXBTO_TO28 (0x1u << CAN_TXBTO_TO28_Pos) -#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */ -#define CAN_TXBTO_TO29 (0x1u << CAN_TXBTO_TO29_Pos) -#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */ -#define CAN_TXBTO_TO30 (0x1u << CAN_TXBTO_TO30_Pos) -#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */ -#define CAN_TXBTO_TO31 (0x1u << CAN_TXBTO_TO31_Pos) -#define CAN_TXBTO_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBTO) MASK Register */ - -/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */ - uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */ - uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */ - uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */ - uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */ - uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */ - uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */ - uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */ - uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */ - uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */ - uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */ - uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */ - uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */ - uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */ - uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */ - uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */ - uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */ - uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */ - uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */ - uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */ - uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */ - uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */ - uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */ - uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */ - uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */ - uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */ - uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */ - uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */ - uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */ - uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */ - uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */ - uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBCF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */ -#define CAN_TXBCF_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */ - -#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */ -#define CAN_TXBCF_CF0 (0x1u << CAN_TXBCF_CF0_Pos) -#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */ -#define CAN_TXBCF_CF1 (0x1u << CAN_TXBCF_CF1_Pos) -#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */ -#define CAN_TXBCF_CF2 (0x1u << CAN_TXBCF_CF2_Pos) -#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */ -#define CAN_TXBCF_CF3 (0x1u << CAN_TXBCF_CF3_Pos) -#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */ -#define CAN_TXBCF_CF4 (0x1u << CAN_TXBCF_CF4_Pos) -#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */ -#define CAN_TXBCF_CF5 (0x1u << CAN_TXBCF_CF5_Pos) -#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */ -#define CAN_TXBCF_CF6 (0x1u << CAN_TXBCF_CF6_Pos) -#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */ -#define CAN_TXBCF_CF7 (0x1u << CAN_TXBCF_CF7_Pos) -#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */ -#define CAN_TXBCF_CF8 (0x1u << CAN_TXBCF_CF8_Pos) -#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */ -#define CAN_TXBCF_CF9 (0x1u << CAN_TXBCF_CF9_Pos) -#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */ -#define CAN_TXBCF_CF10 (0x1u << CAN_TXBCF_CF10_Pos) -#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */ -#define CAN_TXBCF_CF11 (0x1u << CAN_TXBCF_CF11_Pos) -#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */ -#define CAN_TXBCF_CF12 (0x1u << CAN_TXBCF_CF12_Pos) -#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */ -#define CAN_TXBCF_CF13 (0x1u << CAN_TXBCF_CF13_Pos) -#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */ -#define CAN_TXBCF_CF14 (0x1u << CAN_TXBCF_CF14_Pos) -#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */ -#define CAN_TXBCF_CF15 (0x1u << CAN_TXBCF_CF15_Pos) -#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */ -#define CAN_TXBCF_CF16 (0x1u << CAN_TXBCF_CF16_Pos) -#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */ -#define CAN_TXBCF_CF17 (0x1u << CAN_TXBCF_CF17_Pos) -#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */ -#define CAN_TXBCF_CF18 (0x1u << CAN_TXBCF_CF18_Pos) -#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */ -#define CAN_TXBCF_CF19 (0x1u << CAN_TXBCF_CF19_Pos) -#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */ -#define CAN_TXBCF_CF20 (0x1u << CAN_TXBCF_CF20_Pos) -#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */ -#define CAN_TXBCF_CF21 (0x1u << CAN_TXBCF_CF21_Pos) -#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */ -#define CAN_TXBCF_CF22 (0x1u << CAN_TXBCF_CF22_Pos) -#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */ -#define CAN_TXBCF_CF23 (0x1u << CAN_TXBCF_CF23_Pos) -#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */ -#define CAN_TXBCF_CF24 (0x1u << CAN_TXBCF_CF24_Pos) -#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */ -#define CAN_TXBCF_CF25 (0x1u << CAN_TXBCF_CF25_Pos) -#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */ -#define CAN_TXBCF_CF26 (0x1u << CAN_TXBCF_CF26_Pos) -#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */ -#define CAN_TXBCF_CF27 (0x1u << CAN_TXBCF_CF27_Pos) -#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */ -#define CAN_TXBCF_CF28 (0x1u << CAN_TXBCF_CF28_Pos) -#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */ -#define CAN_TXBCF_CF29 (0x1u << CAN_TXBCF_CF29_Pos) -#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */ -#define CAN_TXBCF_CF30 (0x1u << CAN_TXBCF_CF30_Pos) -#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */ -#define CAN_TXBCF_CF31 (0x1u << CAN_TXBCF_CF31_Pos) -#define CAN_TXBCF_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCF) MASK Register */ - -/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */ - uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */ - uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */ - uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */ - uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */ - uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */ - uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */ - uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */ - uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */ - uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */ - uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */ - uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */ - uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */ - uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */ - uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */ - uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */ - uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */ - uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */ - uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */ - uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */ - uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */ - uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */ - uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */ - uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */ - uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */ - uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */ - uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */ - uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */ - uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */ - uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */ - uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */ - uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBTIE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */ -#define CAN_TXBTIE_RESETVALUE 0x00000000u /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */ - -#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */ -#define CAN_TXBTIE_TIE0 (0x1u << CAN_TXBTIE_TIE0_Pos) -#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */ -#define CAN_TXBTIE_TIE1 (0x1u << CAN_TXBTIE_TIE1_Pos) -#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */ -#define CAN_TXBTIE_TIE2 (0x1u << CAN_TXBTIE_TIE2_Pos) -#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */ -#define CAN_TXBTIE_TIE3 (0x1u << CAN_TXBTIE_TIE3_Pos) -#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */ -#define CAN_TXBTIE_TIE4 (0x1u << CAN_TXBTIE_TIE4_Pos) -#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */ -#define CAN_TXBTIE_TIE5 (0x1u << CAN_TXBTIE_TIE5_Pos) -#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */ -#define CAN_TXBTIE_TIE6 (0x1u << CAN_TXBTIE_TIE6_Pos) -#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */ -#define CAN_TXBTIE_TIE7 (0x1u << CAN_TXBTIE_TIE7_Pos) -#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */ -#define CAN_TXBTIE_TIE8 (0x1u << CAN_TXBTIE_TIE8_Pos) -#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */ -#define CAN_TXBTIE_TIE9 (0x1u << CAN_TXBTIE_TIE9_Pos) -#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */ -#define CAN_TXBTIE_TIE10 (0x1u << CAN_TXBTIE_TIE10_Pos) -#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */ -#define CAN_TXBTIE_TIE11 (0x1u << CAN_TXBTIE_TIE11_Pos) -#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */ -#define CAN_TXBTIE_TIE12 (0x1u << CAN_TXBTIE_TIE12_Pos) -#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */ -#define CAN_TXBTIE_TIE13 (0x1u << CAN_TXBTIE_TIE13_Pos) -#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */ -#define CAN_TXBTIE_TIE14 (0x1u << CAN_TXBTIE_TIE14_Pos) -#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */ -#define CAN_TXBTIE_TIE15 (0x1u << CAN_TXBTIE_TIE15_Pos) -#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */ -#define CAN_TXBTIE_TIE16 (0x1u << CAN_TXBTIE_TIE16_Pos) -#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */ -#define CAN_TXBTIE_TIE17 (0x1u << CAN_TXBTIE_TIE17_Pos) -#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */ -#define CAN_TXBTIE_TIE18 (0x1u << CAN_TXBTIE_TIE18_Pos) -#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */ -#define CAN_TXBTIE_TIE19 (0x1u << CAN_TXBTIE_TIE19_Pos) -#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */ -#define CAN_TXBTIE_TIE20 (0x1u << CAN_TXBTIE_TIE20_Pos) -#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */ -#define CAN_TXBTIE_TIE21 (0x1u << CAN_TXBTIE_TIE21_Pos) -#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */ -#define CAN_TXBTIE_TIE22 (0x1u << CAN_TXBTIE_TIE22_Pos) -#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */ -#define CAN_TXBTIE_TIE23 (0x1u << CAN_TXBTIE_TIE23_Pos) -#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */ -#define CAN_TXBTIE_TIE24 (0x1u << CAN_TXBTIE_TIE24_Pos) -#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */ -#define CAN_TXBTIE_TIE25 (0x1u << CAN_TXBTIE_TIE25_Pos) -#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */ -#define CAN_TXBTIE_TIE26 (0x1u << CAN_TXBTIE_TIE26_Pos) -#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */ -#define CAN_TXBTIE_TIE27 (0x1u << CAN_TXBTIE_TIE27_Pos) -#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */ -#define CAN_TXBTIE_TIE28 (0x1u << CAN_TXBTIE_TIE28_Pos) -#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */ -#define CAN_TXBTIE_TIE29 (0x1u << CAN_TXBTIE_TIE29_Pos) -#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */ -#define CAN_TXBTIE_TIE30 (0x1u << CAN_TXBTIE_TIE30_Pos) -#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */ -#define CAN_TXBTIE_TIE31 (0x1u << CAN_TXBTIE_TIE31_Pos) -#define CAN_TXBTIE_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBTIE) MASK Register */ - -/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */ - uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */ - uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */ - uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */ - uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */ - uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */ - uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */ - uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */ - uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */ - uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */ - uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */ - uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */ - uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */ - uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */ - uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */ - uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */ - uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */ - uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */ - uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */ - uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */ - uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */ - uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */ - uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */ - uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */ - uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */ - uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */ - uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */ - uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */ - uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */ - uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */ - uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */ - uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBCIE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */ -#define CAN_TXBCIE_RESETVALUE 0x00000000u /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */ - -#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */ -#define CAN_TXBCIE_CFIE0 (0x1u << CAN_TXBCIE_CFIE0_Pos) -#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */ -#define CAN_TXBCIE_CFIE1 (0x1u << CAN_TXBCIE_CFIE1_Pos) -#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */ -#define CAN_TXBCIE_CFIE2 (0x1u << CAN_TXBCIE_CFIE2_Pos) -#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */ -#define CAN_TXBCIE_CFIE3 (0x1u << CAN_TXBCIE_CFIE3_Pos) -#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */ -#define CAN_TXBCIE_CFIE4 (0x1u << CAN_TXBCIE_CFIE4_Pos) -#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */ -#define CAN_TXBCIE_CFIE5 (0x1u << CAN_TXBCIE_CFIE5_Pos) -#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */ -#define CAN_TXBCIE_CFIE6 (0x1u << CAN_TXBCIE_CFIE6_Pos) -#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */ -#define CAN_TXBCIE_CFIE7 (0x1u << CAN_TXBCIE_CFIE7_Pos) -#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */ -#define CAN_TXBCIE_CFIE8 (0x1u << CAN_TXBCIE_CFIE8_Pos) -#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */ -#define CAN_TXBCIE_CFIE9 (0x1u << CAN_TXBCIE_CFIE9_Pos) -#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */ -#define CAN_TXBCIE_CFIE10 (0x1u << CAN_TXBCIE_CFIE10_Pos) -#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */ -#define CAN_TXBCIE_CFIE11 (0x1u << CAN_TXBCIE_CFIE11_Pos) -#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */ -#define CAN_TXBCIE_CFIE12 (0x1u << CAN_TXBCIE_CFIE12_Pos) -#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */ -#define CAN_TXBCIE_CFIE13 (0x1u << CAN_TXBCIE_CFIE13_Pos) -#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */ -#define CAN_TXBCIE_CFIE14 (0x1u << CAN_TXBCIE_CFIE14_Pos) -#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */ -#define CAN_TXBCIE_CFIE15 (0x1u << CAN_TXBCIE_CFIE15_Pos) -#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */ -#define CAN_TXBCIE_CFIE16 (0x1u << CAN_TXBCIE_CFIE16_Pos) -#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */ -#define CAN_TXBCIE_CFIE17 (0x1u << CAN_TXBCIE_CFIE17_Pos) -#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */ -#define CAN_TXBCIE_CFIE18 (0x1u << CAN_TXBCIE_CFIE18_Pos) -#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */ -#define CAN_TXBCIE_CFIE19 (0x1u << CAN_TXBCIE_CFIE19_Pos) -#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */ -#define CAN_TXBCIE_CFIE20 (0x1u << CAN_TXBCIE_CFIE20_Pos) -#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */ -#define CAN_TXBCIE_CFIE21 (0x1u << CAN_TXBCIE_CFIE21_Pos) -#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */ -#define CAN_TXBCIE_CFIE22 (0x1u << CAN_TXBCIE_CFIE22_Pos) -#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */ -#define CAN_TXBCIE_CFIE23 (0x1u << CAN_TXBCIE_CFIE23_Pos) -#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */ -#define CAN_TXBCIE_CFIE24 (0x1u << CAN_TXBCIE_CFIE24_Pos) -#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */ -#define CAN_TXBCIE_CFIE25 (0x1u << CAN_TXBCIE_CFIE25_Pos) -#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */ -#define CAN_TXBCIE_CFIE26 (0x1u << CAN_TXBCIE_CFIE26_Pos) -#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */ -#define CAN_TXBCIE_CFIE27 (0x1u << CAN_TXBCIE_CFIE27_Pos) -#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */ -#define CAN_TXBCIE_CFIE28 (0x1u << CAN_TXBCIE_CFIE28_Pos) -#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */ -#define CAN_TXBCIE_CFIE29 (0x1u << CAN_TXBCIE_CFIE29_Pos) -#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */ -#define CAN_TXBCIE_CFIE30 (0x1u << CAN_TXBCIE_CFIE30_Pos) -#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */ -#define CAN_TXBCIE_CFIE31 (0x1u << CAN_TXBCIE_CFIE31_Pos) -#define CAN_TXBCIE_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBCIE) MASK Register */ - -/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */ - uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */ -#define CAN_TXEFC_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */ - -#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */ -#define CAN_TXEFC_EFSA_Msk (0xFFFFu << CAN_TXEFC_EFSA_Pos) -#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos)) -#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */ -#define CAN_TXEFC_EFS_Msk (0x3Fu << CAN_TXEFC_EFS_Pos) -#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos)) -#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */ -#define CAN_TXEFC_EFWM_Msk (0x3Fu << CAN_TXEFC_EFWM_Pos) -#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos)) -#define CAN_TXEFC_MASK 0x3F3FFFFFu /**< \brief (CAN_TXEFC) MASK Register */ - -/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */ - uint32_t :2; /*!< bit: 6.. 7 Reserved */ - uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */ - uint32_t :3; /*!< bit: 21..23 Reserved */ - uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */ - uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */ -#define CAN_TXEFS_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */ - -#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */ -#define CAN_TXEFS_EFFL_Msk (0x3Fu << CAN_TXEFS_EFFL_Pos) -#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos)) -#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */ -#define CAN_TXEFS_EFGI_Msk (0x1Fu << CAN_TXEFS_EFGI_Pos) -#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos)) -#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */ -#define CAN_TXEFS_EFPI_Msk (0x1Fu << CAN_TXEFS_EFPI_Pos) -#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos)) -#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */ -#define CAN_TXEFS_EFF (0x1u << CAN_TXEFS_EFF_Pos) -#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */ -#define CAN_TXEFS_TEFL (0x1u << CAN_TXEFS_TEFL_Pos) -#define CAN_TXEFS_MASK 0x031F1F3Fu /**< \brief (CAN_TXEFS) MASK Register */ - -/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */ -#define CAN_TXEFA_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */ - -#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */ -#define CAN_TXEFA_EFAI_Msk (0x1Fu << CAN_TXEFA_EFAI_Pos) -#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos)) -#define CAN_TXEFA_MASK 0x0000001Fu /**< \brief (CAN_TXEFA) MASK Register */ - -/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */ -#define CAN_RXBE_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */ - -#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */ -#define CAN_RXBE_0_ID_Msk (0x1FFFFFFFu << CAN_RXBE_0_ID_Pos) -#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos)) -#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */ -#define CAN_RXBE_0_RTR (0x1u << CAN_RXBE_0_RTR_Pos) -#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */ -#define CAN_RXBE_0_XTD (0x1u << CAN_RXBE_0_XTD_Pos) -#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */ -#define CAN_RXBE_0_ESI (0x1u << CAN_RXBE_0_ESI_Pos) -#define CAN_RXBE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXBE_0) MASK Register */ - -/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ - uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */ -#define CAN_RXBE_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */ - -#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */ -#define CAN_RXBE_1_RXTS_Msk (0xFFFFu << CAN_RXBE_1_RXTS_Pos) -#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos)) -#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */ -#define CAN_RXBE_1_DLC_Msk (0xFu << CAN_RXBE_1_DLC_Pos) -#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos)) -#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */ -#define CAN_RXBE_1_BRS (0x1u << CAN_RXBE_1_BRS_Pos) -#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */ -#define CAN_RXBE_1_FDF (0x1u << CAN_RXBE_1_FDF_Pos) -#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */ -#define CAN_RXBE_1_FIDX_Msk (0x7Fu << CAN_RXBE_1_FIDX_Pos) -#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos)) -#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */ -#define CAN_RXBE_1_ANMF (0x1u << CAN_RXBE_1_ANMF_Pos) -#define CAN_RXBE_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXBE_1) MASK Register */ - -/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXBE_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */ -#define CAN_RXBE_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */ - -#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */ -#define CAN_RXBE_DATA_DB0_Msk (0xFFu << CAN_RXBE_DATA_DB0_Pos) -#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos)) -#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */ -#define CAN_RXBE_DATA_DB1_Msk (0xFFu << CAN_RXBE_DATA_DB1_Pos) -#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos)) -#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */ -#define CAN_RXBE_DATA_DB2_Msk (0xFFu << CAN_RXBE_DATA_DB2_Pos) -#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos)) -#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */ -#define CAN_RXBE_DATA_DB3_Msk (0xFFu << CAN_RXBE_DATA_DB3_Pos) -#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos)) -#define CAN_RXBE_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXBE_DATA) MASK Register */ - -/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0E_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */ -#define CAN_RXF0E_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */ - -#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */ -#define CAN_RXF0E_0_ID_Msk (0x1FFFFFFFu << CAN_RXF0E_0_ID_Pos) -#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos)) -#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */ -#define CAN_RXF0E_0_RTR (0x1u << CAN_RXF0E_0_RTR_Pos) -#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */ -#define CAN_RXF0E_0_XTD (0x1u << CAN_RXF0E_0_XTD_Pos) -#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */ -#define CAN_RXF0E_0_ESI (0x1u << CAN_RXF0E_0_ESI_Pos) -#define CAN_RXF0E_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF0E_0) MASK Register */ - -/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ - uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0E_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */ -#define CAN_RXF0E_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */ - -#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */ -#define CAN_RXF0E_1_RXTS_Msk (0xFFFFu << CAN_RXF0E_1_RXTS_Pos) -#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos)) -#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */ -#define CAN_RXF0E_1_DLC_Msk (0xFu << CAN_RXF0E_1_DLC_Pos) -#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos)) -#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */ -#define CAN_RXF0E_1_BRS (0x1u << CAN_RXF0E_1_BRS_Pos) -#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */ -#define CAN_RXF0E_1_FDF (0x1u << CAN_RXF0E_1_FDF_Pos) -#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */ -#define CAN_RXF0E_1_FIDX_Msk (0x7Fu << CAN_RXF0E_1_FIDX_Pos) -#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos)) -#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */ -#define CAN_RXF0E_1_ANMF (0x1u << CAN_RXF0E_1_ANMF_Pos) -#define CAN_RXF0E_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXF0E_1) MASK Register */ - -/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF0E_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */ -#define CAN_RXF0E_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */ - -#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */ -#define CAN_RXF0E_DATA_DB0_Msk (0xFFu << CAN_RXF0E_DATA_DB0_Pos) -#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos)) -#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */ -#define CAN_RXF0E_DATA_DB1_Msk (0xFFu << CAN_RXF0E_DATA_DB1_Pos) -#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos)) -#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */ -#define CAN_RXF0E_DATA_DB2_Msk (0xFFu << CAN_RXF0E_DATA_DB2_Pos) -#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos)) -#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */ -#define CAN_RXF0E_DATA_DB3_Msk (0xFFu << CAN_RXF0E_DATA_DB3_Pos) -#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos)) -#define CAN_RXF0E_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF0E_DATA) MASK Register */ - -/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1E_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */ -#define CAN_RXF1E_0_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */ - -#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */ -#define CAN_RXF1E_0_ID_Msk (0x1FFFFFFFu << CAN_RXF1E_0_ID_Pos) -#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos)) -#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */ -#define CAN_RXF1E_0_RTR (0x1u << CAN_RXF1E_0_RTR_Pos) -#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */ -#define CAN_RXF1E_0_XTD (0x1u << CAN_RXF1E_0_XTD_Pos) -#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */ -#define CAN_RXF1E_0_ESI (0x1u << CAN_RXF1E_0_ESI_Pos) -#define CAN_RXF1E_0_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF1E_0) MASK Register */ - -/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ - uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1E_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */ -#define CAN_RXF1E_1_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */ - -#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */ -#define CAN_RXF1E_1_RXTS_Msk (0xFFFFu << CAN_RXF1E_1_RXTS_Pos) -#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos)) -#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */ -#define CAN_RXF1E_1_DLC_Msk (0xFu << CAN_RXF1E_1_DLC_Pos) -#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos)) -#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */ -#define CAN_RXF1E_1_BRS (0x1u << CAN_RXF1E_1_BRS_Pos) -#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */ -#define CAN_RXF1E_1_FDF (0x1u << CAN_RXF1E_1_FDF_Pos) -#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */ -#define CAN_RXF1E_1_FIDX_Msk (0x7Fu << CAN_RXF1E_1_FIDX_Pos) -#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos)) -#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */ -#define CAN_RXF1E_1_ANMF (0x1u << CAN_RXF1E_1_ANMF_Pos) -#define CAN_RXF1E_1_MASK 0xFF3FFFFFu /**< \brief (CAN_RXF1E_1) MASK Register */ - -/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_RXF1E_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */ -#define CAN_RXF1E_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */ - -#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */ -#define CAN_RXF1E_DATA_DB0_Msk (0xFFu << CAN_RXF1E_DATA_DB0_Pos) -#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos)) -#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */ -#define CAN_RXF1E_DATA_DB1_Msk (0xFFu << CAN_RXF1E_DATA_DB1_Pos) -#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos)) -#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */ -#define CAN_RXF1E_DATA_DB2_Msk (0xFFu << CAN_RXF1E_DATA_DB2_Pos) -#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos)) -#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */ -#define CAN_RXF1E_DATA_DB3_Msk (0xFFu << CAN_RXF1E_DATA_DB3_Pos) -#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos)) -#define CAN_RXF1E_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_RXF1E_DATA) MASK Register */ - -/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */ - uint32_t :5; /*!< bit: 11..15 Reserved */ - uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */ - uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */ - uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_SIDFE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */ -#define CAN_SIDFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */ - -#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */ -#define CAN_SIDFE_0_SFID2_Msk (0x7FFu << CAN_SIDFE_0_SFID2_Pos) -#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos)) -#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */ -#define CAN_SIDFE_0_SFID1_Msk (0x7FFu << CAN_SIDFE_0_SFID1_Pos) -#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos)) -#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */ -#define CAN_SIDFE_0_SFEC_Msk (0x7u << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos)) -#define CAN_SIDFE_0_SFEC_DISABLE_Val 0x0u /**< \brief (CAN_SIDFE_0) Disable filter element */ -#define CAN_SIDFE_0_SFEC_STF0M_Val 0x1u /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ -#define CAN_SIDFE_0_SFEC_STF1M_Val 0x2u /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ -#define CAN_SIDFE_0_SFEC_REJECT_Val 0x3u /**< \brief (CAN_SIDFE_0) Reject ID if filter match */ -#define CAN_SIDFE_0_SFEC_PRIORITY_Val 0x4u /**< \brief (CAN_SIDFE_0) Set priority if filter match */ -#define CAN_SIDFE_0_SFEC_PRIF0M_Val 0x5u /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ -#define CAN_SIDFE_0_SFEC_PRIF1M_Val 0x6u /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ -#define CAN_SIDFE_0_SFEC_STRXBUF_Val 0x7u /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */ -#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) -#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */ -#define CAN_SIDFE_0_SFT_Msk (0x3u << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos)) -#define CAN_SIDFE_0_SFT_RANGE_Val 0x0u /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ -#define CAN_SIDFE_0_SFT_DUAL_Val 0x1u /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ -#define CAN_SIDFE_0_SFT_CLASSIC_Val 0x2u /**< \brief (CAN_SIDFE_0) Classic filter */ -#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) -#define CAN_SIDFE_0_MASK 0xFFFF07FFu /**< \brief (CAN_SIDFE_0) MASK Register */ - -/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */ -#define CAN_TXBE_0_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */ - -#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */ -#define CAN_TXBE_0_ID_Msk (0x1FFFFFFFu << CAN_TXBE_0_ID_Pos) -#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos)) -#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */ -#define CAN_TXBE_0_RTR (0x1u << CAN_TXBE_0_RTR_Pos) -#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */ -#define CAN_TXBE_0_XTD (0x1u << CAN_TXBE_0_XTD_Pos) -#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */ -#define CAN_TXBE_0_ESI (0x1u << CAN_TXBE_0_ESI_Pos) -#define CAN_TXBE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBE_0) MASK Register */ - -/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :16; /*!< bit: 0..15 Reserved */ - uint32_t DLC:4; /*!< bit: 16..19 Identifier */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t :1; /*!< bit: 22 Reserved */ - uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */ - uint32_t MM:8; /*!< bit: 24..31 Message Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */ -#define CAN_TXBE_1_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */ - -#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */ -#define CAN_TXBE_1_DLC_Msk (0xFu << CAN_TXBE_1_DLC_Pos) -#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos)) -#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */ -#define CAN_TXBE_1_BRS (0x1u << CAN_TXBE_1_BRS_Pos) -#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */ -#define CAN_TXBE_1_FDF (0x1u << CAN_TXBE_1_FDF_Pos) -#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */ -#define CAN_TXBE_1_EFC (0x1u << CAN_TXBE_1_EFC_Pos) -#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */ -#define CAN_TXBE_1_MM_Msk (0xFFu << CAN_TXBE_1_MM_Pos) -#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos)) -#define CAN_TXBE_1_MASK 0xFFBF0000u /**< \brief (CAN_TXBE_1) MASK Register */ - -/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ - uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ - uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ - uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXBE_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */ -#define CAN_TXBE_DATA_RESETVALUE 0x00000000u /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */ - -#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */ -#define CAN_TXBE_DATA_DB0_Msk (0xFFu << CAN_TXBE_DATA_DB0_Pos) -#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos)) -#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */ -#define CAN_TXBE_DATA_DB1_Msk (0xFFu << CAN_TXBE_DATA_DB1_Pos) -#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos)) -#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */ -#define CAN_TXBE_DATA_DB2_Msk (0xFFu << CAN_TXBE_DATA_DB2_Pos) -#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos)) -#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */ -#define CAN_TXBE_DATA_DB3_Msk (0xFFu << CAN_TXBE_DATA_DB3_Pos) -#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos)) -#define CAN_TXBE_DATA_MASK 0xFFFFFFFFu /**< \brief (CAN_TXBE_DATA) MASK Register */ - -/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ID:29; /*!< bit: 0..28 Identifier */ - uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ - uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */ - uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */ -#define CAN_TXEFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */ - -#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */ -#define CAN_TXEFE_0_ID_Msk (0x1FFFFFFFu << CAN_TXEFE_0_ID_Pos) -#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos)) -#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */ -#define CAN_TXEFE_0_RTR (0x1u << CAN_TXEFE_0_RTR_Pos) -#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */ -#define CAN_TXEFE_0_XTD (0x1u << CAN_TXEFE_0_XTD_Pos) -#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */ -#define CAN_TXEFE_0_ESI (0x1u << CAN_TXEFE_0_ESI_Pos) -#define CAN_TXEFE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_TXEFE_0) MASK Register */ - -/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */ - uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ - uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ - uint32_t FDF:1; /*!< bit: 21 FD Format */ - uint32_t ET:2; /*!< bit: 22..23 Event Type */ - uint32_t MM:8; /*!< bit: 24..31 Message Marker */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_TXEFE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */ -#define CAN_TXEFE_1_RESETVALUE 0x00000000u /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */ - -#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */ -#define CAN_TXEFE_1_TXTS_Msk (0xFFFFu << CAN_TXEFE_1_TXTS_Pos) -#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos)) -#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */ -#define CAN_TXEFE_1_DLC_Msk (0xFu << CAN_TXEFE_1_DLC_Pos) -#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos)) -#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */ -#define CAN_TXEFE_1_BRS (0x1u << CAN_TXEFE_1_BRS_Pos) -#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */ -#define CAN_TXEFE_1_FDF (0x1u << CAN_TXEFE_1_FDF_Pos) -#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */ -#define CAN_TXEFE_1_ET_Msk (0x3u << CAN_TXEFE_1_ET_Pos) -#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos)) -#define CAN_TXEFE_1_ET_TXE_Val 0x1u /**< \brief (CAN_TXEFE_1) Tx event */ -#define CAN_TXEFE_1_ET_TXC_Val 0x2u /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */ -#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) -#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) -#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */ -#define CAN_TXEFE_1_MM_Msk (0xFFu << CAN_TXEFE_1_MM_Pos) -#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos)) -#define CAN_TXEFE_1_MASK 0xFFFFFFFFu /**< \brief (CAN_TXEFE_1) MASK Register */ - -/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */ - uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDFE_0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */ -#define CAN_XIDFE_0_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */ - -#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */ -#define CAN_XIDFE_0_EFID1_Msk (0x1FFFFFFFu << CAN_XIDFE_0_EFID1_Pos) -#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos)) -#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */ -#define CAN_XIDFE_0_EFEC_Msk (0x7u << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos)) -#define CAN_XIDFE_0_EFEC_DISABLE_Val 0x0u /**< \brief (CAN_XIDFE_0) Disable filter element */ -#define CAN_XIDFE_0_EFEC_STF0M_Val 0x1u /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ -#define CAN_XIDFE_0_EFEC_STF1M_Val 0x2u /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ -#define CAN_XIDFE_0_EFEC_REJECT_Val 0x3u /**< \brief (CAN_XIDFE_0) Reject ID if filter match */ -#define CAN_XIDFE_0_EFEC_PRIORITY_Val 0x4u /**< \brief (CAN_XIDFE_0) Set priority if filter match */ -#define CAN_XIDFE_0_EFEC_PRIF0M_Val 0x5u /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ -#define CAN_XIDFE_0_EFEC_PRIF1M_Val 0x6u /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ -#define CAN_XIDFE_0_EFEC_STRXBUF_Val 0x7u /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */ -#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) -#define CAN_XIDFE_0_MASK 0xFFFFFFFFu /**< \brief (CAN_XIDFE_0) MASK Register */ - -/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */ - uint32_t :1; /*!< bit: 29 Reserved */ - uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CAN_XIDFE_1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */ -#define CAN_XIDFE_1_RESETVALUE 0x00000000u /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */ - -#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */ -#define CAN_XIDFE_1_EFID2_Msk (0x1FFFFFFFu << CAN_XIDFE_1_EFID2_Pos) -#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos)) -#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */ -#define CAN_XIDFE_1_EFT_Msk (0x3u << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos)) -#define CAN_XIDFE_1_EFT_RANGEM_Val 0x0u /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ -#define CAN_XIDFE_1_EFT_DUAL_Val 0x1u /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ -#define CAN_XIDFE_1_EFT_CLASSIC_Val 0x2u /**< \brief (CAN_XIDFE_1) Classic filter */ -#define CAN_XIDFE_1_EFT_RANGE_Val 0x3u /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ -#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) -#define CAN_XIDFE_1_MASK 0xDFFFFFFFu /**< \brief (CAN_XIDFE_1) MASK Register */ - -/** \brief CAN APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */ - __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */ - __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */ - __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ - __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */ - __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */ - __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */ - __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ - __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ - __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */ - __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */ - __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */ - RoReg8 Reserved1[0x10]; - __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */ - __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */ - __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ - RoReg8 Reserved2[0x4]; - __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */ - __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */ - __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */ - __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */ - RoReg8 Reserved3[0x20]; - __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */ - __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ - __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ - RoReg8 Reserved4[0x4]; - __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */ - __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */ - __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */ - __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */ - __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ - __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ - __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ - __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */ - __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ - __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ - __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ - __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ - __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ - __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ - __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ - __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ - __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ - __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ - __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ - __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ - __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ - __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ - RoReg8 Reserved5[0x8]; - __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ - __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ - __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ -} Can; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_rxbe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ - __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ - __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */ -} CanMramRxbe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_rxf0e hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ - __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ - __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ -} CanMramRxf0e -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_rxf1e hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ - __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ - __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ -} CanMramRxf1e -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_sidfe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */ -} CanMramSidfe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_txbe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ - __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ - __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */ -} CanMramTxbe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_txefe hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ - __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ -} CanMramTxefe -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/** \brief CAN Mram_xifde hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ - __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ -} CanMramXifde -#ifdef __GNUC__ - __attribute__ ((aligned (4))) -#endif -; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define SECTION_CAN_MRAM_RXBE - -#define SECTION_CAN_MRAM_RXF0E - -#define SECTION_CAN_MRAM_RXF1E - -#define SECTION_CAN_MRAM_SIDFE - -#define SECTION_CAN_MRAM_TXBE - -#define SECTION_CAN_MRAM_TXEFE - -#define SECTION_CAN_MRAM_XIFDE - -/*@}*/ - -#endif /* _SAMD51_CAN_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/ccl.h b/atmel-samd/asf4/samd51/include/component/ccl.h deleted file mode 100644 index 890e81edf..000000000 --- a/atmel-samd/asf4/samd51/include/component/ccl.h +++ /dev/null @@ -1,228 +0,0 @@ -/** - * \file - * - * \brief Component description for CCL - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_CCL_COMPONENT_ -#define _SAMD51_CCL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CCL */ -/* ========================================================================== */ -/** \addtogroup SAMD51_CCL Configurable Custom Logic */ -/*@{*/ - -#define CCL_U2225 -#define REV_CCL 0x110 - -/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ -#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ - -#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ -#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) -#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ -#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) -#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */ -#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) -#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ - -/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ -#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ - -#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ -#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) -#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ -#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ -#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ -#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ -#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ -#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ - -/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ - uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ - uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ - uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ - uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */ - uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */ - uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CCL_LUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ -#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ - -#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ -#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) -#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ -#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) -#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ -#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ -#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ -#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ -#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) -#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ -#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) -#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ -#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) -#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ -#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) -#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */ -#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) -#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */ -#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) -#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */ -#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) -#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ -#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) -#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) -#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ - -/** \brief CCL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ - RoReg8 Reserved2[0x2]; - __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ -} Ccl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_CCL_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/cmcc.h b/atmel-samd/asf4/samd51/include/component/cmcc.h deleted file mode 100644 index 92fa6813e..000000000 --- a/atmel-samd/asf4/samd51/include/component/cmcc.h +++ /dev/null @@ -1,357 +0,0 @@ -/** - * \file - * - * \brief Component description for CMCC - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_CMCC_COMPONENT_ -#define _SAMD51_CMCC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CMCC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_CMCC Cortex M Cache Controller */ -/*@{*/ - -#define CMCC_U2015 -#define REV_CMCC 0x600 - -/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */ - uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */ - uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */ - uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */ - uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */ - uint32_t :18; /*!< bit: 14..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_TYPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */ -#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ - -#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */ -#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos) -#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */ -#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos) -#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */ -#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) -#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ -#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ -#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ -#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */ -#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) -#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */ -#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) -#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */ -#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) -#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ - -/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */ - uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_CFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */ -#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ - -#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */ -#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos) -#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */ -#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos) -#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */ -#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ - -/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */ -#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ - -#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */ -#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos) -#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ - -/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_SR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */ -#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ - -#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */ -#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) -#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */ - -/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_LCKWAY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */ -#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ - -#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */ -#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) -#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) -#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ - -/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MAINT0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */ -#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ - -#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */ -#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) -#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ - -/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */ - uint32_t :16; /*!< bit: 12..27 Reserved */ - uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MAINT1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */ -#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ - -#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */ -#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) -#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) -#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */ -#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) -#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ - -/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */ -#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ - -#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ -#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) -#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */ -#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ -#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */ -#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ - -/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */ -#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ - -#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ -#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos) -#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ - -/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */ -#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ - -#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */ -#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) -#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ - -/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MSR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */ -#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ - -#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */ -#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) -#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) -#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ - -/** \brief CMCC APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */ - __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */ - __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */ - __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */ - __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */ - RoReg8 Reserved1[0xC]; - __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ - __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ - __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ - __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ - __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */ - __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */ -} Cmcc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_CMCC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/dac.h b/atmel-samd/asf4/samd51/include/component/dac.h deleted file mode 100644 index c67efda30..000000000 --- a/atmel-samd/asf4/samd51/include/component/dac.h +++ /dev/null @@ -1,544 +0,0 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_DAC_COMPONENT_ -#define _SAMD51_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_DAC Digital-to-Analog Converter */ -/*@{*/ - -#define DAC_U2502 -#define REV_DAC 0x100 - -/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ -#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ - uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ -#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos) -#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ -#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ -#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */ -#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ -#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ -#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ - uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ - uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ - uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ - uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ - uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ - uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */ - uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ - uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ - uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ - uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ -#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos) -#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ -#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos) -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ -#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) -#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ -#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos) -#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ -#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ -#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) -#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ -#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos) -#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ -#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos) -#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ -#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) -#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) -#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */ -#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos) -#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */ -#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos) -#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */ -#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) -#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) -#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ - uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ - uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ - uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ - uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos) -#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos) -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) -#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos) -#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos) -#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) -#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos) -#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos) -#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) -#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) -#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos) -#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos) -#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) -#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) -#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ - uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ - uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ - uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ - uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos) -#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos) -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) -#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos) -#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos) -#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) -#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos) -#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos) -#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) -#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) -#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */ -#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos) -#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */ -#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos) -#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */ -#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) -#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) -#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */ - __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */ - __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ - __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ - __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */ - __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */ - __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */ - __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */ - __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ - __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */ - __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */ -#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos) -#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */ -#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos) -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */ -#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) -#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ -#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos) -#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ -#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos) -#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ -#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) -#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */ -#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos) -#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */ -#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos) -#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */ -#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) -#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) -#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */ -#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos) -#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */ -#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos) -#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */ -#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) -#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) -#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ - uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ - uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ - uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ - uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ -#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos) -#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ -#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos) -#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ -#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) -#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) -#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ -#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos) -#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ -#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos) -#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ -#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) -#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) -#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ - uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ - uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ - uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ - uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ - uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DAC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ -#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ - -#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ -#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) -#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ -#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) -#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ -#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos) -#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ -#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos) -#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ -#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) -#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) -#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ -#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos) -#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ -#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos) -#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ -#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) -#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) -#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ - -/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ - uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ - uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ - uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ - uint16_t :1; /*!< bit: 12 Reserved */ - uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DACCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ -#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ - -#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ -#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) -#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ -#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) -#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ -#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) -#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ -#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ -#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ -#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */ -#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) -#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ -#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) -#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ -#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) -#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ -#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) -#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) -#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */ -#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) -#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) -#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ - -/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ -#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ - -#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ -#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) -#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) -#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ - -/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATABUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ -#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ - -#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ -#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) -#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) -#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ - -/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ -#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ - -#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ -#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) -#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ - -/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */ -#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ - -#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */ -#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) -#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) -#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ - -/** \brief DAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ - __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ - RoReg8 Reserved1[0x1]; - __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ - __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ - __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ - __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ - __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x3]; - __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */ -} Dac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_DAC_COMPONENT_ */ diff --git a/atmel-samd/asf4/samd51/include/component/dmac.h b/atmel-samd/asf4/samd51/include/component/dmac.h deleted file mode 100644 index 295b31fe4..000000000 --- a/atmel-samd/asf4/samd51/include/component/dmac.h +++ /dev/null @@ -1,1416 +0,0 @@ -/** - * \file - * - * \brief Component description for DMAC - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_DMAC_COMPONENT_ -#define _SAMD51_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2503 -#define REV_DMAC 0x100 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t :6; /*!< bit: 2.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) -#define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) -#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */ -#define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos)) -#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */ -#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */ -#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */ -#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) -#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) -#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t CRCERR:1; /*!< bit: 2 CRC Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */ -#define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos) -#define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ - uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ - uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ - uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ - uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */ - uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */ - uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */ - uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */ - uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */ - uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */ - uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */ - uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */ - uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */ - uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */ - uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */ - uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */ - uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */ - uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */ - uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */ - uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) -#define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */ - uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */ - uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */ - uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */ - uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) -#define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */ -#define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos)) -#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) -#define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */ -#define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos)) -#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) -#define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */ -#define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos)) -#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) -#define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */ -#define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos)) -#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t CRCERR:1; /*!< bit: 12 CRC Error */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */ -#define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ - uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ - uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ - uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ - uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */ - uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */ - uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */ - uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */ - uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */ - uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */ - uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */ - uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */ - uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */ - uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */ - uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */ - uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */ - uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */ - uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */ - uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */ - uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos) -#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos) -#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos) -#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos) -#define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos) -#define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos) -#define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos) -#define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos) -#define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos) -#define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos) -#define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos) -#define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos) -#define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos) -#define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos) -#define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos) -#define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos) -#define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos) -#define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos) -#define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos) -#define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) -#define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ - uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ - uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ - uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ - uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */ - uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */ - uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */ - uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */ - uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */ - uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */ - uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */ - uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */ - uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */ - uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */ - uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */ - uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */ - uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */ - uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */ - uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */ - uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ -#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos) -#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ -#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos) -#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ -#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos) -#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ -#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos) -#define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */ -#define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos) -#define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */ -#define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos) -#define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */ -#define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos) -#define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */ -#define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos) -#define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */ -#define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos) -#define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */ -#define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos) -#define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */ -#define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos) -#define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */ -#define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos) -#define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */ -#define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos) -#define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */ -#define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos) -#define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */ -#define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos) -#define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */ -#define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos) -#define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */ -#define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos) -#define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */ -#define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos) -#define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */ -#define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos) -#define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */ -#define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) -#define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ - uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ - uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ - uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ - uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */ - uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */ - uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */ - uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */ - uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */ - uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */ - uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */ - uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */ - uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */ - uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */ - uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */ - uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */ - uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */ - uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */ - uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */ - uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ -#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos) -#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ -#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos) -#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ -#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos) -#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ -#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos) -#define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */ -#define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos) -#define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */ -#define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos) -#define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */ -#define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos) -#define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */ -#define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos) -#define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */ -#define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos) -#define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */ -#define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos) -#define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */ -#define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos) -#define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */ -#define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos) -#define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */ -#define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos) -#define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */ -#define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos) -#define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */ -#define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos) -#define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */ -#define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos) -#define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */ -#define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos) -#define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */ -#define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos) -#define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */ -#define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos) -#define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */ -#define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) -#define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) -#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) -#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) -#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint32_t :4; /*!< bit: 2.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */ - uint32_t :5; /*!< bit: 15..19 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */ - uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */ -#define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */ -#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) -#define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */ -#define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos) -#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos)) -#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */ -#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos) -#define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */ -#define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos)) -#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */ -#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */ -#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */ -#define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */ -#define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos)) -#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */ -#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */ -#define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos)) -#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */ -#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */ -#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */ - -#define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) -#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHPRILVL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */ -#define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */ - -#define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */ -#define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos)) -#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */ -#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */ -#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */ -#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */ -#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */ -#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */ -#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */ -#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */ -#define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */ - -/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */ - uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */ - uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHEVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */ -#define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */ - -#define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */ -#define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos)) -#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */ -#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */ -#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */ -#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */ -#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */ -#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */ -#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */ -#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */ -#define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */ -#define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos)) -#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */ -#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */ -#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */ -#define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos) -#define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */ -#define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos) -#define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ -#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */ -#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ -#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */ -#define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos) -#define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */ -#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< 8 bits, 1 -> 16 bits -#define USB_EPNUM 8 // parameter for rtl : max of ENDPOINT and PIPE NUM -#define USB_EPT_NUM 8 // Number of USB end points -#define USB_GCLK_ID 10 // Index of Generic Clock -#define USB_INITIAL_CONTROL_QOS 3 // CONTROL QOS RESET value -#define USB_INITIAL_DATA_QOS 3 // DATA QOS RESET value -#define USB_MISSING_SOF_DET_IMPLEMENTED 1 // 48 mHz xPLL feature implemented -#define USB_PIPE_NUM 8 // Number of USB pipes -#define USB_SYSTEM_CLOCK_IS_CKUSB 0 // Dual (1'b0) or Single (1'b1) clock system -#define USB_USB_2_AHB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...) -#define USB_USB_2_AHB_RD_DATA_BITS 16 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode -#define USB_USB_2_AHB_RD_THRESHOLD 2 // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested -#define USB_USB_2_AHB_WR_DATA_BITS 8 // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode - -#endif /* _SAMD51_USB_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd51/include/instance/wdt.h b/atmel-samd/asf4/samd51/include/instance/wdt.h deleted file mode 100644 index 98a2ca13d..000000000 --- a/atmel-samd/asf4/samd51/include/instance/wdt.h +++ /dev/null @@ -1,55 +0,0 @@ -/** - * \file - * - * \brief Instance description for WDT - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_WDT_INSTANCE_ -#define _SAMD51_WDT_INSTANCE_ - -/* ========== Register definition for WDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ -#else -#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAMD51_WDT_INSTANCE_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51g18a.h b/atmel-samd/asf4/samd51/include/pio/samd51g18a.h deleted file mode 100644 index 109c04ba5..000000000 --- a/atmel-samd/asf4/samd51/include/pio/samd51g18a.h +++ /dev/null @@ -1,1360 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51G18A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51G18A_PIO_ -#define _SAMD51G18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ -#define MUX_PA27H_TAL_BRK _L_(7) -#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) -#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) - -#endif /* _SAMD51G18A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51g19a.h b/atmel-samd/asf4/samd51/include/pio/samd51g19a.h deleted file mode 100644 index 86babdbe7..000000000 --- a/atmel-samd/asf4/samd51/include/pio/samd51g19a.h +++ /dev/null @@ -1,1360 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51G19A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51G19A_PIO_ -#define _SAMD51G19A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ -#define MUX_PA27H_TAL_BRK _L_(7) -#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) -#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) - -#endif /* _SAMD51G19A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51j18a.h b/atmel-samd/asf4/samd51/include/pio/samd51j18a.h deleted file mode 100644 index d8fa56d5b..000000000 --- a/atmel-samd/asf4/samd51/include/pio/samd51j18a.h +++ /dev/null @@ -1,1863 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51J18A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J18A_PIO_ -#define _SAMD51J18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ -#define MUX_PA27H_TAL_BRK _L_(7) -#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) -#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) -#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ -#define MUX_PB31H_TAL_BRK _L_(7) -#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) -#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) - -#endif /* _SAMD51J18A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51j19a.h b/atmel-samd/asf4/samd51/include/pio/samd51j19a.h deleted file mode 100644 index d5a76b4e3..000000000 --- a/atmel-samd/asf4/samd51/include/pio/samd51j19a.h +++ /dev/null @@ -1,1863 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51J19A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J19A_PIO_ -#define _SAMD51J19A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ -#define MUX_PA27H_TAL_BRK _L_(7) -#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) -#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) -#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ -#define MUX_PB31H_TAL_BRK _L_(7) -#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) -#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) - -#endif /* _SAMD51J19A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51j20a.h b/atmel-samd/asf4/samd51/include/pio/samd51j20a.h deleted file mode 100644 index 59828db2a..000000000 --- a/atmel-samd/asf4/samd51/include/pio/samd51j20a.h +++ /dev/null @@ -1,1863 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51J20A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J20A_PIO_ -#define _SAMD51J20A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ -#define MUX_PA27H_TAL_BRK _L_(7) -#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) -#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) -#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ -#define MUX_PB31H_TAL_BRK _L_(7) -#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) -#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) - -#endif /* _SAMD51J20A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51n19a.h b/atmel-samd/asf4/samd51/include/pio/samd51n19a.h deleted file mode 100644 index 265f482eb..000000000 --- a/atmel-samd/asf4/samd51/include/pio/samd51n19a.h +++ /dev/null @@ -1,2570 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51N19A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51N19A_PIO_ -#define _SAMD51N19A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ -#define MUX_PA27H_TAL_BRK _L_(7) -#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) -#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) -#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ -#define MUX_PB31H_TAL_BRK _L_(7) -#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) -#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAMD51N19A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51n20a.h b/atmel-samd/asf4/samd51/include/pio/samd51n20a.h deleted file mode 100644 index 6f3a1d63c..000000000 --- a/atmel-samd/asf4/samd51/include/pio/samd51n20a.h +++ /dev/null @@ -1,2570 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51N20A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51N20A_PIO_ -#define _SAMD51N20A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ -#define MUX_PA27H_TAL_BRK _L_(7) -#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) -#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) -#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ -#define MUX_PB31H_TAL_BRK _L_(7) -#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) -#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAMD51N20A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51p19a.h b/atmel-samd/asf4/samd51/include/pio/samd51p19a.h deleted file mode 100644 index 82cae824d..000000000 --- a/atmel-samd/asf4/samd51/include/pio/samd51p19a.h +++ /dev/null @@ -1,2884 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51P19A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51P19A_PIO_ -#define _SAMD51P19A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ -#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ -#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ -#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ -#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ -#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ -#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ -#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ -#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ -#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ -#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ -#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ -#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ -#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ -#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ -#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ -#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ -#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ -#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ -#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ -#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ -#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ -#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ -#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ -#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ -#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ -#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ -#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ -#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ -#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ -#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ -#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ -#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ -#define MUX_PD00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) -#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ -#define MUX_PD01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) -#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ -#define MUX_PD08A_EIC_EXTINT3 _L_(0) -#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) -#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) -#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ -#define MUX_PC04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) -#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ -#define MUX_PD09A_EIC_EXTINT4 _L_(0) -#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) -#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) -#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ -#define MUX_PD10A_EIC_EXTINT5 _L_(0) -#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) -#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) -#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ -#define MUX_PC22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) -#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ -#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ -#define MUX_PD11A_EIC_EXTINT6 _L_(0) -#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) -#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) -#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ -#define MUX_PC23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) -#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ -#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ -#define MUX_PD12A_EIC_EXTINT7 _L_(0) -#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) -#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) -#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ -#define MUX_PD20A_EIC_EXTINT10 _L_(0) -#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) -#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) -#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ -#define MUX_PD21A_EIC_EXTINT11 _L_(0) -#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) -#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) -#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ -#define MUX_PB26A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) -#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) -#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ -#define MUX_PB27A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) -#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) -#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ -#define MUX_PB28A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) -#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) -#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ -#define MUX_PC30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) -#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ -#define MUX_PB29A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) -#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) -#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ -#define MUX_PC31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) -#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ -#define MUX_PC22C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) -#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ -#define MUX_PC23C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) -#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ -#define MUX_PD20C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) -#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ -#define MUX_PD21C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) -#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ -#define MUX_PB26C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) -#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ -#define MUX_PB27C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) -#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ -#define MUX_PB28C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) -#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ -#define MUX_PB29C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) -#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ -#define MUX_PC23D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) -#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ -#define MUX_PC22D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) -#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ -#define MUX_PD20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) -#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ -#define MUX_PD21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) -#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ -#define MUX_PC04F_TCC0_WO0 _L_(5) -#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) -#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ -#define MUX_PD08F_TCC0_WO1 _L_(5) -#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) -#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ -#define MUX_PD09F_TCC0_WO2 _L_(5) -#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) -#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ -#define MUX_PD10F_TCC0_WO3 _L_(5) -#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) -#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ -#define MUX_PD11F_TCC0_WO4 _L_(5) -#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) -#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ -#define MUX_PD12F_TCC0_WO5 _L_(5) -#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) -#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ -#define MUX_PC22F_TCC0_WO6 _L_(5) -#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) -#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ -#define MUX_PC23F_TCC0_WO7 _L_(5) -#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) -#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ -#define MUX_PD20F_TCC1_WO0 _L_(5) -#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) -#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ -#define MUX_PD21F_TCC1_WO1 _L_(5) -#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) -#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ -#define MUX_PB26F_TCC1_WO2 _L_(5) -#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) -#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ -#define MUX_PB27F_TCC1_WO3 _L_(5) -#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) -#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ -#define MUX_PB28F_TCC1_WO4 _L_(5) -#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) -#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ -#define MUX_PB29F_TCC1_WO5 _L_(5) -#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) -#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ -#define MUX_PA27H_TAL_BRK _L_(7) -#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) -#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) -#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ -#define MUX_PB31H_TAL_BRK _L_(7) -#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) -#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ -#define MUX_PB27D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) -#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ -#define MUX_PB26D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) -#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ -#define MUX_PB28D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) -#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ -#define MUX_PB29D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) -#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ -#define MUX_PD09D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) -#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ -#define MUX_PC04C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) -#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ -#define MUX_PD08D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) -#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ -#define MUX_PD10D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) -#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ -#define MUX_PD11D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) -#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ -#define MUX_PD08C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) -#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ -#define MUX_PD09C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) -#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ -#define MUX_PD10C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) -#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ -#define MUX_PD11C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) -#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ -#define MUX_PC30B_ADC1_AIN12 _L_(1) -#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) -#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) -#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ -#define MUX_PC31B_ADC1_AIN13 _L_(1) -#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) -#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) -#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ -#define MUX_PD00B_ADC1_AIN14 _L_(1) -#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) -#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) -#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ -#define MUX_PD01B_ADC1_AIN15 _L_(1) -#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) -#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ -#define MUX_PB29J_I2S_MCK1 _L_(9) -#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) -#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ -#define MUX_PB28J_I2S_SCK1 _L_(9) -#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) -#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ -#define MUX_PD20I_SDHC1_SDCD _L_(8) -#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) -#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) -#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ -#define MUX_PD21I_SDHC1_SDWP _L_(8) -#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) -#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAMD51P19A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/pio/samd51p20a.h b/atmel-samd/asf4/samd51/include/pio/samd51p20a.h deleted file mode 100644 index 6e1477e46..000000000 --- a/atmel-samd/asf4/samd51/include/pio/samd51p20a.h +++ /dev/null @@ -1,2884 +0,0 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51P20A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51P20A_PIO_ -#define _SAMD51P20A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ -#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ -#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ -#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ -#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ -#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ -#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ -#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ -#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ -#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ -#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ -#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ -#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ -#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ -#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ -#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ -#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ -#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ -#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ -#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ -#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ -#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ -#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ -#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ -#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ -#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ -#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ -#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ -#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ -#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ -#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ -#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ -#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ -#define MUX_PD00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) -#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ -#define MUX_PD01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) -#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ -#define MUX_PD08A_EIC_EXTINT3 _L_(0) -#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) -#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) -#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ -#define MUX_PC04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) -#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ -#define MUX_PD09A_EIC_EXTINT4 _L_(0) -#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) -#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) -#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ -#define MUX_PD10A_EIC_EXTINT5 _L_(0) -#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) -#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) -#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ -#define MUX_PC22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) -#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ -#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ -#define MUX_PD11A_EIC_EXTINT6 _L_(0) -#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) -#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) -#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ -#define MUX_PC23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) -#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ -#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ -#define MUX_PD12A_EIC_EXTINT7 _L_(0) -#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) -#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) -#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ -#define MUX_PD20A_EIC_EXTINT10 _L_(0) -#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) -#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) -#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ -#define MUX_PD21A_EIC_EXTINT11 _L_(0) -#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) -#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) -#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ -#define MUX_PB26A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) -#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) -#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ -#define MUX_PB27A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) -#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) -#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ -#define MUX_PB28A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) -#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) -#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ -#define MUX_PC30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) -#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ -#define MUX_PB29A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) -#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) -#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ -#define MUX_PC31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) -#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ -#define MUX_PC22C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) -#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ -#define MUX_PC23C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) -#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ -#define MUX_PD20C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) -#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ -#define MUX_PD21C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) -#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ -#define MUX_PB26C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) -#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ -#define MUX_PB27C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) -#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ -#define MUX_PB28C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) -#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ -#define MUX_PB29C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) -#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ -#define MUX_PC23D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) -#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ -#define MUX_PC22D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) -#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ -#define MUX_PD20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) -#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ -#define MUX_PD21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) -#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ -#define MUX_PC04F_TCC0_WO0 _L_(5) -#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) -#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ -#define MUX_PD08F_TCC0_WO1 _L_(5) -#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) -#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ -#define MUX_PD09F_TCC0_WO2 _L_(5) -#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) -#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ -#define MUX_PD10F_TCC0_WO3 _L_(5) -#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) -#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ -#define MUX_PD11F_TCC0_WO4 _L_(5) -#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) -#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ -#define MUX_PD12F_TCC0_WO5 _L_(5) -#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) -#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ -#define MUX_PC22F_TCC0_WO6 _L_(5) -#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) -#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ -#define MUX_PC23F_TCC0_WO7 _L_(5) -#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) -#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ -#define MUX_PD20F_TCC1_WO0 _L_(5) -#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) -#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ -#define MUX_PD21F_TCC1_WO1 _L_(5) -#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) -#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ -#define MUX_PB26F_TCC1_WO2 _L_(5) -#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) -#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ -#define MUX_PB27F_TCC1_WO3 _L_(5) -#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) -#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ -#define MUX_PB28F_TCC1_WO4 _L_(5) -#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) -#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ -#define MUX_PB29F_TCC1_WO5 _L_(5) -#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) -#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TAL peripheral ========== */ -#define PIN_PA27H_TAL_BRK _L_(27) /**< \brief TAL signal: BRK on PA27 mux H */ -#define MUX_PA27H_TAL_BRK _L_(7) -#define PINMUX_PA27H_TAL_BRK ((PIN_PA27H_TAL_BRK << 16) | MUX_PA27H_TAL_BRK) -#define PORT_PA27H_TAL_BRK (_UL_(1) << 27) -#define PIN_PB31H_TAL_BRK _L_(63) /**< \brief TAL signal: BRK on PB31 mux H */ -#define MUX_PB31H_TAL_BRK _L_(7) -#define PINMUX_PB31H_TAL_BRK ((PIN_PB31H_TAL_BRK << 16) | MUX_PB31H_TAL_BRK) -#define PORT_PB31H_TAL_BRK (_UL_(1) << 31) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ -#define MUX_PB27D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) -#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ -#define MUX_PB26D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) -#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ -#define MUX_PB28D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) -#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ -#define MUX_PB29D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) -#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ -#define MUX_PD09D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) -#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ -#define MUX_PC04C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) -#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ -#define MUX_PD08D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) -#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ -#define MUX_PD10D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) -#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ -#define MUX_PD11D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) -#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ -#define MUX_PD08C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) -#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ -#define MUX_PD09C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) -#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ -#define MUX_PD10C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) -#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ -#define MUX_PD11C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) -#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ -#define MUX_PC30B_ADC1_AIN12 _L_(1) -#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) -#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) -#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ -#define MUX_PC31B_ADC1_AIN13 _L_(1) -#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) -#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) -#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ -#define MUX_PD00B_ADC1_AIN14 _L_(1) -#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) -#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) -#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ -#define MUX_PD01B_ADC1_AIN15 _L_(1) -#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) -#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ -#define MUX_PB29J_I2S_MCK1 _L_(9) -#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) -#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ -#define MUX_PB28J_I2S_SCK1 _L_(9) -#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) -#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ -#define MUX_PD20I_SDHC1_SDCD _L_(8) -#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) -#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) -#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ -#define MUX_PD21I_SDHC1_SDWP _L_(8) -#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) -#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAMD51P20A_PIO_ */ diff --git a/atmel-samd/asf4/samd51/include/sam.h b/atmel-samd/asf4/samd51/include/sam.h deleted file mode 100644 index 092538e10..000000000 --- a/atmel-samd/asf4/samd51/include/sam.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * \file - * - * \brief Top level header file - * - * Copyright (c) 2017 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _SAM_ -#define _SAM_ - -#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__) -#include "samd51g18a.h" -#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__) -#include "samd51g19a.h" -#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__) -#include "samd51j18a.h" -#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__) -#include "samd51j19a.h" -#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__) -#include "samd51j20a.h" -#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__) -#include "samd51n19a.h" -#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__) -#include "samd51n20a.h" -#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__) -#include "samd51p19a.h" -#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__) -#include "samd51p20a.h" -#else -#error Library does not support the specified device -#endif - -#endif /* _SAM_ */ diff --git a/atmel-samd/asf4/samd51/include/samd51.h b/atmel-samd/asf4/samd51/include/samd51.h deleted file mode 100644 index d08ac64cb..000000000 --- a/atmel-samd/asf4/samd51/include/samd51.h +++ /dev/null @@ -1,60 +0,0 @@ -/** - * \file - * - * \brief Top header file for SAMD51 - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_ -#define _SAMD51_ - -/** - * \defgroup SAMD51_definitions SAMD51 Device Definitions - * \brief SAMD51 CMSIS Definitions. - */ - -#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__) - #include "samd51g18a.h" -#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__) - #include "samd51g19a.h" -#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__) - #include "samd51j18a.h" -#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__) - #include "samd51j19a.h" -#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__) - #include "samd51j20a.h" -#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__) - #include "samd51n19a.h" -#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__) - #include "samd51n20a.h" -#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__) - #include "samd51p19a.h" -#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__) - #include "samd51p20a.h" -#else - #error Library does not support the specified device. -#endif - -#endif /* _SAMD51_ */ diff --git a/atmel-samd/asf4/samd51/include/samd51g18a.h b/atmel-samd/asf4/samd51/include/samd51g18a.h deleted file mode 100644 index 3be17b543..000000000 --- a/atmel-samd/asf4/samd51/include/samd51g18a.h +++ /dev/null @@ -1,1037 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD51G18A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51G18A_ -#define _SAMD51G18A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51G18A_definitions SAMD51G18A definitions - * This file defines all structures and symbols for SAMD51G18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMD51G18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD51G18A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51G18A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51G18A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51G18A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51G18A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51G18A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51G18A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51G18A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51G18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51G18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51G18A Peripheral Access Controller (PAC) */ - TAL_0_IRQn = 42, /**< 42 SAMD51G18A Trigger Allocator (TAL): TAL_BRK */ - TAL_1_IRQn = 43, /**< 43 SAMD51G18A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ - RAMECC_IRQn = 45, /**< 45 SAMD51G18A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51G18A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51G18A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51G18A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51G18A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TC0_IRQn = 107, /**< 107 SAMD51G18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51G18A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51G18A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51G18A Basic Timer Counter 3 (TC3) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51G18A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51G18A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51G18A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51G18A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51G18A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - PCC_IRQn = 129, /**< 129 SAMD51G18A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51G18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51G18A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51G18A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51G18A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51G18A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51G18A SD/MMC Host Controller 0 (SDHC0) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ - void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pvReserved70; - void* pvReserved71; - void* pvReserved72; - void* pvReserved73; - void* pvReserved74; - void* pvReserved75; - void* pvReserved76; - void* pvReserved77; - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pvReserved101; - void* pvReserved102; - void* pvReserved103; - void* pvReserved104; - void* pvReserved105; - void* pvReserved106; - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pvReserved111; - void* pvReserved112; - void* pvReserved113; - void* pvReserved114; - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pvReserved128; - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pvReserved136; -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void TAL_0_Handler ( void ); -void TAL_1_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -//#define LITTLE_ENDIAN 1 -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ - -#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51g18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060008) -#define ADC0_TOUCH_LINES_NUM 22 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51G18A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51g19a.h b/atmel-samd/asf4/samd51/include/samd51g19a.h deleted file mode 100644 index cc236e8da..000000000 --- a/atmel-samd/asf4/samd51/include/samd51g19a.h +++ /dev/null @@ -1,1037 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD51G19A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51G19A_ -#define _SAMD51G19A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51G19A_definitions SAMD51G19A definitions - * This file defines all structures and symbols for SAMD51G19A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMD51G19A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD51G19A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51G19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51G19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51G19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51G19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51G19A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51G19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51G19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51G19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51G19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51G19A Peripheral Access Controller (PAC) */ - TAL_0_IRQn = 42, /**< 42 SAMD51G19A Trigger Allocator (TAL): TAL_BRK */ - TAL_1_IRQn = 43, /**< 43 SAMD51G19A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ - RAMECC_IRQn = 45, /**< 45 SAMD51G19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51G19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51G19A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51G19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51G19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TC0_IRQn = 107, /**< 107 SAMD51G19A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51G19A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51G19A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51G19A Basic Timer Counter 3 (TC3) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51G19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51G19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51G19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51G19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51G19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - PCC_IRQn = 129, /**< 129 SAMD51G19A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51G19A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51G19A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51G19A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51G19A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51G19A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51G19A SD/MMC Host Controller 0 (SDHC0) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ - void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pvReserved70; - void* pvReserved71; - void* pvReserved72; - void* pvReserved73; - void* pvReserved74; - void* pvReserved75; - void* pvReserved76; - void* pvReserved77; - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pvReserved101; - void* pvReserved102; - void* pvReserved103; - void* pvReserved104; - void* pvReserved105; - void* pvReserved106; - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pvReserved111; - void* pvReserved112; - void* pvReserved113; - void* pvReserved114; - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pvReserved128; - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pvReserved136; -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void TAL_0_Handler ( void ); -void TAL_1_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -//#define LITTLE_ENDIAN 1 -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ - -#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51g19a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ -#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060007) -#define ADC0_TOUCH_LINES_NUM 22 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51G19A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51j18a.h b/atmel-samd/asf4/samd51/include/samd51j18a.h deleted file mode 100644 index a4ea15596..000000000 --- a/atmel-samd/asf4/samd51/include/samd51j18a.h +++ /dev/null @@ -1,1079 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD51J18A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J18A_ -#define _SAMD51J18A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51J18A_definitions SAMD51J18A definitions - * This file defines all structures and symbols for SAMD51J18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMD51J18A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD51J18A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51J18A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J18A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51J18A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51J18A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51J18A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51J18A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51J18A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51J18A Peripheral Access Controller (PAC) */ - TAL_0_IRQn = 42, /**< 42 SAMD51J18A Trigger Allocator (TAL): TAL_BRK */ - TAL_1_IRQn = 43, /**< 43 SAMD51J18A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ - RAMECC_IRQn = 45, /**< 45 SAMD51J18A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51J18A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51J18A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51J18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51J18A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51J18A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51J18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51J18A Basic Timer Counter 5 (TC5) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51J18A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51J18A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51J18A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51J18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51J18A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51J18A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51J18A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51J18A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51J18A SD/MMC Host Controller 0 (SDHC0) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ - void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pvReserved70; - void* pvReserved71; - void* pvReserved72; - void* pvReserved73; - void* pvReserved74; - void* pvReserved75; - void* pvReserved76; - void* pvReserved77; - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pvReserved113; - void* pvReserved114; - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pvReserved136; -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void TAL_0_Handler ( void ); -void TAL_1_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -//#define LITTLE_ENDIAN 1 -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ - -#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51j18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060006) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51J18A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51j19a.h b/atmel-samd/asf4/samd51/include/samd51j19a.h deleted file mode 100644 index c7fae83e1..000000000 --- a/atmel-samd/asf4/samd51/include/samd51j19a.h +++ /dev/null @@ -1,1079 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD51J19A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J19A_ -#define _SAMD51J19A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51J19A_definitions SAMD51J19A definitions - * This file defines all structures and symbols for SAMD51J19A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMD51J19A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD51J19A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51J19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51J19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51J19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51J19A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51J19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51J19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51J19A Peripheral Access Controller (PAC) */ - TAL_0_IRQn = 42, /**< 42 SAMD51J19A Trigger Allocator (TAL): TAL_BRK */ - TAL_1_IRQn = 43, /**< 43 SAMD51J19A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ - RAMECC_IRQn = 45, /**< 45 SAMD51J19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51J19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51J19A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51J19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51J19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51J19A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51J19A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51J19A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51J19A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51J19A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51J19A Basic Timer Counter 5 (TC5) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51J19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51J19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51J19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51J19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51J19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51J19A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51J19A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51J19A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51J19A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51J19A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51J19A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51J19A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51J19A SD/MMC Host Controller 0 (SDHC0) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ - void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pvReserved70; - void* pvReserved71; - void* pvReserved72; - void* pvReserved73; - void* pvReserved74; - void* pvReserved75; - void* pvReserved76; - void* pvReserved77; - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pvReserved113; - void* pvReserved114; - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pvReserved136; -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void TAL_0_Handler ( void ); -void TAL_1_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -//#define LITTLE_ENDIAN 1 -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ - -#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51j19a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ -#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060005) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51J19A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51j20a.h b/atmel-samd/asf4/samd51/include/samd51j20a.h deleted file mode 100644 index ea57a4172..000000000 --- a/atmel-samd/asf4/samd51/include/samd51j20a.h +++ /dev/null @@ -1,1079 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD51J20A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J20A_ -#define _SAMD51J20A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51J20A_definitions SAMD51J20A definitions - * This file defines all structures and symbols for SAMD51J20A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMD51J20A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD51J20A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51J20A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J20A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51J20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51J20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51J20A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51J20A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51J20A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51J20A Peripheral Access Controller (PAC) */ - TAL_0_IRQn = 42, /**< 42 SAMD51J20A Trigger Allocator (TAL): TAL_BRK */ - TAL_1_IRQn = 43, /**< 43 SAMD51J20A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ - RAMECC_IRQn = 45, /**< 45 SAMD51J20A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51J20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51J20A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51J20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51J20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51J20A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51J20A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51J20A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51J20A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51J20A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51J20A Basic Timer Counter 5 (TC5) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51J20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51J20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51J20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51J20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51J20A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51J20A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51J20A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51J20A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51J20A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51J20A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51J20A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51J20A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51J20A SD/MMC Host Controller 0 (SDHC0) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ - void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pvReserved70; - void* pvReserved71; - void* pvReserved72; - void* pvReserved73; - void* pvReserved74; - void* pvReserved75; - void* pvReserved76; - void* pvReserved77; - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pvReserved113; - void* pvReserved114; - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pvReserved136; -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void TAL_0_Handler ( void ); -void TAL_1_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -//#define LITTLE_ENDIAN 1 -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ - -#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51j20a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060004) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51J20A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51n19a.h b/atmel-samd/asf4/samd51/include/samd51n19a.h deleted file mode 100644 index 08d4f1296..000000000 --- a/atmel-samd/asf4/samd51/include/samd51n19a.h +++ /dev/null @@ -1,1121 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD51N19A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51N19A_ -#define _SAMD51N19A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51N19A_definitions SAMD51N19A definitions - * This file defines all structures and symbols for SAMD51N19A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMD51N19A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD51N19A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51N19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51N19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51N19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51N19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51N19A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51N19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51N19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51N19A Peripheral Access Controller (PAC) */ - TAL_0_IRQn = 42, /**< 42 SAMD51N19A Trigger Allocator (TAL): TAL_BRK */ - TAL_1_IRQn = 43, /**< 43 SAMD51N19A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ - RAMECC_IRQn = 45, /**< 45 SAMD51N19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51N19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51N19A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51N19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51N19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51N19A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51N19A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51N19A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51N19A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51N19A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51N19A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAMD51N19A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAMD51N19A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51N19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51N19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51N19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51N19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51N19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51N19A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51N19A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51N19A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51N19A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51N19A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51N19A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51N19A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51N19A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAMD51N19A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ - void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void TAL_0_Handler ( void ); -void TAL_1_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -//#define LITTLE_ENDIAN 1 -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51n19a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ -#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060003) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 3 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51N19A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51n20a.h b/atmel-samd/asf4/samd51/include/samd51n20a.h deleted file mode 100644 index 9947b773a..000000000 --- a/atmel-samd/asf4/samd51/include/samd51n20a.h +++ /dev/null @@ -1,1121 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD51N20A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51N20A_ -#define _SAMD51N20A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51N20A_definitions SAMD51N20A definitions - * This file defines all structures and symbols for SAMD51N20A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMD51N20A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD51N20A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51N20A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51N20A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51N20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51N20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51N20A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51N20A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51N20A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51N20A Peripheral Access Controller (PAC) */ - TAL_0_IRQn = 42, /**< 42 SAMD51N20A Trigger Allocator (TAL): TAL_BRK */ - TAL_1_IRQn = 43, /**< 43 SAMD51N20A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ - RAMECC_IRQn = 45, /**< 45 SAMD51N20A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51N20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51N20A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51N20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51N20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51N20A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51N20A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51N20A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51N20A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51N20A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51N20A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAMD51N20A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAMD51N20A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51N20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51N20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51N20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51N20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51N20A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51N20A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51N20A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51N20A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51N20A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51N20A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51N20A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51N20A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51N20A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAMD51N20A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ - void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void TAL_0_Handler ( void ); -void TAL_1_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -//#define LITTLE_ENDIAN 1 -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51n20a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060002) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 3 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51N20A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51p19a.h b/atmel-samd/asf4/samd51/include/samd51p19a.h deleted file mode 100644 index 97b776c7d..000000000 --- a/atmel-samd/asf4/samd51/include/samd51p19a.h +++ /dev/null @@ -1,1121 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD51P19A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51P19A_ -#define _SAMD51P19A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51P19A_definitions SAMD51P19A definitions - * This file defines all structures and symbols for SAMD51P19A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMD51P19A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD51P19A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51P19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51P19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51P19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51P19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51P19A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51P19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51P19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51P19A Peripheral Access Controller (PAC) */ - TAL_0_IRQn = 42, /**< 42 SAMD51P19A Trigger Allocator (TAL): TAL_BRK */ - TAL_1_IRQn = 43, /**< 43 SAMD51P19A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ - RAMECC_IRQn = 45, /**< 45 SAMD51P19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51P19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51P19A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51P19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51P19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51P19A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51P19A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51P19A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51P19A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51P19A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51P19A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAMD51P19A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAMD51P19A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51P19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51P19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51P19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51P19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51P19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51P19A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51P19A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51P19A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51P19A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51P19A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51P19A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51P19A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51P19A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAMD51P19A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ - void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void TAL_0_Handler ( void ); -void TAL_1_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -//#define LITTLE_ENDIAN 1 -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51p19a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ -#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060001) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 4 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51P19A_H */ diff --git a/atmel-samd/asf4/samd51/include/samd51p20a.h b/atmel-samd/asf4/samd51/include/samd51p20a.h deleted file mode 100644 index 9b19e2aa4..000000000 --- a/atmel-samd/asf4/samd51/include/samd51p20a.h +++ /dev/null @@ -1,1121 +0,0 @@ -/** - * \file - * - * \brief Header file for SAMD51P20A - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51P20A_ -#define _SAMD51P20A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51P20A_definitions SAMD51P20A definitions - * This file defines all structures and symbols for SAMD51P20A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers ******************************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Cortex-M4 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ - /****** SAMD51P20A-specific Interrupt Numbers ***********************/ - PM_IRQn = 0, /**< 0 SAMD51P20A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51P20A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51P20A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51P20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51P20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51P20A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51P20A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51P20A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51P20A Peripheral Access Controller (PAC) */ - TAL_0_IRQn = 42, /**< 42 SAMD51P20A Trigger Allocator (TAL): TAL_BRK */ - TAL_1_IRQn = 43, /**< 43 SAMD51P20A Trigger Allocator (TAL): TAL_IPS_0, TAL_IPS_1 */ - RAMECC_IRQn = 45, /**< 45 SAMD51P20A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51P20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51P20A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51P20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51P20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51P20A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51P20A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51P20A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51P20A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51P20A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51P20A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAMD51P20A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAMD51P20A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51P20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51P20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51P20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51P20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51P20A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51P20A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51P20A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51P20A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51P20A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51P20A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51P20A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51P20A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51P20A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAMD51P20A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNMI_Handler; - void* pfnHardFault_Handler; - void* pfnMemManage_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVC_Handler; - void* pfnDebugMon_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pfnTAL_0_Handler; /* 42 Trigger Allocator IRQ 0 */ - void* pfnTAL_1_Handler; /* 43 Trigger Allocator IRQ 1 */ - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NMI_Handler ( void ); -void HardFault_Handler ( void ); -void MemManage_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVC_Handler ( void ); -void DebugMon_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void TAL_0_Handler ( void ); -void TAL_1_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -//#define LITTLE_ENDIAN 1 -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tal.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tal.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TAL 47 /**< \brief Trigger Allocator (TAL) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TAL (0x4101E000) /**< \brief (TAL) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CB (0x00800000UL) /**< \brief (NVMCTRL) CB Base Address */ -#define NVMCTRL_CBW0 (0x00800000UL) /**< \brief (NVMCTRL) CBW0 Base Address */ -#define NVMCTRL_CBW1 (0x00800010UL) /**< \brief (NVMCTRL) CBW1 Base Address */ -#define NVMCTRL_CBW2 (0x00800020UL) /**< \brief (NVMCTRL) CBW2 Base Address */ -#define NVMCTRL_CBW3 (0x00800030UL) /**< \brief (NVMCTRL) CBW3 Base Address */ -#define NVMCTRL_CBW4 (0x00800040UL) /**< \brief (NVMCTRL) CBW4 Base Address */ -#define NVMCTRL_CBW5 (0x00800050UL) /**< \brief (NVMCTRL) CBW5 Base Address */ -#define NVMCTRL_CBW6 (0x00800060UL) /**< \brief (NVMCTRL) CBW6 Base Address */ -#define NVMCTRL_CBW7 (0x00800070UL) /**< \brief (NVMCTRL) CBW7 Base Address */ -#define NVMCTRL_FS (0x00806000UL) /**< \brief (NVMCTRL) FS Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_SW1 (0x00800090UL) /**< \brief (NVMCTRL) SW1 Base Address */ -#define NVMCTRL_SW2 (0x008000A0UL) /**< \brief (NVMCTRL) SW2 Base Address */ -#define NVMCTRL_SW3 (0x008000B0UL) /**< \brief (NVMCTRL) SW3 Base Address */ -#define NVMCTRL_SW4 (0x008000C0UL) /**< \brief (NVMCTRL) SW4 Base Address */ -#define NVMCTRL_SW5 (0x008000D0UL) /**< \brief (NVMCTRL) SW5 Base Address */ -#define NVMCTRL_SW6 (0x008000E0UL) /**< \brief (NVMCTRL) SW6 Base Address */ -#define NVMCTRL_SW7 (0x008000F0UL) /**< \brief (NVMCTRL) SW7 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_TEMP_LOG_W0 (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG_W0 Base Address */ -#define NVMCTRL_TEMP_LOG_W1 (0x00800110UL) /**< \brief (NVMCTRL) TEMP_LOG_W1 Base Address */ -#define NVMCTRL_TEMP_LOG_W2 (0x00800120UL) /**< \brief (NVMCTRL) TEMP_LOG_W2 Base Address */ -#define NVMCTRL_TEMP_LOG_W3 (0x00800130UL) /**< \brief (NVMCTRL) TEMP_LOG_W3 Base Address */ -#define NVMCTRL_TEMP_LOG_W4 (0x00800140UL) /**< \brief (NVMCTRL) TEMP_LOG_W4 Base Address */ -#define NVMCTRL_TEMP_LOG_W5 (0x00800150UL) /**< \brief (NVMCTRL) TEMP_LOG_W5 Base Address */ -#define NVMCTRL_TEMP_LOG_W6 (0x00800160UL) /**< \brief (NVMCTRL) TEMP_LOG_W6 Base Address */ -#define NVMCTRL_TEMP_LOG_W7 (0x00800170UL) /**< \brief (NVMCTRL) TEMP_LOG_W7 Base Address */ -#define NVMCTRL_TLATCH (0x00802000UL) /**< \brief (NVMCTRL) TLATCH Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TAL ((Tal *)0x4101E000UL) /**< \brief (TAL) APB Base Address */ -#define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ -#define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51p20a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060000) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 4 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51P20A_H */ diff --git a/atmel-samd/asf4/samd51/include/system_samd51.h b/atmel-samd/asf4/samd51/include/system_samd51.h deleted file mode 100644 index cfbd2b921..000000000 --- a/atmel-samd/asf4/samd51/include/system_samd51.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup - * - * Copyright (c) 2017 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SYSTEM_SAMD51_H_INCLUDED_ -#define _SYSTEM_SAMD51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAMD51_H_INCLUDED */ diff --git a/atmel-samd/asf4/samd51/main.c b/atmel-samd/asf4/samd51/main.c deleted file mode 100644 index 4652da488..000000000 --- a/atmel-samd/asf4/samd51/main.c +++ /dev/null @@ -1,11 +0,0 @@ -#include - -int main(void) -{ - /* Initializes MCU, drivers and middleware */ - atmel_start_init(); - - /* Replace with your application code */ - while (1) { - } -} diff --git a/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.c b/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.c deleted file mode 100644 index f0a8de446..000000000 --- a/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.c +++ /dev/null @@ -1,389 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack CDC ACM Function Implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "cdcdf_acm.h" - -#define CDCDF_ACM_VERSION 0x00000001u -#define CDCDF_ACM_COMM_EP_INDEX 0 -#define CDCDF_ACM_DATA_EP_INDEX 1 - -/** USB Device CDC ACM Fucntion Specific Data */ -struct cdcdf_acm_func_data { - /** CDC Device ACM Interface information */ - uint8_t func_iface[2]; - /** CDC Device ACM IN Endpoint */ - uint8_t func_ep_in[2]; - /** CDC Device ACM OUT Endpoint */ - uint8_t func_ep_out; - /** CDC Device ACM Enable Flag */ - bool enabled; -}; - -static struct usbdf_driver _cdcdf_acm; -static struct cdcdf_acm_func_data _cdcdf_acm_funcd; -static struct usb_cdc_line_coding usbd_cdc_line_coding; - -static cdcdf_acm_notify_state_t cdcdf_acm_notify_state = NULL; -static cdcdf_acm_set_line_coding_t cdcdf_acm_set_line_coding = NULL; - -/** - * \brief Enable CDC ACM Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB interface descriptor - * \return Operation status. - */ -static int32_t cdcdf_acm_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct cdcdf_acm_func_data *func_data = (struct cdcdf_acm_func_data *)(drv->func_data); - - usb_ep_desc_t ep_desc; - usb_iface_desc_t ifc_desc; - uint8_t * ifc, *ep; - uint8_t i; - - ifc = desc->sod; - for (i = 0; i < 2; i++) { - if (NULL == ifc) { - return ERR_NOT_FOUND; - } - - ifc_desc.bInterfaceNumber = ifc[2]; - ifc_desc.bInterfaceClass = ifc[5]; - - if ((CDC_CLASS_COMM == ifc_desc.bInterfaceClass) || (CDC_CLASS_DATA == ifc_desc.bInterfaceClass)) { - if (func_data->func_iface[i] == ifc_desc.bInterfaceNumber) { // Initialized - return ERR_ALREADY_INITIALIZED; - } else if (func_data->func_iface[i] != 0xFF) { // Occupied - return ERR_NO_RESOURCE; - } else { - func_data->func_iface[i] = ifc_desc.bInterfaceNumber; - } - } else { // Not supported by this function driver - return ERR_NOT_FOUND; - } - - // Install endpoints - ep = usb_find_desc(ifc, desc->eod, USB_DT_ENDPOINT); - while (NULL != ep) { - ep_desc.bEndpointAddress = ep[2]; - ep_desc.bmAttributes = ep[3]; - ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); - if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { - return ERR_NOT_INITIALIZED; - } - if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { - func_data->func_ep_in[i] = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_in[i]); - } else { - func_data->func_ep_out = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_out); - } - desc->sod = ep; - ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); - } - ifc = usb_find_desc(usb_desc_next(desc->sod), desc->eod, USB_DT_INTERFACE); - } - // Installed - _cdcdf_acm_funcd.enabled = true; - return ERR_NONE; -} - -/** - * \brief Disable CDC ACM Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB device descriptor - * \return Operation status. - */ -static int32_t cdcdf_acm_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct cdcdf_acm_func_data *func_data = (struct cdcdf_acm_func_data *)(drv->func_data); - - usb_iface_desc_t ifc_desc; - uint8_t i; - - if (desc) { - ifc_desc.bInterfaceClass = desc->sod[5]; - // Check interface - if ((ifc_desc.bInterfaceClass != CDC_CLASS_COMM) && (ifc_desc.bInterfaceClass != CDC_CLASS_DATA)) { - return ERR_NOT_FOUND; - } - } - - for (i = 0; i < 2; i++) { - if (func_data->func_iface[i] == 0xFF) { - continue; - } else { - func_data->func_iface[i] = 0xFF; - if (func_data->func_ep_in[i] != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_in[i]); - func_data->func_ep_in[i] = 0xFF; - } - } - } - - if (func_data->func_ep_out != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_out); - func_data->func_ep_out = 0xFF; - } - - _cdcdf_acm_funcd.enabled = false; - return ERR_NONE; -} - -/** - * \brief CDC ACM Control Function - * \param[in] drv Pointer to USB device function driver - * \param[in] ctrl USB device general function control type - * \param[in] param Parameter pointer - * \return Operation status. - */ -static int32_t cdcdf_acm_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) -{ - switch (ctrl) { - case USBDF_ENABLE: - return cdcdf_acm_enable(drv, (struct usbd_descriptors *)param); - - case USBDF_DISABLE: - return cdcdf_acm_disable(drv, (struct usbd_descriptors *)param); - - case USBDF_GET_IFACE: - return ERR_UNSUPPORTED_OP; - - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the CDC class set request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t cdcdf_acm_set_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - struct usb_cdc_line_coding line_coding_tmp; - uint16_t len = req->wLength; - uint8_t * ctrl_buf = usbdc_get_ctrl_buffer(); - - switch (req->bRequest) { - case USB_REQ_CDC_SET_LINE_CODING: - if (sizeof(struct usb_cdc_line_coding) != len) { - return ERR_INVALID_DATA; - } - if (USB_SETUP_STAGE == stage) { - return usbdc_xfer(ep, ctrl_buf, len, false); - } else { - memcpy(&line_coding_tmp, ctrl_buf, sizeof(struct usb_cdc_line_coding)); - if ((NULL == cdcdf_acm_set_line_coding) || (true == cdcdf_acm_set_line_coding(&line_coding_tmp))) { - usbd_cdc_line_coding = line_coding_tmp; - } - return ERR_NONE; - } - case USB_REQ_CDC_SET_CONTROL_LINE_STATE: - usbdc_xfer(0, NULL, 0, 0); - if (NULL != cdcdf_acm_notify_state) { - cdcdf_acm_notify_state(req->wValue); - } - return ERR_NONE; - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the CDC class get request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t cdcdf_acm_get_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - uint16_t len = req->wLength; - - if (USB_DATA_STAGE == stage) { - return ERR_NONE; - } - - switch (req->bRequest) { - case USB_REQ_CDC_GET_LINE_CODING: - if (sizeof(struct usb_cdc_line_coding) != len) { - return ERR_INVALID_DATA; - } - return usbdc_xfer(ep, (uint8_t *)&usbd_cdc_line_coding, len, false); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the CDC class request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t cdcdf_acm_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request - return ERR_NOT_FOUND; - } - if ((req->wIndex == _cdcdf_acm_funcd.func_iface[0]) || (req->wIndex == _cdcdf_acm_funcd.func_iface[1])) { - if (req->bmRequestType & USB_EP_DIR_IN) { - return cdcdf_acm_get_req(ep, req, stage); - } else { - return cdcdf_acm_set_req(ep, req, stage); - } - } else { - return ERR_NOT_FOUND; - } -} - -/** USB Device CDC ACM Handler Struct */ -static struct usbdc_handler cdcdf_acm_req_h = {NULL, (FUNC_PTR)cdcdf_acm_req}; - -/** - * \brief Initialize the USB CDC ACM Function Driver - */ -int32_t cdcdf_acm_init(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _cdcdf_acm.ctrl = cdcdf_acm_ctrl; - _cdcdf_acm.func_data = &_cdcdf_acm_funcd; - - usbdc_register_function(&_cdcdf_acm); - usbdc_register_handler(USBDC_HDL_REQ, &cdcdf_acm_req_h); - return ERR_NONE; -} - -/** - * \brief Deinitialize the USB CDC ACM Function Driver - */ -void cdcdf_acm_deinit(void) -{ - usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_COMM_EP_INDEX]); - usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX]); - usb_d_ep_deinit(_cdcdf_acm_funcd.func_ep_out); -} - -/** - * \brief USB CDC ACM Function Read Data - */ -int32_t cdcdf_acm_read(uint8_t *buf, uint32_t size) -{ - if (!cdcdf_acm_is_enabled()) { - return ERR_DENIED; - } - return usbdc_xfer(_cdcdf_acm_funcd.func_ep_out, buf, size, false); -} - -/** - * \brief USB CDC ACM Function Write Data - */ -int32_t cdcdf_acm_write(uint8_t *buf, uint32_t size) -{ - if (!cdcdf_acm_is_enabled()) { - return ERR_DENIED; - } - return usbdc_xfer(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX], buf, size, true); -} - -/** - * \brief USB CDC ACM Stop the data transfer - */ -void cdcdf_acm_stop_xfer(void) -{ - /* Stop transfer. */ - usb_d_ep_abort(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX]); - usb_d_ep_abort(_cdcdf_acm_funcd.func_ep_out); -} - -/** - * \brief USB CDC ACM Function Register Callback - */ -int32_t cdcdf_acm_register_callback(enum cdcdf_acm_cb_type cb_type, FUNC_PTR func) -{ - switch (cb_type) { - case CDCDF_ACM_CB_READ: - usb_d_ep_register_callback(_cdcdf_acm_funcd.func_ep_out, USB_D_EP_CB_XFER, func); - break; - case CDCDF_ACM_CB_WRITE: - usb_d_ep_register_callback(_cdcdf_acm_funcd.func_ep_in[CDCDF_ACM_DATA_EP_INDEX], USB_D_EP_CB_XFER, func); - break; - case CDCDF_ACM_CB_LINE_CODING_C: - cdcdf_acm_set_line_coding = (cdcdf_acm_set_line_coding_t)func; - break; - case CDCDF_ACM_CB_STATE_C: - cdcdf_acm_notify_state = (cdcdf_acm_notify_state_t)func; - break; - default: - return ERR_INVALID_ARG; - } - return ERR_NONE; -} - -/** - * \brief Check whether CDC ACM Function is enabled - */ -bool cdcdf_acm_is_enabled(void) -{ - return _cdcdf_acm_funcd.enabled; -} - -/** - * \brief Return the CDC ACM line coding structure start address - */ -const struct usb_cdc_line_coding *cdcdf_acm_get_line_coding(void) -{ - return (const struct usb_cdc_line_coding *)&usbd_cdc_line_coding; -} - -/** - * \brief Return version - */ -uint32_t cdcdf_acm_get_version(void) -{ - return CDCDF_ACM_VERSION; -} diff --git a/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.h b/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.h deleted file mode 100644 index 913e734be..000000000 --- a/atmel-samd/asf4/samd51/usb/class/cdc/device/cdcdf_acm.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack CDC ACM Function Definition. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_CDC_ACM_SER_H_ -#define USBDF_CDC_ACM_SER_H_ - -#include "usbdc.h" -#include "usb_protocol_cdc.h" - -/** CDC ACM Class Callback Type */ -enum cdcdf_acm_cb_type { CDCDF_ACM_CB_READ, CDCDF_ACM_CB_WRITE, CDCDF_ACM_CB_LINE_CODING_C, CDCDF_ACM_CB_STATE_C }; - -/** CDC ACM Notify Line State Callback. */ -typedef void (*cdcdf_acm_notify_state_t)(uint16_t); - -/** CDC ACM Set Line Coding Callback. */ -typedef bool (*cdcdf_acm_set_line_coding_t)(struct usb_cdc_line_coding *); - -/** - * \brief Initialize the USB CDC ACM Function Driver - * \return Operation status. - */ -int32_t cdcdf_acm_init(void); - -/** - * \brief Deinitialize the USB CDC ACM Function Driver - * \return Operation status. - */ -void cdcdf_acm_deinit(void); - -/** - * \brief USB CDC ACM Function Read Data - * \param[in] buf Pointer to the buffer which receives data - * \param[in] size the size of data to be received - * \return Operation status. - */ -int32_t cdcdf_acm_read(uint8_t *buf, uint32_t size); - -/** - * \brief USB CDC ACM Function Write Data - * \param[in] buf Pointer to the buffer which stores data - * \param[in] size the size of data to be sent - * \return Operation status. - */ -int32_t cdcdf_acm_write(uint8_t *buf, uint32_t size); - -/** - * \brief USB CDC ACM Stop the currnet data transfer - */ -void cdcdf_acm_stop_xfer(void); - -/** - * \brief USB CDC ACM Function Register Callback - * \param[in] cb_type Callback type of CDC ACM Function - * \param[in] func Pointer to callback function - * \return Operation status. - */ -int32_t cdcdf_acm_register_callback(enum cdcdf_acm_cb_type cb_type, FUNC_PTR func); - -/** - * \brief Check whether CDC ACM Function is enabled - * \return Operation status. - * \return true CDC ACM Function is enabled - * \return false CDC ACM Function is disabled - */ -bool cdcdf_acm_is_enabled(void); - -/** - * \brief Return the CDC ACM line coding structure start address - * \return Pointer to USB CDC ACM line coding data. - */ -const struct usb_cdc_line_coding *cdcdf_acm_get_line_coding(void); - -/** - * \brief Return version - */ -uint32_t cdcdf_acm_get_version(void); - -#endif /* USBDF_CDC_ACM_SER_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/cdc/usb_protocol_cdc.h b/atmel-samd/asf4/samd51/usb/class/cdc/usb_protocol_cdc.h deleted file mode 100644 index 5213bd843..000000000 --- a/atmel-samd/asf4/samd51/usb/class/cdc/usb_protocol_cdc.h +++ /dev/null @@ -1,436 +0,0 @@ -/** - * \file - * - * \brief USB Communication Device Class (CDC) protocol definitions - * - * Copyright (c) 2015 - 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ -#ifndef _USB_PROTOCOL_CDC_H_ -#define _USB_PROTOCOL_CDC_H_ - -#include "usb_includes.h" - -/** - * \ingroup usb_protocol_group - * \defgroup cdc_protocol_group Communication Device Class Definitions - * @{ - */ - -/** - * \name Possible values of class - */ -//@{ -#define CDC_CLASS_DEVICE 0x02 //!< USB Communication Device Class -#define CDC_CLASS_COMM 0x02 //!< CDC Communication Class Interface -#define CDC_CLASS_DATA 0x0A //!< CDC Data Class Interface -//@} - -//! \name USB CDC Subclass IDs -//@{ -#define CDC_SUBCLASS_DLCM 0x01 //!< Direct Line Control Model -#define CDC_SUBCLASS_ACM 0x02 //!< Abstract Control Model -#define CDC_SUBCLASS_TCM 0x03 //!< Telephone Control Model -#define CDC_SUBCLASS_MCCM 0x04 //!< Multi-Channel Control Model -#define CDC_SUBCLASS_CCM 0x05 //!< CAPI Control Model -#define CDC_SUBCLASS_ETH 0x06 //!< Ethernet Networking Control Model -#define CDC_SUBCLASS_ATM 0x07 //!< ATM Networking Control Model -//@} - -//! \name USB CDC Communication Interface Protocol IDs -//@{ -#define CDC_PROTOCOL_V25TER 0x01 //!< Common AT commands -//@} - -//! \name USB CDC Data Interface Protocol IDs -//@{ -#define CDC_PROTOCOL_I430 0x30 //!< ISDN BRI -#define CDC_PROTOCOL_HDLC 0x31 //!< HDLC -#define CDC_PROTOCOL_TRANS 0x32 //!< Transparent -#define CDC_PROTOCOL_Q921M 0x50 //!< Q.921 management protocol -#define CDC_PROTOCOL_Q921 0x51 //!< Q.931 [sic] Data link protocol -#define CDC_PROTOCOL_Q921TM 0x52 //!< Q.921 TEI-multiplexor -#define CDC_PROTOCOL_V42BIS 0x90 //!< Data compression procedures -#define CDC_PROTOCOL_Q931 0x91 //!< Euro-ISDN protocol control -#define CDC_PROTOCOL_V120 0x92 //!< V.24 rate adaption to ISDN -#define CDC_PROTOCOL_CAPI20 0x93 //!< CAPI Commands -#define CDC_PROTOCOL_HOST 0xFD //!< Host based driver - /** - * \brief Describes the Protocol Unit Functional Descriptors [sic] - * on Communication Class Interface - */ -#define CDC_PROTOCOL_PUFD 0xFE -//@} - -//! \name USB CDC Functional Descriptor Types -//@{ -#define CDC_CS_INTERFACE 0x24 //!< Interface Functional Descriptor -#define CDC_CS_ENDPOINT 0x25 //!< Endpoint Functional Descriptor -//@} - -//! \name USB CDC Functional Descriptor Subtypes -//@{ -#define CDC_SCS_HEADER 0x00 //!< Header Functional Descriptor -#define CDC_SCS_CALL_MGMT 0x01 //!< Call Management -#define CDC_SCS_ACM 0x02 //!< Abstract Control Management -#define CDC_SCS_UNION 0x06 //!< Union Functional Descriptor -//@} - -//! \name USB CDC Request IDs -//@{ -#define USB_REQ_CDC_SEND_ENCAPSULATED_COMMAND 0x00 -#define USB_REQ_CDC_GET_ENCAPSULATED_RESPONSE 0x01 -#define USB_REQ_CDC_SET_COMM_FEATURE 0x02 -#define USB_REQ_CDC_GET_COMM_FEATURE 0x03 -#define USB_REQ_CDC_CLEAR_COMM_FEATURE 0x04 -#define USB_REQ_CDC_SET_AUX_LINE_STATE 0x10 -#define USB_REQ_CDC_SET_HOOK_STATE 0x11 -#define USB_REQ_CDC_PULSE_SETUP 0x12 -#define USB_REQ_CDC_SEND_PULSE 0x13 -#define USB_REQ_CDC_SET_PULSE_TIME 0x14 -#define USB_REQ_CDC_RING_AUX_JACK 0x15 -#define USB_REQ_CDC_SET_LINE_CODING 0x20 -#define USB_REQ_CDC_GET_LINE_CODING 0x21 -#define USB_REQ_CDC_SET_CONTROL_LINE_STATE 0x22 -#define USB_REQ_CDC_SEND_BREAK 0x23 -#define USB_REQ_CDC_SET_RINGER_PARMS 0x30 -#define USB_REQ_CDC_GET_RINGER_PARMS 0x31 -#define USB_REQ_CDC_SET_OPERATION_PARMS 0x32 -#define USB_REQ_CDC_GET_OPERATION_PARMS 0x33 -#define USB_REQ_CDC_SET_LINE_PARMS 0x34 -#define USB_REQ_CDC_GET_LINE_PARMS 0x35 -#define USB_REQ_CDC_DIAL_DIGITS 0x36 -#define USB_REQ_CDC_SET_UNIT_PARAMETER 0x37 -#define USB_REQ_CDC_GET_UNIT_PARAMETER 0x38 -#define USB_REQ_CDC_CLEAR_UNIT_PARAMETER 0x39 -#define USB_REQ_CDC_GET_PROFILE 0x3A -#define USB_REQ_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 -#define USB_REQ_CDC_SET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x41 -#define USB_REQ_CDC_GET_ETHERNET_POWER_MANAGEMENT_PATTERNFILTER 0x42 -#define USB_REQ_CDC_SET_ETHERNET_PACKET_FILTER 0x43 -#define USB_REQ_CDC_GET_ETHERNET_STATISTIC 0x44 -#define USB_REQ_CDC_SET_ATM_DATA_FORMAT 0x50 -#define USB_REQ_CDC_GET_ATM_DEVICE_STATISTICS 0x51 -#define USB_REQ_CDC_SET_ATM_DEFAULT_VC 0x52 -#define USB_REQ_CDC_GET_ATM_VC_STATISTICS 0x53 -// Added bNotification codes according cdc spec 1.1 chapter 6.3 -#define USB_REQ_CDC_NOTIFY_RING_DETECT 0x09 -#define USB_REQ_CDC_NOTIFY_SERIAL_STATE 0x20 -#define USB_REQ_CDC_NOTIFY_CALL_STATE_CHANGE 0x28 -#define USB_REQ_CDC_NOTIFY_LINE_STATE_CHANGE 0x29 -//@} - -/* - * Need to pack structures tightly, or the compiler might insert padding - * and violate the spec-mandated layout. - */ -COMPILER_PACK_SET(1) - -//! \name USB CDC Descriptors -//@{ - -//! CDC Header Functional Descriptor -typedef struct usb_cdc_hdr_desc { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - le16_t bcdCDC; -} usb_cdc_hdr_desc_t; - -#define USB_CDC_HDR_DESC_LEN 5 -#define USB_CDC_HDR_DESC_BYTES(bcdCDC) \ - USB_CDC_HDR_DESC_LEN, /* bFunctionLength */ \ - CDC_CS_INTERFACE, /* bDescriptorType */ \ - CDC_SCS_HEADER, /* bDescriptorSubtype */ \ - LE_BYTE0(bcdCDC), LE_BYTE1(bcdCDC) /* bcdCDC */ - -//! CDC Call Management Functional Descriptor -typedef struct usb_cdc_call_mgmt_desc { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bmCapabilities; - uint8_t bDataInterface; -} usb_cdc_call_mgmt_desc_t; - -#define USB_CDC_CALL_MGMT_DESC_LEN 5 -#define USB_CDC_CALL_MGMT_DESC_BYTES(bmCapabilities, bDataInterface) \ - USB_CDC_CALL_MGMT_DESC_LEN, /* bFunctionLength */ \ - CDC_CS_INTERFACE, /* bDescriptorType */ \ - CDC_SCS_CALL_MGMT, /* bDescriptorSubtype */ \ - bmCapabilities, bDataInterface - -//! CDC ACM Functional Descriptor -typedef struct usb_cdc_acm_desc { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bmCapabilities; -} usb_cdc_acm_desc_t; - -#define USB_CDC_ACM_DESC_LEN 4 -#define USB_CDC_ACM_DESC_BYTES(bmCapabilities) \ - USB_CDC_ACM_DESC_LEN, /* bFunctionLength */ \ - CDC_CS_INTERFACE, /* bDescriptorType */ \ - CDC_SCS_ACM, /* bDescriptorSubType */ \ - bmCapabilities - -//! CDC Union Functional Descriptor -typedef struct usb_cdc_union_desc { - uint8_t bFunctionLength; - uint8_t bDescriptorType; - uint8_t bDescriptorSubtype; - uint8_t bMasterInterface; - uint8_t bSlaveInterface0; -} usb_cdc_union_desc_t; - -#define USB_CDC_UNION_DESC_LEN 5 -#define USB_CDC_UNION_DESC_BYTES(bMasterInterface, bSlaveInterface) \ - USB_CDC_UNION_DESC_LEN, CDC_CS_INTERFACE, CDC_SCS_UNION, bMasterInterface, bSlaveInterface - -//! \name USB CDC Call Management Capabilities -//@{ -//! Device handles call management itself -#define CDC_CALL_MGMT_SUPPORTED (1 << 0) -//! Device can send/receive call management info over a Data Class interface -#define CDC_CALL_MGMT_OVER_DCI (1 << 1) -//@} - -//! \name USB CDC ACM Capabilities -//@{ -//! Device supports the request combination of -//! Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature. -#define CDC_ACM_SUPPORT_FEATURE_REQUESTS (1 << 0) -//! Device supports the request combination of -//! Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, -//! and the notification Serial_State. -#define CDC_ACM_SUPPORT_LINE_REQUESTS (1 << 1) -//! Device supports the request Send_Break -#define CDC_ACM_SUPPORT_SENDBREAK_REQUESTS (1 << 2) -//! Device supports the notification Network_Connection. -#define CDC_ACM_SUPPORT_NOTIFY_REQUESTS (1 << 3) -//@} -//@} - -//! \name USB CDC line control -//@{ - -//! \name USB CDC line coding -//@{ - -//! Line Coding structure -typedef struct usb_cdc_line_coding { - le32_t dwDTERate; //!< Data rate, bits per second - uint8_t bCharFormat; //!< 0-1 Stop bit,1-1.5 Stop bits,2-2 Stop bits - uint8_t bParityType; //!< 0-None,1-Odd,2-Even,3-Mark,4-Space - uint8_t bDataBits; //!< 5,6,7,8 or 16 -} usb_cdc_line_coding_t; - -//! Possible values of bCharFormat -enum cdc_char_format { - CDC_STOP_BITS_1 = 0, //!< 1 stop bit - CDC_STOP_BITS_1_5 = 1, //!< 1.5 stop bits - CDC_STOP_BITS_2 = 2 //!< 2 stop bits -}; - -//! Possible values of bParityType -enum cdc_parity { - CDC_PAR_NONE = 0, //!< No parity - CDC_PAR_ODD = 1, //!< Odd parity - CDC_PAR_EVEN = 2, //!< Even parity - CDC_PAR_MARK = 3, //!< Parity forced to 1 (mark) - CDC_PAR_SPACE = 4 //!< Parity forced to 0 (space) -}; -//@} - -//! \name USB CDC control signals -//! spec 1.1 chapter 6.2.14 -//@{ - -//! Control signal structure -typedef struct usb_cdc_control_signal { - union { - le16_t value; - struct { - uint8_t dte_present; - uint8_t carrier_ctrl; - } modem; - struct { - uint8_t DTR : 1; //!< Data Terminal Ready - uint8_t RTS : 1; //!< Request To Send - } rs232; - struct { - uint8_t s108_2 : 1; //!< V.24 signal 108/2 - uint8_t s105 : 1; //!< V.24 signal 105 - } v24; - }; -} usb_cdc_control_signal_t; - -//! \name Possible values in usb_cdc_control_signal_t -//@{ -//! Carrier control for half duplex modems. -//! This signal corresponds to V.24 signal 105 and RS-232 signal RTS. -//! The device ignores the value of this bit -//! when operating in full duplex mode. -#define CDC_CTRL_SIGNAL_ACTIVATE_CARRIER (1 << 1) -//! Indicates to DCE if DTE is present or not. -//! This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR. -#define CDC_CTRL_SIGNAL_DTE_PRESENT (1 << 0) -//@} -//@} - -//! \name USB CDC notification message -//@{ - -typedef struct usb_cdc_notify_msg { - uint8_t bmRequestType; - uint8_t bNotification; - union { - le16_t wValue; - struct { - uint8_t low; - uint8_t high; - } wValueBytes; - }; - union { - le16_t wIndex; - struct { - uint8_t low; - uint8_t high; - } wIndexBytes; - }; - union { - le16_t wLength; - struct { - uint8_t low; - uint8_t high; - } wLengthBytes; - }; -} usb_cdc_notify_msg_t; - -//! \name USB CDC serial state -//@{* - -//! UART State Bitmap (cdc spec 1.1 chapter 6.3.5) -typedef union usb_cdc_uart_state { - le16_t value; - struct { - uint8_t bRxCarrier : 1; - uint8_t bTxCarrier : 1; - uint8_t bBreak : 1; - uint8_t bRingSignal : 1; - uint8_t bFraming : 1; - uint8_t bParity : 1; - uint8_t bOverRun; - } bitmap; - struct { - uint8_t bDCD : 1; - uint8_t bDSR : 1; - uint8_t bBreak : 1; - uint8_t bRingSignal : 1; - uint8_t bFraming : 1; - uint8_t bParity : 1; - uint8_t bOverRun; - } rs232; - struct { - uint8_t bS109 : 1; //!< V.24 signal 109 - uint8_t bS106 : 1; //!< V.24 signal 106 - uint8_t bBreak : 1; - uint8_t bRingSignal : 1; - uint8_t bFraming : 1; - uint8_t bParity : 1; - uint8_t bOverRun; - } v24; -} usb_cdc_uart_state_t; - -//! Hardware handshake support (cdc spec 1.1 chapter 6.3.5) -typedef struct usb_cdc_notify_serial_state { - usb_cdc_notify_msg_t header; - union usb_cdc_uart_state state; -} usb_cdc_notify_serial_state_t; - -//! \name Possible values in usb_cdc_notify_serial_state_t -//@{ -#define CDC_SERIAL_STATE_DCD CPU_TO_LE16((1 << 0)) -#define CDC_SERIAL_STATE_DSR CPU_TO_LE16((1 << 1)) -#define CDC_SERIAL_STATE_BREAK CPU_TO_LE16((1 << 2)) -#define CDC_SERIAL_STATE_RING CPU_TO_LE16((1 << 3)) -#define CDC_SERIAL_STATE_FRAMING CPU_TO_LE16((1 << 4)) -#define CDC_SERIAL_STATE_PARITY CPU_TO_LE16((1 << 5)) -#define CDC_SERIAL_STATE_OVERRUN CPU_TO_LE16((1 << 6)) -//@} -//! @} - -//! @} - -COMPILER_PACK_RESET() - -//! @} - -/** - * \brief Fill a CDC SetLineCoding request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - */ -static inline void usb_fill_SetLineCoding_req(struct usb_req *req, uint8_t iface) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_CDC_SET_LINE_CODING; - req->wValue = 0; - req->wIndex = iface; - req->wLength = sizeof(usb_cdc_line_coding_t); -} - -/** - * \brief Fill a CDC SetControlLineState request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - * \param[in] ctrl Control Signal Bitmap - */ -static inline void usb_fill_SetControlLineState_req(struct usb_req *req, uint8_t iface, uint16_t ctrl) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_CDC_SET_CONTROL_LINE_STATE; - req->wValue = ctrl; - req->wIndex = iface; - req->wLength = 0; -} - -#endif // _USB_PROTOCOL_CDC_H_ diff --git a/atmel-samd/asf4/samd51/usb/class/composite/device/composite_desc.h b/atmel-samd/asf4/samd51/usb/class/composite/device/composite_desc.h deleted file mode 100644 index 9838e40c1..000000000 --- a/atmel-samd/asf4/samd51/usb/class/composite/device/composite_desc.h +++ /dev/null @@ -1,188 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack Composite Class Descriptor Setting. - * - * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_COMPOSITE_DESC_H_ -#define USBDF_COMPOSITE_DESC_H_ - -#include "usb_protocol.h" -#include "usbd_composite_config.h" - -#if CONF_USB_COMPOSITE_CDC_ACM_EN == 1 -#define CONF_CDC_ACM_IFC_LEN 66 -#define CONF_CDC_ACM_IFC_NUM 2 -#define CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM 0 -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM 1 -#define CONF_CDC_ACM_IFC_DESC \ - USB_IAD_DESC_BYTES( \ - CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, 0x02, CDC_CLASS_DEVICE, CDC_SUBCLASS_ACM, CDC_PROTOCOL_V25TER, 0x00) \ - , \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, \ - 0x00, \ - 0x01, \ - CDC_CLASS_DEVICE, \ - CDC_SUBCLASS_ACM, \ - CDC_PROTOCOL_V25TER, \ - 0x00), \ - USB_CDC_HDR_DESC_BYTES(0x1001), USB_CDC_CALL_MGMT_DESC_BYTES(0x01, 0x00), USB_CDC_ACM_DESC_BYTES(0x02), \ - USB_CDC_UNION_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM, 0x01), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR, 3, CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ, 10), \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM, 0x00, 2, 0x0A, 0x00, 0x00, 0x00), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR, 2, CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ, 0x00), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR, 2, CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ, 0x00), -#else -#define CONF_CDC_ACM_IFC_LEN 0 -#define CONF_CDC_ACM_IFC_NUM 0 -#define CONF_USB_COMPOSITE_CDC_ACM_COMM_BIFCNUM -2 -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM -1 -#define CONF_CDC_ACM_IFC_DESC -#endif - -#if CONF_USB_COMPOSITE_HID_MOUSE_EN == 1 -#define CONF_HID_MOUSE_IFC_LEN 25 -#define CONF_HID_MOUSE_IFC_NUM 1 -#define CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM (CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM + 1) -#define CONF_HID_MOUSE_IFC_DESC \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM, 0x00, 0x01, 0x03, 0x01, 0x02, 0x00) \ - , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, 0x34), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ, 10), -#else -#define CONF_HID_MOUSE_IFC_LEN 0 -#define CONF_HID_MOUSE_IFC_NUM 0 -#define CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM CONF_USB_COMPOSITE_CDC_ACM_DATA_BIFCNUM -#define CONF_HID_MOUSE_IFC_DESC -#endif - -#if CONF_USB_COMPOSITE_HID_KEYBOARD_EN == 1 -#define CONF_HID_KEYBOARD_IFC_LEN 32 -#define CONF_HID_KEYBOARD_IFC_NUM 1 -#define CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM (CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM + 1) -#define CONF_HID_KEYBOARD_IFC_DESC \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM, 0x00, 0x02, 0x03, 0x01, 0x01, 0x00) \ - , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, 59), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ, 10), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ, 10), -#else -#define CONF_HID_KEYBOARD_IFC_LEN 0 -#define CONF_HID_KEYBOARD_IFC_NUM 0 -#define CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM CONF_USB_COMPOSITE_HID_MOUSE_BIFCNUM -#define CONF_HID_KEYBOARD_IFC_DESC -#endif - -#if CONF_USB_COMPOSITE_HID_GENERIC_EN == 1 -#define CONF_HID_GENERIC_IFC_LEN 32 -#define CONF_HID_GENERIC_IFC_NUM 1 -#define CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM (CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM + 1) -#define CONF_HID_GENERIC_IFC_DESC \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM, 0x00, 0x02, 0x03, 0x00, 0x00, 0x00) \ - , USB_HID_DESC_BYTES(0x09, 0x21, 0x01, 0x22, CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ, 10), \ - USB_ENDP_DESC_BYTES( \ - CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR, 0x03, CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ, 10), -#else -#define CONF_HID_GENERIC_IFC_LEN 0 -#define CONF_HID_GENERIC_IFC_NUM 0 -#define CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM CONF_USB_COMPOSITE_HID_KEYBOARD_BIFCNUM -#define CONF_HID_GENERIC_IFC_DESC -#endif - -#if CONF_USB_COMPOSITE_MSC_EN == 1 -#define CONF_MSC_IFC_LEN 23 /* (9 + 7 * 2) */ -#define CONF_MSC_IFC_NUM 1 -#define CONF_USB_COMPOSITE_MSC_BIFCNUM (CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM + 1) -#define CONF_MSC_IFC_DESC \ - USB_IFACE_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BIFCNUM, 0x00, 0x02, 0x08, 0x06, 0x50, 0x00) \ - , USB_ENDP_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR, 0x02, CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ, 0), \ - USB_ENDP_DESC_BYTES(CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR, 0x02, CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ, 0), -#else -#define CONF_MSC_IFC_LEN 0 -#define CONF_MSC_IFC_NUM 0 -#define CONF_USB_COMPOSITE_MSC_BIFCNUM CONF_USB_COMPOSITE_HID_GENERIC_BIFCNUM -#define CONF_MSC_IFC_DESC -#endif - -#define CONF_USB_COMPOSITE_TOTAL_LEN \ - (USB_CONFIG_DESC_LEN + CONF_CDC_ACM_IFC_LEN + CONF_HID_MOUSE_IFC_LEN + CONF_HID_KEYBOARD_IFC_LEN \ - + CONF_HID_GENERIC_IFC_LEN \ - + CONF_MSC_IFC_LEN) - -#define CONF_USB_COMPOSITE_IFC_NUM \ - (CONF_CDC_ACM_IFC_NUM + CONF_HID_MOUSE_IFC_NUM + CONF_HID_KEYBOARD_IFC_NUM + CONF_HID_GENERIC_IFC_NUM \ - + CONF_MSC_IFC_NUM) - -#define COMPOSITE_DEV_DESC \ - USB_DEV_DESC_BYTES(CONF_USB_COMPOSITE_BCDUSB, \ - 0xEF, \ - 0x02, \ - 0x01, \ - CONF_USB_COMPOSITE_BMAXPKSZ0, \ - CONF_USB_COMPOSITE_IDVENDER, \ - CONF_USB_COMPOSITE_IDPRODUCT, \ - CONF_USB_COMPOSITE_BCDDEVICE, \ - CONF_USB_COMPOSITE_IMANUFACT, \ - CONF_USB_COMPOSITE_IPRODUCT, \ - CONF_USB_COMPOSITE_ISERIALNUM, \ - CONF_USB_COMPOSITE_BNUMCONFIG) - -#define COMPOSITE_CFG_DESC \ - USB_CONFIG_DESC_BYTES(CONF_USB_COMPOSITE_TOTAL_LEN, \ - CONF_USB_COMPOSITE_IFC_NUM, \ - CONF_USB_COMPOSITE_BCONFIGVAL, \ - CONF_USB_COMPOSITE_ICONFIG, \ - CONF_USB_COMPOSITE_BMATTRI, \ - CONF_USB_COMPOSITE_BMAXPOWER) - -#define COMPOSITE_IFACE_DESCES \ - CONF_CDC_ACM_IFC_DESC \ - CONF_HID_MOUSE_IFC_DESC \ - CONF_HID_KEYBOARD_IFC_DESC \ - CONF_HID_GENERIC_IFC_DESC \ - CONF_MSC_IFC_DESC - -/** USB Device descriptors and configuration descriptors */ -#define COMPOSITE_DESCES_LS_FS \ - COMPOSITE_DEV_DESC, COMPOSITE_CFG_DESC, COMPOSITE_IFACE_DESCES CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC, \ - CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC, CONF_USB_COMPOSITE_PRODUCT_STR_DESC - -#endif /* USBDF_COMPOSITE_DESC_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/composite/device/usbd_composite_config.h b/atmel-samd/asf4/samd51/usb/class/composite/device/usbd_composite_config.h deleted file mode 100644 index 6b18e443d..000000000 --- a/atmel-samd/asf4/samd51/usb/class/composite/device/usbd_composite_config.h +++ /dev/null @@ -1,603 +0,0 @@ -/* Auto-generated config file usbd_composite_config.h */ -#ifndef USBD_COMPOSITE_CONFIG_H -#define USBD_COMPOSITE_CONFIG_H - -// <<< Use Configuration Wizard in Context Menu >>> - -// Composite Device Descriptor - -// bcdUSB -// <0x0200=> USB 2.0 version -// <0x0210=> USB 2.1 version -// usb_composite_bcdusb -#ifndef CONF_USB_COMPOSITE_BCDUSB -#define CONF_USB_COMPOSITE_BCDUSB 0x200 -#endif - -// bMaxPackeSize0 -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_bmaxpksz0 -#ifndef CONF_USB_COMPOSITE_BMAXPKSZ0 -#define CONF_USB_COMPOSITE_BMAXPKSZ0 0x40 -#endif - -// idVender <0x0000-0xFFFF> -// usb_composite_idvender -#ifndef CONF_USB_COMPOSITE_IDVENDER -#define CONF_USB_COMPOSITE_IDVENDER 0x3eb -#endif - -// idProduct <0x0000-0xFFFF> -// usb_composite_idproduct -#ifndef CONF_USB_COMPOSITE_IDPRODUCT -#define CONF_USB_COMPOSITE_IDPRODUCT 0x2421 -#endif - -// bcdDevice <0x0000-0xFFFF> -// usb_composite_bcddevice -#ifndef CONF_USB_COMPOSITE_BCDDEVICE -#define CONF_USB_COMPOSITE_BCDDEVICE 0x100 -#endif - -// iManufacturer <0x00-0xFF> -// usb_composite_imanufact -#ifndef CONF_USB_COMPOSITE_IMANUFACT -#define CONF_USB_COMPOSITE_IMANUFACT 0x0 -#endif - -#ifndef CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC -#define CONF_USB_COMPOSITE_LANGUAGE_ID_STR_DESC 0x04, 0x03, 0x09, 0x04 -#endif - -#ifndef CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC -#define CONF_USB_COMPOSITE_MANUFACTOR_STR_DESC \ - 0x14, 0x03, 0x41, 0x00, 0x54, 0x00, 0x4D, 0x00, 0x45, 0x00, 0x4C, 0x00, 0x20, 0x00, 0x41, 0x00, 0x53, 0x00, 0x46, \ - 0x00 -#endif - -// iProduct <0x00-0xFF> -// usb_composite_iproduct -#ifndef CONF_USB_COMPOSITE_IPRODUCT -#define CONF_USB_COMPOSITE_IPRODUCT 0x0 -#endif - -#ifndef CONF_USB_COMPOSITE_PRODUCT_STR_DESC -#define CONF_USB_COMPOSITE_PRODUCT_STR_DESC \ - 0x22, 0x03, 0x43, 0x00, 0x6f, 0x00, 0x6d, 0x00, 0x70, 0x00, 0x6f, 0x00, 0x73, 0x00, 0x69, 0x00, 0x74, 0x00, 0x65, \ - 0x00, 0x20, 0x00, 0x44, 0x00, 0x65, 0x00, 0x76, 0x00, 0x69, 0x00, 0x63, 0x00, 0x65, 0x00 -#endif - -// iSerialNumber <0x00-0xFF> -// usb_composite_iserialnum -#ifndef CONF_USB_COMPOSITE_ISERIALNUM -#define CONF_USB_COMPOSITE_ISERIALNUM 0x0 -#endif - -// bNumConfigurations <0x01-0xFF> -// usb_composite_bnumconfig -#ifndef CONF_USB_COMPOSITE_BNUMCONFIG -#define CONF_USB_COMPOSITE_BNUMCONFIG 0x1 -#endif -// - -// Composite Configuration Descriptor - -// bConfigurationValue <0x01-0xFF> -// usb_composite_bconfigval -#ifndef CONF_USB_COMPOSITE_BCONFIGVAL -#define CONF_USB_COMPOSITE_BCONFIGVAL 0x1 -#endif - -// iConfiguration <0x00-0xFF> -// usb_composite_iconfig -#ifndef CONF_USB_COMPOSITE_ICONFIG -#define CONF_USB_COMPOSITE_ICONFIG 0x0 -#endif - -// bmAttributes -// <0x80=> Bus power supply, not support for remote wakeup -// <0xA0=> Bus power supply, support for remote wakeup -// <0xC0=> Self powered, not support for remote wakeup -// <0xE0=> Self powered, support for remote wakeup -// usb_composite_bmattri -#ifndef CONF_USB_COMPOSITE_BMATTRI -#define CONF_USB_COMPOSITE_BMATTRI 0x80 -#endif - -// bMaxPower <0x00-0xFF> -// usb_composite_bmaxpower -#ifndef CONF_USB_COMPOSITE_BMAXPOWER -#define CONF_USB_COMPOSITE_BMAXPOWER 0x32 -#endif -// - -// CDC ACM Support -// usb_composite_cdc_acm_support -#ifndef CONF_USB_COMPOSITE_CDC_ACM_EN -#define CONF_USB_COMPOSITE_CDC_ACM_EN 0 -#endif - -// CDC ACM Comm Interrupt IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_cdc_acm_epaddr -#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR -#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_EPADDR 0x82 -#endif - -// CDC ACM Comm Interrupt IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_cdc_acm_comm_int_maxpksz -#ifndef CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ -#define CONF_USB_COMPOSITE_CDC_ACM_COMM_INT_MAXPKSZ 0x40 -#endif - -// CDC ACM Data BULK IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_cdc_acm_data_bulkin_epaddr -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_EPADDR 0x81 -#endif - -// CDC ACM Data BULK IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_cdc_acm_data_builin_maxpksz -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKIN_MAXPKSZ 0x40 -#endif - -// CDC ACM Data BULK OUT Endpoint Address -// <0x01=> EndpointAddress = 0x01 -// <0x02=> EndpointAddress = 0x02 -// <0x03=> EndpointAddress = 0x03 -// <0x04=> EndpointAddress = 0x04 -// <0x05=> EndpointAddress = 0x05 -// <0x06=> EndpointAddress = 0x06 -// <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_cdc_acm_data_bulkout_epaddr -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_EPADDR 0x1 -#endif - -// CDC ACM Data BULK OUT Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_cdc_acm_data_buckout_maxpksz -#ifndef CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ -#define CONF_USB_COMPOSITE_CDC_ACM_DATA_BULKOUT_MAXPKSZ 0x40 -#endif - -// CDC ACM Echo Demo generation -// conf_usb_composite_cdc_echo_demo -// Invoke cdcdf_acm_demo_init(buf[wMaxPacketSize]) to enable the echo demo. -// Buf is packet buffer for data receive and echo back. -// The buffer is 4 byte aligned to support DMA. -#ifndef CONF_USB_COMPOSITE_CDC_ECHO_DEMO -#define CONF_USB_COMPOSITE_CDC_ECHO_DEMO 0 -#endif - -// - -// HID Mouse Support -// usb_composite_hid_mouse_support -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_EN -#define CONF_USB_COMPOSITE_HID_MOUSE_EN 0 -#endif - -// HID Mouse INTERRUPT IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_hid_mouse_intin_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR -#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_EPADDR 0x83 -#endif - -// HID Mouse INTERRUPT IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_mouse_intin_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_MOUSE_INTIN_MAXPKSZ 0x8 -#endif - -// HID Mouse Move Demo generation -// conf_usb_composite_hid_mouse_demo -// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. -// Button1 and button3 are the pins used for mouse moving left and right. -#ifndef CONF_USB_COMPOSITE_HID_MOUSE_DEMO -#define CONF_USB_COMPOSITE_HID_MOUSE_DEMO 0 -#endif - -// - -// HID Keyboard Support -// usb_composite_hid_keyboard_support -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_EN -#define CONF_USB_COMPOSITE_HID_KEYBOARD_EN 0 -#endif - -// HID Keyboard INTERRUPT IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_hid_keyboard_intin_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_EPADDR 0x84 -#endif - -// HID Keyboard INTERRUPT IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_keyboard_intin_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTIN_MAXPKSZ 0x8 -#endif - -// HID Keyboard INTERRUPT OUT Endpoint Address -// <0x01=> EndpointAddress = 0x01 -// <0x02=> EndpointAddress = 0x02 -// <0x03=> EndpointAddress = 0x03 -// <0x04=> EndpointAddress = 0x04 -// <0x05=> EndpointAddress = 0x05 -// <0x06=> EndpointAddress = 0x06 -// <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_hid_keyboard_intout_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_EPADDR 0x2 -#endif - -// HID Keyboard INTERRUPT OUT Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_keyboard_intout_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_KEYBOARD_INTOUT_MAXPKSZ 0x8 -#endif - -// HID Keyboard Caps Lock Demo generation -// conf_usb_composite_hid_keyboard_demo -// Invoke hiddf_demo_init(button1, button2, button3) to enabled the move demo. -// Buffon2 is the pin used for keyboard CAPS LOCK simulation. -#ifndef CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO -#define CONF_USB_COMPOSITE_HID_KEYBOARD_DEMO 0 -#endif - -// - -// HID Generic Support -// usb_composite_hid_generic_support -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_EN -#define CONF_USB_COMPOSITE_HID_GENERIC_EN 0 -#endif - -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN -#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT_LEN 53 -#endif - -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_REPORT -#define CONF_USB_COMPOSITE_HID_GENERIC_REPORT \ - 0x06, 0xFF, 0xFF, 0x09, 0x01, 0xA1, 0x01, 0x09, 0x02, 0x09, 0x03, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, \ - 0x40, 0x81, 0x02, 0x09, 0x04, 0x09, 0x05, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x40, 0x91, 0x02, \ - 0x09, 0x06, 0x09, 0x07, 0x15, 0x00, 0x26, 0xFF, 0x00, 0x75, 0x08, 0x95, 0x04, 0xB1, 0x02, 0xC0 -#endif - -// HID Generic INTERRUPT IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_hid_generic_intin_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR -#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_EPADDR 0x85 -#endif - -// HID Generic INTERRUPT IN Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_hid_generic_intin_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_GENERIC_INTIN_MAXPKSZ 0x40 -#endif - -// HID Generic INTERRUPT OUT Endpoint Address -// <0x01=> EndpointAddress = 0x01 -// <0x02=> EndpointAddress = 0x02 -// <0x03=> EndpointAddress = 0x03 -// <0x04=> EndpointAddress = 0x04 -// <0x05=> EndpointAddress = 0x05 -// <0x06=> EndpointAddress = 0x06 -// <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_hid_generic_intout_epaddr -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR -#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_EPADDR 0x3 -#endif - -// HID Generic INTERRUPT OUT Endpoint wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes -// usb_composite_hid_generic_intout_maxpksz -// Please make sure that the setting here is coincide with the endpoint setting in USB device driver. -#ifndef CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ -#define CONF_USB_COMPOSITE_HID_GENERIC_INTOUT_MAXPKSZ 0x40 -#endif - -// - -// MSC Support -// usb_composite_msc_support -#ifndef CONF_USB_COMPOSITE_MSC_EN -#define CONF_USB_COMPOSITE_MSC_EN 0 -#endif - -// MSC BULK Endpoints wMaxPacketSize -// <0x0008=> 8 bytes -// <0x0010=> 16 bytes -// <0x0020=> 32 bytes -// <0x0040=> 64 bytes - -// usb_composite_msc_bulk_maxpksz -#ifndef CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ -#define CONF_USB_COMPOSITE_MSC_BULK_MAXPKSZ 0x40 -#endif - -// MSC BULK IN Endpoint Address -// <0x81=> EndpointAddress = 0x81 -// <0x82=> EndpointAddress = 0x82 -// <0x83=> EndpointAddress = 0x83 -// <0x84=> EndpointAddress = 0x84 -// <0x85=> EndpointAddress = 0x85 -// <0x86=> EndpointAddress = 0x86 -// <0x87=> EndpointAddress = 0x87 -// <0x88=> EndpointAddress = 0x88 -// <0x89=> EndpointAddress = 0x89 - -// usb_composite_msc_bulkin_epaddr -#ifndef CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR -#define CONF_USB_COMPOSITE_MSC_BULKIN_EPADDR 0x86 -#endif - -// MSC BULK OUT Endpoint Address -// <0x01=> EndpointAddress = 0x01 -// <0x02=> EndpointAddress = 0x02 -// <0x03=> EndpointAddress = 0x03 -// <0x04=> EndpointAddress = 0x04 -// <0x05=> EndpointAddress = 0x05 -// <0x06=> EndpointAddress = 0x06 -// <0x07=> EndpointAddress = 0x07 -// <0x08=> EndpointAddress = 0x08 -// <0x09=> EndpointAddress = 0x09 - -// usb_composite_msc_bulkout_epaddr -#ifndef CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR -#define CONF_USB_COMPOSITE_MSC_BULKOUT_EPADDR 0x4 -#endif - -// Enable Demo code for Disk LUN handling -// usb_composite_msc_demo_en -#ifndef CONF_USB_COMPOSITE_MSC_LUN_DEMO -#define CONF_USB_COMPOSITE_MSC_LUN_DEMO 1 -#endif - -// Disk access cache/buffer of sectors if non-RAM disk enabled <1-64> -// conf_usb_msc_lun_buf_sectors -#ifndef CONF_USB_MSC_LUN_BUF_SECTORS -#define CONF_USB_MSC_LUN_BUF_SECTORS 4 -#endif - -// Enable Demo for RAM Disk -// conf_usb_msc_lun0_enable -#ifndef CONF_USB_MSC_LUN0_ENABLE -#define CONF_USB_MSC_LUN0_ENABLE 1 -#endif - -#ifndef CONF_USB_MSC_LUN0_TYPE -#define CONF_USB_MSC_LUN0_TYPE 0x00 -#endif - -// The disk is removable -// conf_usb_msc_lun0_rmb -#ifndef CONF_USB_MSC_LUN0_RMB -#define CONF_USB_MSC_LUN0_RMB 0x1 -#endif - -#ifndef CONF_USB_MSC_LUN0_ISO -#define CONF_USB_MSC_LUN0_ISO 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN0_ECMA -#define CONF_USB_MSC_LUN0_ECMA 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN0_ANSI -#define CONF_USB_MSC_LUN0_ANSI 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN0_REPO -#define CONF_USB_MSC_LUN0_REPO 0x01 -#endif - -#ifndef CONF_USB_MSC_LUN0_FACTORY -#define CONF_USB_MSC_LUN0_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN0_PRODUCT -#define CONF_USB_MSC_LUN0_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN0_PRODUCT_VERSION -#define CONF_USB_MSC_LUN0_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 -#endif - -// Disk Size (in KB) <1-65535> -// Windows will not show disk less than 20K, so 22K is used to reserve more RAM for app -// conf_usb_msc_lun0_capacity - -#ifndef CONF_USB_MSC_LUN0_CAPACITY -#define CONF_USB_MSC_LUN0_CAPACITY 0x16 -#endif - -#ifndef CONF_USB_MSC_LUN0_BLOCK_SIZE -#define CONF_USB_MSC_LUN0_BLOCK_SIZE 512 -#endif - -#ifndef CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR -#define CONF_USB_MSC_LUN0_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN0_CAPACITY * 1024 / CONF_USB_MSC_LUN0_BLOCK_SIZE - 1) -#endif - -// - -// Enable Demo for SD/MMC Disk -// SD/MMC stack must be added before enable SD/MMC demo -// SD/MMC insert/eject not supported by this simple demo -// conf_usb_msc_lun1_enable -#ifndef CONF_USB_MSC_LUN1_ENABLE -#define CONF_USB_MSC_LUN1_ENABLE 0 -#endif - -#ifndef CONF_USB_MSC_LUN1_TYPE -#define CONF_USB_MSC_LUN1_TYPE 0x00 -#endif - -// The disk is removable -// SD/MMC stack must be added before enable SD/MMC demo -// SD/MMC insert/eject not supported by this simple demo -// conf_usb_msc_lun1_rmb -#ifndef CONF_USB_MSC_LUN1_RMB -#define CONF_USB_MSC_LUN1_RMB 0x1 -#endif - -#ifndef CONF_USB_MSC_LUN1_ISO -#define CONF_USB_MSC_LUN1_ISO 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_ECMA -#define CONF_USB_MSC_LUN1_ECMA 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_ANSI -#define CONF_USB_MSC_LUN1_ANSI 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_REPO -#define CONF_USB_MSC_LUN1_REPO 0x01 -#endif - -#ifndef CONF_USB_MSC_LUN1_FACTORY -#define CONF_USB_MSC_LUN1_FACTORY 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_PRODUCT -#define CONF_USB_MSC_LUN1_PRODUCT 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_PRODUCT_VERSION -#define CONF_USB_MSC_LUN1_PRODUCT_VERSION 0x00, 0x00, 0x00, 0x00 -#endif - -#ifndef CONF_USB_MSC_LUN1_CAPACITY -#define CONF_USB_MSC_LUN1_CAPACITY 0x16 -#endif - -#ifndef CONF_USB_MSC_LUN1_BLOCK_SIZE -#define CONF_USB_MSC_LUN1_BLOCK_SIZE 512 -#endif - -#ifndef CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR -#define CONF_USB_MSC_LUN1_LAST_BLOCK_ADDR \ - ((uint32_t)CONF_USB_MSC_LUN1_CAPACITY * 1024 / CONF_USB_MSC_LUN1_BLOCK_SIZE - 1) -#endif - -// - -// -// - -// <<< end of configuration section >>> - -#endif // USBD_COMPOSITE_CONFIG_H diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.c b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.c deleted file mode 100644 index 2c7cd3584..000000000 --- a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.c +++ /dev/null @@ -1,358 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Generic Function Implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hiddf_generic.h" -#include - -#define HIDDF_GENERIC_VERSION 0x00000001u - -/** USB Device HID Generic Function Specific Data */ -struct hiddf_generic_func_data { - /** HID Device Generic Interface information */ - uint8_t func_iface; - /** HID Device Generic IN Endpoint */ - uint8_t func_ep_in; - /** HID Device Generic OUT Endpoint */ - uint8_t func_ep_out; - /** HID Device Generic Report Descriptor */ - const uint8_t *report_desc; - /** HID Device Generic Report Descriptor Length */ - uint32_t report_desc_len; - /** HID Device Generic Enable Flag */ - bool enabled; -}; - -/* USB Device HID Generic Function Instance */ -static struct usbdf_driver _hiddf_generic; - -/* USB Device HID Generic Function Data Instance */ -static struct hiddf_generic_func_data _hiddf_generic_funcd; - -/* USB Device HID Generic Set Report Function Callback */ -static hiddf_generic_set_report_t hiddf_generic_set_report = NULL; - -/** - * \brief Enable HID Generic Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB interface descriptor - * \return Operation status. - */ -static int32_t hid_generic_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - uint8_t * ifc, *ep, i; - usb_iface_desc_t ifc_desc; - usb_ep_desc_t ep_desc; - - struct hiddf_generic_func_data *func_data = (struct hiddf_generic_func_data *)(drv->func_data); - - ifc = desc->sod; - if (NULL == ifc) { - return ERR_NOT_FOUND; - } - - ifc_desc.bInterfaceNumber = ifc[2]; - ifc_desc.bInterfaceClass = ifc[5]; - - if (HID_CLASS == ifc_desc.bInterfaceClass) { - if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized - return ERR_ALREADY_INITIALIZED; - } else if (func_data->func_iface != 0xFF) { // Occupied - return ERR_NO_RESOURCE; - } else { - func_data->func_iface = ifc_desc.bInterfaceNumber; - } - } else { // Not supported by this function driver - return ERR_NOT_FOUND; - } - - // Install endpoints - for (i = 0; i < 2; i++) { - ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); - desc->sod = ep; - if (NULL != ep) { - ep_desc.bEndpointAddress = ep[2]; - ep_desc.bmAttributes = ep[3]; - ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); - if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { - return ERR_NOT_INITIALIZED; - } - if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { - func_data->func_ep_in = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_in); - } else { - func_data->func_ep_out = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_out); - } - } else { - return ERR_NOT_FOUND; - } - } - - // Installed - _hiddf_generic_funcd.enabled = true; - return ERR_NONE; -} - -/** - * \brief Disable HID Generic Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB device descriptor - * \return Operation status. - */ -static int32_t hid_generic_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct hiddf_generic_func_data *func_data = (struct hiddf_generic_func_data *)(drv->func_data); - - usb_iface_desc_t ifc_desc; - - if (desc) { - ifc_desc.bInterfaceClass = desc->sod[5]; - if (ifc_desc.bInterfaceClass != HID_CLASS) { - return ERR_NOT_FOUND; - } - } - - if (func_data->func_iface != 0xFF) { - func_data->func_iface = 0xFF; - } - - if (func_data->func_ep_in != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_in); - func_data->func_ep_in = 0xFF; - } - - if (func_data->func_ep_out != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_out); - func_data->func_ep_out = 0xFF; - } - - _hiddf_generic_funcd.enabled = false; - return ERR_NONE; -} - -/** - * \brief HID Generic Control Function - * \param[in] drv Pointer to USB device function driver - * \param[in] ctrl USB device general function control type - * \param[in] param Parameter pointer - * \return Operation status. - */ -static int32_t hid_generic_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) -{ - switch (ctrl) { - case USBDF_ENABLE: - return hid_generic_enable(drv, (struct usbd_descriptors *)param); - - case USBDF_DISABLE: - return hid_generic_disable(drv, (struct usbd_descriptors *)param); - - case USBDF_GET_IFACE: - return ERR_UNSUPPORTED_OP; - - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class get descriptor - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_generic_get_desc(uint8_t ep, struct usb_req *req) -{ - switch (req->wValue >> 8) { - case USB_DT_HID_REPORT: - return usbdc_xfer(ep, (uint8_t *)_hiddf_generic_funcd.report_desc, _hiddf_generic_funcd.report_desc_len, false); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_generic_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - uint8_t *ctrl_buf = usbdc_get_ctrl_buffer(); - uint16_t len = req->wLength; - - if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_generic_funcd.func_iface)) { - return hid_generic_get_desc(ep, req); - } else { - if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request - return ERR_NOT_FOUND; - } - if (req->wIndex == _hiddf_generic_funcd.func_iface) { - if (req->bmRequestType & USB_EP_DIR_IN) { - return ERR_INVALID_ARG; - } else { - if (USB_REQ_HID_SET_REPORT == req->bRequest) { - if (USB_SETUP_STAGE == stage) { - return usbdc_xfer(ep, ctrl_buf, len, false); - } else { - if (NULL != hiddf_generic_set_report) { - hiddf_generic_set_report(ctrl_buf, len); - } - return ERR_NONE; - } - } else { - return usbdc_xfer(0, NULL, 0, 0); - } - } - } else { - return ERR_NOT_FOUND; - } - } -} - -/** USB Device HID Generic Handler Struct */ -static struct usbdc_handler hid_generic_req_h = {NULL, (FUNC_PTR)hid_generic_req}; - -/** - * \brief Initialize the USB HID Generic Function Driver - */ -int32_t hiddf_generic_init(const uint8_t *report_desc, uint32_t len) -{ - if (NULL == report_desc || 0 == len) { - return ERR_INVALID_ARG; - } - - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_generic_funcd.report_desc = report_desc; - _hiddf_generic_funcd.report_desc_len = len; - _hiddf_generic.ctrl = hid_generic_ctrl; - _hiddf_generic.func_data = &_hiddf_generic_funcd; - - usbdc_register_function(&_hiddf_generic); - usbdc_register_handler(USBDC_HDL_REQ, &hid_generic_req_h); - - return ERR_NONE; -} - -/** - * \brief Deinitialize the USB HID Generic Function Driver - */ -int32_t hiddf_generic_deinit(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_generic.ctrl = NULL; - _hiddf_generic.func_data = NULL; - - usbdc_unregister_function(&_hiddf_generic); - usbdc_unregister_handler(USBDC_HDL_REQ, &hid_generic_req_h); - return ERR_NONE; -} - -/** - * \brief Check whether HID Generic Function is enabled - */ -bool hiddf_generic_is_enabled(void) -{ - return _hiddf_generic_funcd.enabled; -} - -/** - * \brief USB HID Generic Function Read Data - */ -int32_t hiddf_generic_read(uint8_t *buf, uint32_t size) -{ - if (!hiddf_generic_is_enabled()) { - return ERR_DENIED; - } - return usbdc_xfer(_hiddf_generic_funcd.func_ep_out, buf, size, false); -} - -/** - * \brief USB HID Generic Function Write Data - */ -int32_t hiddf_generic_write(uint8_t *buf, uint32_t size) -{ - if (!hiddf_generic_is_enabled()) { - return ERR_DENIED; - } - return usbdc_xfer(_hiddf_generic_funcd.func_ep_in, buf, size, false); -} - -/** - * \brief USB HID Generic Function Register Callback - */ -int32_t hiddf_generic_register_callback(enum hiddf_generic_cb_type cb_type, FUNC_PTR func) -{ - if (!hiddf_generic_is_enabled()) { - return ERR_DENIED; - } - switch (cb_type) { - case HIDDF_GENERIC_CB_READ: - usb_d_ep_register_callback(_hiddf_generic_funcd.func_ep_out, USB_D_EP_CB_XFER, func); - break; - case HIDDF_GENERIC_CB_WRITE: - usb_d_ep_register_callback(_hiddf_generic_funcd.func_ep_in, USB_D_EP_CB_XFER, func); - break; - case HIDDF_GENERIC_CB_SET_REPORT: - hiddf_generic_set_report = (hiddf_generic_set_report_t)func; - break; - default: - return ERR_INVALID_ARG; - } - - return ERR_NONE; -} - -/** - * \brief Return version - */ -uint32_t hiddf_generic_get_version(void) -{ - return HIDDF_GENERIC_VERSION; -} diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.h b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.h deleted file mode 100644 index c12f1575a..000000000 --- a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_generic.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Generic Function Definition. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_HID_GENERIC_H_ -#define USBDF_HID_GENERIC_H_ - -#include "usbdc.h" -#include "usb_protocol_hid.h" - -/** HID Generic Callback Type */ -enum hiddf_generic_cb_type { HIDDF_GENERIC_CB_READ, HIDDF_GENERIC_CB_WRITE, HIDDF_GENERIC_CB_SET_REPORT }; - -/** HID Generic Set Report Callback. */ -typedef bool (*hiddf_generic_set_report_t)(uint8_t *, uint16_t); - -/** - * \brief Initialize the USB HID Generic Function Driver - * \param[in] report_desc Point to usr HID Report Descriptor - * \param[in] len length of usr HID Report Descriptor - * \return Operation status. - */ -int32_t hiddf_generic_init(const uint8_t *report_desc, uint32_t len); - -/** - * \brief Deinitialize the USB HID Generic Function Driver - * \return Operation status. - */ -int32_t hiddf_generic_deinit(void); - -/** - * \brief Check whether HID Generic Function is enabled - * \return Operation status. - * \return true HID Generic Function is enabled - * \return false HID Generic Function is disabled - */ -bool hiddf_generic_is_enabled(void); - -/** - * \brief USB HID Generic Function Read Data - * \param[in] buf Pointer to the buffer which receives data - * \param[in] size the size of data to be received - * \return Operation status. - */ -int32_t hiddf_generic_read(uint8_t *buf, uint32_t size); - -/** - * \brief USB HID Generic Function Write Data - * \param[in] buf Pointer to the buffer which stores data - * \param[in] size the size of data to be sent - * \return Operation status. - */ -int32_t hiddf_generic_write(uint8_t *buf, uint32_t size); - -/** - * \brief USB HID Generic Function Register Callback - * \param[in] cb_type Callback type of HID Generic Function - * \param[in] func Pointer to callback function - * \return Operation status. - */ -int32_t hiddf_generic_register_callback(enum hiddf_generic_cb_type cb_type, FUNC_PTR func); - -/** - * \brief Return version - */ -uint32_t hiddf_generic_get_version(void); - -#endif /* USBDF_HID_GENERIC_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.c b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.c deleted file mode 100644 index 835481e41..000000000 --- a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.c +++ /dev/null @@ -1,365 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Keyboard Function Implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hiddf_keyboard.h" -#include - -#define HIDDF_KEYBOARD_VERSION 0x00000001u - -#define KEYBOARD_REPORT_DESC_LEN 59 - -/** USB Device HID Keyboard Function Specific Data */ -struct hiddf_keyboard_func_data { - /* HID Device Keyboard Report */ - uint8_t kb_report[8]; - /** HID Device Keyboard Interface information */ - uint8_t func_iface; - /** HID Device Keyboard IN Endpoint */ - uint8_t func_ep_in; - /** HID Device Keyboard OUT Endpoint */ - uint8_t func_ep_out; - /** HID Device Keyboard Enable Flag */ - bool enabled; -}; - -/* HID report descriptor for standard HID keyboard */ -const uint8_t keyboard_report_desc[KEYBOARD_REPORT_DESC_LEN] = { - 0x05, 0x01, /* Usage Page (Generic Desktop) */ - 0x09, 0x06, /* Usage (Keyboard) */ - 0xA1, 0x01, /* Collection (Application) */ - 0x05, 0x07, /* Usage Page (Keyboard) */ - 0x19, 0xE0, /* Usage Minimum (224) */ - 0x29, 0xE7, /* Usage Maximum (231) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x08, /* Report Count (8) */ - 0x81, 0x02, /* Input (Data, Variable, Absolute) */ - 0x81, 0x01, /* Input (Constant) */ - 0x19, 0x00, /* Usage Minimum (0) */ - 0x29, 0x65, /* Usage Maximum (101) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x65, /* Logical Maximum (101) */ - 0x75, 0x08, /* Report Size (8) */ - 0x95, 0x06, /* Report Count (6) */ - 0x81, 0x00, /* Input (Data, Array) */ - 0x05, 0x08, /* Usage Page (LED) */ - 0x19, 0x01, /* Usage Minimum (1) */ - 0x29, 0x05, /* Usage Maximum (5) */ - 0x15, 0x00, /* Logical Minimum (0) */ - 0x25, 0x01, /* Logical Maximum (1) */ - 0x75, 0x01, /* Report Size (1) */ - 0x95, 0x05, /* Report Count (5) */ - 0x91, 0x02, /* Output (Data, Variable, Absolute) */ - 0x95, 0x03, /* Report Count (3) */ - 0x91, 0x01, /* Output (Constant) */ - 0xC0 /* End Collection */ -}; - -/* USB Device HID Keyboard Function Instance */ -static struct usbdf_driver _hiddf_keyboard; - -/* USB Device HID Keyboard Function Data Instance */ -static struct hiddf_keyboard_func_data _hiddf_keyboard_funcd; - -/** - * \brief Enable HID Keyboard Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB interface descriptor - * \return Operation status. - */ -static int32_t hid_keyboard_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - uint8_t * ifc, *ep, i; - usb_iface_desc_t ifc_desc; - usb_ep_desc_t ep_desc; - - struct hiddf_keyboard_func_data *func_data = (struct hiddf_keyboard_func_data *)(drv->func_data); - - ifc = desc->sod; - if (NULL == ifc) { - return ERR_NOT_FOUND; - } - - ifc_desc.bInterfaceNumber = ifc[2]; - ifc_desc.bInterfaceClass = ifc[5]; - - if (HID_CLASS == ifc_desc.bInterfaceClass) { - if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized - return ERR_ALREADY_INITIALIZED; - } else if (func_data->func_iface != 0xFF) { // Occupied - return ERR_NO_RESOURCE; - } else { - func_data->func_iface = ifc_desc.bInterfaceNumber; - } - } else { // Not supported by this function driver - return ERR_NOT_FOUND; - } - - // Install endpoints - for (i = 0; i < 2; i++) { - ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); - desc->sod = ep; - if (NULL != ep) { - ep_desc.bEndpointAddress = ep[2]; - ep_desc.bmAttributes = ep[3]; - ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); - if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { - return ERR_NOT_INITIALIZED; - } - if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { - func_data->func_ep_in = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_in); - } else { - func_data->func_ep_out = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_out); - } - } else { - return ERR_NOT_FOUND; - } - } - - // Installed - _hiddf_keyboard_funcd.enabled = true; - return ERR_NONE; -} - -/** - * \brief Disable HID Keyboard Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB device descriptor - * \return Operation status. - */ -static int32_t hid_keyboard_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct hiddf_keyboard_func_data *func_data = (struct hiddf_keyboard_func_data *)(drv->func_data); - - usb_iface_desc_t ifc_desc; - - if (desc) { - ifc_desc.bInterfaceClass = desc->sod[5]; - if (ifc_desc.bInterfaceClass != HID_CLASS) { - return ERR_NOT_FOUND; - } - } - - if (func_data->func_iface != 0xFF) { - func_data->func_iface = 0xFF; - } - - if (func_data->func_ep_in != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_in); - func_data->func_ep_in = 0xFF; - } - - if (func_data->func_ep_out != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_out); - func_data->func_ep_out = 0xFF; - } - - _hiddf_keyboard_funcd.enabled = false; - return ERR_NONE; -} - -/** - * \brief HID Keyboard Control Function - * \param[in] drv Pointer to USB device function driver - * \param[in] ctrl USB device general function control type - * \param[in] param Parameter pointer - * \return Operation status. - */ -static int32_t hid_keyboard_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) -{ - switch (ctrl) { - case USBDF_ENABLE: - return hid_keyboard_enable(drv, (struct usbd_descriptors *)param); - - case USBDF_DISABLE: - return hid_keyboard_disable(drv, (struct usbd_descriptors *)param); - - case USBDF_GET_IFACE: - return ERR_UNSUPPORTED_OP; - - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class get descriptor - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_keyboard_get_desc(uint8_t ep, struct usb_req *req) -{ - switch (req->wValue >> 8) { - case USB_DT_HID_REPORT: - return usbdc_xfer(ep, (uint8_t *)keyboard_report_desc, KEYBOARD_REPORT_DESC_LEN, false); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_keyboard_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_keyboard_funcd.func_iface)) { - return hid_keyboard_get_desc(ep, req); - } else { - if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request - return ERR_NOT_FOUND; - } - if (req->wIndex == _hiddf_keyboard_funcd.func_iface) { - if (req->bmRequestType & USB_EP_DIR_IN) { - return ERR_INVALID_ARG; - } else { - return usbdc_xfer(0, NULL, 0, 0); - } - } else { - return ERR_NOT_FOUND; - } - } - (void)stage; -} - -/** USB Device HID Keyboard Handler Struct */ -static struct usbdc_handler hid_keyboard_req_h = {NULL, (FUNC_PTR)hid_keyboard_req}; - -/** - * \brief Initialize the USB HID Keyboard Function Driver - */ -int32_t hiddf_keyboard_init(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_keyboard.ctrl = hid_keyboard_ctrl; - _hiddf_keyboard.func_data = &_hiddf_keyboard_funcd; - - usbdc_register_function(&_hiddf_keyboard); - usbdc_register_handler(USBDC_HDL_REQ, &hid_keyboard_req_h); - return ERR_NONE; -} - -/** - * \brief Deinitialize the USB HID Keyboard Function Driver - */ -int32_t hiddf_keyboard_deinit(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_keyboard.ctrl = NULL; - _hiddf_keyboard.func_data = NULL; - - usbdc_unregister_function(&_hiddf_keyboard); - usbdc_unregister_handler(USBDC_HDL_REQ, &hid_keyboard_req_h); - return ERR_NONE; -} - -/** - * \brief Check whether HID Keyboard Function is enabled - */ -bool hiddf_keyboard_is_enabled(void) -{ - return _hiddf_keyboard_funcd.enabled; -} - -/** - * \brief Process the HID Keyboard key state change request - * \param keys_desc[] keys_descriptor array for state changing - * \param keys_count total keys amount for state changing - * \return Operation status. - */ -int32_t hiddf_keyboard_keys_state_change(struct hiddf_kb_key_descriptors keys_desc[], uint8_t keys_count) -{ - uint8_t i, j; - uint8_t modifier_keys, regular_keys; - - if (!hiddf_keyboard_is_enabled()) { - return ERR_DENIED; - } - - memset(_hiddf_keyboard_funcd.kb_report, 0x00, 8); - modifier_keys = 0; - - for (i = 0; i < keys_count; i++) { - if (true == keys_desc[i].b_modifier) { - modifier_keys++; - } - } - - regular_keys = keys_count - modifier_keys; - - if (regular_keys > 6) { - memset(&_hiddf_keyboard_funcd.kb_report[2], 0xFF, 6); - } else { - i = 2; - for (j = 0; j < keys_count; j++) { - if (HID_KB_KEY_DOWN == keys_desc[j].state) { - if (true == keys_desc[j].b_modifier) { - _hiddf_keyboard_funcd.kb_report[0] |= keys_desc[j].key_id; - } else { - _hiddf_keyboard_funcd.kb_report[i++] = keys_desc[j].key_id; - } - } - } - } - return usbdc_xfer(_hiddf_keyboard_funcd.func_ep_in, &_hiddf_keyboard_funcd.kb_report[0], 8, false); -} - -/** - * \brief Return version - */ -uint32_t hiddf_keyboard_get_version(void) -{ - return HIDDF_KEYBOARD_VERSION; -} diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.h b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.h deleted file mode 100644 index 3295d1b78..000000000 --- a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_keyboard.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Keyboard Function Definition. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_HID_KEYBOARD_H_ -#define USBDF_HID_KEYBOARD_H_ - -#include "usbdc.h" -#include "usb_protocol_hid.h" - -/** HID Keyboard Class Key State Type */ -enum hiddf_kb_key_state { HID_KB_KEY_UP, HID_KB_KEY_DOWN }; - -/** Describes the USB HID Keyboard Key descriptors. */ -struct hiddf_kb_key_descriptors { - /* HID Key Value, defined in usb_protocol_hid.h */ - uint8_t key_id; - /* Flag whether it is a modifier key */ - bool b_modifier; - /* Key State */ - enum hiddf_kb_key_state state; -}; - -/** - * \brief Initialize the USB HID Keyboard Function Driver - * \return Operation status. - */ -int32_t hiddf_keyboard_init(void); - -/** - * \brief Deinitialize the USB HID Keyboard Function Driver - * \return Operation status. - */ -int32_t hiddf_keyboard_deinit(void); - -/** - * \brief Check whether HID Keyboard Function is enabled - * \return Operation status. - * \return true HID Keyboard Function is enabled - * \return false HID Keyboard Function is disabled - */ -bool hiddf_keyboard_is_enabled(void); - -/** - * \brief Process the HID Keyboard key state change request - * \param keys_desc[] keys_descriptor array for state changing - * \param keys_count total keys amount for state changing - * \return Operation status. - */ -int32_t hiddf_keyboard_keys_state_change(struct hiddf_kb_key_descriptors keys_desc[], uint8_t keys_count); - -/** - * \brief Return version - */ -uint32_t hiddf_keyboard_get_version(void); - -#endif /* USBDF_HID_KEYBOARD_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.c b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.c deleted file mode 100644 index 7a58ce66e..000000000 --- a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.c +++ /dev/null @@ -1,363 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Mouse Function Implementation. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "hiddf_mouse.h" - -#define HIDDF_MOUSE_VERSION 0x00000001u - -#define MOUSE_REPORT_DESC_LEN 52 - -/** USB Device HID Mouse Function Specific Data */ -struct hiddf_mouse_func_data { - /* HID Device Mouse Report */ - union { - /** Interpreted by bytes. */ - struct { - /** Button Status. */ - uint8_t button_state; - /** X Axis Variant.*/ - uint8_t x_axis_var; - /** Y Axis Variant.*/ - uint8_t y_axis_var; - /** Scroll Variant.*/ - uint8_t scroll_var; - } bytes; - uint32_t u32; - } mouse_report; - /** HID Device Mouse Interface information */ - uint8_t func_iface; - /** HID Device Mouse IN Endpoint */ - uint8_t func_ep_in; - /** HID Device Mouse Enable Flag */ - bool enabled; -}; - -/* HID report descriptor for standard HID mouse */ -const uint8_t mouse_report_desc[MOUSE_REPORT_DESC_LEN] = { - 0x05, 0x01, /* Usage Page (Generic Desktop), */ - 0x09, 0x02, /* Usage (Mouse), */ - 0xA1, 0x01, /* Collection (Application), */ - 0x09, 0x01, /* Usage (Pointer), */ - 0xA1, 0x00, /* Collection (Physical), */ - 0x05, 0x09, /* Usage Page (Buttons), */ - 0x19, 0x01, /* Usage Minimum (01), */ - 0x29, 0x03, /* Usage Maximum (03), */ - 0x15, 0x00, /* Logical Minimum (0), */ - 0x25, 0x01, /* Logical Maximum (1), */ - 0x75, 0x01, /* Report Size (1), */ - 0x95, 0x03, /* Report Count (3), */ - 0x81, 0x02, /* Input (Data, Variable, Absolute) */ - 0x75, 0x05, /* Report Size (5), */ - 0x95, 0x01, /* Report Count (1), */ - 0x81, 0x01, /* Input (Constant), */ - 0x05, 0x01, /* Usage Page (Generic Desktop), */ - 0x09, 0x30, /* Usage (X), */ - 0x09, 0x31, /* Usage (Y), */ - 0x09, 0x38, /* Usage (Scroll), */ - 0x15, 0x81, /* Logical Minimum (-127), */ - 0x25, 0x7F, /* Logical Maximum (127), */ - 0x75, 0x08, /* Report Size (8), */ - 0x95, 0x03, /* Report Count (3), */ - 0x81, 0x06, /* Input (Data, Variable, Relative) */ - 0xC0, /* End Collection, */ - 0xC0, /* End Collection */ -}; - -/* USB Device HID Mouse Function Instance */ -static struct usbdf_driver _hiddf_mouse; - -/* USB Device HID Mouse Function Data Instance */ -static struct hiddf_mouse_func_data _hiddf_mouse_funcd; - -/** - * \brief Enable HID Mouse Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB interface descriptor - * \return Operation status. - */ -static int32_t hid_mouse_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - uint8_t * ifc, *ep; - usb_iface_desc_t ifc_desc; - usb_ep_desc_t ep_desc; - - struct hiddf_mouse_func_data *func_data = (struct hiddf_mouse_func_data *)(drv->func_data); - - ifc = desc->sod; - if (NULL == ifc) { - return ERR_NOT_FOUND; - } - - ifc_desc.bInterfaceNumber = ifc[2]; - ifc_desc.bInterfaceClass = ifc[5]; - - if (HID_CLASS == ifc_desc.bInterfaceClass) { - if (func_data->func_iface == ifc_desc.bInterfaceNumber) { // Initialized - return ERR_ALREADY_INITIALIZED; - } else if (func_data->func_iface != 0xFF) { // Occupied - return ERR_NO_RESOURCE; - } else { - func_data->func_iface = ifc_desc.bInterfaceNumber; - } - } else { // Not supported by this function driver - return ERR_NOT_FOUND; - } - - // Install endpoints - ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); - desc->sod = ep; - if (NULL != ep) { - ep_desc.bEndpointAddress = ep[2]; - ep_desc.bmAttributes = ep[3]; - ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); - if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { - return ERR_NOT_INITIALIZED; - } - if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { - func_data->func_ep_in = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_in); - } else { - return ERR_INVALID_DATA; - } - } else { - return ERR_NOT_FOUND; - } - // Installed - _hiddf_mouse_funcd.enabled = true; - return ERR_NONE; -} - -/** - * \brief Disable HID Mouse Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB device descriptor - * \return Operation status. - */ -static int32_t hid_mouse_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct hiddf_mouse_func_data *func_data = (struct hiddf_mouse_func_data *)(drv->func_data); - - usb_iface_desc_t ifc_desc; - - if (desc) { - ifc_desc.bInterfaceClass = desc->sod[5]; - if (ifc_desc.bInterfaceClass != HID_CLASS) { - return ERR_NOT_FOUND; - } - } - - if (func_data->func_iface != 0xFF) { - func_data->func_iface = 0xFF; - } - - if (func_data->func_ep_in != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_in); - func_data->func_ep_in = 0xFF; - } - - _hiddf_mouse_funcd.enabled = false; - return ERR_NONE; -} - -/** - * \brief HID Mouse Control Function - * \param[in] drv Pointer to USB device function driver - * \param[in] ctrl USB device general function control type - * \param[in] param Parameter pointer - * \return Operation status. - */ -static int32_t hid_mouse_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) -{ - switch (ctrl) { - case USBDF_ENABLE: - return hid_mouse_enable(drv, (struct usbd_descriptors *)param); - - case USBDF_DISABLE: - return hid_mouse_disable(drv, (struct usbd_descriptors *)param); - - case USBDF_GET_IFACE: - return ERR_UNSUPPORTED_OP; - - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class get descriptor - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_mouse_get_desc(uint8_t ep, struct usb_req *req) -{ - switch (req->wValue >> 8) { - case USB_DT_HID_REPORT: - return usbdc_xfer(ep, (uint8_t *)mouse_report_desc, MOUSE_REPORT_DESC_LEN, false); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the HID class request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t hid_mouse_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - if ((0x81 == req->bmRequestType) && (0x06 == req->bRequest) && (req->wIndex == _hiddf_mouse_funcd.func_iface)) { - return hid_mouse_get_desc(ep, req); - } else { - if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { // class request - return ERR_NOT_FOUND; - } - if (req->wIndex == _hiddf_mouse_funcd.func_iface) { - if (req->bmRequestType & USB_EP_DIR_IN) { - return ERR_INVALID_ARG; - } else { - return usbdc_xfer(0, NULL, 0, 0); - } - } else { - return ERR_NOT_FOUND; - } - } - (void)stage; -} - -/** USB Device HID Mouse Handler Struct */ -static struct usbdc_handler hid_mouse_req_h = {NULL, (FUNC_PTR)hid_mouse_req}; - -/** - * \brief Initialize the USB HID Mouse Function Driver - */ -int32_t hiddf_mouse_init(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_mouse.ctrl = hid_mouse_ctrl; - _hiddf_mouse.func_data = &_hiddf_mouse_funcd; - - usbdc_register_function(&_hiddf_mouse); - usbdc_register_handler(USBDC_HDL_REQ, &hid_mouse_req_h); - return ERR_NONE; -} - -/** - * \brief Deinitialize the USB HID Mouse Function Driver - */ -int32_t hiddf_mouse_deinit(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _hiddf_mouse.ctrl = NULL; - _hiddf_mouse.func_data = NULL; - - usbdc_unregister_function(&_hiddf_mouse); - usbdc_unregister_handler(USBDC_HDL_REQ, &hid_mouse_req_h); - return ERR_NONE; -} - -/** - * \brief Check whether HID Mouse Function is enabled - */ -bool hiddf_mouse_is_enabled(void) -{ - return _hiddf_mouse_funcd.enabled; -} - -/** - * \brief Move the mouse pointer - * \param pos Signed value to move - * \param type HID mouse class pointer move type - * \return Operation status. - */ -int32_t hiddf_mouse_move(int8_t pos, enum hiddf_mouse_move_type type) -{ - - _hiddf_mouse_funcd.mouse_report.u32 = 0; - - if (type == HID_MOUSE_X_AXIS_MV) { - _hiddf_mouse_funcd.mouse_report.bytes.x_axis_var = pos; - } else if (type == HID_MOUSE_Y_AXIS_MV) { - _hiddf_mouse_funcd.mouse_report.bytes.y_axis_var = pos; - } else if (type == HID_MOUSE_SCROLL_MV) { - _hiddf_mouse_funcd.mouse_report.bytes.scroll_var = pos; - } else { - return ERR_INVALID_ARG; - } - - return usbdc_xfer(_hiddf_mouse_funcd.func_ep_in, &_hiddf_mouse_funcd.mouse_report.bytes.button_state, 4, false); -} - -/** - * \brief Changes button state - * \param b_state New button state - * \param type Button type - * \return Operation status. - */ -int32_t hiddf_mouse_button_change(enum hiddf_mouse_button_state b_state, enum hiddf_mouse_button_type type) -{ - _hiddf_mouse_funcd.mouse_report.u32 = 0; - - if (b_state == HID_MOUSE_BTN_DOWN) { - _hiddf_mouse_funcd.mouse_report.bytes.button_state = type; - } else { - _hiddf_mouse_funcd.mouse_report.bytes.button_state = 0x00; - } - - return usbdc_xfer(_hiddf_mouse_funcd.func_ep_in, &_hiddf_mouse_funcd.mouse_report.bytes.button_state, 4, false); -} - -/** - * \brief Return version - */ -uint32_t hiddf_mouse_get_version(void) -{ - return HIDDF_MOUSE_VERSION; -} diff --git a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.h b/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.h deleted file mode 100644 index 464b1e92d..000000000 --- a/atmel-samd/asf4/samd51/usb/class/hid/device/hiddf_mouse.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack HID Mouse Function Definition. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_HID_MOUSE_H_ -#define USBDF_HID_MOUSE_H_ - -#include "usbdc.h" -#include "usb_protocol_hid.h" - -/** HID Mouse Class Button State Type */ -enum hiddf_mouse_button_state { HID_MOUSE_BTN_UP, HID_MOUSE_BTN_DOWN }; - -/* HID Mosue Class Button Type */ -enum hiddf_mouse_button_type { HID_MOUSE_LEFT_BTN = 0x01, HID_MOUSE_RIGHT_BTN = 0x02, HID_MOUSE_MIDDLE_BTN = 0x04 }; - -/* HID Mouse Class Pointer Move Type */ -enum hiddf_mouse_move_type { HID_MOUSE_X_AXIS_MV = 0x01, HID_MOUSE_Y_AXIS_MV = 0x02, HID_MOUSE_SCROLL_MV = 0x03 }; - -/** - * \brief Initialize the USB HID Mouse Function Driver - * \return Operation status. - */ -int32_t hiddf_mouse_init(void); - -/** - * \brief Deinitialize the USB HID Mouse Function Driver - * \return Operation status. - */ -int32_t hiddf_mouse_deinit(void); - -/** - * \brief Check whether HID Mouse Function is enabled - * \return Operation status. - * \return true HID Mouse Function is enabled - * \return false HID Mouse Function is disabled - */ -bool hiddf_mouse_is_enabled(void); - -/** - * \brief Move the mouse pointer - * \param pos Signed value to move - * \param type HID mouse class pointer move type - * \return Operation status. - */ -int32_t hiddf_mouse_move(int8_t pos, enum hiddf_mouse_move_type type); - -/** - * \brief Changes button state - * \param b_state New button state - * \param type Button type - * \return Operation status. - */ -int32_t hiddf_mouse_button_change(enum hiddf_mouse_button_state b_state, enum hiddf_mouse_button_type type); - -/** - * \brief Return version - */ -uint32_t hiddf_mouse_get_version(void); - -#endif /* USBDF_CDC_ACM_SER_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/hid/usb_protocol_hid.h b/atmel-samd/asf4/samd51/usb/class/hid/usb_protocol_hid.h deleted file mode 100644 index 71d74e632..000000000 --- a/atmel-samd/asf4/samd51/usb/class/hid/usb_protocol_hid.h +++ /dev/null @@ -1,597 +0,0 @@ -/** - * \file - * - * \brief USB Human Interface Device (HID) protocol definitions. - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _USB_PROTOCOL_HID_H_ -#define _USB_PROTOCOL_HID_H_ - -#include "usb_includes.h" - -/** - * \ingroup usb_protocol_group - * \defgroup usb_hid_protocol USB Human Interface Device (HID) - * protocol definitions - * \brief USB Human Interface Device (HID) protocol definitions - * - * @{ - */ - -//! \name Possible Class value -//@{ -#define HID_CLASS 0x03 -//@} - -//! \name Possible SubClass value -//@{ -//! Interface subclass NO support BOOT protocol -#define HID_SUB_CLASS_NOBOOT 0x00 -//! Interface subclass support BOOT protocol -#define HID_SUB_CLASS_BOOT 0x01 -//@} - -//! \name Possible protocol value -//@{ -//! Protocol generic standard -#define HID_PROTOCOL_GENERIC 0x00 -//! Protocol keyboard standard -#define HID_PROTOCOL_KEYBOARD 0x01 -//! Protocol mouse standard -#define HID_PROTOCOL_MOUSE 0x02 -//@} - -//! \brief Hid USB requests (bRequest) - -#define USB_REQ_HID_GET_REPORT 0x01 -#define USB_REQ_HID_GET_IDLE 0x02 -#define USB_REQ_HID_GET_PROTOCOL 0x03 -#define USB_REQ_HID_SET_REPORT 0x09 -#define USB_REQ_HID_SET_IDLE 0x0A -#define USB_REQ_HID_SET_PROTOCOL 0x0B - -//! \brief HID USB descriptor types -#define USB_DT_HID 0x21 -#define USB_DT_HID_REPORT 0x22 -#define USB_DT_HID_PHYSICAL 0x23 - -//! \brief HID Type for report descriptor -#define USB_HID_ITEM_REPORT_TYPE_MAIN 0 -#define USB_HID_ITEM_REPORT_TYPE_GLOBAL 1 -#define USB_HID_ITEM_REPORT_TYPE_LOCAL 2 -#define USB_HID_ITEM_REPORT_TYPE_LONG 3 - -//! \brief HID report type -#define USB_HID_REPORT_TYPE_INPUT 1 -#define USB_HID_REPORT_TYPE_OUTPUT 2 -#define USB_HID_REPORT_TYPE_FEATURE 3 - -//! \brief HID protocol -#define USB_HID_PROCOTOL_BOOT 0 -#define USB_HID_PROCOTOL_REPORT 1 - -#define USB_HID_DESC_BYTES(bLength, bCountryCode, bNumDescriptors, bDescriptorType, bDescriptorLength) \ - bLength, 0x21, 0x10, 0x01, bCountryCode, bNumDescriptors, bDescriptorType, LE_BYTE0(bDescriptorLength), \ - LE_BYTE1(bDescriptorLength) - -COMPILER_PACK_SET(1) - -//! \brief HID Descriptor -typedef struct usb_hid_descriptor { - uint8_t bLength; //!< Size of this descriptor in bytes - uint8_t bDescriptorType; //!< HID descriptor type - le16_t bcdHID; //!< Binary Coded Decimal Spec. release - uint8_t bCountryCode; //!< Hardware target country - uint8_t bNumDescriptors; //!< Number of HID class descriptors to follow - uint8_t bRDescriptorType; //!< Report descriptor type - le16_t wDescriptorLength; //!< Total length of Report descriptor -} usb_hid_descriptor_t; - -COMPILER_PACK_RESET() - -//! \name HID Report type -//! Used by SETUP_HID_GET_REPORT & SETUP_HID_SET_REPORT -//! @{ -#define REPORT_TYPE_INPUT 0x01 -#define REPORT_TYPE_OUTPUT 0x02 -#define REPORT_TYPE_FEATURE 0x03 -//! @} - -//! \name Constants of field DESCRIPTOR_HID -//! @{ -//! Numeric expression identifying the HID Class -//! Specification release (here V1.11) -#define USB_HID_BDC_V1_11 0x0111 -//! Numeric expression specifying the number of class descriptors -//! Note: Always at least one i.e. Report descriptor. -#define USB_HID_NUM_DESC 0x01 - -//! \name Country code -//! @{ -#define USB_HID_NO_COUNTRY_CODE 0 // Not Supported -#define USB_HID_COUNTRY_ARABIC 1 // Arabic -#define USB_HID_COUNTRY_BELGIAN 2 // Belgian -#define USB_HID_COUNTRY_CANADIAN_BILINGUAL 3 // Canadian-Bilingual -#define USB_HID_COUNTRY_CANADIAN_FRENCH 4 // Canadian-French -#define USB_HID_COUNTRY_CZECH_REPUBLIC 5 // Czech Republic -#define USB_HID_COUNTRY_DANISH 6 // Danish -#define USB_HID_COUNTRY_FINNISH 7 // Finnish -#define USB_HID_COUNTRY_FRENCH 8 // French -#define USB_HID_COUNTRY_GERMAN 9 // German -#define USB_HID_COUNTRY_GREEK 10 // Greek -#define USB_HID_COUNTRY_HEBREW 11 // Hebrew -#define USB_HID_COUNTRY_HUNGARY 12 // Hungary -#define USB_HID_COUNTRY_INTERNATIONAL_ISO 13 // International (ISO) -#define USB_HID_COUNTRY_ITALIAN 14 // Italian -#define USB_HID_COUNTRY_JAPAN_KATAKANA 15 // Japan (Katakana) -#define USB_HID_COUNTRY_KOREAN 16 // Korean -#define USB_HID_COUNTRY_LATIN_AMERICAN 17 // Latin American -#define USB_HID_COUNTRY_NETHERLANDS_DUTCH 18 // Netherlands/Dutch -#define USB_HID_COUNTRY_NORWEGIAN 19 // Norwegian -#define USB_HID_COUNTRY_PERSIAN_FARSI 20 // Persian (Farsi) -#define USB_HID_COUNTRY_POLAND 21 // Poland -#define USB_HID_COUNTRY_PORTUGUESE 22 // Portuguese -#define USB_HID_COUNTRY_RUSSIA 23 // Russia -#define USB_HID_COUNTRY_SLOVAKIA 24 // Slovakia -#define USB_HID_COUNTRY_SPANISH 25 // Spanish -#define USB_HID_COUNTRY_SWEDISH 26 // Swedish -#define USB_HID_COUNTRY_SWISS_FRENCH 27 // Swiss/French -#define USB_HID_COUNTRY_SWISS_GERMAN 28 // Swiss/German -#define USB_HID_COUNTRY_SWITZERLAND 29 // Switzerland -#define USB_HID_COUNTRY_TAIWAN 30 // Taiwan -#define USB_HID_COUNTRY_TURKISH_Q 31 // Turkish-Q -#define USB_HID_COUNTRY_UK 32 // UK -#define USB_HID_COUNTRY_US 33 // US -#define USB_HID_COUNTRY_YUGOSLAVIA 34 // Yugoslavia -#define USB_HID_COUNTRY_TURKISH_F 35 // Turkish-F - //! @} - //! @} -//! @} - -//! \name HID KEYS values -//! @{ -#define HID_A 0x04 -#define HID_B 0x05 -#define HID_C 0x06 -#define HID_D 0x07 -#define HID_E 0x08 -#define HID_F 0x09 -#define HID_G 0x0A -#define HID_H 0x0B -#define HID_I 0x0C -#define HID_J 0x0D -#define HID_K 0x0E -#define HID_L 0x0F -#define HID_M 0x10 -#define HID_N 0x11 -#define HID_O 0x12 -#define HID_P 0x13 -#define HID_Q 0x14 -#define HID_R 0x15 -#define HID_S 0x16 -#define HID_T 0x17 -#define HID_U 0x18 -#define HID_V 0x19 -#define HID_W 0x1A -#define HID_X 0x1B -#define HID_Y 0x1C -#define HID_Z 0x1D -#define HID_1 30 -#define HID_2 31 -#define HID_3 32 -#define HID_4 33 -#define HID_5 34 -#define HID_6 35 -#define HID_7 36 -#define HID_8 37 -#define HID_9 38 -#define HID_0 39 -#define HID_ENTER 40 -#define HID_ESCAPE 41 -#define HID_BACKSPACE 42 -#define HID_TAB 43 -#define HID_SPACEBAR 44 -#define HID_UNDERSCORE 45 -#define HID_PLUS 46 -#define HID_OPEN_BRACKET 47 // { -#define HID_CLOSE_BRACKET 48 // } -#define HID_BACKSLASH 49 -#define HID_ASH 50 // # ~ -#define HID_COLON 51 // ; : -#define HID_QUOTE 52 // ' " -#define HID_TILDE 53 -#define HID_COMMA 54 -#define HID_DOT 55 -#define HID_SLASH 56 -#define HID_CAPS_LOCK 57 -#define HID_F1 58 -#define HID_F2 59 -#define HID_F3 60 -#define HID_F4 61 -#define HID_F5 62 -#define HID_F6 63 -#define HID_F7 64 -#define HID_F8 65 -#define HID_F9 66 -#define HID_F10 67 -#define HID_F11 68 -#define HID_F12 69 -#define HID_PRINTSCREEN 70 -#define HID_SCROLL_LOCK 71 -#define HID_PAUSE 72 -#define HID_INSERT 73 -#define HID_HOME 74 -#define HID_PAGEUP 75 -#define HID_DELETE 76 -#define HID_END 77 -#define HID_PAGEDOWN 78 -#define HID_RIGHT 79 -#define HID_LEFT 80 -#define HID_DOWN 81 -#define HID_UP 82 -#define HID_KEYPAD_NUM_LOCK 83 -#define HID_KEYPAD_DIVIDE 84 -#define HID_KEYPAD_AT 85 -#define HID_KEYPAD_MULTIPLY 85 -#define HID_KEYPAD_MINUS 86 -#define HID_KEYPAD_PLUS 87 -#define HID_KEYPAD_ENTER 88 -#define HID_KEYPAD_1 89 -#define HID_KEYPAD_2 90 -#define HID_KEYPAD_3 91 -#define HID_KEYPAD_4 92 -#define HID_KEYPAD_5 93 -#define HID_KEYPAD_6 94 -#define HID_KEYPAD_7 95 -#define HID_KEYPAD_8 96 -#define HID_KEYPAD_9 97 -#define HID_KEYPAD_0 98 - -//! \name HID modifier values -//! @{ -#define HID_MODIFIER_NONE 0x00 -#define HID_MODIFIER_LEFT_CTRL 0x01 -#define HID_MODIFIER_LEFT_SHIFT 0x02 -#define HID_MODIFIER_LEFT_ALT 0x04 -#define HID_MODIFIER_LEFT_UI 0x08 -#define HID_MODIFIER_RIGHT_CTRL 0x10 -#define HID_MODIFIER_RIGHT_SHIFT 0x20 -#define HID_MODIFIER_RIGHT_ALT 0x40 -#define HID_MODIFIER_RIGHT_UI 0x80 -//! @} -//! @} - -//! \name HID KEYS LED values -//! @{ -#define HID_LED_NUM_LOCK (1 << 0) -#define HID_LED_CAPS_LOCK (1 << 1) -#define HID_LED_SCROLL_LOCK (1 << 2) -#define HID_LED_COMPOSE (1 << 3) -#define HID_LED_KANA (1 << 4) -//! @} - -/** \name Standard HID mouse definitions from HID spec. example */ -/*@{*/ - -/** \brief Structure for standard HID keyboard modified keys */ -typedef union hid_kbd_modifier { - uint8_t byte; - struct { - uint8_t lctrl : 1; /**< Left Ctrl */ - uint8_t lshift : 1; /**< Left Shift */ - uint8_t lalt : 1; /**< Left Alt */ - uint8_t lgui : 1; /**< Left Gui */ - uint8_t rctrl : 1; /**< Right Ctrl */ - uint8_t rshift : 1; /**< Right Shift */ - uint8_t ralt : 1; /**< Right Alt */ - uint8_t rgui : 1; /**< Right Gui */ - } bm; -} hid_kbd_modifier_t; -#define HID_KBD_L_CTRL (1 << 0) /**< Left Ctrl */ -#define HID_KBD_L_SHIFT (1 << 1) /**< Left Shift */ -#define HID_KBD_L_ALT (1 << 2) /**< Left Alt */ -#define HID_KBD_L_GUI (1 << 3) /**< Left Gui */ -#define HID_KBD_R_CTRL (1 << 4) /**< Right Ctrl */ -#define HID_KBD_R_SHIFT (1 << 5) /**< Right Shift */ -#define HID_KBD_R_ALT (1 << 6) /**< Right Alt */ -#define HID_KBD_R_GUI (1 << 7) /**< Right Gui */ - -/** \brief Structure for standard HID keyboard input report */ -typedef union hid_kbd_input_report { - uint8_t byte[8]; - struct { - union hid_kbd_modifier modifier; - uint8_t reserved_oem; - uint8_t key[6]; /** < Key array */ - } field; -} hid_kbd_input_report_t; -/** Access to the modifier keys in HID keyboard report - * \param rpt Pointer to report data of bytes - */ -#define hid_kbd_modifier_keys(rpt) (rpt[0]) -/** Access to the OEM reserved in HID keyboard report - * \param rpt Pointer to report data of bytes - */ -#define hid_kbd_oem(rpt) (rpt[1]) -/** Access to the Key code in HID keyboard report - * \param rpt Pointer to report data of bytes - * \param i Index in the report key array (0~n) - */ -#define hid_kbd_keycode(rpt, i) (rpt[2 + i]) - -/** \brief Structure for standard HID keyboard output report */ -typedef union hid_kbd_output_report { - uint8_t byte; - struct { - uint8_t num_lock : 1; /**< LED of Num Lock */ - uint8_t caps_lock : 1; /**< LED of Caps Lock */ - uint8_t scroll_lock : 1; /**< LED of Scroll Lock */ - uint8_t compose : 1; /**< LED of COMPOSE LOCK */ - uint8_t kana : 1; /**< LED of KANA */ - uint8_t constant : 3; - } field; -} hid_kbd_output_report_t; -#define HID_KBD_NUM_LOCK (1 << 0) /**< LED of Num Lock */ -#define HID_KBD_CAPS_LOCK (1 << 1) /**< LED of Caps Lock */ -#define HID_KBD_SCROLL_LOCK (1 << 2) /**< LED of Scroll Lock */ -#define HID_KBD_COMPOSE (1 << 3) /**< LED of COMPOSE LOCK */ -#define HID_KBD_KANA (1 << 4) /**< LED of KANA */ - -/*@}*/ - -/** \name Standard HID mouse definitions from HID spec. example */ -/*@{*/ -/** \brief Structure for standard HID mouse report */ -typedef union hid_mouse_report { - uint8_t byte[3]; - struct { - uint8_t btn1 : 1; /**< Button 1 */ - uint8_t btn2 : 2; /**< Button 2 */ - uint8_t btn3 : 3; /**< Button 3 */ - uint8_t device_spec : 5; - int8_t x; /**< X displacement */ - int8_t y; /**< Y displacement */ - } field; - /* More bytes are optional */ -} hid_mouse_report_t; -#define HID_MOUSE_BTN1 (1 << 0) /**< Button 1 */ -#define HID_MOUSE_BTN2 (1 << 1) /**< Button 2 */ -#define HID_MOUSE_BTN3 (1 << 2) /**< Button 3 */ - -/** Access to the button state in HID mouse report - * \param rpt Pointer to report data of bytes - */ -#define hid_mouse_btn_state(rpt) (rpt[0]) -/** Check if the button is done in HID mouse report - * \param rpt Pointer to report data of bytes - * \param btn Button bitmap to check - */ -#define hid_mouse_is_btn_down(rpt, btn) (rpt[0] & (btn)) -/** Access to the relative X displacement in HID mouse report - * \param rpt Pointer to report data of bytes - */ -#define hid_mouse_x(rpt) ((int8_t)rpt[1]) -/** Access to the relative Y displacement in HID mouse report - * \param rpt Pointer to report data of bytes - */ -#define hid_mouse_y(rpt) ((int8_t)rpt[2]) - -/*@}*/ - -/** \name Standard HID joystick definitions from HID spec. example */ -/*@{*/ - -/** \brief Structure for standard HID joystick report */ -typedef union hid_joystick_report { - uint8_t byte[4]; - struct { - int8_t x; - int8_t y; - uint8_t hat_sw : 4; /**< Hat switch */ - uint8_t btn1 : 1; /**< Button 1 */ - uint8_t btn2 : 1; /**< Button 2 */ - uint8_t btn3 : 1; /**< Button 3 */ - uint8_t btn4 : 1; /**< Button 4 */ - uint8_t throttle; - } field; -} hid_joystick_report_t; -#define HID_JOYSTICK_BTN1 (1 << 4) /**< Button 1 */ -#define HID_JOYSTICK_BTN2 (1 << 5) /**< Button 2 */ -#define HID_JOYSTICK_BTN3 (1 << 6) /**< Button 3 */ -#define HID_JOYSTICK_BTN4 (1 << 7) /**< Button 4 */ - -/** Access to the absolute X position in HID joystick report - * \param rpt Pointer to report data of bytes - */ -#define hid_joystick_x(rpt) ((int8_t)rpt[0]) -/** Access to the absolute Y position in HID joystick report - * \param rpt Pointer to report data of bytes - */ -#define hid_joystick_y(rpt) ((int8_t)rpt[1]) -/** Access to the button state in HID joystick report - * \param rpt Pointer to report data of bytes - */ -#define hid_joystick_btn_state(rpt) (rpt[2]) -/** Check if the button is done in HID joystick report - * \param rpt Pointer to report data of bytes - * \param btn Button bitmap to check - */ -#define hid_joystick_is_btn_down(rpt, btn) (rpt[2] & (btn)) -/** Get the Hat switch in HID joystick report - * \param rpt Pointer to report data of bytes - */ -#define hid_joystick_hat_sw(rpt) (rpt[2] & 0xF) -/** Access to the throttle in HID joystick report - * \param rpt Pointer to report data of bytes - */ -#define hid_joystick_throttle(rpt) (rpt[3]) - -/*@}*/ - -/** - * \brief Fill a GetHIDDescriptor request - * \param[out] req Pointer to the request to fill - * \param[in] type Descriptor type - * \param[in] index Descriptor index - * \param[in] iface Interface Number - * \param[in] len Descriptor Length - */ -static inline void usb_fill_GetHIDDesc_req(struct usb_req *req, uint8_t type, uint8_t index, uint8_t iface, - uint16_t len) -{ - req->bmRequestType = 0x81; - req->bRequest = USB_REQ_GET_DESC; - req->wValue = (type << 8) | index; - req->wIndex = iface; - req->wLength = len; -} - -/** - * \brief Fill a SetHIDDescriptor request - * \param[out] req Pointer to the request to fill - * \param[in] type Descriptor type - * \param[in] index Descriptor index - * \param[in] iface Interface Number - * \param[in] len Descriptor Length - */ -static inline void usb_fill_SetHIDDesc_req(struct usb_req *req, uint8_t type, uint8_t index, uint8_t iface, - uint16_t len) -{ - req->bmRequestType = 0x01; - req->bRequest = USB_REQ_SET_DESC; - req->wValue = (type << 8) | index; - req->wIndex = iface; - req->wLength = len; -} - -/** - * \brief Fill a GetReport request - * \param[out] req Pointer to the request to fill - * \param[in] type Report type - * \param[in] id Report ID - * \param[in] iface Interface Number - * \param[in] len Report Length - */ -static inline void usb_fill_GetReport_req(struct usb_req *req, uint8_t type, uint8_t id, uint8_t iface, uint16_t len) -{ - req->bmRequestType = 0xA1; - req->bRequest = USB_REQ_HID_GET_REPORT; - req->wValue = (type << 8) | id; - req->wIndex = iface; - req->wLength = len; -} - -/** - * \brief Fill a SetReport request - * \param[out] req Pointer to the request to fill - * \param[in] type Report type - * \param[in] id Report ID - * \param[in] iface Interface Number - * \param[in] len Report Length - */ -static inline void usb_fill_SetReport_req(struct usb_req *req, uint8_t type, uint8_t id, uint8_t iface, uint16_t len) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_HID_GET_REPORT; - req->wValue = (type << 8) | id; - req->wIndex = iface; - req->wLength = len; -} - -/** - * \brief Fill a GetIdle request - * \param[out] req Pointer to the request to fill - * \param[in] id Report ID - * \param[in] iface Interface Number - */ -static inline void usb_fill_GetIdle_req(struct usb_req *req, uint8_t id, uint8_t iface) -{ - req->bmRequestType = 0xA1; - req->bRequest = USB_REQ_HID_GET_IDLE; - req->wValue = id; - req->wIndex = iface; - req->wLength = 1; -} - -/** - * \brief Fill a SetIdle request - * \param[out] req Pointer to the request to fill - * \param[in] duration Duration value - * \param[in] id Report ID - * \param[in] iface Interface Number - */ -static inline void usb_fill_SetIdle_req(struct usb_req *req, uint8_t duration, uint8_t id, uint8_t iface) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_HID_SET_IDLE; - req->wValue = (duration << 8) | id; - req->wIndex = iface; - req->wLength = 0; -} - -/** - * \brief Fill a GetProtocol request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - */ -static inline void usb_fill_GetProtocol_req(struct usb_req *req, uint8_t iface) -{ - req->bmRequestType = 0xA1; - req->bRequest = USB_REQ_HID_GET_PROTOCOL; - req->wValue = 0; - req->wIndex = iface; - req->wLength = 1; -} - -/** - * \brief Fill a SetProtocol request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - */ -static inline void usb_fill_SetProtocol_req(struct usb_req *req, uint8_t protocol, uint8_t iface) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_HID_SET_PROTOCOL; - req->wValue = protocol; - req->wIndex = iface; - req->wLength = 0; -} - -#endif // _USB_PROTOCOL_HID_H_ diff --git a/atmel-samd/asf4/samd51/usb/class/hub/usb_protocol_hub.h b/atmel-samd/asf4/samd51/usb/class/hub/usb_protocol_hub.h deleted file mode 100644 index dbfc04a2c..000000000 --- a/atmel-samd/asf4/samd51/usb/class/hub/usb_protocol_hub.h +++ /dev/null @@ -1,364 +0,0 @@ -/** - * \file - * - * \brief USB hub protocol definitions. - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _USB_PROTOCOL_HUB_H_ -#define _USB_PROTOCOL_HUB_H_ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** \name Possible class value */ -/*@{*/ -#define HUB_CLASS 0x09 -/*@}*/ - -/** \brief Hub USB requests (bRequest) */ -enum usb_reqid_hub { - USB_REQ_HUB_GET_STATUS = 0, - /** CLEAR_FEATURE */ - USB_REQ_HUB_CLR_FTR = 1, - /** SET_FEATURE */ - USB_REQ_HUB_SET_FTR = 3, - /** GET_DESCRIPTOR */ - USB_REQ_HUB_GET_DESC = 6, - /** SET_DESCRIPTOR */ - USB_REQ_HUB_SET_DESC = 7, - /** CLEAR_TT_BUFFER */ - USB_REQ_HUB_CLR_TT_BUF = 8, - /** RESET_TT */ - USB_REQ_HUB_RESET_TT = 9, - /** GET_TT_STATE */ - USB_REQ_HUB_GET_TT_STATE = 10, - /** STOP_TT */ - USB_REQ_HUB_STOP_TT -}; - -/** \brief Hub USB descriptor type */ -enum usb_descriptor_type_hub { USB_DT_HUB = 0x29 }; - -/** \brief Hub feature selector */ -enum usb_hub_ftr_sel { - USB_HUB_FTR_C_HUB_LOCAL_POWER = 0, - USB_HUB_FTR_C_HUB_OVER_CURRENT = 1, - USB_HUB_FTR_PORT_CONNECTION = 0, - USB_HUB_FTR_PORT_ENABLE = 1, - USB_HUB_FTR_PORT_SUSPEND = 2, - USB_HUB_FTR_PORT_OVER_CURRENT = 3, - USB_HUB_FTR_PORT_RESET = 4, - USB_HUB_FTR_PORT_POWER = 8, - USB_HUB_FTR_PORT_LOW_SPEED = 9, - USB_HUB_FTR_PORT_LS = 9, - USB_HUB_FTR_PORT_HIGH_SPEED = 10, - USB_HUB_FTR_PORT_HS = 10, - USB_HUB_FTR_C_PORT_CONNECTION = 16, - USB_HUB_FTR_C_PORT_ENABLE = 17, - USB_HUB_FTR_C_PORT_SUSPEND = 18, - USB_HUB_FTR_C_PORT_OVER_CURRENT = 19, - USB_HUB_FTR_C_PORT_RESET = 20, - USB_HUB_FTR_PORT_TEST = 21, - USB_HUB_FTR_PORT_INDICATOR -}; - -COMPILER_PACK_SET(1) - -/** - * \brief General Hub Descriptor - */ -typedef struct usb_hub_descriptor { - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint16_t wHubCharacteristics; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint32_t variables[1]; -} usb_hub_descriptor_t; - -/** - * \brief Hub Descriptor with no more than 7 ports - */ -typedef struct usb_hub_descriptor_7p { - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint16_t wHubCharacteristics; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint8_t DeviceRemovable[1]; - uint8_t PortPwrCtrlMask[1]; -} usb_hub_descriptor_7p_t; - -/** - * \brief Hub Descriptor with no more than 15 ports - */ -typedef struct usb_hub_descriptor_15p { - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint16_t wHubCharacteristics; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint8_t DeviceRemovable[2]; - uint8_t PortPwrCtrlMask[2]; -} usb_hub_descriptor_15p_t; - -/** - * \brief Hub Descriptor with no more than 23 ports - */ -typedef struct usb_hub_descriptor_23p { - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint16_t wHubCharacteristics; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint8_t DeviceRemovable[3]; - uint8_t PortPwrCtrlMask[3]; -} usb_hub_descriptor_23p_t; - -/** - * \brief Hub Descriptor with no more than 31 ports - */ -typedef struct usb_hub_descriptor_31p { - uint8_t bDescLength; - uint8_t bDescriptorType; - uint8_t bNbrPorts; - uint16_t wHubCharacteristics; - uint8_t bPwrOn2PwrGood; - uint8_t bHubContrCurrent; - uint8_t DeviceRemovable[4]; - uint8_t PortPwrCtrlMask[4]; -} usb_hub_descriptor_31p_t; - -COMPILER_PACK_RESET() - -/** - * \brief Check if hub change is detected - * \param[in] bitmap Pointer to the bitmap location - * \return \c true if hub change is detected - */ -static inline bool usb_is_hub_change_detected(const uint8_t *bitmap) -{ - return (*bitmap & 0x1); -} - -/** - * \brief Check if port change is detected - * \param[in] bitmap Pointer to the bitmap location - * \param[in] port Port number ( 1 ~ n ) - * \return \c true if port change is detected - */ -static inline bool usb_is_port_change_detected(const uint8_t *bitmap, const uint8_t port) -{ - uint8_t idx = port >> 3; - uint8_t pos = port & 0x7; - return (bitmap[idx] & (1u << pos)); -} - -/** - * \brief Fill a ClearHubFeature request - * \param[out] req Pointer to the request to fill - * \param[in] ftr Feature selector - */ -static inline void usb_fill_ClrHubFtr_req(struct usb_req *req, uint8_t ftr) -{ - req->bmRequestType = 0x20; - req->bRequest = USB_REQ_CLEAR_FTR; - req->wValue = ftr; - req->wIndex = 0; - req->wLength = 0; -} - -/** - * \brief Fill a ClearPortFeature request - * \param[out] req Pointer to the request to fill - * \param[in] ftr Feature selector - * \param[in] port Port number ( 1 ~ n ) - */ -static inline void usb_fill_ClrPortFtr_req(struct usb_req *req, uint8_t ftr, uint8_t port) -{ - req->bmRequestType = 0x23; - req->bRequest = USB_REQ_CLEAR_FTR; - req->wValue = ftr; - req->wIndex = port; - req->wLength = 0; -} - -/** - * \brief Fill a ClearTTBuffer request - * \param[out] req Pointer to the request to fill - * \param[in] dev Dev_Addr - * \param[in] ep EP_Num - * \param[in] tt_port TT_port - */ -static inline void usb_fill_ClrTTBuf_req(struct usb_req *req, uint8_t dev, uint8_t ep, uint8_t tt_port) -{ - req->bmRequestType = 0x23; - req->bRequest = USB_REQ_HUB_CLR_TT_BUF; - req->wValue = (dev << 8) | ep; - req->wIndex = tt_port; - req->wLength = 0; -} - -/** - * \brief Fill a GetHubDescriptor request - * \param[out] req Pointer to the request to fill - * \param[in] len Length of available buffer for request data - */ -static inline void usb_fill_GetHubDesc_req(struct usb_req *req, uint16_t len) -{ - req->bmRequestType = 0xA0; - req->bRequest = USB_REQ_GET_DESC; - req->wValue = (USB_DT_HUB << 8) | 0; - req->wIndex = 0; - req->wLength = len; -} - -/** - * \brief Fill a GetHubStatus request - * \param[out] req Pointer to the request to fill - */ -static inline void usb_fill_GetHubStatus_req(struct usb_req *req) -{ - req->bmRequestType = 0xA0; - req->bRequest = USB_REQ_GET_STATUS; - req->wValue = 0; - req->wIndex = 0; - req->wLength = 4; -} - -/** - * \brief Fill a GetPortStatus request - * \param[out] req Pointer to the request to fill - * \param[in] port Port number ( 1 ~ n ) - */ -static inline void usb_fill_GetPortStatus_req(struct usb_req *req, uint8_t port) -{ - req->bmRequestType = 0xA3; - req->bRequest = USB_REQ_GET_STATUS; - req->wValue = 0; - req->wIndex = port; - req->wLength = 4; -} - -/** - * \brief Fill a ResetTT request - * \param[out] req Pointer to the request to fill - * \param[in] port Port number ( 1 ~ n ) - */ -static inline void usb_fill_ResetTT_req(struct usb_req *req, uint8_t port) -{ - req->bmRequestType = 0x23; - req->bRequest = USB_REQ_HUB_RESET_TT; - req->wValue = 0; - req->wIndex = port; - req->wLength = 0; -} - -/** - * \brief Fill a SetHubFeature request - * \param[out] req Pointer to the request to fill - * \param[in] ftr Feature selector - */ -static inline void usb_fill_SetHubFtr_req(struct usb_req *req, uint8_t ftr) -{ - req->bmRequestType = 0x20; - req->bRequest = USB_REQ_SET_FTR; - req->wValue = ftr; - req->wIndex = 0; - req->wLength = 0; -} - -/** - * \brief Fill a SetPortFeature request - * \param[out] req Pointer to the request to fill - * \param[in] ftr Feature selector - * \param[in] port Port number ( 1 ~ n ) - */ -static inline void usb_fill_SetPortFtr_req(struct usb_req *req, uint8_t ftr, uint8_t port) -{ - req->bmRequestType = 0x23; - req->bRequest = USB_REQ_SET_FTR; - req->wValue = ftr; - req->wIndex = port; - req->wLength = 0; -} - -/** - * \brief Fill a GetTTState request - * \param[out] req Pointer to the request to fill - * \param[in] tt_flags TT_Flags - * \param[in] port Port number ( 1 ~ n ) - * \param[in] len TT State Length - */ -static inline void usb_fill_GetTTState_req(struct usb_req *req, uint16_t tt_flags, uint8_t port, uint16_t len) -{ - req->bmRequestType = 0xA3; - req->bRequest = USB_REQ_HUB_GET_TT_STATE; - req->wValue = tt_flags; - req->wIndex = port; - req->wLength = len; -} - -/** - * \brief Fill a StopTT request - * \param[out] req Pointer to the request to fill - * \param[in] port Port number ( 1 ~ n ) - */ -static inline void usb_fill_StopTT_req(struct usb_req *req, uint8_t port) -{ - req->bmRequestType = 0x23; - req->bRequest = USB_REQ_HUB_STOP_TT; - req->wValue = 0; - req->wIndex = port; - req->wLength = 0; -} - -#ifdef __cplusplus -} -#endif - -#endif /* _USB_PROTOCOL_HUB_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.c b/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.c deleted file mode 100644 index b398ba609..000000000 --- a/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.c +++ /dev/null @@ -1,754 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack MSC Function Implementation. - * - * Copyright (C) 2016 - 2017 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "mscdf.h" -#include - -#define MSCDF_VERSION 0x00000001u - -#define ERR_RPT_ZLP 0 /* Uses ZLP on IN error case */ - -/** MSC Class Transfer Stage Type */ -enum mscdf_xfer_stage_type { MSCDF_CMD_STAGE, MSCDF_DATA_STAGE, MSCDF_STATUS_STAGE }; - -/** USB Device MSC Function Specific Data */ -struct mscdf_func_data { - /** MSC Device Interface information */ - uint8_t func_iface; - /** MSC Device IN Endpoint */ - uint8_t func_ep_in; - /** MSC Device OUT Endpoint */ - uint8_t func_ep_out; - /** MSC Device Max LUN */ - uint8_t func_max_lun; - /** MSC Transfer Block Address */ - uint8_t *xfer_blk_addr; - /** MSC Transfer Block Size */ - uint32_t xfer_blk_size; - /** MSC Transfer Total Bytes */ - uint32_t xfer_tot_bytes; - /** MSC Transfer Stage */ - enum mscdf_xfer_stage_type xfer_stage; - /** MSC Transfer Busy Flag */ - bool xfer_busy; - /** MSC Device Enable Flag */ - bool enabled; -}; - -static struct usbdf_driver _mscdf; -static struct mscdf_func_data _mscdf_funcd; - -/* If callbacks are not registered: - * - Return default inquiry information - * - Return NOT FOUND for all other CBW - */ -static mscdf_inquiry_disk_t mscdf_inquiry_disk = NULL; -static mscdf_get_disk_capacity_t mscdf_get_disk_capacity = NULL; -static mscdf_eject_disk_t mscdf_eject_disk = NULL; -static mscdf_start_read_disk_t mscdf_read_disk = NULL; -static mscdf_start_write_disk_t mscdf_write_disk = NULL; -static mscdf_test_disk_ready_t mscdf_test_disk_ready = NULL; -static mscdf_xfer_blocks_done_t mscdf_xfer_blocks_done = NULL; - -COMPILER_ALIGNED(4) -static struct scsi_inquiry_data _inquiry_default = { - 0x00, /* Peripheral Qual / Peripheral Dev Type */ - SCSI_INQ_RMB, /* Flags 1 */ - 0x00, /* Version */ - 0x01, /* Flags 3 */ - 31, /* Additional Length (n-4) */ - 0x00, /* Flags 5 */ - 0x00, /* Flags 6 */ - 0x00, /* Flags 7 */ - {0, 0, 0, 0, 0, 0, 0, 0}, /* VID[8] */ - {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* PID[16] */ - {0, 0, 0, 0} /* PREV[4] */ -}; - -COMPILER_ALIGNED(4) -static struct usb_msc_cbw mscdf_cbw; - -COMPILER_ALIGNED(4) -static struct usb_msc_csw mscdf_csw = {USB_CSW_SIGNATURE, 0, 0, 0}; - -COMPILER_ALIGNED(4) -static struct scsi_request_sense_data mscdf_sense_data - = {SCSI_SENSE_CURRENT, 0x00, 0x00, {0x00, 0x00, 0x00, 0x00}, 0x0A}; - -/** - * \brief USB MSC wait Command Block - */ -static bool mscdf_wait_cbw(void) -{ - _mscdf_funcd.xfer_stage = MSCDF_CMD_STAGE; - return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_out, (uint8_t *)&mscdf_cbw, 31, false); -} - -/** - * \brief USB MSC Send Command Status - */ -static bool mscdf_send_csw(void) -{ - _mscdf_funcd.xfer_stage = MSCDF_STATUS_STAGE; - return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_in, (uint8_t *)&mscdf_csw, sizeof(struct usb_msc_csw), false); -} - -#if ERR_RPT_ZLP -/** - * \brief USB MSC Send ZLP data - */ -static bool mscdf_send_zlp(void) -{ - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - return ERR_NONE == usbdc_xfer(_mscdf_funcd.func_ep_in, (uint8_t *)&mscdf_csw, 0, true); -} -#define mscdf_terminate_in() mscdf_send_zlp() -#else -/** - * \brief USB MSC Halt IN endpoint - */ -static bool mscdf_halt_in(void) -{ - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - return ERR_NONE == usb_d_ep_halt(_mscdf_funcd.func_ep_in, USB_EP_HALT_SET); -} -#define mscdf_terminate_in() mscdf_halt_in() -#endif - -/** - * \brief USB MSC Request Sense - * \param[in] err_codes Error code - */ -static void mscdf_request_sense(int32_t err_codes) -{ - switch (err_codes) { - case ERR_NOT_FOUND: - mscdf_sense_data.sense_flag_key = SCSI_SK_NOT_READY; - mscdf_sense_data.AddSense = BE16(SCSI_ASC_MEDIUM_NOT_PRESENT); - break; - - case ERR_BUSY: - mscdf_sense_data.sense_flag_key = SCSI_SK_UNIT_ATTENTION; - mscdf_sense_data.AddSense = BE16(SCSI_ASC_NOT_READY_TO_READY_CHANGE); - break; - - case ERR_DENIED: - mscdf_sense_data.sense_flag_key = SCSI_SK_DATA_PROTECT; - mscdf_sense_data.AddSense = BE16(SCSI_ASC_WRITE_PROTECTED); - break; - - default: - mscdf_sense_data.sense_flag_key = SCSI_SK_ILLEGAL_REQUEST; - mscdf_sense_data.AddSense = BE16(SCSI_ASC_INVALID_COMMAND_OPERATION_CODE); - break; - } -} - -/** - * \brief USB MSC Stack invalid command process - */ -static bool mscdf_invalid_cmd(void) -{ - struct usb_msc_cbw *pcbw = &mscdf_cbw; - struct usb_msc_csw *pcsw = &mscdf_csw; - - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - - mscdf_request_sense(ERR_UNSUPPORTED_OP); - - if ((pcbw->bmCBWFlags & USB_EP_DIR_IN) && pcsw->dCSWDataResidue) { - return mscdf_terminate_in(); - } else { - return mscdf_send_csw(); - } -} - -/** - * \brief USB MSC Function Read / Write Data - * \param[in] count the amount of bytes has been transferred - * \return Operation status. - */ -static bool mscdf_read_write(uint32_t count) -{ - struct usb_msc_cbw *pcbw = &mscdf_cbw; - struct usb_msc_csw *pcsw = &mscdf_csw; - int32_t ret = ERR_UNSUPPORTED_OP; - uint32_t address, nblocks; - uint8_t ep; - - if (_mscdf_funcd.xfer_stage == MSCDF_CMD_STAGE) { - address = (uint32_t)(pcbw->CDB[2] << 24) + (uint32_t)(pcbw->CDB[3] << 16) + (uint32_t)(pcbw->CDB[4] << 8) - + pcbw->CDB[5]; - nblocks = (uint32_t)(pcbw->CDB[7] << 8) + pcbw->CDB[8]; - if (pcbw->CDB[0] == SBC_READ10) { - if (NULL != mscdf_read_disk) { - ret = mscdf_read_disk(pcbw->bCBWLUN, address, nblocks); - } else { - ret = ERR_NOT_FOUND; - } - } else if (pcbw->CDB[0] == SBC_WRITE10) { - if (NULL != mscdf_write_disk) { - ret = mscdf_write_disk(pcbw->bCBWLUN, address, nblocks); - } else { - ret = ERR_NOT_FOUND; - } - } - if (ERR_NONE == ret) { - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - return false; - } - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ret); - return mscdf_terminate_in(); - - } else if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { - if (count == 0) { - return mscdf_send_csw(); - } - if (pcsw->dCSWDataResidue < count || _mscdf_funcd.xfer_tot_bytes < count) { - return true; - } - - pcsw->dCSWDataResidue -= count; - _mscdf_funcd.xfer_tot_bytes -= count; - - if (_mscdf_funcd.xfer_tot_bytes == 0) { - _mscdf_funcd.xfer_busy = false; - if (NULL != mscdf_xfer_blocks_done) { - mscdf_xfer_blocks_done(pcbw->bCBWLUN); - } - if (pcsw->dCSWDataResidue == 0 && pcbw->CDB[0] == SBC_READ10) { - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - return mscdf_send_csw(); - } else { - return false; - } - } else { - _mscdf_funcd.xfer_blk_addr += count; - if (pcbw->CDB[0] == SBC_READ10) { - ep = _mscdf_funcd.func_ep_in; - } else { - ep = _mscdf_funcd.func_ep_out; - } - return usbdc_xfer(ep, _mscdf_funcd.xfer_blk_addr, _mscdf_funcd.xfer_tot_bytes, false); - } - } else { - return true; - } -} - -/** - * \brief Callback invoked when bulk IN data received - * \param[in] ep Endpoint number - * \param[in] rc transfer return status - * \param[in] count the amount of bytes has been transferred - * \return Operation status. - */ -static bool mscdf_cb_ep_bulk_in(const uint8_t ep, const enum usb_xfer_code rc, const uint32_t count) -{ - struct usb_msc_cbw *pcbw = &mscdf_cbw; - (void)ep; - (void)rc; - - if (rc == USB_XFER_UNHALT) { - if (_mscdf_funcd.xfer_stage != MSCDF_CMD_STAGE) { - return mscdf_send_csw(); - } - } - - if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { - if (pcbw->CDB[0] == SBC_READ10) { - return mscdf_read_write(count); - } else { - return mscdf_send_csw(); - } - } else if (_mscdf_funcd.xfer_stage == MSCDF_STATUS_STAGE) { - return mscdf_wait_cbw(); - } else { - return true; - } -} - -/** - * \brief Callback invoked when bulk OUT data received - * \param[in] ep Endpoint number - * \param[in] rc transfer return status - * \param[in] count the amount of bytes has been transferred - * \return Operation status. - */ -static bool mscdf_cb_ep_bulk_out(const uint8_t ep, const enum usb_xfer_code rc, const uint32_t count) -{ - struct usb_msc_cbw *pcbw = &mscdf_cbw; - struct usb_msc_csw *pcsw = &mscdf_csw; - uint8_t * pbuf = NULL; - int32_t ret; - - (void)ep; - if (rc == USB_XFER_UNHALT) { - return mscdf_wait_cbw(); - } - - if (_mscdf_funcd.xfer_stage == MSCDF_CMD_STAGE) { - if (pcbw->dCBWSignature == USB_CBW_SIGNATURE) { - pcsw->dCSWTag = pcbw->dCBWTag; - pcsw->dCSWDataResidue = pcbw->dCBWDataTransferLength; - - switch (pcbw->CDB[0]) { - case SPC_INQUIRY: - if (NULL != mscdf_inquiry_disk) { - pbuf = mscdf_inquiry_disk(pcbw->bCBWLUN); - } - if (NULL == pbuf) { - pbuf = (uint8_t *)&_inquiry_default; - } - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - return usbdc_xfer(_mscdf_funcd.func_ep_in, pbuf, 36, false); - - case SBC_READ_CAPACITY10: - if (NULL != mscdf_get_disk_capacity) { - pbuf = mscdf_get_disk_capacity(pcbw->bCBWLUN); - } - if (NULL != pbuf) { - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - _mscdf_funcd.xfer_blk_size - = (uint32_t)(pbuf[4] << 24) + (uint32_t)(pbuf[5] << 16) + (uint32_t)(pbuf[6] << 8) + pbuf[7]; - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - return usbdc_xfer(_mscdf_funcd.func_ep_in, pbuf, 8, false); - } else { - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ERR_NOT_FOUND); - return mscdf_terminate_in(); - } - - case SBC_READ10: - case SBC_WRITE10: - return mscdf_read_write(count); - - case SPC_PREVENT_ALLOW_MEDIUM_REMOVAL: - if (0x00 == pcbw->CDB[4]) { - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - return mscdf_send_csw(); - } - break; - - case SBC_START_STOP_UNIT: - if (0x02 == pcbw->CDB[4]) { - if (NULL != mscdf_eject_disk) { - ret = mscdf_eject_disk(pcbw->bCBWLUN); - if (ERR_NONE == ret) { - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - } else { - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ret); - } - } else { - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ERR_NOT_FOUND); - } - return mscdf_send_csw(); - } - break; - - case SPC_REQUEST_SENSE: - _mscdf_funcd.xfer_stage = MSCDF_DATA_STAGE; - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - return usbdc_xfer(_mscdf_funcd.func_ep_in, - (uint8_t *)&mscdf_sense_data, - sizeof(struct scsi_request_sense_data), - false); - - case SPC_TEST_UNIT_READY: - if (NULL != mscdf_test_disk_ready) { - ret = mscdf_test_disk_ready(pcbw->bCBWLUN); - if (ERR_NONE == ret) { - pcsw->bCSWStatus = USB_CSW_STATUS_PASS; - pcsw->dCSWDataResidue = 0; - } else { - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ret); - } - } else { - pcsw->bCSWStatus = USB_CSW_STATUS_FAIL; - mscdf_request_sense(ERR_NOT_FOUND); - } - return mscdf_send_csw(); - - default: - break; - } - return mscdf_invalid_cmd(); - } else { - return true; - } - } else if (_mscdf_funcd.xfer_stage == MSCDF_DATA_STAGE) { - return mscdf_read_write(count); - } else { - return true; - } -} - -/** - * \brief Enable MSC Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB interface descriptor - * \return Operation status. - */ -static int32_t mscdf_enable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct mscdf_func_data *func_data = (struct mscdf_func_data *)(drv->func_data); - - usb_ep_desc_t ep_desc; - usb_iface_desc_t ifc_desc; - uint8_t * ifc, *ep; - - ifc = desc->sod; - if (NULL == ifc) { - return ERR_NOT_FOUND; - } - - ifc_desc.bInterfaceNumber = ifc[2]; - ifc_desc.bInterfaceClass = ifc[5]; - - if (MSC_CLASS == ifc_desc.bInterfaceClass) { - if (func_data->func_iface == ifc_desc.bInterfaceNumber) { /* Initialized */ - return ERR_ALREADY_INITIALIZED; - } else if (func_data->func_iface != 0xFF) { /* Occupied */ - return ERR_NO_RESOURCE; - } else { - func_data->func_iface = ifc_desc.bInterfaceNumber; - } - } else { /* Not supported by this function driver */ - return ERR_NOT_FOUND; - } - - /* Install endpoints */ - ep = usb_find_desc(ifc, desc->eod, USB_DT_ENDPOINT); - while (NULL != ep) { - ep_desc.bEndpointAddress = ep[2]; - ep_desc.bmAttributes = ep[3]; - ep_desc.wMaxPacketSize = usb_get_u16(ep + 4); - if (usb_d_ep_init(ep_desc.bEndpointAddress, ep_desc.bmAttributes, ep_desc.wMaxPacketSize)) { - return ERR_NOT_INITIALIZED; - } - if (ep_desc.bEndpointAddress & USB_EP_DIR_IN) { - func_data->func_ep_in = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_in); - usb_d_ep_register_callback(func_data->func_ep_in, USB_D_EP_CB_XFER, (FUNC_PTR)mscdf_cb_ep_bulk_in); - } else { - func_data->func_ep_out = ep_desc.bEndpointAddress; - usb_d_ep_enable(func_data->func_ep_out); - usb_d_ep_register_callback(func_data->func_ep_out, USB_D_EP_CB_XFER, (FUNC_PTR)mscdf_cb_ep_bulk_out); - } - desc->sod = ep; - ep = usb_find_ep_desc(usb_desc_next(desc->sod), desc->eod); - } - // Installed - _mscdf_funcd.enabled = true; - return mscdf_wait_cbw(); -} - -/** - * \brief Disable MSC Function - * \param[in] drv Pointer to USB device function driver - * \param[in] desc Pointer to USB device descriptor - * \return Operation status. - */ -static int32_t mscdf_disable(struct usbdf_driver *drv, struct usbd_descriptors *desc) -{ - struct mscdf_func_data *func_data = (struct mscdf_func_data *)(drv->func_data); - - usb_iface_desc_t ifc_desc; - - if (desc) { - ifc_desc.bInterfaceClass = desc->sod[5]; - // Check interface - if (ifc_desc.bInterfaceClass != MSC_CLASS) { - return ERR_NOT_FOUND; - } - } - - if (func_data->func_iface != 0xFF) { - func_data->func_iface = 0xFF; - } - - if (func_data->func_ep_in != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_in); - func_data->func_ep_in = 0xFF; - } - - if (func_data->func_ep_out != 0xFF) { - usb_d_ep_deinit(func_data->func_ep_out); - func_data->func_ep_out = 0xFF; - } - - func_data->xfer_stage = MSCDF_CMD_STAGE; - func_data->xfer_busy = false; - func_data->enabled = false; - - return ERR_NONE; -} - -/** - * \brief MSC Control Function - * \param[in] drv Pointer to USB device function driver - * \param[in] ctrl USB device general function control type - * \param[in] param Parameter pointer - * \return Operation status. - */ -static int32_t mscdf_ctrl(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param) -{ - switch (ctrl) { - case USBDF_ENABLE: - return mscdf_enable(drv, (struct usbd_descriptors *)param); - - case USBDF_DISABLE: - return mscdf_disable(drv, (struct usbd_descriptors *)param); - - case USBDF_GET_IFACE: - return ERR_UNSUPPORTED_OP; - - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the MSC class set request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - */ -static int32_t mscdf_set_req(uint8_t ep, struct usb_req *req) -{ - (void)ep; - switch (req->bRequest) { - case USB_REQ_MSC_BULK_RESET: - _mscdf_funcd.xfer_stage = MSCDF_CMD_STAGE; - usb_d_ep_halt(_mscdf_funcd.func_ep_in, USB_EP_HALT_SET); - usb_d_ep_halt(_mscdf_funcd.func_ep_out, USB_EP_HALT_SET); - return usbdc_xfer(0, NULL, 0, 0); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the MSC class get request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \param[in] stage USB control transfer stages. - * \return Operation status. - */ -static int32_t mscdf_get_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - uint16_t len = req->wLength; - - if (USB_DATA_STAGE == stage) { - return ERR_NONE; - } - - switch (req->bRequest) { - case USB_REQ_MSC_GET_MAX_LUN: - return usbdc_xfer(ep, &_mscdf_funcd.func_max_lun, len, false); - default: - return ERR_INVALID_ARG; - } -} - -/** - * \brief Process the MSC class request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \param[in] stage USB control transfer stages. - * \return Operation status. - */ -static int32_t mscdf_req(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - if (0x01 != ((req->bmRequestType >> 5) & 0x03)) { /* class request */ - return ERR_NOT_FOUND; - } - if (req->wIndex == _mscdf_funcd.func_iface) { - if (req->bmRequestType & USB_EP_DIR_IN) { - return mscdf_get_req(ep, req, stage); - } else { - return mscdf_set_req(ep, req); - } - } else { - return ERR_NOT_FOUND; - } -} - -/** USB Device MSC Handler Struct */ -static struct usbdc_handler mscdf_req_h = {NULL, (FUNC_PTR)mscdf_req}; - -/** - * \brief Initialize the USB MSC Function Driver - */ -int32_t mscdf_init(uint8_t max_lun) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _mscdf.ctrl = mscdf_ctrl; - _mscdf.func_data = &_mscdf_funcd; - _mscdf_funcd.func_max_lun = max_lun; - - usbdc_register_function(&_mscdf); - usbdc_register_handler(USBDC_HDL_REQ, &mscdf_req_h); - return ERR_NONE; -} - -/** - * \brief De-initialize the USB MSC Function Driver - */ -int32_t mscdf_deinit(void) -{ - if (usbdc_get_state() > USBD_S_POWER) { - return ERR_DENIED; - } - - _mscdf.ctrl = NULL; - _mscdf.func_data = NULL; - - usbdc_unregister_function(&_mscdf); - usbdc_unregister_handler(USBDC_HDL_REQ, &mscdf_req_h); - return ERR_NONE; -} - -/** - * \brief USB MSC Function Register Callback - */ -int32_t mscdf_register_callback(enum mscdf_cb_type cb_type, FUNC_PTR func) -{ - switch (cb_type) { - case MSCDF_CB_INQUIRY_DISK: - mscdf_inquiry_disk = (mscdf_inquiry_disk_t)func; - break; - case MSCDF_CB_GET_DISK_CAPACITY: - mscdf_get_disk_capacity = (mscdf_get_disk_capacity_t)func; - break; - case MSCDF_CB_EJECT_DISK: - mscdf_eject_disk = (mscdf_eject_disk_t)func; - break; - case MSCDF_CB_START_READ_DISK: - mscdf_read_disk = (mscdf_start_read_disk_t)func; - break; - case MSCDF_CB_START_WRITE_DISK: - mscdf_write_disk = (mscdf_start_write_disk_t)func; - break; - case MSCDF_CB_TEST_DISK_READY: - mscdf_test_disk_ready = (mscdf_test_disk_ready_t)func; - break; - case MSCDF_CB_XFER_BLOCKS_DONE: - mscdf_xfer_blocks_done = (mscdf_xfer_blocks_done_t)func; - break; - default: - return ERR_INVALID_ARG; - } - return ERR_NONE; -} - -/** - * \brief Check whether MSC Function is enabled - */ -bool mscdf_is_enabled(void) -{ - return _mscdf_funcd.enabled; -} - -/** - * \brief Process the transfer between USB and Memory. - * - * Routine called by the main loop - */ -int32_t mscdf_xfer_blocks(bool rd, uint8_t *blk_addr, uint32_t blk_cnt) -{ - uint8_t ep; - - if (false == mscdf_is_enabled()) { - return ERR_DENIED; - } else if (true == _mscdf_funcd.xfer_busy) { - return ERR_BUSY; - } else { - _mscdf_funcd.xfer_blk_addr = blk_addr; - _mscdf_funcd.xfer_tot_bytes = _mscdf_funcd.xfer_blk_size * blk_cnt; - if (0 == _mscdf_funcd.xfer_tot_bytes) { - if (false == rd) { - /* For write command, this means no need for more data to receive. - * All the data have been written into disk. - */ - mscdf_csw.bCSWStatus = USB_CSW_STATUS_PASS; - return mscdf_send_csw(); - } else { - return ERR_INVALID_ARG; - } - } else { - if (NULL == blk_addr) { - return ERR_INVALID_ARG; - } - if (true == rd) { - ep = _mscdf_funcd.func_ep_in; - } else { - ep = _mscdf_funcd.func_ep_out; - } - _mscdf_funcd.xfer_busy = true; - usbdc_xfer(ep, blk_addr, _mscdf_funcd.xfer_tot_bytes, false); - return ERR_NONE; - } - } -} - -/** - * \brief Return version - */ -uint32_t mscdf_get_version(void) -{ - return MSCDF_VERSION; -} diff --git a/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.h b/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.h deleted file mode 100644 index 5847a2604..000000000 --- a/atmel-samd/asf4/samd51/usb/class/msc/device/mscdf.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack MSC Function Definition. - * - * Copyright (C) 2016 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef USBDF_MSC_H_ -#define USBDF_MSC_H_ - -#include "usbdc.h" -#include "usb_protocol_msc.h" -#include "spc_protocol.h" -#include "sbc_protocol.h" - -/** MSC Class Callback Type */ -enum mscdf_cb_type { - MSCDF_CB_INQUIRY_DISK, - MSCDF_CB_GET_DISK_CAPACITY, - MSCDF_CB_START_READ_DISK, - MSCDF_CB_START_WRITE_DISK, - MSCDF_CB_EJECT_DISK, - MSCDF_CB_TEST_DISK_READY, - MSCDF_CB_XFER_BLOCKS_DONE -}; - -/** MSC Inquiry Disk Callback. */ -typedef uint8_t *(*mscdf_inquiry_disk_t)(uint8_t); - -/** MSC Get Disk Capacity Callback. */ -typedef uint8_t *(*mscdf_get_disk_capacity_t)(uint8_t); - -/** MSC Read Data From Disk Callback. */ -typedef int32_t (*mscdf_start_read_disk_t)(uint8_t, uint32_t, uint32_t); - -/** MSC Write Data To Disk Callback. */ -typedef int32_t (*mscdf_start_write_disk_t)(uint8_t, uint32_t, uint32_t); - -/** MSC Eject Disk Callback. */ -typedef int32_t (*mscdf_eject_disk_t)(uint8_t); - -/** MSC Test Disk Ready Callback. */ -typedef int32_t (*mscdf_test_disk_ready_t)(uint8_t); - -/** MSC Tansfer Block Done Callback. */ -typedef int32_t (*mscdf_xfer_blocks_done_t)(uint8_t); - -/** - * \brief Initialize the USB MSC Function Driver - * \param[in] max_lun max logic unit support - * \return Operation status. - */ -int32_t mscdf_init(uint8_t max_lun); - -/** - * \brief Deinitialize the USB MSC Function Driver - * \return Operation status. - */ -int32_t mscdf_deinit(void); - -/** - * \brief USB MSC Function Register Callback - * \param[in] cb_type Callback type of MSC Function - * \param[in] func Pointer to callback function - * \return Operation status. - */ -int32_t mscdf_register_callback(enum mscdf_cb_type cb_type, FUNC_PTR func); - -/** - * \brief Check whether MSC Function is enabled - * \return Operation status. - * \return true MSC Function is enabled - * \return false MSC Function is disabled - */ -bool mscdf_is_enabled(void); - -/** - * \brief USB MSC multi-blocks data transfer between USB and Memory. - * \param[in] rd true read disk command, false write disk command. - * \param[in] blk_addr transfer block address. - * \param[in] blk_cnt transfer block count. It is regarded as disk - * writing done when input blk_cnt as zero. - * \return Operation status. - */ -int32_t mscdf_xfer_blocks(bool rd, uint8_t *blk_addr, uint32_t blk_cnt); - -/** - * \brief Return version - */ -uint32_t mscdf_get_version(void); - -#endif /* USBDF_MSC_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/msc/sbc_protocol.h b/atmel-samd/asf4/samd51/usb/class/msc/sbc_protocol.h deleted file mode 100644 index 925933522..000000000 --- a/atmel-samd/asf4/samd51/usb/class/msc/sbc_protocol.h +++ /dev/null @@ -1,163 +0,0 @@ -/** - * \file - * - * \brief SCSI Block Commands - * - * This file contains definitions of some of the commands found in the - * SCSI SBC-2 standard. - * - * Note that the SBC specification depends on several commands defined - * by the SCSI Primary Commands (SPC) standard. Each version of the SBC - * standard is meant to be used in conjunction with a specific version - * of the SPC standard, as follows: - * - SBC depends on SPC - * - SBC-2 depends on SPC-3 - * - SBC-3 depends on SPC-4 - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _SBC_PROTOCOL_H_ -#define _SBC_PROTOCOL_H_ - -/** - * \ingroup usb_msc_protocol - * \defgroup usb_sbc_protocol SCSI Block Commands protocol definitions - * - * @{ - */ - -/** \name SCSI commands defined by SBC-2 */ -#define SBC_FORMAT_UNIT 0x04 -#define SBC_READ6 0x08 -#define SBC_WRITE6 0x0A -#define SBC_START_STOP_UNIT 0x1B -#define SBC_READ_CAPACITY10 0x25 -#define SBC_READ10 0x28 -#define SBC_WRITE10 0x2A -#define SBC_VERIFY10 0x2F - -/** \name SBC-2 Mode page definitions */ -enum scsi_sbc_mode { - SCSI_MS_MODE_RW_ERR_RECOV = 0x01, /**< Read-Write Error Recovery mode page */ - SCSI_MS_MODE_FORMAT_DEVICE = 0x03, /**< Format Device mode page */ - SCSI_MS_MODE_FLEXIBLE_DISK = 0x05, /**< Flexible Disk mode page */ - SCSI_MS_MODE_CACHING = 0x08 -}; - -/** \name SBC-2 Device-Specific Parameter */ -#define SCSI_MS_SBC_WP 0x80 /**< Write Protected */ -#define SCSI_MS_SBC_DPOFUA 0x10 /**< DPO and FUA supported */ - -/** - * \brief SBC-2 Short LBA mode parameter block descriptor - * \note Fields are MSB first (BE) - */ -struct sbc_slba_block_desc { - be32_t nr_blocks; /**< Number of Blocks (BE32) */ - be32_t block_len; /**< Block Length (BE32) */ -#define SBC_SLBA_BLOCK_LEN_MASK 0x00FFFFFFU /**< Mask reserved bits */ -}; - -/** - * \brief SBC-2 Caching mode page - * \note Fields are MSB first (BE) - */ -struct sbc_caching_mode_page { - uint8_t page_code; - uint8_t page_length; - uint8_t flags2; -#define SBC_MP_CACHE_IC (1 << 7) /**< Initiator Control */ -#define SBC_MP_CACHE_ABPF (1 << 6) /**< Abort Pre-Fetch */ -#define SBC_MP_CACHE_CAP (1 << 5) /**< Catching Analysis Permitted */ -#define SBC_MP_CACHE_DISC (1 << 4) /**< Discontinuity */ -#define SBC_MP_CACHE_SIZE (1 << 3) /**< Size enable */ -#define SBC_MP_CACHE_WCE (1 << 2) /**< Write back Cache Enable */ -#define SBC_MP_CACHE_MF (1 << 1) /**< Multiplication Factor */ -#define SBC_MP_CACHE_RCD (1 << 0) /**< Read Cache Disable */ - uint8_t retention; - be16_t dis_pf_transfer_len; - be16_t min_prefetch; - be16_t max_prefetch; - be16_t max_prefetch_ceil; - uint8_t flags12; -#define SBC_MP_CACHE_FSW (1 << 7) /**< Force Sequential Write */ -#define SBC_MP_CACHE_LBCSS (1 << 6) /**< Logical Blk Cache Seg Sz */ -#define SBC_MP_CACHE_DRA (1 << 5) /**< Disable Read-Ahead */ -#define SBC_MP_CACHE_NV_DIS (1 << 0) /**< Non-Volatile Cache Disable */ - uint8_t nr_cache_segments; - be16_t cache_segment_size; - uint8_t reserved[4]; -}; - -/** - * \brief SBC-2 Read-Write Error Recovery mode page - * \note Fields are MSB first (BE) - */ -struct sbc_rdwr_error_recovery_mode_page { - uint8_t page_code; - uint8_t page_length; -#define SPC_MP_RW_ERR_RECOV_PAGE_LENGTH 0x0A - uint8_t flags1; -#define SBC_MP_RW_ERR_RECOV_AWRE (1 << 7) -#define SBC_MP_RW_ERR_RECOV_ARRE (1 << 6) -#define SBC_MP_RW_ERR_RECOV_TB (1 << 5) -#define SBC_MP_RW_ERR_RECOV_RC (1 << 4) -#define SBC_MP_RW_ERR_RECOV_ERR (1 << 3) -#define SBC_MP_RW_ERR_RECOV_PER (1 << 2) -#define SBC_MP_RW_ERR_RECOV_DTE (1 << 1) -#define SBC_MP_RW_ERR_RECOV_DCR (1 << 0) - uint8_t read_retry_count; - uint8_t correction_span; - uint8_t head_offset_count; - uint8_t data_strobe_offset_count; - uint8_t flags2; - uint8_t write_retry_count; - uint8_t flags3; - be16_t recovery_time_limit; -}; - -/** - * \brief SBC-2 READ CAPACITY (10) parameter data (8 bytes) - * \note Fields are MSB first (BE) - */ -struct sbc_read_capacity10_data { - be32_t max_lba; /**< LBA of last logical block (BE32) */ - be32_t block_len; /**< Number of bytes in the last logical block (BE32) */ -}; - -#endif /*_SBC_PROTOCOL_H_*/ diff --git a/atmel-samd/asf4/samd51/usb/class/msc/spc_protocol.h b/atmel-samd/asf4/samd51/usb/class/msc/spc_protocol.h deleted file mode 100644 index c44cbef32..000000000 --- a/atmel-samd/asf4/samd51/usb/class/msc/spc_protocol.h +++ /dev/null @@ -1,340 +0,0 @@ -/** - * \file - * - * \brief SCSI Primary Commands - * - * This file contains definitions of some of the commands found in the - * SPC-2 standard. - * - * Copyright (c) 2009-2012 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -#ifndef _SPC_PROTOCOL_H_ -#define _SPC_PROTOCOL_H_ - -/** - * \ingroup usb_msc_protocol - * \defgroup usb_spc_protocol SCSI Primary Commands protocol definitions - * - * - */ - -/**< \name SCSI commands defined by SPC-2 */ -#define SPC_TEST_UNIT_READY 0x00 -#define SPC_REQUEST_SENSE 0x03 -#define SPC_INQUIRY 0x12 -#define SPC_MODE_SELECT6 0x15 -#define SPC_MODE_SENSE6 0x1A -#define SPC_SEND_DIAGNOSTIC 0x1D -#define SPC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E -#define SPC_MODE_SENSE10 0x5A -#define SPC_REPORT_LUNS 0xA0 - -/**< \brief May be set in byte 0 of the INQUIRY CDB */ -/**< Enable Vital Product Data */ -#define SCSI_INQ_REQ_EVPD 0x01 -/**< Command Support Data specified by the PAGE OR OPERATION CODE field */ -#define SCSI_INQ_REQ_CMDT 0x02 - -COMPILER_PACK_SET(1) - -/** - * \brief SCSI Standard Inquiry data structure - */ -struct scsi_inquiry_data { - uint8_t pq_pdt; /**< Peripheral Qual / Peripheral Dev Type */ -#define SCSI_INQ_PQ_CONNECTED 0x00 /**< Peripheral connected */ -#define SCSI_INQ_PQ_NOT_CONN 0x20 /**< Peripheral not connected */ -#define SCSI_INQ_PQ_NOT_SUPP 0x60 /**< Peripheral not supported */ -#define SCSI_INQ_DT_DIR_ACCESS 0x00 /**< Direct Access (SBC) */ -#define SCSI_INQ_DT_SEQ_ACCESS 0x01 /**< Sequential Access */ -#define SCSI_INQ_DT_PRINTER 0x02 /**< Printer */ -#define SCSI_INQ_DT_PROCESSOR 0x03 /**< Processor device */ -#define SCSI_INQ_DT_WRITE_ONCE 0x04 /**< Write-once device */ -#define SCSI_INQ_DT_CD_DVD 0x05 /**< CD/DVD device */ -#define SCSI_INQ_DT_OPTICAL 0x07 /**< Optical Memory */ -#define SCSI_INQ_DT_MC 0x08 /**< Medium Changer */ -#define SCSI_INQ_DT_ARRAY 0x0c /**< Storage Array Controller */ -#define SCSI_INQ_DT_ENCLOSURE 0x0d /**< Enclosure Services */ -#define SCSI_INQ_DT_RBC 0x0e /**< Simplified Direct Access */ -#define SCSI_INQ_DT_OCRW 0x0f /**< Optical card reader/writer */ -#define SCSI_INQ_DT_BCC 0x10 /**< Bridge Controller Commands */ -#define SCSI_INQ_DT_OSD 0x11 /**< Object-based Storage */ -#define SCSI_INQ_DT_NONE 0x1f /**< No Peripheral */ - uint8_t flags1; /**< Flags (byte 1) */ -#define SCSI_INQ_RMB 0x80 /**< Removable Medium */ - uint8_t version; /**< Version */ -#define SCSI_INQ_VER_NONE 0x00 /**< No standards conformance */ -#define SCSI_INQ_VER_SPC 0x03 /**< SCSI Primary Commands (link to SBC) */ -#define SCSI_INQ_VER_SPC2 0x04 /**< SCSI Primary Commands - 2 (link to SBC-2) */ -#define SCSI_INQ_VER_SPC3 0x05 /**< SCSI Primary Commands - 3 (link to SBC-2) */ -#define SCSI_INQ_VER_SPC4 0x06 /**< SCSI Primary Commands - 4 (link to SBC-3) */ - uint8_t flags3; /**< Flags (byte 3) */ -#define SCSI_INQ_NORMACA 0x20 /**< Normal ACA Supported */ -#define SCSI_INQ_HISUP 0x10 /**< Hierarchal LUN addressing */ -#define SCSI_INQ_RSP_SPC2 0x02 /**< SPC-2 / SPC-3 response format */ - uint8_t addl_len; /**< Additional Length (n-4) */ -#define SCSI_INQ_ADDL_LEN(tot) ((tot)-5) /**< Total length is \a tot */ - uint8_t flags5; /**< Flags (byte 5) */ -#define SCSI_INQ_SCCS 0x80 - uint8_t flags6; /**< Flags (byte 6) */ -#define SCSI_INQ_BQUE 0x80 -#define SCSI_INQ_ENCSERV 0x40 -#define SCSI_INQ_MULTIP 0x10 -#define SCSI_INQ_MCHGR 0x08 -#define SCSI_INQ_ADDR16 0x01 - uint8_t flags7; /**< Flags (byte 7) */ -#define SCSI_INQ_WBUS16 0x20 -#define SCSI_INQ_SYNC 0x10 -#define SCSI_INQ_LINKED 0x08 -#define SCSI_INQ_CMDQUE 0x02 - uint8_t vendor_id[8]; /**< T10 Vendor Identification */ - uint8_t product_id[16]; /**< Product Identification */ - uint8_t product_rev[4]; /**< Product Revision Level */ -}; - -/** - * \brief SCSI Standard Request sense data structure - */ -#define SCSI_SENSE_VALID 0x80 /**< Indicates the INFORMATION field contains valid information */ -#define SCSI_SENSE_RESPONSE_CODE_MASK 0x7F -#define SCSI_SENSE_CURRENT 0x70 /**< Response code 70h (current errors) */ -#define SCSI_SENSE_DEFERRED 0x71 - -#define SCSI_SENSE_FILEMARK 0x80 /**< Indicates that the current command has read a filemark or setmark. */ -#define SCSI_SENSE_EOM 0x40 /**< Indicates that an end-of-medium condition exists. */ -#define SCSI_SENSE_ILI \ - 0x20 /**< Indicates that the requested logical block length did not match the logical block length of the data on \ - the medium. */ -#define SCSI_SENSE_RESERVED 0x10 /**< Reserved */ -#define SCSI_SENSE_KEY(x) (x & 0x0F) /**< Sense Key */ - -#define SCSI_SENSE_ADDL_LEN(total_len) ((total_len)-8) - -#define SCSI_SENSE_SKSV 0x80 /**< Indicates the SENSE-KEY SPECIFIC field contains valid information */ - -struct scsi_request_sense_data { - /** 1st byte: REQUEST SENSE response flags*/ - uint8_t valid_reponse_code; - /** 2nd byte */ - uint8_t obsolete; - /** 3rd byte */ - uint8_t sense_flag_key; - /** 4th to 7th bytes - INFORMATION field */ - uint8_t information[4]; - /** 8th byte - ADDITIONAL SENSE LENGTH field */ - uint8_t AddSenseLen; - /** 9th to 12th byte - COMMAND-SPECIFIC INFORMATION field */ - uint8_t CmdSpecINFO[4]; - /** 13th to 14th byte - ADDITIONAL SENSE CODE and QUALIFIER field */ - union { - struct { - uint8_t code; /**< ADDITIONAL SENSE CODE (ASC) */ - uint8_t qualifier; /**< ADDITIONAL SENSE CODE QUALIFIER (ASCQ) */ - } add_sense; - be16_t AddSense; /**< ASC | ASCQ */ - }; - /** 15th byte - FIELD REPLACEABLE UNIT CODE field */ - uint8_t FldReplUnitCode; - /** 16th byte */ - uint8_t SenseKeySpec[3]; -}; - -COMPILER_PACK_RESET() - -/**< Vital Product Data page codes */ -enum scsi_vpd_page_code { - SCSI_VPD_SUPPORTED_PAGES = 0x00, - SCSI_VPD_UNIT_SERIAL_NUMBER = 0x80, - SCSI_VPD_DEVICE_IDENTIFICATION = 0x83 -}; -#define SCSI_VPD_HEADER_SIZE 4 - -/**< Constants associated with the Device Identification VPD page */ -#define SCSI_VPD_ID_HEADER_SIZE 4 - -#define SCSI_VPD_CODE_SET_BINARY 1 -#define SCSI_VPD_CODE_SET_ASCII 2 -#define SCSI_VPD_CODE_SET_UTF8 3 - -#define SCSI_VPD_ID_TYPE_T10 1 - -/**< Sense keys */ -enum scsi_sense_key { - SCSI_SK_NO_SENSE = 0x0, - SCSI_SK_RECOVERED_ERROR = 0x1, - SCSI_SK_NOT_READY = 0x2, - SCSI_SK_MEDIUM_ERROR = 0x3, - SCSI_SK_HARDWARE_ERROR = 0x4, - SCSI_SK_ILLEGAL_REQUEST = 0x5, - SCSI_SK_UNIT_ATTENTION = 0x6, - SCSI_SK_DATA_PROTECT = 0x7, - SCSI_SK_BLANK_CHECK = 0x8, - SCSI_SK_VENDOR_SPECIFIC = 0x9, - SCSI_SK_COPY_ABORTED = 0xa, - SCSI_SK_ABORTED_COMMAND = 0xb, - SCSI_SK_VOLUME_OVERFLOW = 0xd, - SCSI_SK_MISCOMPARE = 0xe -}; - -/**< Additional Sense Code | Additional Sense Code Qualifier pairs (BE16) */ -enum scsi_asc_ascq { - SCSI_ASC_NO_ADDITIONAL_SENSE_INFO = 0x0000, - SCSI_ASC_LU_NOT_READY_REBUILD_IN_PROGRESS = 0x0405, - SCSI_ASC_WRITE_ERROR = 0x0c00, - SCSI_ASC_UNRECOVERED_READ_ERROR = 0x1100, - SCSI_ASC_INVALID_COMMAND_OPERATION_CODE = 0x2000, - SCSI_ASC_INVALID_FIELD_IN_CDB = 0x2400, - SCSI_ASC_WRITE_PROTECTED = 0x2700, - SCSI_ASC_NOT_READY_TO_READY_CHANGE = 0x2800, - SCSI_ASC_MEDIUM_NOT_PRESENT = 0x3A00, - SCSI_ASC_INTERNAL_TARGET_FAILURE = 0x4400 -}; - -/** - * \brief SPC-2 Mode parameter - * This subclauses describes the block descriptors and the pages - * used with MODE SELECT and MODE SENSE commands - * that are applicable to all SCSI devices. - */ -enum scsi_spc_mode { - SCSI_MS_MODE_VENDOR_SPEC = 0x00, - SCSI_MS_MODE_INFEXP = 0x1C, /**< Informational exceptions control page */ - SCSI_MS_MODE_ALL = 0x3f -}; - -/** - * \brief SPC-2 Informational exceptions control page - * See chapter 8.3.8 - * \note Fields are MSB first (BE) - */ -struct spc_control_page_info_execpt { - uint8_t page_code; - uint8_t page_length; -#define SPC_MP_INFEXP_PAGE_LENGTH 0x0A - uint8_t flags1; -#define SPC_MP_INFEXP_PERF (1 << 7) /**< Initiator Control */ -#define SPC_MP_INFEXP_EBF (1 << 5) /**< Caching Analysis Permitted */ -#define SPC_MP_INFEXP_EWASC (1 << 4) /**< Discontinuity */ -#define SPC_MP_INFEXP_DEXCPT (1 << 3) /**< Size enable */ -#define SPC_MP_INFEXP_TEST (1 << 2) /**< Write-back Cache Enable */ -#define SPC_MP_INFEXP_LOGERR (1 << 0) /**< Log errors bit */ - uint8_t mrie; -#define SPC_MP_INFEXP_MRIE_NO_REPORT 0x00 -#define SPC_MP_INFEXP_MRIE_ASYNC_EVENT 0x01 -#define SPC_MP_INFEXP_MRIE_GEN_UNIT 0x02 -#define SPC_MP_INFEXP_MRIE_COND_RECOV_ERROR 0x03 -#define SPC_MP_INFEXP_MRIE_UNCOND_RECOV_ERROR 0x04 -#define SPC_MP_INFEXP_MRIE_NO_SENSE 0x05 -#define SPC_MP_INFEXP_MRIE_ONLY_REPORT 0x06 - be32_t interval_timer; - be32_t report_count; -}; - -enum scsi_spc_mode_sense_pc { - SCSI_MS_SENSE_PC_CURRENT = 0, - SCSI_MS_SENSE_PC_CHANGEABLE = 1, - SCSI_MS_SENSE_PC_DEFAULT = 2, - SCSI_MS_SENSE_PC_SAVED = 3 -}; - -/** - * \brief Check whether dbd field is set in sense code - * \param[in] cdb pointer to the sense code block - * \return Operation status. - */ -static inline bool scsi_mode_sense_dbd_is_set(const uint8_t *cdb) -{ - return (cdb[1] >> 3) & 1; -} - -/** - * \brief Get page code from mode sense code - * \param[in] cdb pointer to the sense code block - * \return Operation status. - */ -static inline uint8_t scsi_mode_sense_get_page_code(const uint8_t *cdb) -{ - return cdb[2] & 0x3f; -} - -/** - * \brief Get pc from mode sense code - * \param[in] cdb pointer to the sense code block - * \return Operation status. - */ -static inline uint8_t scsi_mode_sense_get_pc(const uint8_t *cdb) -{ - return cdb[2] >> 6; -} - -/** - * \brief SCSI Mode Parameter Header used by MODE SELECT(6) and MODE SENSE(6) - * \note Fields are MSB first (BE) - */ -struct scsi_mode_param_header6 { - uint8_t mode_data_length; /**< Number of bytes after this */ - uint8_t medium_type; /**< Medium Type */ - uint8_t device_specific_parameter; /**< Defined by command set */ - uint8_t block_descriptor_length; /**< Length of block descriptors */ -}; - -/** - * \brief SCSI Mode Parameter Header used by MODE SELECT(10) and MODE SENSE(10) - * \note Fields are MSB first (BE) - */ -struct scsi_mode_param_header10 { - le16_t mode_data_length; /**< Number of bytes after this */ - uint8_t medium_type; /**< Medium Type */ - uint8_t device_specific_parameter; /**< Defined by command set */ - uint8_t flags4; /**< LONGLBA in bit 0 */ - uint8_t reserved; - le16_t block_descriptor_length; /**< Length of block descriptors */ -}; - -/** - * \brief SCSI Page_0 Mode Page header (SPF not set) - */ -struct scsi_mode_page_0_header { - uint8_t page_code; -#define SCSI_PAGE_CODE_PS (1 << 7) /**< Parameters Savable */ -#define SCSI_PAGE_CODE_SPF (1 << 6) /**< SubPage Format */ - uint8_t page_length; /**< Number of bytes after this */ -#define SCSI_MS_PAGE_LEN(total) ((total)-2) -}; - -#endif /**< SPC_PROTOCOL_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/class/msc/usb_protocol_msc.h b/atmel-samd/asf4/samd51/usb/class/msc/usb_protocol_msc.h deleted file mode 100644 index f69eae232..000000000 --- a/atmel-samd/asf4/samd51/usb/class/msc/usb_protocol_msc.h +++ /dev/null @@ -1,177 +0,0 @@ -/** - * \file - * - * \brief USB Mass Storage Class (MSC) protocol definitions. - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#ifndef _USB_PROTOCOL_MSC_H_ -#define _USB_PROTOCOL_MSC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * \ingroup usb_protocol_group - * \defgroup usb_msc_protocol USB Mass Storage Class (MSC) protocol definitions - * - * @{ - */ - -/** - * \name Possible Class value - */ -//@{ -#define MSC_CLASS 0x08 -//@} - -/** - * \name Possible SubClass value - * \note In practice, most devices should use - * #MSC_SUBCLASS_TRANSPARENT and specify the actual command set in - * the standard INQUIRY data block, even if the MSC spec indicates - * otherwise. In particular, RBC is not supported by certain major - * operating systems like Windows XP. - */ -//@{ -#define MSC_SUBCLASS_RBC 0x01 /**< Reduced Block Commands */ -#define MSC_SUBCLASS_ATAPI 0x02 /**< CD/DVD devices */ -#define MSC_SUBCLASS_QIC_157 0x03 /**< Tape devices */ -#define MSC_SUBCLASS_UFI 0x04 /**< Floppy disk drives */ -#define MSC_SUBCLASS_SFF_8070I 0x05 /**< Floppy disk drives */ -#define MSC_SUBCLASS_TRANSPARENT 0x06 /**< Determined by INQUIRY */ - //@} - -/** - * \name Possible protocol value - * \note Only the BULK protocol should be used in new designs. - */ -//@{ -#define MSC_PROTOCOL_CBI 0x00 /**< Command/Bulk/Interrupt */ -#define MSC_PROTOCOL_CBI_ALT 0x01 /**< W/o command completion */ -#define MSC_PROTOCOL_BULK 0x50 /**< Bulk-only */ - //@} - -/** - * \brief MSC USB requests (bRequest) - */ - -#define USB_REQ_MSC_BULK_RESET 0xFF /**< Mass Storage Reset */ -#define USB_REQ_MSC_GET_MAX_LUN 0xFE /**< Get Max LUN */ - -COMPILER_PACK_SET(1) - -/** - * \name A Command Block Wrapper (CBW) - * \note Fields are LSB first (LE) - */ -//@{ -struct usb_msc_cbw { - le32_t dCBWSignature; /**< Must contain 'USBC' (0x43425355, LE32) */ - le32_t dCBWTag; /**< Unique command ID (LE32) */ - le32_t dCBWDataTransferLength; /**< Number of bytes to transfer (LE32) */ - uint8_t bmCBWFlags; /**< Direction in bit 7 */ - uint8_t bCBWLUN; /**< Logical Unit Number */ - uint8_t bCBWCBLength; /**< Number of valid CDB bytes */ - uint8_t CDB[16]; /**< SCSI Command Descriptor Block */ -}; - -#define USB_CBW_SIGNATURE 0x43425355 /**< dCBWSignature value */ -#define USB_CBW_DIRECTION_IN (1 << 7) /**< Data from device to host */ -#define USB_CBW_DIRECTION_OUT (0 << 7) /**< Data from host to device */ -#define USB_CBW_LUN_MASK 0x0F /**< Valid bits in bCBWLUN */ -#define USB_CBW_LEN_MASK 0x1F /**< Valid bits in bCBWCBLength */ - //@} - -/** - * \name A Command Status Wrapper (CSW) - * \note Fields are LSB first (LE) - */ -//@{ -struct usb_msc_csw { - le32_t dCSWSignature; /**< Must contain 'USBS' */ - le32_t dCSWTag; /**< Same as dCBWTag */ - le32_t dCSWDataResidue; /**< Number of bytes not transfered */ - uint8_t bCSWStatus; /**< Status code */ -}; - -#define USB_CSW_SIGNATURE 0x53425355 /**< dCSWSignature value */ -#define USB_CSW_STATUS_PASS 0x00 /**< Command Passed */ -#define USB_CSW_STATUS_FAIL 0x01 /**< Command Failed */ -#define USB_CSW_STATUS_PE 0x02 /**< Phase Error */ -//@} - -COMPILER_PACK_RESET() - -//@} - -/** - * \brief Fill a Bulk-Only Mass Storage Reset request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - */ -static inline void usb_fill_BOMSReset_req(struct usb_req *req, uint8_t iface) -{ - req->bmRequestType = 0x21; - req->bRequest = USB_REQ_MSC_BULK_RESET; - req->wValue = 0; - req->wIndex = iface; - req->wLength = 0; -} - -/** - * \brief Fill a GetMaxLUN request - * \param[out] req Pointer to the request to fill - * \param[in] iface Interface Number - */ -static inline void usb_fill_GetMaxLUN_req(struct usb_req *req, uint8_t iface) -{ - req->bmRequestType = 0xA1; - req->bRequest = USB_REQ_MSC_GET_MAX_LUN; - req->wValue = 0; - req->wIndex = iface; - req->wLength = 1; -} - -#ifdef __cplusplus -} -#endif - -#endif // _USB_PROTOCOL_MSC_H_ diff --git a/atmel-samd/asf4/samd51/usb/class/vendor/usb_protocol_vendor.h b/atmel-samd/asf4/samd51/usb/class/vendor/usb_protocol_vendor.h deleted file mode 100644 index e865fb808..000000000 --- a/atmel-samd/asf4/samd51/usb/class/vendor/usb_protocol_vendor.h +++ /dev/null @@ -1,63 +0,0 @@ -/** - * \file - * - * \brief USB Vendor class protocol definitions. - * - * Copyright (c) 2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _USB_PROTOCOL_VENDOR_H_ -#define _USB_PROTOCOL_VENDOR_H_ - -/** - * \ingroup usb_protocol_group - * \defgroup usb_vendor_protocol USB Vendor Class definitions - * - */ - -/** - * \name Vendor class values - */ -#define VENDOR_CLASS 0xFF -#define VENDOR_SUBCLASS 0xFF -#define VENDOR_PROTOCOL 0xFF - -#endif /* _USB_PROTOCOL_VENDOR_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/device/usbdc.c b/atmel-samd/asf4/samd51/usb/device/usbdc.c deleted file mode 100644 index c9645541d..000000000 --- a/atmel-samd/asf4/samd51/usb/device/usbdc.c +++ /dev/null @@ -1,838 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack Core Layer Implementation. - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel micro controller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ - -#include "usbdc.h" - -#define USBDC_VERSION 0x00000001u - -/** - * \brief USB Device Core Sof Handler - */ -struct usbdc_sof_handler { - struct usbdc_sof_handler *next; - usbdc_sof_cb_t cb; -}; - -/** - * \brief USB Device Core Request Handler - */ -struct usbdc_req_handler { - struct usbdc_req_handler *next; - usbdc_req_cb_t cb; -}; - -/** - * \brief USB Device Core Change Handler - */ -struct usbdc_change_handler { - struct usbdc_change_handler *next; - usbdc_change_cb_t cb; -}; - -/** - * \brief USB Device Core Handler - */ -struct usbdc_handlers { - struct list_descriptor sof_list; - struct list_descriptor req_list; - struct list_descriptor change_list; -}; - -/** - * \brief USB Device Core Driver Structure - */ -struct usbdc_driver { - /** Pointer to descriptions of descriptors. */ - struct usbdc_descriptors desces; - /** Callback handlers. */ - struct usbdc_handlers handlers; - /** list of function drivers. */ - struct list_descriptor func_list; - /** Control buffer. */ - uint8_t *ctrl_buf; - /** Device status. */ - uint16_t status; - /** Device state. */ - uint8_t state; - /** Configuration value. */ - uint8_t cfg_value; - /** Control endpoint size. */ - uint8_t ctrl_size; -}; - -/** - * \brief USB Device Core Driver Instance - */ -static struct usbdc_driver usbdc; - -/** - * \brief Process the GetDescriptor request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_get_desc_req(const uint8_t ep, struct usb_req *req) -{ - uint8_t *cfg_desc, *str_desc; - uint16_t total_len; - uint16_t length = req->wLength; - uint8_t type = (uint8_t)(req->wValue >> 8); - uint8_t index = req->wValue & 0x00FF; - bool need_zlp = !(length & (usbdc.ctrl_size - 1)); - - switch (type) { - case USB_DT_DEVICE: - if (length > 0x12) { - length = 0x12; - } - usbdc_xfer(ep, usbdc.desces.ls_fs->sod, length, false); - return true; - case USB_DT_CONFIG: - cfg_desc = usb_find_cfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, index + 1); - if (NULL == cfg_desc) { - return false; - } - total_len = usb_cfg_desc_total_len(cfg_desc); - if (length <= total_len) { - need_zlp = false; - } else { - length = total_len; - } - usbdc_xfer(ep, cfg_desc, length, need_zlp); - return true; - case USB_DT_STRING: - str_desc = usb_find_str_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, index); - if (NULL == str_desc) { - return false; - } - total_len = str_desc[0]; - if (length <= total_len) { - need_zlp = false; - } else { - length = total_len; - } - usbdc_xfer(ep, str_desc, length, need_zlp); - return true; - - default: - break; - } - return false; -} - -/** - * \brief Process the GetStatus request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_get_status_req(const uint8_t ep, const struct usb_req *req) -{ - int32_t st; - (void)ep; - - switch (req->bmRequestType & USB_REQT_RECIP_MASK) { - case USB_REQT_RECIP_DEVICE: - case USB_REQT_RECIP_INTERFACE: - st = 0; - break; - case USB_REQT_RECIP_ENDPOINT: - st = usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_GET); - if (st < 0) { - return false; - } - st = st & 0x1; - break; - default: - return false; - } - memcpy(usbdc.ctrl_buf, &st, 2); - usbdc_xfer(ep, usbdc.ctrl_buf, 2, false); - return true; -} - -/** - * \brief Process the standard Get Interface - * \param[in] req Point to usb request struct. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_get_interface(struct usb_req *req) -{ - struct usbdf_driver *func = (struct usbdf_driver *)usbdc.func_list.head; - int32_t rc; - - while (NULL != func) { - if (0 > (rc = func->ctrl(func, USBDF_GET_IFACE, req))) { - func = func->next; - } else { - usbdc.ctrl_buf[0] = (uint8_t)rc; - usbdc_xfer(0, usbdc.ctrl_buf, 1, false); - return true; - } - } - return false; -} - -/** - * \brief Process the standard Get request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_get_req(const uint8_t ep, struct usb_req *req) -{ - switch (req->bRequest) { - case USB_REQ_GET_DESC: - return usbdc_get_desc_req(ep, req); - case USB_REQ_GET_CONFIG: - *(uint8_t *)usbdc.ctrl_buf = usbdc.cfg_value; - usbdc_xfer(ep, usbdc.ctrl_buf, 1, false); - return true; - case USB_REQ_GET_STATUS: - return usbdc_get_status_req(ep, req); - case USB_REQ_GET_INTERFACE: - return usbdc_get_interface(req); - default: - return false; - } -} - -/** - * \brief Process the standard ClearFeature request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_clear_ftr_req(const uint8_t ep, const struct usb_req *req) -{ - (void)ep; - switch (req->bmRequestType & USB_REQT_RECIP_MASK) { - case USB_REQT_RECIP_ENDPOINT: - if (req->wLength != 0) { - return false; - } - usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_CLR); - usbdc_xfer(ep, NULL, 0, true); - return true; - default: - return false; - } -} - -/** - * \brief Process the standard SetFeature request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_set_ftr_req(const uint8_t ep, const struct usb_req *req) -{ - (void)ep; - switch (req->bmRequestType & USB_REQT_RECIP_MASK) { - case USB_REQT_RECIP_ENDPOINT: - if (req->wLength != 0) { - return false; - } - usb_d_ep_halt(req->wIndex & 0xFF, USB_EP_HALT_SET); - usbdc_xfer(ep, NULL, 0, true); - return true; - default: - return false; - } -} - -/** - * \brief Unconfig, close all interfaces - */ -static void usbdc_unconfig(void) -{ - struct usbdf_driver *func = (struct usbdf_driver *)usbdc.func_list.head; - while (NULL != func) { - func->ctrl(func, USBDF_DISABLE, NULL); - func = func->next; - } -} - -/** - * \brief Apply Set Configuration Value - */ -static void usbdc_set_config(void) -{ - struct usbd_descriptors desc; - struct usbdf_driver * func; - uint8_t * cfg_desc; - uint16_t total_len; - uint8_t last_iface = 0xFF; - - if (usbdc.cfg_value == 0) { - usbdc_unconfig(); - return; - } - - cfg_desc = usb_find_cfg_desc(usbdc.desces.ls_fs->sod, usbdc.desces.ls_fs->eod, usbdc.cfg_value); - - if (NULL == cfg_desc) { - return; - } - - total_len = usb_cfg_desc_total_len(cfg_desc); - desc.eod = cfg_desc + total_len; - desc.sod = usb_find_desc(cfg_desc, desc.eod, USB_DT_INTERFACE); - - while (NULL != desc.sod) { - /* Apply very first alternate setting (must be 0) of the interface */ - if (last_iface != desc.sod[2] /* bInterfaceNumber */) { - last_iface = desc.sod[2]; - func = (struct usbdf_driver *)usbdc.func_list.head; - while (NULL != func) { - if (func->ctrl(func, USBDF_ENABLE, &desc)) { - func = func->next; - } else { - break; - } - } - } - desc.sod = usb_desc_next(desc.sod); - desc.sod = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE); - } -} - -/** - * \brief Apply the USB device address - * \param[in] addr address to be set. - */ -static void usbdc_set_address(uint8_t addr) -{ - usb_d_set_address(addr); -} - -/** - * \brief Process the standard Set Interface - * \param[in] alt_set Alternate Setting. - * \param[in] ifc_id Interface Index. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_set_interface(uint16_t alt_set, uint16_t ifc_id) -{ - struct usbd_descriptors desc; - struct usbdf_driver * func; - uint8_t * ifc; - - desc.sod = usbdc.desces.ls_fs->sod; - desc.eod = usbdc.desces.ls_fs->eod; - if (NULL == (ifc = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE))) { - return false; - } - - while (ifc[2] != ifc_id || ifc[3] != alt_set) { - desc.sod = usb_desc_next(desc.sod); - ifc = usb_find_desc(desc.sod, desc.eod, USB_DT_INTERFACE); - if (NULL == ifc) { - return false; - } - } - - desc.sod = ifc; - func = (struct usbdf_driver *)usbdc.func_list.head; - - while (NULL != func) { - if (func->ctrl(func, USBDF_DISABLE, &desc)) { - func = func->next; - } else if (ERR_NONE == func->ctrl(func, USBDF_ENABLE, &desc)) { - usbdc_xfer(0, NULL, 0, 0); - return true; - } else { - return false; - } - } - - return false; -} - -/** - * \brief Process the standard Set request - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_set_req(const uint8_t ep, struct usb_req *req) -{ - switch (req->bRequest) { - case USB_REQ_SET_ADDRESS: - case USB_REQ_SET_CONFIG: - if (ERR_NONE == usbdc_xfer(ep, NULL, 0, true)) { - return true; - } else { - return false; - } - case USB_REQ_CLEAR_FTR: - return usbdc_clear_ftr_req(ep, req); - case USB_REQ_SET_FTR: - return usbdc_set_ftr_req(ep, req); - case USB_REQ_SET_INTERFACE: - return usbdc_set_interface(req->wValue, req->wIndex); - default: - return false; - } -} - -/** Invoke all registered SOF callbacks. */ -static void usbdc_sof_notify(void) -{ - struct usbdc_sof_handler *sof = (struct usbdc_sof_handler *)usbdc.handlers.sof_list.head; - - while (sof != NULL) { - if (NULL != sof->cb) { - sof->cb(); - } - sof = sof->next; - } -} - -/** Invoke all registered Change notification callbacks. */ -static void usbdc_change_notify(enum usbdc_change_type change, uint32_t value) -{ - struct usbdc_change_handler *cg = (struct usbdc_change_handler *)usbdc.handlers.change_list.head; - - while (cg != NULL) { - if (NULL != cg->cb) { - cg->cb(change, value); - } - cg = cg->next; - } -} - -/** Invoke all registered request callbacks until request handled. */ -static bool usbdc_request_handler(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage) -{ - struct usbdc_req_handler *h = (struct usbdc_req_handler *)usbdc.handlers.req_list.head; - int32_t rc; - - while (h != NULL) { - if (NULL != h->cb) { - rc = h->cb(ep, req, stage); - if (0 == rc) { - return true; - } else if (ERR_NOT_FOUND != rc) { - return false; - } - } - h = h->next; - } - return false; -} - -/** - * \brief Callback invoked on USB device SOF - */ -static void usbd_sof_cb(void) -{ - usbdc_sof_notify(); -} - -/** - * \brief Callback invoked when control request is received - * \param[in] ep Endpoint address. - * \param[in] req Pointer to the request. - * \return Operation status. - * \retval true Request is handled OK. - * \retval false Request not supported. - */ -static bool usbdc_cb_ctl_req(const uint8_t ep, struct usb_req *req) -{ - if (usbdc_request_handler(ep, req, USB_SETUP_STAGE)) { - return true; - } - - // STD request handling - switch (req->bmRequestType & (USB_REQT_TYPE_MASK | USB_REQT_DIR_IN)) { - case USB_REQT_TYPE_STANDARD: - return usbdc_set_req(ep, req); - case (USB_REQT_TYPE_STANDARD | USB_REQT_DIR_IN): - return usbdc_get_req(ep, req); - default: - return false; - } -} - -/** - * \brief When control status stage is end - * \param[in] req Pointer to the request. - */ -static void usbdc_ctrl_status_end(const struct usb_req *req) -{ - switch (req->bRequest) { - case USB_REQ_SET_CONFIG: - usbdc.cfg_value = req->wValue; - usbdc_set_config(); - usbdc.state = req->wValue ? USBD_S_CONFIG : USBD_S_ADDRESS; - usbdc_change_notify(USBDC_C_STATE, usbdc.state); - break; - case USB_REQ_SET_ADDRESS: - usbdc_set_address(req->wValue); - usbdc.state = req->wValue ? USBD_S_ADDRESS : USBD_S_DEFAULT; - usbdc_change_notify(USBDC_C_STATE, usbdc.state); - break; - default: - break; - } -} - -/** - * \brief When control data stage is end - * \param[in] req Pointer to the request. - */ -static bool usbdc_ctrl_data_end(struct usb_req *req) -{ - usbdc_request_handler(0, req, USB_DATA_STAGE); - return false; -} - -/** - * \brief Callback invoked when control data done or status done - * \param[in] ep Endpoint number with direction on bit 8. - * \param[in] code Status code. - * \param[in] req Pointer to the control setup request. - * \return Data has error or not. - * \retval true There is data error, protocol error. - * \retval false There is no data error. - */ -static bool usbdc_cb_ctl_done(const uint8_t ep, const enum usb_xfer_code code, struct usb_req *req) -{ - (void)ep; - - switch (code) { - case USB_XFER_DONE: - usbdc_ctrl_status_end(req); - break; - case USB_XFER_DATA: - return usbdc_ctrl_data_end(req); - default: - break; - } - return false; -} - -/** - * \brief USB Device Core Reset - */ -void usbdc_reset(void) -{ - usbdc_unconfig(); - - usbdc.state = USBD_S_DEFAULT; - usbdc.cfg_value = 0; - - // Setup EP0 - usb_d_ep_deinit(0); - usb_d_ep0_init(usbdc.ctrl_size); - usb_d_ep_register_callback(0, USB_D_EP_CB_SETUP, (FUNC_PTR)usbdc_cb_ctl_req); - usb_d_ep_register_callback(0, USB_D_EP_CB_XFER, (FUNC_PTR)usbdc_cb_ctl_done); - usb_d_ep_enable(0); -} - -/** - * \brief Callback invoked on USB device events - * \param[in] ev Event code. - * \param[in] param Event parameter for event handling. - */ -static void usbd_event_cb(const enum usb_event ev, const uint32_t param) -{ - (void)param; - - switch (ev) { - case USB_EV_VBUS: - usbdc_change_notify(USBDC_C_CONN, param); - break; - - case USB_EV_RESET: - usbdc_reset(); - break; - - default: - break; - } -} - -/** - * \brief Issue USB device transfer - */ -int32_t usbdc_xfer(uint8_t ep, uint8_t *buf, uint32_t size, bool zlp) -{ - struct usb_d_transfer xfer = {(uint8_t *)buf, size, ep, zlp}; - return usb_d_ep_transfer(&xfer); -} - -/** - * \brief Register the handler - */ -void usbdc_register_handler(enum usbdc_handler_type type, const struct usbdc_handler *h) -{ - switch (type) { - case USBDC_HDL_SOF: - list_insert_at_end(&usbdc.handlers.sof_list, (void *)h); - break; - case USBDC_HDL_REQ: - list_insert_at_end(&usbdc.handlers.req_list, (void *)h); - break; - case USBDC_HDL_CHANGE: - list_insert_at_end(&usbdc.handlers.change_list, (void *)h); - break; - default: - break; - } -} - -/** - * \brief Unregister the handler - */ -void usbdc_unregister_handler(enum usbdc_handler_type type, const struct usbdc_handler *h) -{ - switch (type) { - case USBDC_HDL_SOF: - list_delete_element(&usbdc.handlers.sof_list, (void *)h); - break; - case USBDC_HDL_REQ: - list_delete_element(&usbdc.handlers.req_list, (void *)h); - break; - case USBDC_HDL_CHANGE: - list_delete_element(&usbdc.handlers.change_list, (void *)h); - break; - default: - break; - } -} - -/** - * \brief Initialize the USB device core driver - */ -int32_t usbdc_init(uint8_t *ctrl_buf) -{ - ASSERT(ctrl_buf); - - int32_t rc; - - rc = usb_d_init(); - if (rc < 0) { - return rc; - } - - memset(&usbdc, 0, sizeof(usbdc)); - usbdc.ctrl_buf = ctrl_buf; - usb_d_register_callback(USB_D_CB_SOF, (FUNC_PTR)usbd_sof_cb); - usb_d_register_callback(USB_D_CB_EVENT, (FUNC_PTR)usbd_event_cb); - - return 0; -} - -/** - * \brief De-initialize the USB device core driver - */ -int32_t usbdc_deinit(void) -{ - usb_d_deinit(); - return 0; -} - -/** - * \brief Register/unregister function support of a USB device function - * - * Must be invoked when USB device is stopped. - */ -void usbdc_register_function(struct usbdf_driver *func) -{ - list_insert_at_end(&usbdc.func_list, func); -} - -/** - * \brief Unregister function support of a USB device function - * - * Must be invoked when USB device is stopped. - */ -void usbdc_unregister_function(struct usbdf_driver *func) -{ - list_delete_element(&usbdc.func_list, func); -} - -/** - * \brief Validate the descriptor - */ -int32_t usbdc_validate_desces(struct usbd_descriptors *desces) -{ - uint8_t *sod, *eod; - if (desces == NULL) { - return ERR_NOT_FOUND; - } - sod = usb_find_desc(desces->sod, desces->eod, USB_DT_DEVICE); - if (sod == NULL) { - return ERR_BAD_DATA; - } - sod = usb_find_desc(desces->sod, desces->eod, USB_DT_CONFIG); - if (sod == NULL) { - return ERR_BAD_DATA; - } - eod = sod + usb_cfg_desc_total_len(sod); - if (eod > desces->eod) { - return ERR_BAD_DATA; - } - return 0; -} - -/** - * \brief Validate the descriptor - */ -int32_t usbdc_check_desces(struct usbdc_descriptors *desces) -{ -#ifdef CONF_USBD_HS_SP - int32_t rc; - if (desces->hs == NULL && desces->ls_fs == NULL) { - return ERR_NOT_FOUND; - } - if (desces->hs) { - rc = usbdc_validate_desces(desces->hs); - if (rc < 0) { - return rc; - } - } -#endif - return usbdc_validate_desces(desces->ls_fs); -} - -/** - * \brief Start the USB device driver with specific descriptors set - */ -int32_t usbdc_start(struct usbd_descriptors *desces) -{ - if (usbdc.state >= USBD_S_POWER) { - return ERR_BUSY; - } - - if (desces) { - usbdc.desces.ls_fs = desces; - } else { - return ERR_BAD_DATA; - } - - usbdc.ctrl_size = desces->sod[7]; - usbdc.state = USBD_S_POWER; - usb_d_enable(); - return ERR_NONE; -} - -/** - * \brief Stop the USB device driver - */ -int32_t usbdc_stop(void) -{ - usb_d_disable(); - usbdc.state = USBD_S_OFF; - return ERR_NONE; -} - -/** - * \brief Attach the USB device to host - */ -void usbdc_attach(void) -{ - usb_d_attach(); -} - -/** - * \brief Detach the USB device from host - */ -void usbdc_detach(void) -{ - usb_d_detach(); -} - -/** - * \brief Send remote wakeup to host - */ -void usbdc_remotewakeup(void) -{ - usb_d_send_remotewakeup(); - usbdc.state = USBD_S_POWER; -} - -/** - * \brief Return USB Device endpoint0 buffer - */ -uint8_t *usbdc_get_ctrl_buffer(void) -{ - return usbdc.ctrl_buf; -} - -/** - * \brief Return current USB state - */ -uint8_t usbdc_get_state(void) -{ - if (usbdc.state & USBD_S_SUSPEND) { - return USBD_S_SUSPEND; - } - return usbdc.state; -} - -/** - * \brief Return version - */ -uint32_t usbdc_get_version(void) -{ - return USBDC_VERSION; -} diff --git a/atmel-samd/asf4/samd51/usb/device/usbdc.h b/atmel-samd/asf4/samd51/usb/device/usbdc.h deleted file mode 100644 index 515d28f1b..000000000 --- a/atmel-samd/asf4/samd51/usb/device/usbdc.h +++ /dev/null @@ -1,246 +0,0 @@ -/** - * \file - * - * \brief USB Device Stack Core Layer Definition. - * - * Copyright (C) 2015-2016 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef _USB_USBDC_H_ -#define _USB_USBDC_H_ - -#include "usb_includes.h" -#include "usb_protocol.h" -#include "hal_usb_device.h" - -/** USB device states. */ -enum usbd_state { - USBD_S_OFF = 0, - USBD_S_POWER = 1, - USBD_S_DEFAULT = 2, - USBD_S_ADDRESS = 3, - USBD_S_CONFIG = 4, - USBD_S_SUSPEND = 0x10 -}; - -/** USB device core handler type. */ -enum usbdc_handler_type { USBDC_HDL_SOF, USBDC_HDL_REQ, USBDC_HDL_CHANGE }; - -/** USB device core change notification type. */ -enum usbdc_change_type { - /** Change of connection, detected by vbus. */ - USBDC_C_CONN, - /** Change of state, by RESET, SetAddress(), SetConfig(). */ - USBDC_C_STATE, - /** Change of power. */ - USBDC_C_POWER, - /** Change of remote wakeup setting. */ - USBDC_C_REMOTE_WAKEUP -}; - -/** Power change. */ -enum usbdc_power_type { USBDC_ACTIVE, USBDC_SLEEP, USBDC_SUSPEND }; - -/** USB device general function control code. */ -enum usbdf_control { - /** Enable the function. - * int32_t ctrl(usbdf, USBDF_ENABLE, struct usbd_descriptors *desc); - * Parameter holds interface descriptor and - * configuration descriptor end position. - */ - USBDF_ENABLE, - /** Disable the function. - * int32_t ctrl(usbdf, USBDF_DISABLE, struct usbd_descriptors *desc); - * Parameter holds interface descriptor and - * configuration descriptor end position. - * Input NULL to force disable the function anyway. - */ - USBDF_DISABLE, - /** Get interface alternate setting. - * int32_t ctrl(usbdf, USBDF_GET_IFACE, struct usb_req *req); - * Parameter holds interface number who should return - * the alternate setting. - */ - USBDF_GET_IFACE -}; - -/** Describes a list of USB descriptors. */ -struct usbd_descriptors { - /** Pointer to Start of Descriptors. */ - uint8_t *sod; - /** Pointer to End of Descriptors. */ - uint8_t *eod; -}; - -/** Describes the USB device core descriptors. */ -struct usbdc_descriptors { - struct usbd_descriptors *ls_fs; -#ifdef CONF_USBD_HS_SP - struct usbd_descriptors *hs; -#endif -}; - -/** Describes a list of core handler descriptor. */ -struct usbdc_handler { - /** Pointer to next handler. */ - struct usbdc_handler *next; - /** Pointer to handler function. */ - FUNC_PTR func; -}; - -/** Forward declaration for USB device function driver. */ -struct usbdf_driver; - -/** SOF handling function. */ -typedef void (*usbdc_sof_cb_t)(void); - -/** REQ handling function. */ -typedef int32_t (*usbdc_req_cb_t)(uint8_t ep, struct usb_req *req, enum usb_ctrl_stage stage); - -/** Change notification callback function. */ -typedef void (*usbdc_change_cb_t)(enum usbdc_change_type change, uint32_t value); - -/** Control function for USB device general function driver. */ -typedef int32_t (*usbdf_control_cb_t)(struct usbdf_driver *drv, enum usbdf_control ctrl, void *param); - -/** USB device general function driver descriptor. */ -struct usbdf_driver { - /** Pointer to next function.*/ - struct usbdf_driver *next; - /** Pointer to control function.*/ - usbdf_control_cb_t ctrl; - /** Pointer to function driver specific data. */ - void *func_data; -}; - -/** - * \brief Register the handler - * \param[in] type USB device core handler type. - * \param[in] h Pointer to usb device core handler. - */ -void usbdc_register_handler(enum usbdc_handler_type type, const struct usbdc_handler *h); - -/** - * \brief Unregister the handler - * \param[in] type USB device core handler type. - * \param[in] h Pointer to usb device core handler. - */ -void usbdc_unregister_handler(enum usbdc_handler_type type, const struct usbdc_handler *h); - -/** - * \brief Initialize the USB device core driver - * \param[in] ctrl_buf Pointer to a buffer to be used by usb device ctrl endpoint - * Note: the size of ctrl_buf should not be less than the size of EP0 - * \return Operation status. - */ -int32_t usbdc_init(uint8_t *ctrl_buf); - -/** - * \brief Deinitialize the USB device core driver - * \return Operation status. - */ -int32_t usbdc_deinit(void); - -/** - * \brief Register function support of a USB device function - * \param[in] func Pointer to usb device function driver structure - */ -void usbdc_register_function(struct usbdf_driver *func); - -/** - * \brief Unregister function support of a USB device function - * \param[in] func Pointer to usb device function driver structure - */ -void usbdc_unregister_function(struct usbdf_driver *func); - -/** - * \brief Validate the descriptors - * \param[in] desces Pointer to usb device core descriptors - * \return Operation status. - */ -int32_t usbdc_validate_desces(struct usbd_descriptors *desces); - -/** - * \brief Issue USB device data transfer - * \param[in] ep endpointer address. - * \param[in] buf Pointer to data transfer buffer. - * \param[in] size the size of data transfer. - * \param[in] zlp flag to indicate zero length packet. - * \return Operation status. - */ -int32_t usbdc_xfer(uint8_t ep, uint8_t *buf, uint32_t size, bool zlp); - -/** - * \brief Start the USB device driver with specific descriptors set - * \param[in] desces Pointer to usb device core descriptors - * \return Operation status. - */ -int32_t usbdc_start(struct usbd_descriptors *desces); - -/** - * \brief Stop the USB device driver - * \return Operation status. - */ -int32_t usbdc_stop(void); - -/** - * \brief Attach the USB device to host - */ -void usbdc_attach(void); - -/** - * \brief Detach the USB device from host - */ -void usbdc_detach(void); - -/** - * \brief Send remote wakeup to host - */ -void usbdc_remotewakeup(void); - -/** - * \brief Return USB device ctrl end pointer buffer start address - */ -uint8_t *usbdc_get_ctrl_buffer(void); - -/** - * \brief Return current USB state - */ -uint8_t usbdc_get_state(void); - -/** - * \brief Return version - */ -uint32_t usbdc_get_version(void); - -#endif /* USBDC_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/usb_atmel.h b/atmel-samd/asf4/samd51/usb/usb_atmel.h deleted file mode 100644 index 3ca7a2927..000000000 --- a/atmel-samd/asf4/samd51/usb/usb_atmel.h +++ /dev/null @@ -1,189 +0,0 @@ -/** - * \file - * - * \brief All USB VIDs and PIDs from Atmel USB applications - * - * Copyright (c) 2015 Atmel Corporation. All rights reserved. - * - * \asf_license_start - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel microcontroller product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - * \asf_license_stop - * - */ -/* - * Support and FAQ: visit Atmel Support - */ - -#ifndef _USB_ATMEL_H_ -#define _USB_ATMEL_H_ - -/** - * \defgroup usb_group USB Stack - * - * This stack includes the USB Device Stack, USB Host Stack and common - * definitions. - * @{ - */ - -//! @} - -/** - * \ingroup usb_group - * \defgroup usb_atmel_ids_group Atmel USB Identifiers - * - * This module defines Atmel PID and VIDs constants. - * - * @{ - */ - -//! \name Vendor Identifier assigned by USB org to ATMEL -#define USB_VID_ATMEL 0x03EB - -//! \name Product Identifier assigned by ATMEL to AVR applications -//! @{ - -//! \name The range from 2000h to 20FFh is reserved to the old PID for C51, MEGA, and others. -//! @{ -#define USB_PID_ATMEL_MEGA_HIDGENERIC 0x2013 -#define USB_PID_ATMEL_MEGA_HIDKEYBOARD 0x2017 -#define USB_PID_ATMEL_MEGA_CDC 0x2018 -#define USB_PID_ATMEL_MEGA_AUDIO_IN 0x2019 -#define USB_PID_ATMEL_MEGA_MS 0x201A -#define USB_PID_ATMEL_MEGA_AUDIO_IN_OUT 0x201B -#define USB_PID_ATMEL_MEGA_HIDMOUSE 0x201C -#define USB_PID_ATMEL_MEGA_HIDMOUSE_CERTIF_U4 0x201D -#define USB_PID_ATMEL_MEGA_CDC_MULTI 0x201E -#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_USBKEY 0x2022 -#define USB_PID_ATMEL_MEGA_MS_HIDMS_HID_STK525 0x2023 -#define USB_PID_ATMEL_MEGA_MS_2 0x2029 -#define USB_PID_ATMEL_MEGA_MS_HIDMS 0x202A -#define USB_PID_ATMEL_MEGA_MS_3 0x2032 -#define USB_PID_ATMEL_MEGA_LIBUSB 0x2050 -//! @} - -//! \name The range 2100h to 21FFh is reserved to PIDs for AVR Tools. -//! @{ -#define USB_PID_ATMEL_XPLAINED 0x2122 -#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_2_4GHZ 0x214A -#define USB_PID_ATMEL_XMEGA_USB_ZIGBIT_SUBGHZ 0x214B -//! @} - -//! \name The range 2300h to 23FFh is reserved to PIDs for demo from ASF1.7=> -//! @{ -#define USB_PID_ATMEL_UC3_ENUM 0x2300 -#define USB_PID_ATMEL_UC3_MS 0x2301 -#define USB_PID_ATMEL_UC3_MS_SDRAM_LOADER 0x2302 -#define USB_PID_ATMEL_UC3_EVK1100_CTRLPANEL 0x2303 -#define USB_PID_ATMEL_UC3_HID 0x2304 -#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID 0x2305 -#define USB_PID_ATMEL_UC3_EVK1101_CTRLPANEL_HID_MS 0x2306 -#define USB_PID_ATMEL_UC3_CDC 0x2307 -#define USB_PID_ATMEL_UC3_AUDIO_MICRO 0x2308 -#define USB_PID_ATMEL_UC3_CDC_DEBUG 0x2310 // Virtual Com (debug interface) on EVK11xx -#define USB_PID_ATMEL_UC3_AUDIO_SPEAKER_MICRO 0x2311 -#define USB_PID_ATMEL_UC3_CDC_MSC 0x2312 -//! @} - -//! \name The range 2400h to 24FFh is reserved to PIDs for ASF applications -//! @{ -#define USB_PID_ATMEL_ASF_HIDMOUSE 0x2400 -#define USB_PID_ATMEL_ASF_HIDKEYBOARD 0x2401 -#define USB_PID_ATMEL_ASF_HIDGENERIC 0x2402 -#define USB_PID_ATMEL_ASF_MSC 0x2403 -#define USB_PID_ATMEL_ASF_CDC 0x2404 -#define USB_PID_ATMEL_ASF_PHDC 0x2405 -#define USB_PID_ATMEL_ASF_HIDMTOUCH 0x2406 -#define USB_PID_ATMEL_ASF_MSC_HIDMOUSE 0x2420 -#define USB_PID_ATMEL_ASF_MSC_HIDS_CDC 0x2421 -#define USB_PID_ATMEL_ASF_MSC_HIDKEYBOARD 0x2422 -#define USB_PID_ATMEL_ASF_VENDOR_CLASS 0x2423 -#define USB_PID_ATMEL_ASF_MSC_CDC 0x2424 -#define USB_PID_ATMEL_ASF_TWO_CDC 0x2425 -#define USB_PID_ATMEL_ASF_SEVEN_CDC 0x2426 -#define USB_PID_ATMEL_ASF_XPLAIN_BC_POWERONLY 0x2430 -#define USB_PID_ATMEL_ASF_XPLAIN_BC_TERMINAL 0x2431 -#define USB_PID_ATMEL_ASF_XPLAIN_BC_TOUCH 0x2432 -#define USB_PID_ATMEL_ASF_AUDIO_SPEAKER 0x2433 -#define USB_PID_ATMEL_ASF_XMEGA_B1_XPLAINED 0x2434 -//! @} - -//! \name The range 2F00h to 2FFFh is reserved to official PIDs for AVR bootloaders -//! Note, !!!! don't use this range for demos or examples !!!! -//! @{ -#define USB_PID_ATMEL_DFU_ATXMEGA64C3 0x2FD6 -#define USB_PID_ATMEL_DFU_ATXMEGA128C3 0x2FD7 -#define USB_PID_ATMEL_DFU_ATXMEGA16C4 0x2FD8 -#define USB_PID_ATMEL_DFU_ATXMEGA32C4 0x2FD9 -#define USB_PID_ATMEL_DFU_ATXMEGA256C3 0x2FDA -#define USB_PID_ATMEL_DFU_ATXMEGA384C3 0x2FDB -#define USB_PID_ATMEL_DFU_ATUCL3_L4 0x2FDC -#define USB_PID_ATMEL_DFU_ATXMEGA64A4U 0x2FDD -#define USB_PID_ATMEL_DFU_ATXMEGA128A4U 0x2FDE - -#define USB_PID_ATMEL_DFU_ATXMEGA64B3 0x2FDF -#define USB_PID_ATMEL_DFU_ATXMEGA128B3 0x2FE0 -#define USB_PID_ATMEL_DFU_ATXMEGA64B1 0x2FE1 -#define USB_PID_ATMEL_DFU_ATXMEGA256A3BU 0x2FE2 -#define USB_PID_ATMEL_DFU_ATXMEGA16A4U 0x2FE3 -#define USB_PID_ATMEL_DFU_ATXMEGA32A4U 0x2FE4 -#define USB_PID_ATMEL_DFU_ATXMEGA64A3U 0x2FE5 -#define USB_PID_ATMEL_DFU_ATXMEGA128A3U 0x2FE6 -#define USB_PID_ATMEL_DFU_ATXMEGA192A3U 0x2FE7 -#define USB_PID_ATMEL_DFU_ATXMEGA64A1U 0x2FE8 -#define USB_PID_ATMEL_DFU_ATUC3D 0x2FE9 -#define USB_PID_ATMEL_DFU_ATXMEGA128B1 0x2FEA -#define USB_PID_ATMEL_DFU_AT32UC3C 0x2FEB -#define USB_PID_ATMEL_DFU_ATXMEGA256A3U 0x2FEC -#define USB_PID_ATMEL_DFU_ATXMEGA128A1U 0x2FED -#define USB_PID_ATMEL_DFU_ATMEGA8U2 0x2FEE -#define USB_PID_ATMEL_DFU_ATMEGA16U2 0x2FEF -#define USB_PID_ATMEL_DFU_ATMEGA32U2 0x2FF0 -#define USB_PID_ATMEL_DFU_AT32UC3A3 0x2FF1 -#define USB_PID_ATMEL_DFU_ATMEGA32U6 0x2FF2 -#define USB_PID_ATMEL_DFU_ATMEGA16U4 0x2FF3 -#define USB_PID_ATMEL_DFU_ATMEGA32U4 0x2FF4 -#define USB_PID_ATMEL_DFU_AT32AP7200 0x2FF5 -#define USB_PID_ATMEL_DFU_AT32UC3B 0x2FF6 -#define USB_PID_ATMEL_DFU_AT90USB82 0x2FF7 -#define USB_PID_ATMEL_DFU_AT32UC3A 0x2FF8 -#define USB_PID_ATMEL_DFU_AT90USB64 0x2FF9 -#define USB_PID_ATMEL_DFU_AT90USB162 0x2FFA -#define USB_PID_ATMEL_DFU_AT90USB128 0x2FFB -// 2FFCh to 2FFFh used by C51 family products -//! @} - -//! @} - -//! @} - -#endif // _USB_ATMEL_H_ diff --git a/atmel-samd/asf4/samd51/usb/usb_debug.h b/atmel-samd/asf4/samd51/usb/usb_debug.h deleted file mode 100644 index 4d8893208..000000000 --- a/atmel-samd/asf4/samd51/usb/usb_debug.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * \file - * - * \brief USB Debug Files. - * - * This file contains the USB definitions and data structures provided by the - * USB 2.0 specification. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef _USB_DEBUG_H_ -#define _USB_DEBUG_H_ - -#define udbg_print(...) - -#endif diff --git a/atmel-samd/asf4/samd51/usb/usb_includes.h b/atmel-samd/asf4/samd51/usb/usb_includes.h deleted file mode 100644 index b3874d31e..000000000 --- a/atmel-samd/asf4/samd51/usb/usb_includes.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - * \file - * - * \brief USB Include Header Files. - * - * This file contains the USB definitions and data structures provided by the - * USB 2.0 specification. - * - * Copyright (C) 2015 - 2017 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef _USB_INCLUDES_H_ -#define _USB_INCLUDES_H_ - -#ifdef USB_USER_INCLUDES - -#include "usb_user_includes.h" - -#else -/* Include START headers */ -#include -#include -#include -#include -#include -#include -#include - -typedef uint16_t le16_t; -typedef uint32_t le32_t; -typedef uint16_t be16_t; -typedef uint32_t be32_t; - -#if (defined __GNUC__) || (defined __CC_ARM) -#define is_constant(exp) __builtin_constant_p(exp) -#else -#define is_constant(exp) (0) -#endif - -/*! \brief Toggles the endianism of \a u16 (by swapping its bytes). - * - * \param u16 U16 of which to toggle the endianism. - * - * \return Value resulting from \a u16 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#define swap_u16(u16) ((uint16_t)(((uint16_t)(u16) >> 8) | ((uint16_t)(u16) << 8))) - -/*! \brief Toggles the endianism of \a u32 (by swapping its bytes). - * - * \param u32 U32 of which to toggle the endianism. - * - * \return Value resulting from \a u32 with toggled endianism. - * - * \note More optimized if only used with values known at compile time. - */ -#if (defined __GNUC__) -#define swap_u32(u32) \ - (is_constant(u32) \ - ? ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16))) \ - : ((uint32_t)__builtin_bswap32((uint32_t)(u32)))) -#else -#define swap_u32(u32) \ - ((uint32_t)(((uint32_t)swap_u16((uint32_t)(u32) >> 16)) | ((uint32_t)swap_u16((uint32_t)(u32)) << 16))) -#endif - -/** Get a value from/to LE16 data */ -#define LE16(x) (x) -/** Get a value from/to LE32 data */ -#define LE32(x) (x) -/** Get a value from/to BE16 data */ -#define BE16(x) swap_u16(x) -/** Get a value from/to BE32 data */ -#define BE32(x) swap_u32(x) - -/** Get byte 0 for BE 16-bit value */ -#define BE16B0(a) ((uint8_t)((a) >> 8)) -/** Get byte 1 for BE 16-bit value */ -#define BE16B1(a) ((uint8_t)((a) >> 0)) - -/** Get byte 0 for BE 32-bit value */ -#define BE32B0(a) ((uint8_t)((a) >> 24)) -/** Get byte 1 for BE 32-bit value */ -#define BE32B1(a) ((uint8_t)((a) >> 16)) -/** Get byte 2 for BE 32-bit value */ -#define BE32B2(a) ((uint8_t)((a) >> 8)) -/** Get byte 3 for BE 32-bit value */ -#define BE32B3(a) ((uint8_t)((a) >> 0)) - -/** Get byte 0 for LE 16-bit value */ -#define LE16B0(a) ((uint8_t)((a) >> 0)) -/** Get byte 1 for LE 16-bit value */ -#define LE16B1(a) ((uint8_t)((a) >> 8)) - -/** Get byte 0 for LE 32-bit value */ -#define LE32B0(a) ((uint8_t)((a) >> 0)) -/** Get byte 1 for LE 32-bit value */ -#define LE32B1(a) ((uint8_t)((a) >> 8)) -/** Get byte 2 for LE 32-bit value */ -#define LE32B2(a) ((uint8_t)((a) >> 16)) -/** Get byte 3 for LE 32-bit value */ -#define LE32B3(a) ((uint8_t)((a) >> 24)) - -#endif /* USB_USER_INCLUDES */ - -#endif /* _USB_INCLUDES_H_ */ diff --git a/atmel-samd/asf4/samd51/usb/usb_protocol.c b/atmel-samd/asf4/samd51/usb/usb_protocol.c deleted file mode 100644 index 534e4d1d9..000000000 --- a/atmel-samd/asf4/samd51/usb/usb_protocol.c +++ /dev/null @@ -1,146 +0,0 @@ -/** - * \file - * - * \brief USB protocol implementation. - * - * This file contains the USB definitions and data structures provided by the - * USB 2.0 specification. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#define CONF_NO_ASSERT_CHECK - -#include "usb_protocol.h" - -#ifdef CONF_NO_ASSERT_CHECK -#define _param_error_check(cond) -#define _desc_len_check() \ - if (usb_desc_len(desc) < 2) { \ - /* Encounter an invalid descriptor. */ \ - return NULL; \ - } -#else -#define _param_error_check(cond) ASSERT(cond) -#define _desc_len_check() ASSERT(usb_desc_len(desc) >= 2) -#endif - -uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type) -{ - _param_error_check(desc && eof && (desc < eof)); - - while (desc < eof) { - _desc_len_check(); - if (type == usb_desc_type(desc)) { - return desc; - } - desc = usb_desc_next(desc); - } - return NULL; -} - -uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n) -{ - _param_error_check(desc && eof && (desc < eof)); - - while (desc < eof) { - _desc_len_check(); - if (USB_DT_INTERFACE == usb_desc_type(desc)) { - if (iface_n != desc[2]) { - return desc; - } - } - desc = usb_desc_next(desc); - } - return eof; -} - -uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof) -{ - _param_error_check(desc && eof && (desc < eof)); - - while (desc < eof) { - _desc_len_check(); - if (USB_DT_INTERFACE == usb_desc_type(desc)) { - break; - } - if (USB_DT_ENDPOINT == usb_desc_type(desc)) { - return desc; - } - desc = usb_desc_next(desc); - } - return NULL; -} - -uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value) -{ - _param_error_check(desc && eof && (desc < eof)); - - desc = usb_find_desc(desc, eof, USB_DT_CONFIG); - if (!desc) { - return NULL; - } - while (desc < eof) { - _desc_len_check(); - if (desc[1] != USB_DT_CONFIG) { - break; - } - if (desc[5] == cfg_value) { - return desc; - } - desc = usb_cfg_desc_next(desc); - } - return NULL; -} - -uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index) -{ - uint8_t i; - - _param_error_check(desc && eof && (desc < eof)); - - for (i = 0; desc < eof;) { - desc = usb_find_desc(desc, eof, USB_DT_STRING); - if (desc) { - _desc_len_check(); - if (i == str_index) { - return desc; - } - i++; - desc = usb_desc_next(desc); - } else { - return NULL; - } - } - return NULL; -} diff --git a/atmel-samd/asf4/samd51/usb/usb_protocol.h b/atmel-samd/asf4/samd51/usb/usb_protocol.h deleted file mode 100644 index bb8d1ecd5..000000000 --- a/atmel-samd/asf4/samd51/usb/usb_protocol.h +++ /dev/null @@ -1,765 +0,0 @@ -/** - * \file - * - * \brief USB protocol definitions. - * - * This file contains the USB definitions and data structures provided by the - * USB 2.0 specification. - * - * Copyright (C) 2015 Atmel Corporation. All rights reserved. - * - * \page License - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * 3. The name of Atmel may not be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * 4. This software may only be redistributed and used in connection with an - * Atmel AVR product. - * - * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE - * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - * DAMAGE. - */ - -#ifndef _USB_PROTOCOL_H_ -#define _USB_PROTOCOL_H_ - -#include "usb_includes.h" - -/** - * \ingroup usb_group - * \defgroup usb_protocol_group USB Protocol Definitions - * - * This module defines constants and data structures provided by the USB - * 2.0 specification. - * - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef __CC_ARM -#pragma anon_unions -#endif - -/*! Value for field bcdUSB */ -#define USB_V2_0 (0x0200) /*!< USB Specification version 2.00 */ -#define USB_V2_1 (0x0201) /*!< USB Specification version 2.01 (support BOS) */ - -/*! \name Generic definitions (Class, subclass and protocol) - */ -/*! @{ */ -#define USB_CLASS_NO (0x00) -#define USB_SUBCLASS_NO (0x00) -#define USB_PROTOCOL_NO (0x00) -/*! @} */ - -/*! \name IAD (Interface Association Descriptor) constants */ -/*! @{ */ -#define USB_CLASS_IAD (0xEF) -#define USB_SUBCLASS_IAD (0x02) -#define USB_PROTOCOL_IAD (0x01) -/*! @} */ - -/** - * \brief USB request data transfer direction (bmRequestType) - */ -#define USB_REQT_DIR_OUT (0 << 7) /*!< Host to device */ -#define USB_REQT_DIR_H2D (0 << 7) /*!< Host to device */ -#define USB_REQT_DIR_IN (1 << 7) /*!< Device to host */ -#define USB_REQT_DIR_D2H (1 << 7) /*!< Device to host */ -#define USB_REQT_DIR_MASK (1 << 7) /*!< Mask */ - -/** - * \brief USB request types (bmRequestType) - */ -#define USB_REQT_TYPE_STANDARD (0 << 5) /*!< Standard request */ -#define USB_REQT_TYPE_CLASS (1 << 5) /*!< Class-specific request */ -#define USB_REQT_TYPE_VENDOR (2 << 5) /*!< Vendor-specific request */ -#define USB_REQT_TYPE_MASK (3 << 5) /*!< Mask */ - -/** - * \brief USB recipient codes (bmRequestType) - */ -#define USB_REQT_RECIP_DEVICE (0 << 0) /*!< Recipient device */ -#define USB_REQT_RECIP_INTERFACE (1 << 0) /*!< Recipient interface */ -#define USB_REQT_RECIP_ENDPOINT (2 << 0) /*!< Recipient endpoint */ -#define USB_REQT_RECIP_OTHER (3 << 0) /*!< Recipient other */ -#define USB_REQT_RECIP_MASK (0x1F) /*!< Mask */ - -/** - * \brief Standard USB control transfer stages. - */ -enum usb_ctrl_stage { USB_SETUP_STAGE = 0, USB_DATA_STAGE = 1, USB_STATUS_STAGE = 2 }; - -/** - * \brief Standard USB requests (bRequest) - */ -enum usb_req_code { - USB_REQ_GET_STATUS = 0, - USB_REQ_CLEAR_FTR = 1, - USB_REQ_SET_FTR = 3, - USB_REQ_SET_ADDRESS = 5, - USB_REQ_GET_DESC = 6, - USB_REQ_SET_DESC = 7, - USB_REQ_GET_CONFIG = 8, - USB_REQ_SET_CONFIG = 9, - USB_REQ_GET_INTERFACE = 10, - USB_REQ_SET_INTERFACE = 11, - USB_REQ_SYNCH_FRAME = 12, - USB_REQ_SET_SEL = 48, - USB_REQ_ISOCH_DELAY = 49 -}; - -/** - * \brief Standard USB device status flags - * - */ -enum usb_dev_status { - USB_DEV_STAT_BUS_POWERED = 0, - USB_DEV_STAT_SELF_POWERED = 1, - USB_DEV_STAT_REMOTEWAKEUP = 2, - USB_DEV_STAT_U1_ENABLE = 4, - USB_DEV_STAT_U2_ENABLE = 8, - USB_DEV_STAT_LTM_ENABLE = 16 -}; - -/** - * \brief Standard USB Interface status flags - * - */ -enum usb_interface_status { - USB_IFACE_STAT_RESERVED = 0, - USB_IFACE_STAT_REMOTEWAKE_CAP = 1, - USB_IFACE_STAT_REMOTEWAKE = 2 -}; - -/** - * \brief Standard USB endpoint status flags - * - */ -enum usb_endpoint_status { USB_EP_STAT_HALT = 1 }; - -/** - * \brief Standard USB device feature flags - * - * \note valid for SetFeature request. - */ -enum usb_device_feature { - USB_DEV_FTR_REMOTE_WAKEUP = 1, /*!< Remote wakeup enabled */ - USB_DEV_FTR_TEST_MODE = 2, /*!< USB test mode */ - USB_DEV_FTR_OTG_B_HNP_ENABLE = 3, - USB_DEV_FTR_OTG_A_HNP_SP = 4, - USB_DEV_FTR_OTG_A_ALT_HNP_SP = 5, - USB_DEV_FTR_U1_ENABLE = 48, - USB_DEV_FTR_U2_ENABLE = 49, - USB_DEV_FTR_LTM_ENABLE = 50 -}; - -/** - * \brief Test Mode possible on HS USB device - * - * \note valid for USB_DEV_FTR_TEST_MODE request. - */ -enum usb_device_hs_test_mode { - USB_DEV_TEST_MODE_J = 1, - USB_DEV_TEST_MODE_K = 2, - USB_DEV_TEST_MODE_SE0_NAK = 3, - USB_DEV_TEST_MODE_PACKET = 4, - USB_DEV_TEST_MODE_FORCE_ENABLE = 5 -}; - -/** - * \brief Standard Feature Selectors for Interface - */ -enum usb_iface_feature { USB_IFACE_FTR_FUNC_SUSP = 0 }; - -/** - * \brief Standard USB endpoint feature/status flags - */ -enum usb_endpoint_feature { USB_EP_FTR_HALT = 0 }; - -/** - * \brief Standard USB Test Mode Selectors - */ -enum usb_test_mode_selector { - USB_TEST_J = 0x01, - USB_TEST_K = 0x02, - USB_TEST_SE0_NAK = 0x03, - USB_TEST_PACKET = 0x04, - USB_TEST_FORCE_ENABLE = 0x05 -}; - -/** - * \brief Standard USB descriptor types - */ -enum usb_descriptor_type { - USB_DT_DEVICE = 1, - USB_DT_CONFIG = 2, - USB_DT_STRING = 3, - USB_DT_INTERFACE = 4, - USB_DT_ENDPOINT = 5, - USB_DT_DEVICE_QUALIFIER = 6, - USB_DT_OTHER_SPEED_CONFIG = 7, - USB_DT_INTERFACE_POWER = 8, - USB_DT_OTG = 9, - USB_DT_DEBUG = 10, - USB_DT_IAD = 11, - USB_DT_BOS = 15, - USB_DT_DEV_CAP = 16, - USB_DT_SS_EP_COMPANION = 48 -}; - -/** - * \brief Capability types - */ -enum usb_capability_type { - USB_CAPT_WIRELESS = 1, - USB_CAPT_2_0_EXT = 2, - USB_CAPT_SUPER_SPEED = 3, - USB_CAPT_CONTAINER_ID = 4 -}; - -/** - * \brief USB 2.0 Extension attributes - */ -enum usb_2_0_ext_attr { USB_2_0_EXT_LPM_SP = 1 }; - -/** - * \brief USB SuperSpeed Capability attributes - */ -enum usb_ss_cap_attr { USB_SS_LTM_SP }; - -/** - * \brief USB Speed Supports - */ -enum usb_speed_sp { - USB_SPEED_LOW_SP = 1, - USB_SPEED_LS_SP = 1, - USB_SPEED_FULL_SP = 2, - USB_SPEED_FS_SP = 2, - USB_SPEED_HIGH_SP = 4, - USB_SPEED_HS_SP = 4, - USB_SPEED_SUPER_SP = 8, - USB_SPEED_SS_SP = 8 -}; - -/** - * \brief Standard USB endpoint transfer types - */ -enum usb_ep_type { - USB_EP_TYPE_CONTROL = 0x00, - USB_EP_TYPE_ISOCHRONOUS = 0x01, - USB_EP_TYPE_BULK = 0x02, - USB_EP_TYPE_INTERRUPT = 0x03, - USB_EP_TYPE_MASK = 0x03u -}; - -/** - * \brief USB endpoint interrupt types - */ -enum usb_ep_int_type { USB_EP_INT_T_PERIODIC = 0x00u, USB_EP_INT_T_NOTIFICATION = 0x01u, USB_EP_INT_T_MASK = 0x03u }; - -/** - * \brief Standard USB endpoint synchronization types - */ -enum usb_ep_sync_type { - USB_EP_SYNC_T_NO = 0x00u, - USB_EP_SYNC_T_ASYNC = 0x02u, - USB_EP_SYNC_T_ADAPTIVE = 0x02u, - USB_EP_SYNC_T_SYNC = 0x03u, - USB_EP_SYNC_T_MASK = 0x03u -}; - -/** - * \brief Standard USB endpoint usage types - */ -enum usb_ep_usage_type { - USB_EP_USAGE_T_DATA = 0x00u, - USB_EP_USAGE_T_FEEDBACK = 0x01u, - USB_EP_USAGE_T_FEEDBACK_DATA = 0x02u, - USB_EP_USAGE_T_MASK = 0x03u -}; - -/** - * \brief Standard USB language IDs for string descriptors - */ -enum usb_langid { - USB_LANGID_EN_US = 0x0409 /*!< English (United States) */ -}; - -/** - * \brief Mask selecting the index part of an endpoint address - */ -#define USB_EP_ADDR_MASK 0x0f -/** - * \brief Endpoint transfer direction is IN - */ -#define USB_EP_DIR_IN 0x80 -/** - * \brief Endpoint transfer direction is OUT - */ -#define USB_EP_DIR_OUT 0x00 - -/** - * \brief Maximum length in bytes of a USB descriptor - * - * The maximum length of a USB descriptor is limited by the 8-bit - * bLength field. - */ -#define USB_DESC_LEN_MAX 255 - -/* - * 2-byte alignment requested for all USB structures. - */ -COMPILER_PACK_SET(1) - -/** - * \brief A USB Device SETUP request - * - * The data payload of SETUP packets always follows this structure. - */ -typedef struct usb_req { - uint8_t bmRequestType; - uint8_t bRequest; - union { - le16_t wValue; - struct { - uint8_t l; - uint8_t h; - } wValueBytes; - }; - union { - le16_t wIndex; - struct { - uint8_t l; - uint8_t h; - } wIndexBytes; - }; - union { - le16_t wLength; - struct { - uint8_t l; - uint8_t h; - } wLengthBytes; - }; -} usb_req_t; - -/** - * \brief Standard USB device descriptor structure - */ -typedef struct usb_dev_desc { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - le16_t idVendor; - le16_t idProduct; - le16_t bcdDevice; - uint8_t iManufacturer; - uint8_t iProduct; - uint8_t iSerialNumber; - uint8_t bNumConfigurations; -} usb_dev_desc_t; - -/** - * \brief Binary device Object Store (BOS) descriptor structure - */ -typedef struct usb_bos_desc { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t wTotalLength; - uint8_t bNumDeviceCaps; -} usb_bos_desc_t; - -/** - * \brief Device Capability Descriptor structure - */ -typedef struct usb_cap_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; - uint8_t Vars[1]; -} usb_cap_desc_t; - -/** - * \brief USB 2.0 Extension Descriptor structure - */ -typedef struct usb_2_0_ext { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; - uint32_t bmAttributes; -} usb_2_0_ext_t; - -/** - * \brief LPM Device Capabilities descriptor structure - */ -typedef struct usb_2_0_ext usb_lpm_cap_desc_t; - -/** - * \brief SuperSpeed USB Device Capability structure - */ -typedef struct usb_ss_cap_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; - uint8_t bmAttributes; - le16_t wSpeedsSupported; - uint8_t bFunctionalitySupport; - uint8_t bU1DevExitLat; - uint8_t bU2DevExitLat; -} usb_ss_cap_desc_t; - -/** - * \brief USB Container ID Descriptor structure - */ -typedef struct usb_container_id_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bDevCapabilityType; - uint8_t bReserved; - uint8_t ContainerID[16]; -} usb_container_id_desc_t; - -/** - * \brief Standard USB device qualifier descriptor structure - * - * This descriptor contains information about the device when running at - * the "other" speed (i.e. if the device is currently operating at high - * speed, this descriptor can be used to determine what would change if - * the device was operating at full speed.) - */ -typedef struct usb_dev_qual_desc { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t bcdUSB; - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - uint8_t bMaxPacketSize0; - uint8_t bNumConfigurations; - uint8_t bReserved; -} usb_dev_qual_desc_t; - -/** - * \brief Standard USB configuration descriptor structure - */ -typedef struct usb_config_desc { - uint8_t bLength; - uint8_t bDescriptorType; - le16_t wTotalLength; - uint8_t bNumInterfaces; - uint8_t bConfigurationValue; - uint8_t iConfiguration; - uint8_t bmAttributes; - uint8_t bMaxPower; -} usb_config_desc_t; - -#define USB_CONFIG_ATTR_MUST_SET (1 << 7) /*!< Must always be set */ -#define USB_CONFIG_ATTR_BUS_POWERED (0 << 6) /*!< Bus-powered */ -#define USB_CONFIG_ATTR_SELF_POWERED (1 << 6) /*!< Self-powered */ -#define USB_CONFIG_ATTR_REMOTE_WAKEUP (1 << 5) /*!< remote wakeup supported */ - -#define USB_CONFIG_MAX_POWER(ma) (((ma) + 1) / 2) /*!< Max power in mA */ - -/** - * \brief Standard USB association descriptor structure - */ -typedef struct usb_iad_desc { - uint8_t bLength; /*!< Size of this descriptor in bytes */ - uint8_t bDescriptorType; /*!< Interface descriptor type */ - uint8_t bFirstInterface; /*!< Number of interface */ - uint8_t bInterfaceCount; /*!< value to select alternate setting */ - uint8_t bFunctionClass; /*!< Class code assigned by the USB */ - uint8_t bFunctionSubClass; /*!< Sub-class code assigned by the USB */ - uint8_t bFunctionProtocol; /*!< Protocol code assigned by the USB */ - uint8_t iFunction; /*!< Index of string descriptor */ -} usb_iad_desc_t; - -/** - * \brief Standard USB interface descriptor structure - */ -typedef struct usb_iface_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; - uint8_t bNumEndpoints; - uint8_t bInterfaceClass; - uint8_t bInterfaceSubClass; - uint8_t bInterfaceProtocol; - uint8_t iInterface; -} usb_iface_desc_t; - -/** - * \brief Standard USB endpoint descriptor structure - */ -typedef struct usb_ep_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - le16_t wMaxPacketSize; - uint8_t bInterval; -} usb_ep_desc_t; - -/** - * \brief SuperSpeed Endpoint Companion descriptor structure - */ -typedef struct usb_ss_ep_comp_desc { - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bMaxBurst; - uint8_t bmAttributes; - le16_t wBytesPerInterval; -} usb_ss_ep_comp_desc_t; - -/** - * \brief LPM Token bmAttributes structure - */ -typedef struct usb_lpm_attributes { - uint8_t bLinkState : 4; - uint8_t HIRD : 4; - uint8_t bRemoteWake : 1; - uint8_t Reserved : 2; -} usb_lpm_attributes_t; - -/** - * \brief A standard USB string descriptor structure - */ -typedef struct usb_str_desc { - uint8_t bLength; - uint8_t bDescriptorType; -} usb_str_desc_t; - -typedef struct usb_str_langid_desc { - usb_str_desc_t desc; - le16_t string[1]; -} usb_str_langid_desc_t; - -COMPILER_PACK_RESET() - -/** \name Macros to build USB standard descriptors */ -/*@{*/ - -/** Build bytes for USB device descriptor. */ -#define USB_DEV_DESC_BYTES(bcdUSB, \ - bDeviceClass, \ - bDeviceSubClass, \ - bDeviceProtocol, \ - bMaxPacketSize0, \ - idVendor, \ - idProduct, \ - bcdDevice, \ - iManufacturer, \ - iProduct, \ - iSerialNumber, \ - bNumConfigurations) \ - 18, /* bLength */ \ - 0x01, /* bDescriptorType: DEVICE */ \ - LE_BYTE0(bcdUSB), LE_BYTE1(bcdUSB), bDeviceClass, bDeviceSubClass, bDeviceProtocol, bMaxPacketSize0, \ - LE_BYTE0(idVendor), LE_BYTE1(idVendor), LE_BYTE0(idProduct), LE_BYTE1(idProduct), LE_BYTE0(bcdDevice), \ - LE_BYTE1(bcdDevice), iManufacturer, iProduct, iSerialNumber, bNumConfigurations - -#define USB_DEV_DESC_LEN 18 - -/** Build bytes for USB configuration descriptor. */ -#define USB_CONFIG_DESC_BYTES( \ - wTotalLength, bNumInterfaces, bConfigurationValue, iConfiguration, bmAttributes, bMaxPower) \ - 9, /* bLength */ \ - 0x02, /* bDescriptorType: CONFIGURATION */ \ - LE_BYTE0(wTotalLength), LE_BYTE1(wTotalLength), bNumInterfaces, bConfigurationValue, iConfiguration, \ - bmAttributes, bMaxPower - -#define USB_CONFIG_DESC_LEN 9 - -/** Build bytes for USB IAD descriptor. */ -#define USB_IAD_DESC_BYTES( \ - bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction) \ - 8, /* bLength */ \ - USB_DT_IAD, /* bDescriptorType */ \ - bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol, iFunction - -#define USB_IAD_DESC_LEN 8 - -/** Build bytes for USB interface descriptor. */ -#define USB_IFACE_DESC_BYTES(bInterfaceNumber, \ - bAlternateSetting, \ - bNumEndpoints, \ - bInterfaceClass, \ - bInterfaceSubClass, \ - bInterfaceProtocol, \ - iInterface) \ - 9, /* bLength */ \ - 0x04, /* bDescriptorType: INTERFACE */ \ - bInterfaceNumber, bAlternateSetting, bNumEndpoints, bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, \ - iInterface - -#define USB_IFACE_DESC_LEN 9 - -/** Build bytes for USB endpoint descriptor. */ -#define USB_ENDP_DESC_BYTES(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ - 7, /* bLength */ \ - 0x05, /* bDescriptorType: ENDPOINT */ \ - bEndpointAddress, bmAttributes, LE_BYTE0(wMaxPacketSize), LE_BYTE1(wMaxPacketSize), bInterval - -#define USB_ENDP_DESC_LEN 7 - -/*@}*/ - -/** \brief Get a word (calculate by little endian 16-bit data) - * \param[in] ptr Byte pointer to the address to get data - * \return a 16-bit word - */ -static inline uint16_t usb_get_u16(const uint8_t *ptr) -{ - return (ptr[0] + (ptr[1] << 8)); -} - -/** \brief Get a double word (calculate by little endian 32-bit data) - * \param[in] ptr Byte pointer to the address to get data - * \return a 32-bit word - */ -static inline uint32_t usb_get_u32(const uint8_t *ptr) -{ - return (ptr[0] + (ptr[1] << 8) + (ptr[2] << 16) + (ptr[3] << 24)); -} - -/** \brief Get descriptor length - * \param[in] desc Byte pointer to the descriptor start address - * \return descriptor length - */ -static inline uint8_t usb_desc_len(const uint8_t *desc) -{ - return desc[0]; -} - -/** \brief Get descriptor type - * \param[in] desc Byte pointer to the descriptor start address - * \return descriptor type - */ -static inline uint8_t usb_desc_type(const uint8_t *desc) -{ - return desc[1]; -} - -/** \brief Get next USB descriptor - * \param[in] desc Byte pointer to the descriptor start address - * \return Byte pointer to the next descriptor - */ -static inline uint8_t *usb_desc_next(uint8_t *desc) -{ - return (desc + usb_desc_len(desc)); -} - -/** \brief Get idVendor of USB Device Descriptor - * \param[in] dev_desc Byte pointer to the descriptor start address - * \return 16-bit idVendor value - */ -static inline uint16_t usb_dev_desc_vid(const uint8_t *dev_desc) -{ - return usb_get_u16(dev_desc + 8); -} - -/** \brief Get idProduct of USB Device Descriptor - * \param[in] dev_desc Byte pointer to the descriptor start address - * \return 16-bit idProduct value - */ -static inline uint16_t usb_dev_desc_pid(const uint8_t *dev_desc) -{ - return usb_get_u16(dev_desc + 10); -} - -/** \brief Get wTotalLength of USB Configuration Descriptor - * \param[in] cfg_desc Byte pointer to the descriptor start address - * \return 16-bit total length of configuration list - */ -static inline uint16_t usb_cfg_desc_total_len(const uint8_t *cfg_desc) -{ - return usb_get_u16(cfg_desc + 2); -} - -/** \brief Get Next USB Descriptor After the Configuration Descriptors list - * \param[in] cfg_desc Byte pointer to the descriptor start address - * \return Byte pointer to descriptor after configuration end - */ -static inline uint8_t *usb_cfg_desc_next(uint8_t *cfg_desc) -{ - return (cfg_desc + usb_cfg_desc_total_len(cfg_desc)); -} - -/** \brief Find specific USB Descriptor by its type - * \param[in] desc Byte pointer to the descriptor start address - * \param[in] eof Byte pointer to the descriptor end address - * \param[in] type The descriptor type expected - * \return Pointer to the descriptor - * \retval NULL if not found - */ -uint8_t *usb_find_desc(uint8_t *desc, uint8_t *eof, uint8_t type); - -/** Get interface descriptor next to the specified one (by interface number) - * \param[in] desc Byte pointer to the descriptor start address - * \param[in] eof Byte pointer to the descriptor end address - * \param[in] iface_n The interface number to check - * \return Pointer to the descriptor - * \retval >= eof if not found - */ -uint8_t *usb_find_iface_after(uint8_t *desc, uint8_t *eof, uint8_t iface_n); - -/** Find endpoint descriptor, breaks if interface descriptor detected - * \param[in] desc Byte pointer to the descriptor start address - * \param[in] eof Byte pointer to the descriptor end address - * \return Pointer to the descriptor - * \retval NULL if not found - */ -uint8_t *usb_find_ep_desc(uint8_t *desc, uint8_t *eof); - -/** Find configuration descriptor by its configuration number - * \param[in] desc Byte pointer to the descriptor start address - * \param[in] eof Byte pointer to the descriptor end address - * \param[in] cfg_value The configure value expected - * \return Pointer to the descriptor - * \retval NULL if not found - */ -uint8_t *usb_find_cfg_desc(uint8_t *desc, uint8_t *eof, uint8_t cfg_value); - -/** Find string descriptor by its index - * \param[in] desc Byte pointer to the descriptor start address - * \param[in] eof Byte pointer to the descriptor end address - * \param[in] str_index The string index expected - * \return Pointer to the descriptor - * \retval NULL if not found - */ -uint8_t *usb_find_str_desc(uint8_t *desc, uint8_t *eof, uint8_t str_index); - -#ifdef __cplusplus -} -#endif - -/*! @} */ - -#endif /* _USB_PROTOCOL_H_ */ diff --git a/atmel-samd/asf4/samd51/usb_start.c b/atmel-samd/asf4/samd51/usb_start.c deleted file mode 100644 index 683392806..000000000 --- a/atmel-samd/asf4/samd51/usb_start.c +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file or main.c - * to avoid loosing it when reconfiguring. - */ -#include "atmel_start.h" -#include "usb_start.h" - -#define CONF_USB_MSC_MAX_LUN 0 - -static uint8_t multi_desc_bytes[] = { - /* Device descriptors and Configuration descriptors list. */ - COMPOSITE_DESCES_LS_FS, -}; - -static struct usbd_descriptors multi_desc = {multi_desc_bytes, multi_desc_bytes + sizeof(multi_desc_bytes)}; - -/** Ctrl endpoint buffer */ -static uint8_t ctrl_buffer[64]; - -void composite_device_init(void) -{ - /* usb stack init */ - usbdc_init(ctrl_buffer); - -/* usbdc_register_funcion inside */ -#if CONF_USB_COMPOSITE_CDC_ACM_EN - cdcdf_acm_init(); -#endif -#if CONF_USB_COMPOSITE_HID_MOUSE_EN - hiddf_mouse_init(); -#endif -#if CONF_USB_COMPOSITE_HID_KEYBOARD_EN - hiddf_keyboard_init(); -#endif -#if CONF_USB_COMPOSITE_MSC_EN - mscdf_init(CONF_USB_MSC_MAX_LUN); -#endif -} - -void composite_device_start(void) -{ - usbdc_start(&multi_desc); - usbdc_attach(); -} - -void composite_device_example(void) -{ - - /* Initialize */ - /* It's done with system init ... */ - - /* Before start do function related initializations */ - /* Add your code here ... */ - - /* Start device */ - composite_device_start(); - - /* Main loop */ - while (1) { - if (cdcdf_acm_is_enabled()) { - /* CDC ACM process*/ - } - if (hiddf_mouse_is_enabled()) { - /* HID Mouse process */ - } - if (hiddf_keyboard_is_enabled()) { - /* HID Keyboard process */ - }; - if (mscdf_is_enabled()) { - /* MSC process */ - } - } -} - -void usb_init(void) -{ - - composite_device_init(); -} diff --git a/atmel-samd/asf4/samd51/usb_start.h b/atmel-samd/asf4/samd51/usb_start.h deleted file mode 100644 index 912bf289c..000000000 --- a/atmel-samd/asf4/samd51/usb_start.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Code generated from Atmel Start. - * - * This file will be overwritten when reconfiguring your Atmel Start project. - * Please copy examples or other code you want to keep to a separate file or main.c - * to avoid loosing it when reconfiguring. - */ -#ifndef USB_DEVICE_MAIN_H -#define USB_DEVICE_MAIN_H - -#ifdef __cplusplus -extern "C" { -#endif // __cplusplus - -#include "cdcdf_acm.h" -#include "hiddf_mouse.h" -#include "hiddf_keyboard.h" -#include "hiddf_generic.h" -#include "mscdf.h" -#include "composite_desc.h" - -/** - * \brief Initialize device and attach functions - */ -void composite_device_init(void); -/** - * \brief Start the device - */ -void composite_device_start(void); -/** - * Example of using Composite Function. - * \note - * In this example, we will use a PC as a USB host: - * - Connect the DEBUG USB on XPLAINED board to PC for program download. - * - Connect the TARGET USB on XPLAINED board to PC for running program. - */ -void composite_device_example(void); - -/** - * \berif Initialize USB - */ -void usb_init(void); - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // USB_DEVICE_MAIN_H -- cgit v1.2.3